US20050194664A1 - Bonding pad arrangement method for semiconductor devices - Google Patents
Bonding pad arrangement method for semiconductor devices Download PDFInfo
- Publication number
- US20050194664A1 US20050194664A1 US11/107,897 US10789705A US2005194664A1 US 20050194664 A1 US20050194664 A1 US 20050194664A1 US 10789705 A US10789705 A US 10789705A US 2005194664 A1 US2005194664 A1 US 2005194664A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor device
- pads
- pad
- edge
- bond
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49121—Beam lead frame or beam lead device
Definitions
- the present invention relates to a semiconductor device and, more particularly, to pad arrangements for reducing bonding failures and signal skew.
- the pad pitch limit, or pad-to-pad design rule may define the minimum size.
- FIGS. 1A to 1 C are views of representative pad arrangements that are used on conventional semiconductor devices.
- FIG. 1A illustrates pads 98 arranged in a single row on a chip 100
- FIG. 1B illustrates pads 98 arranged in two rows on a chip 100
- FIG. 1C illustrates pads 98 arranged around the periphery of a chip 100 .
- FIG. 2 illustrates a conventional configuration of bonding wires 104 used to connect two rows of bond pads to the corresponding portions of a lead frame 102 .
- the separation between the bonding wires 104 used to connect pads 1 - 3 , 6 - 11 and 14 - 16 to the corresponding portions of the lead frame 102 is reduced, increasing the likelihood that one or more shorts may be formed between a bond wire and a pad and/or an adjacent bond wire.
- Increasing the number of bond pads tends to reduce the spacing between adjacent bond wires and to increase the likelihood of shorts.
- bonding wires 104 connected between the more distant portions of the lead frame 102 and certain of the pads, e.g., pads 1 , 8 , 9 and 16 are substantially longer than those bonding wires connected between closer portions of the lead frame and other pads, e.g., pads 4 , 5 , 12 and 13 .
- Different bonding wire lengths may result in a timing skew between the signals being transmitted through the bonding wires to the respective pads. These timing skews will tend to compromise signal integrity, disrupt high-speed operations and limit the rate at which the semiconductor device may be successfully operated.
- exemplary embodiments of the invention are directed to a method of arranging pads on a semiconductor device in a manner that will tend to reduce the likelihood of shorts and/or reduce the signal time skew during operation of the semiconductor device.
- Exemplary embodiments of the invention are directed to methods of arranging pads on semiconductor devices to allow a plurality of bonding wires to have substantially the same length.
- Exemplary embodiments of the invention provide methods of arranging pads, such as pad-on-cell (POC) type pads, on semiconductor devices to form pad groupings having an oblique arrangement with respect to the chip edge and/or other pad groupings.
- Exemplary pad groupings configurations may be symmetrical or asymmetrical with respect to the chip edge and may include one or more V-shaped, sawtooth or zigzag-type pad arrangements that may allow reductions in the semiconductor package size, reduce the length variation in the bond wires, and reduce the likelihood of shorting between bonding wires and/or pads.
- FIGS. 1A to 1 C are plan views illustrating certain conventional pad arrangements
- FIG. 2 is a view illustrating a bonding wire configuration between a conventional lead from and semiconductor device pads with an increased likelihood of shorting or bonding failures
- FIG. 3 is a plan view showing a pad arrangement in which lead frames are bonded with pads in accordance with a first exemplary embodiment of the invention
- FIG. 4 is a plan view showing a pad arrangement in which lead frames are bonded with pads in accordance with a second exemplary embodiment of the invention
- FIG. 5 is a plan view of a pad arrangement in accordance with a third exemplary embodiment of the invention.
- FIGS. 6A and 6B are plan views of pad arrangements in accordance with a fourth exemplary embodiment of the invention.
- FIG. 7A is a plan view of a pad arrangement in accordance with a fifth exemplary embodiment of the invention
- FIG. 7B is a plan view of a pad arrangement in which the angles ⁇ and ⁇ are substantially equal
- FIG. 7C is a plan view of a pad arrangement in which the bonding wire have substantially equal lengths
- FIG. 8 is a plan view of a pad arrangement in accordance with a sixth exemplary embodiment of the invention.
- FIG. 9 is a plan view of a pad arrangement in accordance with a seventh exemplary embodiment of the present invention.
- FIG. 10 is a plan view of an embodiment in which two series of pads are arranged with the corresponding axes being substantially parallel.
- FIG. 3 is a plan view showing an arrangement of pads 1 - 16 on a semiconductor chip 100 according to a first exemplary embodiment of the invention with portions of a conventional lead frame 102 being connected to the pads with bonding wires 104 .
- pads 1 - 8 and 9 - 12 are arranged to form two shallow “V” shapes having legs arranged obliquely with respect to one of the edges 106 of chip 100 .
- this arrangement of the pads allows the bonding wires 104 between the several end pads on each leg of the “V” shape, i.e., pads 1 - 3 , 6 - 8 , 9 - 11 and 14 - 16 to be bonded to a conventional lead frame 102 while improving the separation between adjacent bonding wires and the overlap of other pads to reduce the likelihood of shorting.
- Increasing the oblique angle between a group of pads and the edge of the chip can increase the number of pads that may be successfully bonded to the lead frame and permit the mounting of semiconductor devices having an increased number of pads.
- FIG. 4 is a plan view showing an arrangement of pads 1 - 10 on a semiconductor chip 100 according to a second exemplary embodiment of the invention with portions of a conventional lead frame 102 being connected to the pads with bonding wires 104 .
- pads 1 - 5 and 6 - 10 are arranged in opposing “V” shapes configured to allow connection to a conventional lead frame 102 using bonding wires 104 of substantially equal length. By allowing the use of bonding wires of substantially equal length, this pad arrangement reduces signal skew and improves signal integrity.
- FIG. 5 is a plan view of a pad arrangement in accordance with a third exemplary embodiment of the invention.
- a plurality of memory cell array blocks including memory cell array blocks MCB 0 to MCB 3 , and sense amplifiers, including S/A 0 to S/A 3 , are provided on a semiconductor chip 100 .
- Each of the memory cell array blocks is associated with a pair of pads, including pads 1 - 10 , which may be POC-type pads.
- the pads in each memory cell array block are offset in such a manner that the first pads in each of the memory cell array blocks are arranged in a first line and the second pads in each of the memory cell array blocks are arranged in a second line, the first and second lines being substantially parallel to each other and to the edge 106 of the chip 100 .
- the offset between the pads and the step distance between adjacent memory cell array blocks may be such that a line from a first pad to a second pad to the next first pad, e.g., from pad 1 to pad 2 to pad 3 , etc., will have a somewhat zigzag or sawtooth pattern. Offsetting the pads in each of the memory cell array blocks in this manner increases the number of pads that can be successfully bonded to a lead frame when compared with pads arranged in a single row.
- FIGS. 6A and 6B are plan views of pad arrangements in accordance with a fourth exemplary embodiment of the present invention.
- pads 1 - 10 which may be POC-type pads, are arranged on a semiconductor chip 100 over a plurality of memory cell array blocks, MCB 0 to MCB 4 , in a general “V” shape with the point of the “V” directed toward the center of the chip.
- the V-shaped pad arrangement illustrated in FIG. 6A allows the lengths of the bonding wires 104 used to connect the pads 98 and a lead frame (not shown) to be substantially equal, reducing the incidence of signal skew and improving the signal integrity.
- the pads may also be arranged in a “V” shape in which the point of the “V” is directed away from the center toward the edge 106 of the chip 100 .
- this pad arrangement improves the separation between adjacent bonding wires, particularly for those pads at the ends of the legs of the “V,” and will reduce the likelihood of shorting.
- FIG. 7 is a plan view of a pad arrangement in accordance with a fifth exemplary embodiment of the present invention.
- pads 1 - 10 are again arranged to form a somewhat asymmetric “V” shape.
- Pads 1 - 5 are generally aligned along a first line 108 defining a first oblique angle a with the edge 106 of chip 100 .
- pads 6 - 10 are generally aligned along a second line 110 defining a second oblique angle ⁇ with the edge 106 of chip 100 .
- the selection of different angles ⁇ and ⁇ allows the pad arrangement to be adjusted to compensate for the off-center mounting of the chip 100 within a lead frame (not shown).
- the selection of the angles ⁇ and ⁇ chips can improve the bonding performance by providing a larger effective angle for pads that are to be bonded to more distant portions of the lead frame while providing an angle that will tend to equalize the lengths of the bonding wires to pads that will be connected to closer portions of the lead frame.
- FIG. 8 is a plan view of a pad arrangement in accordance with a sixth exemplary embodiment of the present invention.
- pads 1 to 10 are arranged over memory cell array blocks MCB 0 to MCB 4 in an asymmetric “V” shape with pads 1 - 5 forming a first leg of the “V” and pads 6 - 10 forming the second leg.
- the oblique angle ⁇ formed between a line 108 though pads 1 to 5 and the edge 106 of chip 100 is different than the angle ⁇ formed between a line 110 through pads 6 - 10 and the edge 106 of chip 100 .
- FIG. 9 is a plan view of a pad arrangement in accordance with a seventh exemplary embodiment of the present invention.
- the pad arrangement illustrated in FIG. 9 is substantially similar to the pad arrangement illustrated in FIG. 8 , except that the pads of FIG. 9 are conventional pads arranged on a semiconductor substrate rather than POC-type pads. The reasons for and the benefits resulting from such a pad arrangement are similar to those discussed in connection with FIG. 8 .
- Pad arrangements in accord with the exemplary embodiments of the invention make it possible to reduce the occurrence of shorts between the bonding wires, the pads and/or the lead frame in a semiconductor package. Pad arrangements in accord with the exemplary embodiments of the invention may also make it possible to reduce the difference in the length of the bonding wires, thereby reducing signal skew and improving signal integrity.
Abstract
A variety of pad arrangements are provided for semiconductor devices for reducing the likelihood of bonding failures, particularly those due to shorts, and/or for reducing the difference in length between bonding wires to decrease signal skew during operation of the semiconductor device and improve signal integrity.
Description
- This is a divisional application of U.S. patent application Ser. No. 10/465,554, filed on Jun. 20, 2003, which claims priority under 35 U.S.C. § 119 of Korean Patent Application 2002-35925 filed on Jun. 26, 2002, the entire contents of which are hereby incorporated by reference.
- 1. Field of the Invention
- The present invention relates to a semiconductor device and, more particularly, to pad arrangements for reducing bonding failures and signal skew.
- 2. Discussion of the Related Art
- As semiconductor manufacturing processes have improved, design rules have been reduced to allow for smaller and/or higher density semiconductor devices. However, for semiconductor devices having a large number of pads, the pad pitch limit, or pad-to-pad design rule, may define the minimum size.
-
FIGS. 1A to 1C are views of representative pad arrangements that are used on conventional semiconductor devices.FIG. 1A illustratespads 98 arranged in a single row on achip 100,FIG. 1B illustratespads 98 arranged in two rows on achip 100 andFIG. 1C illustratespads 98 arranged around the periphery of achip 100. -
FIG. 2 illustrates a conventional configuration ofbonding wires 104 used to connect two rows of bond pads to the corresponding portions of alead frame 102. As reflected inFIG. 2 , the separation between thebonding wires 104 used to connect pads 1-3, 6-11 and 14-16 to the corresponding portions of thelead frame 102 is reduced, increasing the likelihood that one or more shorts may be formed between a bond wire and a pad and/or an adjacent bond wire. Increasing the number of bond pads tends to reduce the spacing between adjacent bond wires and to increase the likelihood of shorts. - Further,
bonding wires 104 connected between the more distant portions of thelead frame 102 and certain of the pads, e.g.,pads pads - Accordingly, exemplary embodiments of the invention are directed to a method of arranging pads on a semiconductor device in a manner that will tend to reduce the likelihood of shorts and/or reduce the signal time skew during operation of the semiconductor device.
- Exemplary embodiments of the invention are directed to methods of arranging pads on semiconductor devices to allow a plurality of bonding wires to have substantially the same length.
- Exemplary embodiments of the invention provide methods of arranging pads, such as pad-on-cell (POC) type pads, on semiconductor devices to form pad groupings having an oblique arrangement with respect to the chip edge and/or other pad groupings. Exemplary pad groupings configurations may be symmetrical or asymmetrical with respect to the chip edge and may include one or more V-shaped, sawtooth or zigzag-type pad arrangements that may allow reductions in the semiconductor package size, reduce the length variation in the bond wires, and reduce the likelihood of shorting between bonding wires and/or pads.
- It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation to those of skill in the art of the invention as claimed.
- Exemplary embodiments of the invention may be further understood through the written description and the accompanying FIGURES in which:
-
FIGS. 1A to 1C are plan views illustrating certain conventional pad arrangements; -
FIG. 2 is a view illustrating a bonding wire configuration between a conventional lead from and semiconductor device pads with an increased likelihood of shorting or bonding failures; -
FIG. 3 is a plan view showing a pad arrangement in which lead frames are bonded with pads in accordance with a first exemplary embodiment of the invention; -
FIG. 4 is a plan view showing a pad arrangement in which lead frames are bonded with pads in accordance with a second exemplary embodiment of the invention; -
FIG. 5 is a plan view of a pad arrangement in accordance with a third exemplary embodiment of the invention; -
FIGS. 6A and 6B are plan views of pad arrangements in accordance with a fourth exemplary embodiment of the invention; -
FIG. 7A is a plan view of a pad arrangement in accordance with a fifth exemplary embodiment of the invention,FIG. 7B is a plan view of a pad arrangement in which the angles α and β are substantially equal,FIG. 7C is a plan view of a pad arrangement in which the bonding wire have substantially equal lengths; -
FIG. 8 is a plan view of a pad arrangement in accordance with a sixth exemplary embodiment of the invention; -
FIG. 9 is a plan view of a pad arrangement in accordance with a seventh exemplary embodiment of the present invention; andFIG. 10 is a plan view of an embodiment in which two series of pads are arranged with the corresponding axes being substantially parallel. - Exemplary embodiments of the invention will be described below with reference to accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein; rather, these exemplary embodiments are provided so that this disclosure is thorough and complete, and conveys the concept of the invention to those skilled in the art. In the drawings, the sizing and spacing of elements may be enlarged or reduced for clarity and are not intended to be to scale.
-
FIG. 3 is a plan view showing an arrangement of pads 1-16 on asemiconductor chip 100 according to a first exemplary embodiment of the invention with portions of aconventional lead frame 102 being connected to the pads withbonding wires 104. As illustrated inFIG. 3 , pads 1-8 and 9-12 are arranged to form two shallow “V” shapes having legs arranged obliquely with respect to one of theedges 106 ofchip 100. - As illustrated in
FIG. 3 , this arrangement of the pads allows thebonding wires 104 between the several end pads on each leg of the “V” shape, i.e., pads 1-3, 6-8, 9-11 and 14-16 to be bonded to aconventional lead frame 102 while improving the separation between adjacent bonding wires and the overlap of other pads to reduce the likelihood of shorting. Increasing the oblique angle between a group of pads and the edge of the chip can increase the number of pads that may be successfully bonded to the lead frame and permit the mounting of semiconductor devices having an increased number of pads. -
FIG. 4 is a plan view showing an arrangement of pads 1-10 on asemiconductor chip 100 according to a second exemplary embodiment of the invention with portions of aconventional lead frame 102 being connected to the pads withbonding wires 104. As illustrated inFIG. 4 , pads 1-5 and 6-10 are arranged in opposing “V” shapes configured to allow connection to aconventional lead frame 102 usingbonding wires 104 of substantially equal length. By allowing the use of bonding wires of substantially equal length, this pad arrangement reduces signal skew and improves signal integrity. -
FIG. 5 is a plan view of a pad arrangement in accordance with a third exemplary embodiment of the invention. As illustrated inFIG. 5 , a plurality of memory cell array blocks, including memory cell array blocks MCB0 to MCB3, and sense amplifiers, including S/A0 to S/A3, are provided on asemiconductor chip 100. Each of the memory cell array blocks is associated with a pair of pads, including pads 1-10, which may be POC-type pads. The pads in each memory cell array block are offset in such a manner that the first pads in each of the memory cell array blocks are arranged in a first line and the second pads in each of the memory cell array blocks are arranged in a second line, the first and second lines being substantially parallel to each other and to theedge 106 of thechip 100. The offset between the pads and the step distance between adjacent memory cell array blocks may be such that a line from a first pad to a second pad to the next first pad, e.g., frompad 1 topad 2 topad 3, etc., will have a somewhat zigzag or sawtooth pattern. Offsetting the pads in each of the memory cell array blocks in this manner increases the number of pads that can be successfully bonded to a lead frame when compared with pads arranged in a single row. -
FIGS. 6A and 6B are plan views of pad arrangements in accordance with a fourth exemplary embodiment of the present invention. As illustrated inFIG. 6A , pads 1-10, which may be POC-type pads, are arranged on asemiconductor chip 100 over a plurality of memory cell array blocks, MCB0 to MCB4, in a general “V” shape with the point of the “V” directed toward the center of the chip. As did the pad arrangement illustrated inFIG. 4 , the V-shaped pad arrangement illustrated inFIG. 6A allows the lengths of thebonding wires 104 used to connect thepads 98 and a lead frame (not shown) to be substantially equal, reducing the incidence of signal skew and improving the signal integrity. - As illustrated in
FIG. 6B , the pads may also be arranged in a “V” shape in which the point of the “V” is directed away from the center toward theedge 106 of thechip 100. As it did in the exemplary embodiment illustrated inFIG. 3 , this pad arrangement improves the separation between adjacent bonding wires, particularly for those pads at the ends of the legs of the “V,” and will reduce the likelihood of shorting. -
FIG. 7 is a plan view of a pad arrangement in accordance with a fifth exemplary embodiment of the present invention. As illustrated inFIG. 7 , pads 1-10 are again arranged to form a somewhat asymmetric “V” shape. Pads 1-5 are generally aligned along afirst line 108 defining a first oblique angle a with theedge 106 ofchip 100. Similarly, pads 6-10 are generally aligned along asecond line 110 defining a second oblique angle β with theedge 106 ofchip 100. The selection of different angles α and β allows the pad arrangement to be adjusted to compensate for the off-center mounting of thechip 100 within a lead frame (not shown). In off-center mounting configurations, such as may be used in a multi-chip package, the selection of the angles α and β chips can improve the bonding performance by providing a larger effective angle for pads that are to be bonded to more distant portions of the lead frame while providing an angle that will tend to equalize the lengths of the bonding wires to pads that will be connected to closer portions of the lead frame. -
FIG. 8 is a plan view of a pad arrangement in accordance with a sixth exemplary embodiment of the present invention. As illustrated inFIG. 8 ,pads 1 to 10 are arranged over memory cell array blocks MCB0 to MCB4 in an asymmetric “V” shape with pads 1-5 forming a first leg of the “V” and pads 6-10 forming the second leg. Like the pad arrangement illustrated inFIG. 7 , the oblique angle α formed between aline 108 thoughpads 1 to 5 and theedge 106 ofchip 100 is different than the angle β formed between aline 110 through pads 6-10 and theedge 106 ofchip 100. -
FIG. 9 is a plan view of a pad arrangement in accordance with a seventh exemplary embodiment of the present invention. The pad arrangement illustrated inFIG. 9 is substantially similar to the pad arrangement illustrated inFIG. 8 , except that the pads ofFIG. 9 are conventional pads arranged on a semiconductor substrate rather than POC-type pads. The reasons for and the benefits resulting from such a pad arrangement are similar to those discussed in connection withFIG. 8 . - Pad arrangements in accord with the exemplary embodiments of the invention make it possible to reduce the occurrence of shorts between the bonding wires, the pads and/or the lead frame in a semiconductor package. Pad arrangements in accord with the exemplary embodiments of the invention may also make it possible to reduce the difference in the length of the bonding wires, thereby reducing signal skew and improving signal integrity.
- It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims (11)
1. A semiconductor device having a plurality of bond pads comprising:
a plurality of bond pad pairs, each pair of bond pads including a first bond pad and a second bond pad, wherein
each of the first bond pads is positioned at a first perpendicular distance from a first edge of the semiconductor device; and
each of the second bond pads is positioned at a second perpendicular distance from the first edge of the semiconductor device and separated from a corresponding first bond pad by a third distance in a direction parallel to the first edge of the semiconductor device, wherein:
the first and second perpendicular distances are not identical.
2. The semiconductor device according to claim 1 , wherein:
the semiconductor device is configured as a pad-on-cell (POC) device including a plurality of memory cell array blocks, and wherein
at least one bond pad pair is arranged on each memory cell array block.
3. The semiconductor device according to claim 2 , wherein:
each second bond pad is separated from an adjacent non-paired first bond pad by a step distance in a direction generally parallel to the first edge of the semiconductor device.
4. The semiconductor device according to claim 3 , wherein:
the third distance is an offset distance.
5. The semiconductor device according to claim 3 , wherein:
the offset distance and the step distance are approximately equal.
6. The semiconductor device according to claim 3 , wherein:
a ratio between the offset distance and the step distance is at least 1:4.
7. A semiconductor package comprising:
a semiconductor device according to claim 1;
a lead frame, the lead frame including a plurality of connection regions, the connection regions being arranged along an axis substantially parallel to the first edge of the semiconductor device; and
a plurality of bond wires extending between connection regions of the lead frame and the bond pads, wherein:
the semiconductor device is configured as a pad-on-cell (POC) device that includes a plurality of memory cell array blocks, and further wherein, at least one bond pad pair is arranged over each memory cell array block.
8. A semiconductor package according to claim 7 , wherein:
the semiconductor device includes
a second edge parallel to the first edge;
third and fourth edges perpendicular to the first and second edges; and
a plurality of third bond pads arranged adjacent at least one of the second, third and fourth edges of the semiconductor device.
9. The semiconductor package comprising:
a semiconductor device according to claim 1 , wherein the semiconductor device is configured as a pad-on-cell (POC) device that includes a plurality of memory cell array blocks separated by a plurality of sense amplifiers and wherein adjacent ones of the bond pads are arranged over at least one memory cell array block.
10. The semiconductor package according to claim 9 , wherein:
the bond pad pairs are positioned outside a periphery of the sense amplifiers.
11. The semiconductor package according to claim 9 , wherein:
the semiconductor device includes
a second edge parallel to the first edge;
third and fourth edges perpendicular to the first and second edges; and
a plurality of third bond pads arranged adjacent at least one of the second, third and fourth edges of the semiconductor device.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0035925A KR100476925B1 (en) | 2002-06-26 | 2002-06-26 | Semiconductor chip having pad arrangement for preventing bonding failure and signal skew of pad |
KR2002-35925 | 2002-06-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050194664A1 true US20050194664A1 (en) | 2005-09-08 |
Family
ID=29774940
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/465,554 Expired - Lifetime US6949837B2 (en) | 2002-06-26 | 2003-06-20 | Bonding pad arrangement method for semiconductor devices |
US11/107,897 Abandoned US20050194664A1 (en) | 2002-06-26 | 2005-04-18 | Bonding pad arrangement method for semiconductor devices |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/465,554 Expired - Lifetime US6949837B2 (en) | 2002-06-26 | 2003-06-20 | Bonding pad arrangement method for semiconductor devices |
Country Status (2)
Country | Link |
---|---|
US (2) | US6949837B2 (en) |
KR (1) | KR100476925B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180061306A1 (en) * | 2016-08-25 | 2018-03-01 | Lg Display Co., Ltd. | Display panel and display device |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4758787B2 (en) * | 2006-03-02 | 2011-08-31 | パナソニック株式会社 | Semiconductor integrated circuit |
US20090051050A1 (en) * | 2007-08-24 | 2009-02-26 | Actel Corporation | corner i/o pad density |
US8450841B2 (en) * | 2011-08-01 | 2013-05-28 | Freescale Semiconductor, Inc. | Bonded wire semiconductor device |
US9288905B2 (en) | 2013-11-11 | 2016-03-15 | Seagate Technology Llc | Shaped internal leads for a printed circuit substrate |
KR101815754B1 (en) * | 2016-03-10 | 2018-01-08 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5757082A (en) * | 1995-07-31 | 1998-05-26 | Rohm Co., Ltd. | Semiconductor chips, devices incorporating same and method of making same |
US5815427A (en) * | 1997-04-02 | 1998-09-29 | Micron Technology, Inc. | Modular memory circuit and method for forming same |
US5818114A (en) * | 1995-05-26 | 1998-10-06 | Hewlett-Packard Company | Radially staggered bond pad arrangements for integrated circuit pad circuitry |
US6008532A (en) * | 1997-10-23 | 1999-12-28 | Lsi Logic Corporation | Integrated circuit package having bond fingers with alternate bonding areas |
US6303948B1 (en) * | 1996-02-29 | 2001-10-16 | Kabushiki Kaisha Toshiba | Pad layout and lead layout in semiconductor device |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2698452B2 (en) * | 1989-09-25 | 1998-01-19 | 沖電気工業株式会社 | Resin-sealed semiconductor device and method of assembling the same |
JPH0574844A (en) * | 1991-09-13 | 1993-03-26 | Fujitsu Ltd | Semiconductor chip |
JPH0637131A (en) * | 1992-07-15 | 1994-02-10 | Hitachi Ltd | Semiconductor integrated circuit device |
KR940010291A (en) * | 1992-10-30 | 1994-05-24 | 김광호 | Multi-Pin Semiconductor Packages |
JPH0774203A (en) * | 1993-09-01 | 1995-03-17 | Fujitsu Ltd | Semiconductor integrated circuit device and its manufacture |
JPH08330351A (en) * | 1995-05-29 | 1996-12-13 | Hitachi Ltd | Semiconductor integrated circuit device |
JP2848348B2 (en) * | 1996-08-29 | 1999-01-20 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
-
2002
- 2002-06-26 KR KR10-2002-0035925A patent/KR100476925B1/en active IP Right Grant
-
2003
- 2003-06-20 US US10/465,554 patent/US6949837B2/en not_active Expired - Lifetime
-
2005
- 2005-04-18 US US11/107,897 patent/US20050194664A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5818114A (en) * | 1995-05-26 | 1998-10-06 | Hewlett-Packard Company | Radially staggered bond pad arrangements for integrated circuit pad circuitry |
US5757082A (en) * | 1995-07-31 | 1998-05-26 | Rohm Co., Ltd. | Semiconductor chips, devices incorporating same and method of making same |
US6303948B1 (en) * | 1996-02-29 | 2001-10-16 | Kabushiki Kaisha Toshiba | Pad layout and lead layout in semiconductor device |
US5815427A (en) * | 1997-04-02 | 1998-09-29 | Micron Technology, Inc. | Modular memory circuit and method for forming same |
US6008532A (en) * | 1997-10-23 | 1999-12-28 | Lsi Logic Corporation | Integrated circuit package having bond fingers with alternate bonding areas |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180061306A1 (en) * | 2016-08-25 | 2018-03-01 | Lg Display Co., Ltd. | Display panel and display device |
US10565921B2 (en) * | 2016-08-25 | 2020-02-18 | Lg Display Co., Ltd. | Display panel and display device |
Also Published As
Publication number | Publication date |
---|---|
KR20040000911A (en) | 2004-01-07 |
US6949837B2 (en) | 2005-09-27 |
US20040000726A1 (en) | 2004-01-01 |
KR100476925B1 (en) | 2005-03-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6753598B2 (en) | Transverse hybrid LOC package | |
US7615853B2 (en) | Chip-stacked package structure having leadframe with multi-piece bus bar | |
US7675168B2 (en) | Integrated circuit with staggered differential wire bond pairs | |
US20050194664A1 (en) | Bonding pad arrangement method for semiconductor devices | |
US5757082A (en) | Semiconductor chips, devices incorporating same and method of making same | |
US6677219B2 (en) | Method of forming a ball grid array package | |
US6121690A (en) | Semiconductor device having two pluralities of electrode pads, pads of different pluralities having different widths and respective pads of different pluralities having an aligned transverse edge | |
US20010054759A1 (en) | Semiconductor device | |
US20050242431A1 (en) | Integrated circuit dies | |
US8796077B2 (en) | Semiconductor device | |
US6091089A (en) | Semiconductor integrated circuit device | |
US6097082A (en) | Semiconductor device | |
US20030042619A1 (en) | Configuration of conductive bumps and redistribution layer on a flip chip | |
US20090072416A1 (en) | Semiconductor device, and manufacturing method of semiconductor device | |
USRE44699E1 (en) | Semiconductor integrated circuit having pads layout for increasing signal integrity and reducing chip size | |
US6323548B1 (en) | Semiconductor integrated circuit device | |
US6953997B1 (en) | Semiconductor device with improved bonding pad connection and placement | |
JPH04364051A (en) | Semiconductor device | |
US6531762B1 (en) | Semiconductor package | |
JP4699829B2 (en) | Bonding structure for lead frame substrate and substrate substrate semiconductor package and manufacturing method thereof | |
US20010026005A1 (en) | Substrate for mounting a semiconductor chip and method for manufacturing a semiconductor device | |
JP2879787B2 (en) | Semiconductor package for high density surface mounting and semiconductor mounting substrate | |
JPS6185832A (en) | Wire-bonding | |
US20230110997A1 (en) | Semiconductor device | |
US20060186403A1 (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |