US20050264340A1 - Method and apparatus for reducing charge injection in control of mems electrostatic actuator array - Google Patents
Method and apparatus for reducing charge injection in control of mems electrostatic actuator array Download PDFInfo
- Publication number
- US20050264340A1 US20050264340A1 US10/855,359 US85535904A US2005264340A1 US 20050264340 A1 US20050264340 A1 US 20050264340A1 US 85535904 A US85535904 A US 85535904A US 2005264340 A1 US2005264340 A1 US 2005264340A1
- Authority
- US
- United States
- Prior art keywords
- gate
- semiconductor switch
- voltage
- control circuit
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0833—Several active elements per pixel in active matrix panels forming a linear amplifier or follower
- G09G2300/0838—Several active elements per pixel in active matrix panels forming a linear amplifier or follower with level shifting
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/088—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements using a non-linear two-terminal element
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
- G09G3/3466—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on interferometric effect
Definitions
- the present invention relates generally to a MEMS (Micro-Electro-Mechanical Systems) and more specifically to a control arrangement for a MEMS actuator which reduces charge errors and which allows more precise control of the MEMS actuator position and increases control range.
- MEMS Micro-Electro-Mechanical Systems
- MOS Metal Oxide Semiconductor
- FIG. 1 is a schematic depiction of an embodiment of the invention showing a variable capacitor and a charge injection control circuit which is connected to the variable capacitor through a semiconductor device such as transistor and which controls the development of charge on the upper of the two electrodes.
- FIG. 2 is a circuit diagram showing a first embodiment of an injection control circuit which is applied to the arrangement illustrated in FIG. 1 .
- FIG. 3 is a circuit diagram showing a second embodiment of an injection control circuit.
- FIGS. 4A-4C graphically depict operational characteristics of the circuit arrangement shown in FIG. 2 (first embodiment).
- FIGS. 5A-5C graphically depict the operational characteristics of the circuit arrangement shown in FIG. 3 (second embodiment).
- FIG. 6 is a circuit diagram showing a third embodiment of the injection control circuit.
- FIGS. 7A-7C graphically depict operation characteristics of the circuit arrangement shown in FIG. 6 (third embodiment).
- FIG. 8 is a circuit diagram of a fourth embodiment of the injection control circuit which includes one or more diodes in each array of sub-circuit and which limits the “on” and “off” gate voltages of the MOS switch.
- FIG. 9 graphically depict the operation characteristics of the circuit arrangement shown in FIG. 8 (fourth embodiment) on charge injection.
- FIG. 10 is a circuit diagram which shows an example of a modified level shifter circuit which comprises an embodiment of the invention and which can be used with the other embodiments.
- FIGS. 11A and 11B are graphs which show operation characteristics of an unoptimized level shifter circuit of the type shown in FIG. 10 .
- FIGS. 12A and 12B are graphs which show operation characteristics of a level shifter circuit modified in the manner illustrated in FIG. 10 .
- FIG. 1 shows an embodiment of the invention.
- a variable capacitor C 1 consists of a bottom fixed plate (which can be grounded), and a movable top plate which is suspended by flexure beams (not shown).
- the variable gap A between the two plates is controlled by controlling the charge on the upper or top plate.
- an injection control circuit is connected with the upper plate via a solid state switch.
- this arrangement comprises a variable capacitor having a fixed plate and movable plate disposed in predetermined spatial relationship with respect to the fixed plate; and a semiconductor switch which has a source, a drain and a gate, which is associated with a selected one of the fixed and movable plates of the capacitor and which is arranged to selectively connect the selected one of the fixed and movable plates with a voltage source.
- a charge injection control circuit is associated with the semiconductor switch so as to attenuate current injection into the selected one of the fixed and movable plates of the capacitor.
- FIG. 1 C 1 denotes the variable capacitor (flexures are not shown).
- M 1 is an analog switch formed by an NMOS device, a PMOS device, or NMOS and PMOS devices.
- V_ref is an analog reference voltage.
- En is the enable signal which is generated by the charge injection control circuit. To “write” a charge to C 1 and change Gap A, V_ref is established, and then M 1 is turned on by En which is generated by the charge control circuit. After an appropriate time (a function of the circuit's electrical time constant), M 1 is turned off.
- This process changes the amount of charge on C 1 and induces the situation wherein the electrostatic charge which has accumulated on C 1 draws the movable plate toward the fixed plate.
- the circuit of FIG. 1 is replicated N ⁇ M times, in N rows and M columns.
- En could be a row signal, for a total of N En signals, and V_ref could be a column signal for M V_ref signals.
- charge errors occur by way of two mechanisms. The first is due to channel charge, which must flow out from the channel region of the transistor to the drain and source junctions. The second charge is due to overlap capacitance between the gate and drain. The embodiments of the invention described here minimize these sources of charge error.
- each En row signal may be voltage level-shifted from a low voltage (5 V, for example) output from the control logic to a high-voltage (12 V, for example) signal appropriate for the array by means of a high-voltage level shifter circuit.
- the gates of the analog MOS switches in the array can experience voltage swings of 0-12 V, which can inject significant noise due to gate-drain coupling and channel charge injection. It is desired to limit the voltage swing on the gate of the MOS switch to reduce charge injection into the MEMS device. Embodiments that accomplish this are described below:
- the first and second embodiments of the charge injection control circuit are directed to reducing charge injection in MEMS electrostatic actuators by decreasing gate voltage swing on the drive transistor.
- these circuits comprise first and second semiconductor elements which are circuited with a gate of the semiconductor switches and which modify a gate signal which is applied to the gate in a manner wherein at least one of:
- FIG. 2 shows details of the first embodiment of the charge injection control circuit.
- this embodiment requires the addition of two devices to each array subcircuit to limit the “off” gate voltage of the MOS switch and slow the switch closure to the degree that instead of the charge beneath the gate being permitted to distribute 50/50 between the source and the drain, most of the charge is, due to the differential capacitance between the source and drain, permitted to drain off to the source side.
- M 1 b and C 1 b represent M 1 and C 1 of FIG. 1 respectively.
- M 6 b and M 7 b are used to condition the signal ngate_vb, which enables/disables MOS switch M 1 b.
- M 7 b NMOS
- row_enb a high-voltage signal.
- M 1 b is on, the gate of M 1 b is driven to all the way to ground (0 V).
- M 1 b off instead of driving the gate of M 1 b to a full vpp, which would inject maximum coupling noise, the gate of M 1 b is only driven to vref by M 6 b.
- a gate voltage of vref is the minimum voltage required to fully turn M 1 b off.
- NMOS device for M 6 b has the added benefit of smoothing out (slowing) the turn-off voltage slope on ngate_vb, which reduces charge injection in M 1 b due to channel charge dispersion.
- FIG. 3 shows a second embodiment of the invention. This embodiment is also directed limiting the “off” gate voltage of the MOS switch and is such that M 1 c and C 1 c respectively represent M 1 and C 1 of FIG. 1 .
- the signal/element designations which end in the letter “b” in FIG. 2 have corresponding designations wherein the letter “b” is replaced with the letter “c”.
- the letter “b” is replaced by the letter “d”.
- the high voltage signal row_enb in FIG. 2 becomes row_enc and row_end in FIGS. 3 and 6 respectively.
- the signals row-en and row-en-bar are high voltage signals which are applied in accordance with the need to vary the gap A of the variable capacitors.
- M 6 c and M 7 c are used to condition the signal ngate_vc, which enables/disables NMOS switch M 1 c.
- M 1 c NMOS
- M 7 c PMOS
- row_en_barc row_en_barc
- a high-voltage signal To turn M 1 c on, the gate of M 1 c is driven to a full high voltage vpp.
- M 1 c off instead of driving the gate of M 1 c to 0 V, which would inject maximum coupling noise, the gate of M 1 c is only driven to vref by M 6 c .
- a gate voltage of vref is the minimum voltage required to fully turn M 1 c off.
- Using a PMOS device for M 6 c has the added benefit of smoothing out the voltage slope on ngate_vc, which reduces charge injection in M 1 c due to channel charge
- Simulations which were run to test the above embodiments used a 10 fF load capacitance on the drain of the MOS switch to represent the capacitive load presented by the MEMS actuator.
- the results for the first and second embodiments are respectively depicted in FIGS. 4A-4C and 5 A- 5 C. All simulations use a Vref of 5V and Vpp of 9V.
- the circuit shown in FIG. 2 (that is to say, the PMOS switch) was simulated to demonstrate the advantageous effects of M 6 b and M 6 c on charge injection.
- each of the traces labeled “Unoptimized” is a trace of the waveform of the drain of the PMOS switch, the gate of which is driven directly by the bottom waveform (or its complement, in this case).
- the “optimized” waveform uses the extra devices M 6 b and M 7 b to limit the voltage swing on the gate of the PMOS switch.
- 5.546 fC femto Coulomb
- 2.856 fC are injected onto the capacitive load.
- FIG. 3 The circuit of FIG. 3 (NMOS switch) was simulated to demonstrate the advantageous effects of M 6 b and M 6 c on charge injection. The results are depicted graphically in FIGS. 5A-5C .
- the waveform labeled “Unoptimized” in FIG. 5A is a trace of the waveform of the drain of the NMOS switch, the gate of which is driven directly by the waveform shown in FIG. 5C .
- the “optimized” waveform ( FIG. 5B ) uses the extra devices M 6 b and M 7 b to limit the voltage swing on the gate of the NMOS switch. In the unoptimized case, 2.565 fC are injected onto the capacitive load. In the optimized case, only 1.115 fC are injected onto the capacitive load.
- FIG. 6 shows a third embodiment of the charge injection control circuit. This embodiment is directed limiting both “on” and “off” gate voltages to the MOS switch and includes the addition of two devices and one or two reference voltages to each array subcircuit. The reference voltages can be common to the entire array and the embodiment utilizes a PMOS analog switch.
- the reference voltages v_gate_off and v_gate_on can be set depending on the range of voltages that will be used for vref. For example, v_gate_on could be set to approximately one volt below the minimum vref, and v_gate_off could be set to approximately the maximum vref, thus ensuring that the accumulation charge (when M 1 d is off) and inversion charge (when M 1 d is on) are minimized.
- FIG. 7 shows simulation results from the circuit of FIG. 6 .
- the bottom waveform is row_end
- the middle waveform is ngate_vd
- the top waveform is the voltage on C 1 d.
- FIG. 7A The results of FIG. 7A can be compared with those of the unoptimized case of FIG. 4A .
- 5.546 fC (by way of example) are injected onto the capacitive load (see FIG. 4 ).
- 1.445 fC (by way of example only) are injected onto the capacitive load.
- FIG. 8 shows a fourth embodiment of the invention which requires the addition of one or more diodes to each array sub circuit, as well as a resistor which may be implemented using an active device such as an NMOS or PMOS.
- This embodiment limits the “on” and “off” gate voltages of the MOS switch. In the case of a PMOS switch, the gate voltage of the switch can be limited to an acceptable range around vref by means of the circuit shown in this figure.
- the series diodes can be replaced by a single diode designed to have an appropriate VT, or a Zener diode, or some other number/combination of diodes. It may be desirable to limit only the “on” gate voltage or only the “off” gate voltage, in which case D ⁇ 2, 4, and 6> or D ⁇ 1, 3 and 5> may be unnecessary.
- the resistor in R 1 may be realized using a MOS device in order to minimize the area consumed. The resistance should, however, be sufficiently large to minimize static current flow.
- FIG. 9 The results shown in FIG. 9 are compared with the unoptimized case of FIG. 4A .
- the trace is vgate (0-9 V digital)
- the middle trace ( FIG. 9B ) is the voltage of the gate of the PMOS device
- the trace shown in FIG. 9A is the voltage on the 10 fF load capacitance.
- FIG. 9A The results of FIG. 9A are compared with those of the unoptimized case of FIG. 4A .
- 5.546 fC (by way of example) are injected onto the capacitive load (see FIG. 4A ).
- 2.063 fC are injected onto the capacitive load.
- the next embodiment is directed to reducing charge injection in control of MEMS electrostatic actuator arrays by increasing MOS switch turn-off time.
- the accumulated channel charge exits to the source node and the drain node under capacitive coupling and resistive conduction.
- the transistor conduction channel disappears very quickly since there is insufficient time for the charge at the source node and the charge at the drain node to communicate.
- the percentage of the charge injected into the data-holding node approaches 50 percent independent of the ratio of source capacitance to drain capacitance.
- the communication between the charge at the source node and the charge at the drain node is so strong that it tends to make the final voltages at both sides equal. This allows the majority of channel charge to go to the node with larger capacitance.
- each En row signal may be voltage level-shifted from a low voltage (5 V, for example) output from the control logic to a high-voltage (12 V, for example) signal appropriate for the array by means of a conventional high-voltage level shifter circuit such as that shown in FIG. 10 .
- semiconductor elements M 10 a -M 10 f are connected between terminals vpp, In and gnd, and Out and Out_Bar, in the illustrated manner.
- Out or Out_Bar could be used as the row control signal En.
- this level shifter circuit will normally be designed to minimize rise and fall times on the outputs. Therefore, in an effort to minimize charge injection into each MEMS device, the circuit of the FIG. 10 is modified to increase rise and fall times on Out and Out_Bar. This is done by decreasing W/L of selected ones of M 10 a -M 10 f, and/or adding a capacitive load to Out and Out_Bar in the manner shown.
- FIG. 11B shows the charge injected into the drain of the PMOS switch, the gate of which was connected to the output of the unoptimized level shifter, assuming the circuit is running at 9 V and V_ref is 5 V in the manner depicted in FIG. 11A .
- FIG. 11B shows the charge injected into the drain of the PMOS switch, the gate of which was connected to the output of the unoptimized level shifter, assuming the circuit is running at 9 V and V_ref is 5 V in the manner depicted in FIG. 11A .
- injection noise can be reduced by either: 1) reducing the amount of channel charge, 2) increasing the ratio of channel charge dumped between the source and drain by lowering the gate slew rate and increasing the source to drain node capacitance ratio, or 3) partially compensating the channel charges by using both N and P devices on the variable capacitor node.
- injection charge partition noise
- the use of both N & P compensating devices is not necessary and the drain capacitance can be reduced by about half.
- the injection control circuit embodiments of the invention can be applied to controlling a micro-electromechanical system (MEMS) which combine mechanical devices, such as mirrors and actuators, with electronic control circuitry for controlling the mechanical devices.
- MEMS micro-electromechanical system
- one such MEMS arrangement can comprise a diffractive light device (DLD), wherein the variable capacitor is composed of a fixed reflective ground plate and a semi-transparent, (electrostatically) movable second plate.
- DLD diffractive light device
- the variable gap between the plates is used to produce interference or diffraction of light passing thereinto, and can be used for spatial light modulation in high resolution displays and for wavelength management in optical communication systems.
- the above disclosure refers to slowing down the lever shifter
Abstract
Description
- The present invention relates generally to a MEMS (Micro-Electro-Mechanical Systems) and more specifically to a control arrangement for a MEMS actuator which reduces charge errors and which allows more precise control of the MEMS actuator position and increases control range.
- When a MOS (Metal Oxide Semiconductor) switch turns off, charge injection errors occur by way of two mechanisms. The first is due to channel charge, which must flow out from the channel region of the transistor to the drain and source junctions. The second charge is due to overlap capacitance between the gate and drain. These can induce drawbacks in MEMS devices wherein this charge can diminish the degree to which a gap in a device, such as variable capacitor, which is associated with the transistor and the control of the MEMS, can be accurately controlled. In the worst case, these effects can be sufficient to cause a capacitor to go into pull-in mode and undesirably snap down.
- An arrangement which enables the charge injection into a MEMS variable capacitor to be diminished during MOS switch off is therefore necessary.
-
FIG. 1 is a schematic depiction of an embodiment of the invention showing a variable capacitor and a charge injection control circuit which is connected to the variable capacitor through a semiconductor device such as transistor and which controls the development of charge on the upper of the two electrodes. -
FIG. 2 is a circuit diagram showing a first embodiment of an injection control circuit which is applied to the arrangement illustrated inFIG. 1 . -
FIG. 3 is a circuit diagram showing a second embodiment of an injection control circuit. -
FIGS. 4A-4C graphically depict operational characteristics of the circuit arrangement shown inFIG. 2 (first embodiment). -
FIGS. 5A-5C graphically depict the operational characteristics of the circuit arrangement shown inFIG. 3 (second embodiment). -
FIG. 6 is a circuit diagram showing a third embodiment of the injection control circuit. -
FIGS. 7A-7C graphically depict operation characteristics of the circuit arrangement shown inFIG. 6 (third embodiment). -
FIG. 8 is a circuit diagram of a fourth embodiment of the injection control circuit which includes one or more diodes in each array of sub-circuit and which limits the “on” and “off” gate voltages of the MOS switch. -
FIG. 9 graphically depict the operation characteristics of the circuit arrangement shown inFIG. 8 (fourth embodiment) on charge injection. -
FIG. 10 is a circuit diagram which shows an example of a modified level shifter circuit which comprises an embodiment of the invention and which can be used with the other embodiments. -
FIGS. 11A and 11B are graphs which show operation characteristics of an unoptimized level shifter circuit of the type shown inFIG. 10 . -
FIGS. 12A and 12B are graphs which show operation characteristics of a level shifter circuit modified in the manner illustrated inFIG. 10 . - The embodiments of the invention relate to accurately controlling the gap of a MEMs capacitor.
FIG. 1 shows an embodiment of the invention. In this embodiment a variable capacitor C1 consists of a bottom fixed plate (which can be grounded), and a movable top plate which is suspended by flexure beams (not shown). The variable gap A between the two plates is controlled by controlling the charge on the upper or top plate. As shown, an injection control circuit is connected with the upper plate via a solid state switch. - In a nutshell this arrangement comprises a variable capacitor having a fixed plate and movable plate disposed in predetermined spatial relationship with respect to the fixed plate; and a semiconductor switch which has a source, a drain and a gate, which is associated with a selected one of the fixed and movable plates of the capacitor and which is arranged to selectively connect the selected one of the fixed and movable plates with a voltage source. A charge injection control circuit is associated with the semiconductor switch so as to attenuate current injection into the selected one of the fixed and movable plates of the capacitor.
- In more detail,
FIG. 1 C1 denotes the variable capacitor (flexures are not shown). M1 is an analog switch formed by an NMOS device, a PMOS device, or NMOS and PMOS devices. V_ref is an analog reference voltage. En is the enable signal which is generated by the charge injection control circuit. To “write” a charge to C1 and change Gap A, V_ref is established, and then M1 is turned on by En which is generated by the charge control circuit. After an appropriate time (a function of the circuit's electrical time constant), M1 is turned off. - This process changes the amount of charge on C1 and induces the situation wherein the electrostatic charge which has accumulated on C1 draws the movable plate toward the fixed plate.
- To produce an array of MEMS actuators, the circuit of
FIG. 1 is replicated N×M times, in N rows and M columns. En could be a row signal, for a total of N En signals, and V_ref could be a column signal for M V_ref signals. - However, as noted above in connection with the prior art, significant error can be introduced into the system by the charge injected onto C1 by M1 when M1 is turned off. In the worst case, as noted above, this charge can be large enough to cause C1 to go into pull-in mode and snap down. Alternatively, this charge can simply diminish the level of control to which Gap A can be controlled.
- When MOS switches turn off, charge errors occur by way of two mechanisms. The first is due to channel charge, which must flow out from the channel region of the transistor to the drain and source junctions. The second charge is due to overlap capacitance between the gate and drain. The embodiments of the invention described here minimize these sources of charge error.
- In the case of an array of MEMS actuators, the die can consist of control circuitry which runs at low-voltage logic on the periphery of the array, while the array itself, may be required to operate at higher voltages. In this case, each En row signal may be voltage level-shifted from a low voltage (5 V, for example) output from the control logic to a high-voltage (12 V, for example) signal appropriate for the array by means of a high-voltage level shifter circuit.
- In an array operating at 12 V (for example), the gates of the analog MOS switches in the array can experience voltage swings of 0-12 V, which can inject significant noise due to gate-drain coupling and channel charge injection. It is desired to limit the voltage swing on the gate of the MOS switch to reduce charge injection into the MEMS device. Embodiments that accomplish this are described below:
- The first and second embodiments of the charge injection control circuit are directed to reducing charge injection in MEMS electrostatic actuators by decreasing gate voltage swing on the drive transistor. In a nutshell, these circuits comprise first and second semiconductor elements which are circuited with a gate of the semiconductor switches and which modify a gate signal which is applied to the gate in a manner wherein at least one of:
-
- a) a voltage variation time of the gate signal is set so that current can predominantly drain from a channel of the semiconductor switch to the source when the semiconductor switch is closing, and
- b) the voltage of the signal which is applied to the gate is limited to limit the degree to which the semiconductor switch enters into an inversion region and/or an accumulation region.
-
FIG. 2 shows details of the first embodiment of the charge injection control circuit. As will be appreciated, this embodiment requires the addition of two devices to each array subcircuit to limit the “off” gate voltage of the MOS switch and slow the switch closure to the degree that instead of the charge beneath the gate being permitted to distribute 50/50 between the source and the drain, most of the charge is, due to the differential capacitance between the source and drain, permitted to drain off to the source side. - In
FIG. 2 , M1 b and C1 b represent M1 and C1 ofFIG. 1 respectively. M6 b and M7 b are used to condition the signal ngate_vb, which enables/disables MOS switch M1 b. To turn on M1 b (PMOS), M7 b (NMOS) is activated by row_enb, a high-voltage signal. When M1 b is on, the gate of M1 b is driven to all the way to ground (0 V). To turn M1 b off, instead of driving the gate of M1 b to a full vpp, which would inject maximum coupling noise, the gate of M1 b is only driven to vref by M6 b. Because the source of M1 b is at vref, a gate voltage of vref is the minimum voltage required to fully turn M1 b off. Using an NMOS device for M6 b has the added benefit of smoothing out (slowing) the turn-off voltage slope on ngate_vb, which reduces charge injection in M1 b due to channel charge dispersion. -
FIG. 3 shows a second embodiment of the invention. This embodiment is also directed limiting the “off” gate voltage of the MOS switch and is such that M1 c and C1 c respectively represent M1 and C1 ofFIG. 1 . It will be noted that the signal/element designations which end in the letter “b” inFIG. 2 have corresponding designations wherein the letter “b” is replaced with the letter “c”. InFIG. 6 , the letter “b” is replaced by the letter “d”. Thus, the high voltage signal row_enb inFIG. 2 , becomes row_enc and row_end inFIGS. 3 and 6 respectively. - The signals row-en and row-en-bar are high voltage signals which are applied in accordance with the need to vary the gap A of the variable capacitors.
- M6 c and M7 c are used to condition the signal ngate_vc, which enables/disables NMOS switch M1 c. When M1 c (NMOS) is turned on, M7 c (PMOS) is activated by row_en_barc, a high-voltage signal. To turn M1 c on, the gate of M1 c is driven to a full high voltage vpp. To turn M1 c off, instead of driving the gate of M1 c to 0 V, which would inject maximum coupling noise, the gate of M1 c is only driven to vref by M6 c. Because the source of M1 c is at vref, a gate voltage of vref is the minimum voltage required to fully turn M1 c off. Using a PMOS device for M6 c has the added benefit of smoothing out the voltage slope on ngate_vc, which reduces charge injection in M1 c due to channel charge
- Simulations which were run to test the above embodiments used a 10 fF load capacitance on the drain of the MOS switch to represent the capacitive load presented by the MEMS actuator. The results for the first and second embodiments are respectively depicted in
FIGS. 4A-4C and 5A-5C. All simulations use a Vref of 5V and Vpp of 9V. The circuit shown inFIG. 2 (that is to say, the PMOS switch) was simulated to demonstrate the advantageous effects of M6 b and M6 c on charge injection. - In the graphs depicted in
FIGS. 4A-4C , each of the traces labeled “Unoptimized” is a trace of the waveform of the drain of the PMOS switch, the gate of which is driven directly by the bottom waveform (or its complement, in this case). The “optimized” waveform uses the extra devices M6 b and M7 b to limit the voltage swing on the gate of the PMOS switch. In the unoptimized case, 5.546 fC (femto Coulomb) are (by way of example) injected onto the capacitive load. In the optimized case, only 2.856 fC (by way of example) are injected onto the capacitive load. - The circuit of
FIG. 3 (NMOS switch) was simulated to demonstrate the advantageous effects of M6 b and M6 c on charge injection. The results are depicted graphically inFIGS. 5A-5C . - The waveform labeled “Unoptimized” in
FIG. 5A is a trace of the waveform of the drain of the NMOS switch, the gate of which is driven directly by the waveform shown inFIG. 5C . The “optimized” waveform (FIG. 5B ) uses the extra devices M6 b and M7 b to limit the voltage swing on the gate of the NMOS switch. In the unoptimized case, 2.565 fC are injected onto the capacitive load. In the optimized case, only 1.115 fC are injected onto the capacitive load. -
FIG. 6 shows a third embodiment of the charge injection control circuit. This embodiment is directed limiting both “on” and “off” gate voltages to the MOS switch and includes the addition of two devices and one or two reference voltages to each array subcircuit. The reference voltages can be common to the entire array and the embodiment utilizes a PMOS analog switch. - In
FIG. 6 , the reference voltages v_gate_off and v_gate_on can be set depending on the range of voltages that will be used for vref. For example, v_gate_on could be set to approximately one volt below the minimum vref, and v_gate_off could be set to approximately the maximum vref, thus ensuring that the accumulation charge (when M1 d is off) and inversion charge (when M1 d is on) are minimized. - The operation of the circuit shown in
FIG. 6 was verified using the same set of conditions as were used inFIGS. 4 and 5 .FIG. 7 shows simulation results from the circuit ofFIG. 6 . The bottom waveform is row_end, the middle waveform is ngate_vd, and the top waveform is the voltage on C1 d. - The results of
FIG. 7A can be compared with those of the unoptimized case ofFIG. 4A . In the unoptimized case, 5.546 fC (by way of example) are injected onto the capacitive load (seeFIG. 4 ). In the optimized case ofFIG. 7B , 1.445 fC (by way of example only) are injected onto the capacitive load. -
FIG. 8 shows a fourth embodiment of the invention which requires the addition of one or more diodes to each array sub circuit, as well as a resistor which may be implemented using an active device such as an NMOS or PMOS. This embodiment limits the “on” and “off” gate voltages of the MOS switch. In the case of a PMOS switch, the gate voltage of the switch can be limited to an acceptable range around vref by means of the circuit shown in this figure. - Note that the series diodes can be replaced by a single diode designed to have an appropriate VT, or a Zener diode, or some other number/combination of diodes. It may be desirable to limit only the “on” gate voltage or only the “off” gate voltage, in which case D<2, 4, and 6> or D<1, 3 and 5> may be unnecessary. The resistor in R1 may be realized using a MOS device in order to minimize the area consumed. The resistance should, however, be sufficiently large to minimize static current flow.
- The results shown in
FIG. 9 are compared with the unoptimized case ofFIG. 4A . InFIG. 9C , the trace is vgate (0-9 V digital), the middle trace (FIG. 9B ) is the voltage of the gate of the PMOS device, and the trace shown inFIG. 9A is the voltage on the 10 fF load capacitance. - The results of
FIG. 9A are compared with those of the unoptimized case ofFIG. 4A . In the unoptimized case, 5.546 fC (by way of example) are injected onto the capacitive load (seeFIG. 4A ). In the optimized case ofFIG. 9A , 2.063 fC are injected onto the capacitive load. - With the embodiments of the invention, by decreasing the magnitude of the swing of the gate voltage of a MOS switch, charge error resulting from charge injection when the MOS switch turns off is minimized. The schematics described in connection with the preceding embodiments merely provide a few examples of circuits that can perform this function. The circuits described above can be replicated at each array sub circuit, or they can be replicated only once per row (or column) to condition row/column control signals. Note that these embodiments need not be used alone and can be used in conjunction with other methods of reducing charge injection, such as increasing turn-off time on the gate of the MOS switch, and using complimentary MOS switches.
- The next embodiment is directed to reducing charge injection in control of MEMS electrostatic actuator arrays by increasing MOS switch turn-off time.
- As noted above, when MOS switches turn off, charge errors occur by two mechanisms. The first is due to channel charge, which must flow out from the channel region of the transistor to the drain and source junctions. The second charge is due to overlap capacitance between the gate and drain.
- When a MOS transistor turns off, the accumulated channel charge exits to the source node and the drain node under capacitive coupling and resistive conduction. Under fast switching-off conditions, the transistor conduction channel disappears very quickly since there is insufficient time for the charge at the source node and the charge at the drain node to communicate. Hence, the percentage of the charge injected into the data-holding node approaches 50 percent independent of the ratio of source capacitance to drain capacitance. However, under slow switching-off conditions, the communication between the charge at the source node and the charge at the drain node is so strong that it tends to make the final voltages at both sides equal. This allows the majority of channel charge to go to the node with larger capacitance.
- As noted above, in the case of an array of MEMS actuators, the die can consist of control circuitry which runs at low-voltage logic on the periphery of the array, and the array itself, which may be required to operate at higher voltages. In this case, each En row signal may be voltage level-shifted from a low voltage (5 V, for example) output from the control logic to a high-voltage (12 V, for example) signal appropriate for the array by means of a conventional high-voltage level shifter circuit such as that shown in
FIG. 10 . In this example, semiconductor elements M10 a-M10 f are connected between terminals vpp, In and gnd, and Out and Out_Bar, in the illustrated manner. Inasmuch as voltage level shifting circuits are well known in the art and in that a number of variations can be used, no further disclosure will be given with respect to the construction, arrangement and operation of this circuit for the sake of brevity. - With the level shifting circuit shown in
FIG. 10 , Out or Out_Bar, for example, could be used as the row control signal En. However, in the case where control of the array is purely digital and when it is desired to operate control of the array at maximum clock rates, this level shifter circuit will normally be designed to minimize rise and fall times on the outputs. Therefore, in an effort to minimize charge injection into each MEMS device, the circuit of theFIG. 10 is modified to increase rise and fall times on Out and Out_Bar. This is done by decreasing W/L of selected ones of M10 a-M10 f, and/or adding a capacitive load to Out and Out_Bar in the manner shown. - The charge injected by a PMOS switch (e.g. M1) was monitored by monitoring the voltage on a small (10 fF) capacitive load on the drain of the switch, the gate of which was connected to the output of the unoptimized level shifter in
FIG. 10 .FIG. 11B shows the charge injected into the drain of the PMOS switch, the gate of which was connected to the output of the unoptimized level shifter, assuming the circuit is running at 9 V and V_ref is 5 V in the manner depicted inFIG. 11A . - The charge injected by a PMOS switch (e.g. M1) was monitored by monitoring the voltage on a small (10 fF) capacitive load on the drain of the switch, the gate of which was connected to the output of the unoptimized level shifter of the type shown
FIG. 10 but without the capacitance load.FIG. 11B shows the charge injected into the drain of the PMOS switch, the gate of which was connected to the output of the unoptimized level shifter, assuming the circuit is running at 9 V and V_ref is 5 V in the manner depicted inFIG. 11A . - As the PMOS switch (M1) arrangement turns off, the charge injected onto the drain of the switch raises the voltage on the capacitor by 557.2 mV, which correlates to 5.572 fC, given the 10 fF load. In
FIG. 12B , there are two modifications made to the conditioning of the En signal that turns the PMOS switch on and off: (a) W/L of the drivers in the level shifter are decreased, and (b) a 2 pF capacitive load was added to the En signal. The 2 pF capacitive load added to the V_ref signal, allowed the majority of the channel charge to leave via the source of the switch, since the source capacitance is much greater than the drain capacitance. It is worth noting at this point that the 2 pF load added to the vref signal (source of the MOS switch) is the parasitic capacitance inherent in running a V_ref over a large array. The drain of the MOS switch is only connected to the associated MEMS device, so capacitance on that node is quite small. - As the PMOS switch turns off, the charge injected onto the drain of the switch raises 340.05 mV, which correlates to 3.4005 fC, given the 10 fF load. This represents a 1.6× improvement in minimization of charge injection.
- Thus, by increasing the time it takes for an analog MOS switch to turn off, charge injected into the drain due to channel charge accumulation can be decreased. With short turn-off times, channel charge is split approximately equally between the source and drain. With longer turn-off times achieved by weakening signal drivers and adding capacitive loads, and with the MOS switch source capacitance (capacitance on reference voltage) much greater than the MOS switch drain capacitance, the voltage between source and drain of the MOS switch is equalized, resulting in most channel charge exiting the channel out of the source terminal.
- Thus, as will be appreciated, injection noise can be reduced by either: 1) reducing the amount of channel charge, 2) increasing the ratio of channel charge dumped between the source and drain by lowering the gate slew rate and increasing the source to drain node capacitance ratio, or 3) partially compensating the channel charges by using both N and P devices on the variable capacitor node.
- The latter method, however, tends to suffer from a drawback of essentially doubling the parasitic capacitance on the variable capacitor node. Reduction of this capacitance is essential for increasing the stable gap range before snapdown when operating the MEMS actuator in charge control mode. It should be noted that in a voltage control mode, a smaller stable gap range is available, but maximizing the capacitance can be beneficial.
- If injection charge (partition noise) can be reduced so that only one device is necessary, the use of both N & P compensating devices is not necessary and the drain capacitance can be reduced by about half.
- Although not shown, the injection control circuit embodiments of the invention can be applied to controlling a micro-electromechanical system (MEMS) which combine mechanical devices, such as mirrors and actuators, with electronic control circuitry for controlling the mechanical devices. Merely by way of example, one such MEMS arrangement can comprise a diffractive light device (DLD), wherein the variable capacitor is composed of a fixed reflective ground plate and a semi-transparent, (electrostatically) movable second plate. The variable gap between the plates is used to produce interference or diffraction of light passing thereinto, and can be used for spatial light modulation in high resolution displays and for wavelength management in optical communication systems. By controlling the gap between the fixed and movable plates of the variable capacitor shown in
FIG. 1 , and thus using the variable capacitor as a linear acting motor, it is possible that the above mentioned interference/diffraction can be controlled. - The precision of this control is enabled by the injection control circuits which are disclosed in connection with the embodiments of the invention.
- As will be appreciated, the invention has been disclosed with reference to only a limited number of embodiments, however, the various changes and modifications which can be made without departing from the scope of the invention which is limited only by the appended claims, will be self-evident to those skilled in the art of or circuit design or that which closely pertains thereto.
- For example, while the above disclosure refers to slowing down the lever shifter, it is within the scope of the present invention to slow down at least one of the row and column drivers. That is to say, the technique used in the above example of the level shifter can be applied to other types of row and column drivers such as CMOS inverters and the like.
Claims (20)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/855,359 US6970031B1 (en) | 2004-05-28 | 2004-05-28 | Method and apparatus for reducing charge injection in control of MEMS electrostatic actuator array |
EP05009243A EP1603105A3 (en) | 2004-05-28 | 2005-04-27 | Method and apparatus for reducing charge injection in control of MEMS electrostatic actuator array |
CNA2005100760602A CN1722598A (en) | 2004-05-28 | 2005-05-27 | Method and apparatus for reducing charge injection in control of mems electrostatic actuator array |
JP2005156819A JP2006043870A (en) | 2004-05-28 | 2005-05-30 | Method and device for reducing charge injection in controlling mems electrostatic actuator array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/855,359 US6970031B1 (en) | 2004-05-28 | 2004-05-28 | Method and apparatus for reducing charge injection in control of MEMS electrostatic actuator array |
Publications (2)
Publication Number | Publication Date |
---|---|
US6970031B1 US6970031B1 (en) | 2005-11-29 |
US20050264340A1 true US20050264340A1 (en) | 2005-12-01 |
Family
ID=35058232
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/855,359 Expired - Fee Related US6970031B1 (en) | 2004-05-28 | 2004-05-28 | Method and apparatus for reducing charge injection in control of MEMS electrostatic actuator array |
Country Status (4)
Country | Link |
---|---|
US (1) | US6970031B1 (en) |
EP (1) | EP1603105A3 (en) |
JP (1) | JP2006043870A (en) |
CN (1) | CN1722598A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070146376A1 (en) * | 1999-10-05 | 2007-06-28 | Idc, Llc. | Systems and methods of controlling micro-electromechanical devices |
US20110261046A1 (en) * | 2010-04-22 | 2011-10-27 | Qualcomm Mems Technologies, Inc. | System and method for pixel-level voltage boosting |
CN104301839A (en) * | 2013-07-18 | 2015-01-21 | 英飞凌科技股份有限公司 | MEMS Devices, interface circuits, and methods of making thereof |
US9048120B2 (en) | 2012-11-26 | 2015-06-02 | Samsung Electronics Co., Ltd. | Integrated junction and junctionless nanotransistors |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100703140B1 (en) | 1998-04-08 | 2007-04-05 | 이리다임 디스플레이 코포레이션 | Interferometric modulation and its manufacturing method |
US8928967B2 (en) | 1998-04-08 | 2015-01-06 | Qualcomm Mems Technologies, Inc. | Method and device for modulating light |
TWI289708B (en) | 2002-12-25 | 2007-11-11 | Qualcomm Mems Technologies Inc | Optical interference type color display |
US7342705B2 (en) | 2004-02-03 | 2008-03-11 | Idc, Llc | Spatial light modulator with integrated optical compensation structure |
US7855824B2 (en) | 2004-03-06 | 2010-12-21 | Qualcomm Mems Technologies, Inc. | Method and system for color optimization in a display |
US7436389B2 (en) * | 2004-07-29 | 2008-10-14 | Eugene J Mar | Method and system for controlling the output of a diffractive light device |
US7710636B2 (en) * | 2004-09-27 | 2010-05-04 | Qualcomm Mems Technologies, Inc. | Systems and methods using interferometric optical modulators and diffusers |
US7813026B2 (en) | 2004-09-27 | 2010-10-12 | Qualcomm Mems Technologies, Inc. | System and method of reducing color shift in a display |
US8004504B2 (en) | 2004-09-27 | 2011-08-23 | Qualcomm Mems Technologies, Inc. | Reduced capacitance display element |
US7630123B2 (en) | 2004-09-27 | 2009-12-08 | Qualcomm Mems Technologies, Inc. | Method and device for compensating for color shift as a function of angle of view |
US7508571B2 (en) | 2004-09-27 | 2009-03-24 | Idc, Llc | Optical films for controlling angular characteristics of displays |
US7203111B2 (en) * | 2005-02-08 | 2007-04-10 | Hewlett-Packard Development Company, L.P. | Method and apparatus for driver circuit in a MEMS device |
US7916980B2 (en) | 2006-01-13 | 2011-03-29 | Qualcomm Mems Technologies, Inc. | Interconnect structure for MEMS device |
US7529017B1 (en) | 2006-05-25 | 2009-05-05 | Silicon Light Machines Corporation | Circuit and method for snapdown prevention in voltage controlled MEMS devices |
EP2366945A1 (en) | 2006-10-06 | 2011-09-21 | Qualcomm Mems Technologies, Inc. | Optical loss layer integrated in an illumination apparatus of a display |
US8872085B2 (en) | 2006-10-06 | 2014-10-28 | Qualcomm Mems Technologies, Inc. | Display device having front illuminator with turning features |
WO2008045463A2 (en) | 2006-10-10 | 2008-04-17 | Qualcomm Mems Technologies, Inc. | Display device with diffractive optics |
US7864395B2 (en) | 2006-10-27 | 2011-01-04 | Qualcomm Mems Technologies, Inc. | Light guide including optical scattering elements and a method of manufacture |
US7777954B2 (en) | 2007-01-30 | 2010-08-17 | Qualcomm Mems Technologies, Inc. | Systems and methods of providing a light guiding layer |
US8072402B2 (en) | 2007-08-29 | 2011-12-06 | Qualcomm Mems Technologies, Inc. | Interferometric optical modulator with broadband reflection characteristics |
US8068710B2 (en) | 2007-12-07 | 2011-11-29 | Qualcomm Mems Technologies, Inc. | Decoupled holographic film and diffuser |
WO2009102733A2 (en) | 2008-02-12 | 2009-08-20 | Qualcomm Mems Technologies, Inc. | Integrated front light diffuser for reflective displays |
US8237488B2 (en) | 2010-05-06 | 2012-08-07 | Aeroflex Colorado Springs Inc. | Continuous-time circuit and method for capacitance equalization based on electrically tunable voltage pre-distortion of a C-V characteristic |
US8203374B2 (en) | 2010-05-06 | 2012-06-19 | Aeroflex Colorado Springs Inc. | Electrically tunable continuous-time circuit and method for compensating a polynomial voltage-dependent characteristic of capacitance |
US8670171B2 (en) | 2010-10-18 | 2014-03-11 | Qualcomm Mems Technologies, Inc. | Display having an embedded microlens array |
US8902484B2 (en) | 2010-12-15 | 2014-12-02 | Qualcomm Mems Technologies, Inc. | Holographic brightness enhancement film |
US20150070747A1 (en) * | 2013-09-09 | 2015-03-12 | Qualcomm Mems Technologies, Inc. | Display element reset using polarity reversal |
GB2531552B (en) * | 2014-10-21 | 2017-12-27 | Polatis Ltd | Crosstalk reduction technique for multi-channel driver circuits |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4670861A (en) * | 1985-06-21 | 1987-06-02 | Advanced Micro Devices, Inc. | CMOS N-well bias generator and gating system |
US5479121A (en) * | 1995-02-27 | 1995-12-26 | Industrial Technology Research Institute | Compensating circuit for MOSFET analog switches |
US5650744A (en) * | 1996-02-20 | 1997-07-22 | Vlsi Technology, Inc. | Charge neutralizing system for circuits having charge injection problems and method therefor |
US5739720A (en) * | 1995-05-23 | 1998-04-14 | Analog Devices, Inc. | Switched capacitor offset suppression |
US6075400A (en) * | 1998-08-13 | 2000-06-13 | Pericom Semiconductor Corp. | Cancellation of injected charge in a bus switch |
US6320394B1 (en) * | 1996-02-14 | 2001-11-20 | Stmicroelectronics S.R.L. | Capacitive distance sensor |
US6342700B1 (en) * | 1998-04-27 | 2002-01-29 | Sharp Kabushiki Kaisha | Two-dimensional image detector |
US6437583B1 (en) * | 1996-02-14 | 2002-08-20 | Stmicroelectronics, Inc.. | Capacitive distance sensor |
US6522187B1 (en) * | 2001-03-12 | 2003-02-18 | Linear Technology Corporation | CMOS switch with linearized gate capacitance |
US6535051B2 (en) * | 2000-06-09 | 2003-03-18 | Samsung Electronics Co., Ltd. | Charge pump circuit |
US6635857B1 (en) * | 2000-07-10 | 2003-10-21 | National Semiconductor Corporation | Method and apparatus for a pixel cell architecture having high sensitivity, low lag and electronic shutter |
US6781434B2 (en) * | 2000-12-28 | 2004-08-24 | Intel Corporation | Low charge-dump transistor switch |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5636052A (en) * | 1994-07-29 | 1997-06-03 | Lucent Technologies Inc. | Direct view display based on a micromechanical modulation |
JP2001272654A (en) | 2000-03-28 | 2001-10-05 | Sanyo Electric Co Ltd | Active matrix type liquid crystal display device |
US20030189448A1 (en) * | 2002-04-08 | 2003-10-09 | Silicon Video, Inc. | MOSFET inverter with controlled slopes and a method of making |
US6741384B1 (en) | 2003-04-30 | 2004-05-25 | Hewlett-Packard Development Company, L.P. | Control of MEMS and light modulator arrays |
-
2004
- 2004-05-28 US US10/855,359 patent/US6970031B1/en not_active Expired - Fee Related
-
2005
- 2005-04-27 EP EP05009243A patent/EP1603105A3/en not_active Ceased
- 2005-05-27 CN CNA2005100760602A patent/CN1722598A/en active Pending
- 2005-05-30 JP JP2005156819A patent/JP2006043870A/en active Pending
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4670861A (en) * | 1985-06-21 | 1987-06-02 | Advanced Micro Devices, Inc. | CMOS N-well bias generator and gating system |
US5479121A (en) * | 1995-02-27 | 1995-12-26 | Industrial Technology Research Institute | Compensating circuit for MOSFET analog switches |
US5739720A (en) * | 1995-05-23 | 1998-04-14 | Analog Devices, Inc. | Switched capacitor offset suppression |
US6320394B1 (en) * | 1996-02-14 | 2001-11-20 | Stmicroelectronics S.R.L. | Capacitive distance sensor |
US6437583B1 (en) * | 1996-02-14 | 2002-08-20 | Stmicroelectronics, Inc.. | Capacitive distance sensor |
US5650744A (en) * | 1996-02-20 | 1997-07-22 | Vlsi Technology, Inc. | Charge neutralizing system for circuits having charge injection problems and method therefor |
US6342700B1 (en) * | 1998-04-27 | 2002-01-29 | Sharp Kabushiki Kaisha | Two-dimensional image detector |
US6075400A (en) * | 1998-08-13 | 2000-06-13 | Pericom Semiconductor Corp. | Cancellation of injected charge in a bus switch |
US6535051B2 (en) * | 2000-06-09 | 2003-03-18 | Samsung Electronics Co., Ltd. | Charge pump circuit |
US6635857B1 (en) * | 2000-07-10 | 2003-10-21 | National Semiconductor Corporation | Method and apparatus for a pixel cell architecture having high sensitivity, low lag and electronic shutter |
US6781434B2 (en) * | 2000-12-28 | 2004-08-24 | Intel Corporation | Low charge-dump transistor switch |
US6522187B1 (en) * | 2001-03-12 | 2003-02-18 | Linear Technology Corporation | CMOS switch with linearized gate capacitance |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070146376A1 (en) * | 1999-10-05 | 2007-06-28 | Idc, Llc. | Systems and methods of controlling micro-electromechanical devices |
US7355782B2 (en) | 1999-10-05 | 2008-04-08 | Idc, Llc | Systems and methods of controlling micro-electromechanical devices |
US20110261046A1 (en) * | 2010-04-22 | 2011-10-27 | Qualcomm Mems Technologies, Inc. | System and method for pixel-level voltage boosting |
US9048120B2 (en) | 2012-11-26 | 2015-06-02 | Samsung Electronics Co., Ltd. | Integrated junction and junctionless nanotransistors |
US9171845B2 (en) | 2012-11-26 | 2015-10-27 | Samsung Electronics Co., Ltd. | Integrated junction and junctionless nanotransistors |
CN104301839A (en) * | 2013-07-18 | 2015-01-21 | 英飞凌科技股份有限公司 | MEMS Devices, interface circuits, and methods of making thereof |
Also Published As
Publication number | Publication date |
---|---|
CN1722598A (en) | 2006-01-18 |
EP1603105A3 (en) | 2008-01-23 |
JP2006043870A (en) | 2006-02-16 |
US6970031B1 (en) | 2005-11-29 |
EP1603105A2 (en) | 2005-12-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6970031B1 (en) | Method and apparatus for reducing charge injection in control of MEMS electrostatic actuator array | |
KR100297140B1 (en) | A liquid crystal display driving circuit with low power consumption and precise voltage output | |
KR100478268B1 (en) | Display device having an improved voltage level converter | |
KR100616337B1 (en) | Voltage detecting circuit and internal voltage generating circuit comprising it | |
KR20070078782A (en) | Output circuit and disply device using the same | |
JPH07154221A (en) | Delay circuit | |
CN104049663A (en) | Charge injection type switched capacitor voltage stabilizer applied to high load current | |
JP2573320B2 (en) | Output buffer circuit | |
US20190296704A1 (en) | Operational amplifier circuit and current detection device using the same | |
US10819352B2 (en) | Output circuit and method for providing an output current | |
US6903671B2 (en) | Digital-to-analog converter with low skew and glitch | |
US8461743B2 (en) | Electrostatic actuator apparatus and method of driving the same | |
US8934309B2 (en) | Semiconductor integrated circuit and semiconductor physical quantity sensor device | |
JP4676507B2 (en) | Load capacity drive circuit | |
KR101433862B1 (en) | Driving Circuit of Liquid Crystal Display Device and Driving Device | |
KR19990014027A (en) | Medium Potential Generation Circuit | |
KR100523649B1 (en) | Differential amplifier | |
US8786162B2 (en) | Device for driving a piezoelectric element | |
CN112289270B (en) | Source electrode driving circuit, display device and pixel driving method | |
US7466601B2 (en) | Output driver | |
KR20230021895A (en) | Error compensation circuit for analog capacitor memory circuits | |
KR100298912B1 (en) | Semiconductor device having device supplying voltage higher than power supply voltage | |
US7859490B2 (en) | Current drive device | |
KR100317101B1 (en) | Semiconductor circuit with circuitry that supplies voltage higher than the supply voltage | |
KR100266638B1 (en) | Power on reset circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MARTIN, ERIC;PIEHL, ART;GHOZEIL, ADAM;REEL/FRAME:014728/0438;SIGNING DATES FROM 20040513 TO 20040517 |
|
AS | Assignment |
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., TEXAS Free format text: CORRECT 1ST INVENTORS NAME (ADD MIDDLE INITIAL);ASSIGNORS:MARTIN, ERIC T.;PIEHL, ART;GHOZEIL, ADAM;REEL/FRAME:016293/0519;SIGNING DATES FROM 20040513 TO 20040517 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.) |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20171129 |