US20050282361A1 - Semiconductor wafer and manufacturing process thereof - Google Patents
Semiconductor wafer and manufacturing process thereof Download PDFInfo
- Publication number
- US20050282361A1 US20050282361A1 US11/167,967 US16796705A US2005282361A1 US 20050282361 A1 US20050282361 A1 US 20050282361A1 US 16796705 A US16796705 A US 16796705A US 2005282361 A1 US2005282361 A1 US 2005282361A1
- Authority
- US
- United States
- Prior art keywords
- die
- terminal pad
- wafer body
- scribe line
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Abstract
A semiconductor wafer includes a wafer body, a plurality of analog IC dies spacedly and alignedly formed on the wafer body to define a scribe line as a margin formed between each two dies wherein each of the dies has an internal circuit formed therewithin and at least a terminal pad formed along the scribe line, and a conductive arrangement including at least a conductive element formed on the wafer body to electrically connect the terminal pad with the internal circuit of the die in such a manner that when the die is cut off from the wafer body along the scribe line, the terminal pad is cut off from the die so as to keep the internal circuit in the die.
Description
- This is a divisional application of a non-provisional application, application Ser. No. 10/841,035 filed on May 6, 2004.
- 1. Field of Invention
- The present invention relates to semiconductor, and more particularly to a semiconductor wafer and its manufacturing process thereof, wherein the terminal pad is disposed along a scribe line of a semiconductor wafer to enlarge the usage area of the analog IC die.
- 2. Description of Related Arts
- A conventional semiconductor wafer comprises a wafer body and a plurality of dies spacedly formed on the wafer body to define a scribe line as a margin between each two dies. Accordingly, each of the dies, which is also called as an analog IC chip, is an integrated circuit consisting of silicon based substrate.
- Before each of the dies is cut into an individual component, a wafer test must be performed to ensure each of the dies is functioning in an optimum condition. Generally, each of the dies comprises a plurality of bond pads and a plurality of terminal pads spacedly formed within the die, wherein the terminal pads can be test pads for measuring the voltage of the die via a measuring tool, such as probe card, or trim pads for trimming the reference voltage of the die and the reference function thereof.
- Accordingly, there are two trimming methods, which are laser cut and electrical test, are commonly used for trimming the dies. The laser cut is performed to trim the trim fuse such that the properties of dies are corresponding changed once the trim fuse is cut. However, the operation of the laser cut is costly and complicated so as to highly increase the manufacturing cost of the die. In addition, during the operation of the laser cut, the voltage of each of the dies cannot be predicted so that the quality of each of the dies cannot be standardized.
- Another trimming method is preformed by electrical trim, wherein an electric current is applied on each of the dies to trim the trim fuse. Since the electrical current can be selectively controlled, the trim fuses can be selectively removed from the dies so as to generate the reference voltage of the die and the reference function thereof.
- Furthermore, the conventional semiconductor wafer has several drawbacks. Since the terminal pads are disposed within each of the dies, the size of the die must be big enough to hold the bond pads, the terminal pads, and the trim fuses in position. Therefore, the limited size of each of the dies can only hold up to a certain number of pads thereon. In other words, the complicated integrated circuits are limited on the size of each of the dies so as to highly increase the manufacturing cost of the semiconductor wafer.
- In addition, when the dies are cut off from the semiconductor wafer, the terminal pads are stayed on each of the dies. It is worth to mention that the terminal pads are only used for measuring the voltage of the corresponding die or programming the trim fuse. The terminal pads are useless after the measurement. Therefore, the terminal pads will used up the limited space of each of the dies.
- A main object of the present invention is to provide a semiconductor wafer, wherein the terminal pad are disposed along a scribe line of a semiconductor wafer to electrically connect with the die, so as to enlarge the usage area of the die.
- Another object of the present invention is to provide a semiconductor wafer, wherein a conductive arrangement is extended from the scribe line to the die for electrically connecting the terminal pad with the die, such that when the die is cut off from the wafer body, the terminal pad is removed from the die by simply cutting off the conductive arrangement along the scribe line.
- Another object of the present invention is to provide a semiconductor wafer, wherein the terminal pad is formed as a comb shape to minimize the residue is stayed at the cutting tip of the cutting tool when a cutting tool cuts off the die along the scribe line, so as to enhance the cutting operation of the die.
- Another object of the present invention is to provide a semiconductor wafer, wherein since the terminal pad is moved from the die to the scribe line of the wafer body, the usage area of the die is enlarged such that more integrated circuits can be added into the die for enhancing the function of the die.
- Another object of the present invention is to provide a semiconductor wafer, wherein no substantial structural design of the die is altered such that the semiconductor wafer can be tested by any existing trimming test, so as to minimize the manufacturing cost of the present invention.
- Another object of the present invention is to provide a trim fuse semiconductor wafer, wherein the manufacturing process thereof is as simple as repositioning the terminal pad from the die to dispose along the scribe line of the wafer and electrically connecting the terminal pad with the die via the conductive arrangement. Therefore, no extra component is required in the present invention so as to further lower the manufacturing cost of the present invention.
- Accordingly, in order to accomplish the above objects, the present invention provides a semiconductor wafer, comprising:
-
- a wafer body;
- a plurality of analog IC dies spacedly and alignedly formed on the wafer body to define a scribe line as a margin formed between each two dies, wherein each of the dies has an internal circuit formed therewithin and at least a terminal pad formed along the scribe line; and
- a conductive arrangement, comprising at least a conductive element formed on the wafer body to electrically connect the terminal pad with the internal circuit of the die in such a manner that when the die is cut off from the wafer body along the scribe line, the terminal pad is cut off from the die so as to keep the internal circuit in the die.
- These and other objectives, features, and advantages of the present invention will become apparent from the following detailed description, the accompanying drawings, and the appended claims.
-
FIG. 1 is a front view of the semiconductor wafer according to the above preferred embodiment of the present invention, illustrating the analogy IC die electrically connected with a terminal pad. -
FIG. 2 is a perspective view of an analog IC die electrically connected with a terminal pad on the semiconductor wafer according to the above preferred embodiment of the present invention. -
FIG. 3 is a sectional perspective view of the analog IC die electrically connected with a terminal pad on the semiconductor wafer according to the above preferred embodiment of the present invention. - Referring to
FIGS. 1 and 2 of the drawings, a semiconductor wafer according to a preferred embodiment of the present invention is illustrated, wherein the semiconductor wafer comprises awafer body 10, and a plurality of analog IC dies 20 spacedly and alignedly formed on thewafer body 10 to define ascribe line 11 as a margin formed between each twodies 20, wherein each of thedies 20 has aninternal circuit 21 formed therewithin and at least aterminal pad 22 formed along thescribe line 11. - The semiconductor wafer further comprises a
conductive arrangement 30 which comprises at least aconductive element 31 formed on thewafer body 10 to electrically connect theterminal pad 22 with theinternal circuit 21 of thedie 20 in such a manner that when thedie 20 is cut off from thewafer body 10 along thescribe line 11, theterminal pad 22 is cut off from thedie 20 so as to keep theinternal circuit 21 in thedie 20. - The present invention further provides a process of manufacturing the semiconductor wafer which comprises the following steps:
-
- (1) Spacedly and alignedly form the analog IC dies 20 on the
wafer body 10 to define thescribe line 11 as a margin formed between each twodies 20.
- (1) Spacedly and alignedly form the analog IC dies 20 on the
- (2) Align the
terminal pad 22 on thescribe line 11 of thewafer body 10 adjacent to therespective die 20. - (3) Form the
conductive element 31 on thewafer body 10 to electrically connect theterminal pad 22 with theinternal circuit 21 of thedie 20. - (4) Cut off the die 20 from the
wafer body 10 along thescribe line 11 thereof such that theterminal pad 22 is removed from the die 20 so as to keep theinternal circuit 21 within the die 20. - According to the preferred embodiment, each of the
dies 20 is an analog IC that provides an accurate performance. Therefore, the voltage measurement of the each of thedies 20 must be precise. Likewise, each of thedies 20 is trimmed to program the die 20 so as to generate a reference voltage and a reference function. - Each of the
dies 20 is constructed by a plurality of integrated circuits electrically connected with each other to form theinternal circuit 21 wherein theterminal pad 22 is electrically connected with theinternal circuit 21 of therespective die 20 via theconductive element 31. - The
terminal pad 22 is embodied as a trim pad electrically extended from of theintegrated circuit 21 of the die 20. Accordingly, each of thedies 20 further has atrim fuse 23 electrically extended from theterminal pad 22 such that therespective die 20 is adapted to be trimmed to generate the reference voltage and the reference function of thedie 20. Alternatively, theterminal pad 22 can be a test pad for electrically coupling with the measuring tool to measure the voltage of thedie 20. - As shown in
FIG. 3 , theterminal pad 22, having as a comb shaped, defines a plurality ofterminal teeth 221 spacedly formed on thescribe line 11 of thewafer body 10, wherein theconductive element 31 is extended from thescribe line 11 of thewafer body 10 to thedie 20 so as to electrically connect theterminal teeth 221 of theterminal pad 22 with theinternal circuit 21 of thedie 20. - In addition, steps (1), (2), and (3) are preformed at the same time such that the analog IC dies 20, the
terminal pad 22, and theconductive element 31 are spacedly formed on thewafer body 10. - It is worth to mention that in order to cut off the
die 20 from thewafer body 10, a cutting tool, such as a diamond-head cutting device, is employed to cut along thescribe line 11 of thewafer body 10 so as to individually separate thedie 20 from thewafer body 10. However, when the cutting tip of the cutting tool slidably cuts along thescribe line 11 of thewafer body 10, residue of theterminal pad 22 will stay at the cutting tip of the cutting tool which has the serrated edge shape. Therefore, in order to prevent the residue of theterminal pad 22 stayed at the cutting tip of the cutting tool, theterminal pad 22 is formed as a comb shape that the spaced apartterminal teeth 221 of theterminal pad 22 are adapted to minimize the residue is stayed at the cutting tip of the cutting tool when the cutting tip thereof slidably cuts along theterminal teeth 221 of theterminal pad 22. - The
conductive element 31, which is preferably made of metal layer such as lead, is extended from thescribe line 11 of thewafer body 10 to thedie 20 so as to electrically connect theterminal pad 22 with theinternal circuit 21 of thedie 20. Alternatively, theconductive element 31 can be made of poly layer to electrically connect theterminal pad 22 with theinternal circuit 21 of thedie 20. - Accordingly, when the
terminal pad 22 is embodied as the trim pad, theconductive arrangement 30 further comprises a supplementconductive element 32 electrically extended from theconductive element 32 to thetrim fuse 23 such that thetrim fuse 23 is adapted to be trimmed by the trim pad of theterminal pad 22 through the supplementconductive element 32. After thedie 20 is trimmed, the trim pad of theterminal pad 22 is removed from thedie 20, as shown inFIG. 3 . - It is worth to mention that the
trim fuse 23 is disposed within the die 20 such that thetrim fuse 23 is remained in the die 20 after thedie 20 is cut off from thewafer body 10. In addition, a portion of theconductive element 31 on thescribe line 11 of thewafer body 10 is removed from the die 20 since thedie 20 is cut off from thewafer body 10 along thescribe line 11 thereof. - When the
terminal pad 22 is embodied as the test pad, notrim fuse 23 is needed in thedie 20, such that theconductive element 32 is extended from thescribe line 11 of thewafer body 10 to the die 20 so as to electrically connect the test pad of theterminal pad 22 with theinternal circuit 21 of thedie 20. Therefore, after measuring the voltage of the die 20, the test pad of theterminal pad 22 is removed from thedie 20. - Accordingly, since the
terminal pad 22 is disposed along thescribe line 11 of thewafer body 10, the usage area of the die 20 is substantially enlarged such that more integrated circuits can be added into thedie 20 for enhancing the function thereof in comparison with the conventional die that the terminal pad is provided within the die. Furthermore, theterminal pad 22 is used for testing thedie 20 when theterminal pad 22 is embodied as the test pad or for trimming the die 20 when theterminal pad 22 is embodied as the trim pad. Therefore, after trimming the die 20 or testing thedie 20, theterminal pad 22 does not perform any function for the die 20 such that theterminal pad 22 can be removed from the die 20 while only theinternal circuit 21 is kept within thedie 20 for operation. - One skilled in the art will understand that the embodiment of the present invention as shown in the drawings and described above is exemplary only and not intended to be limiting.
- It will thus be seen that the objects of the present invention have been fully and effectively accomplished. It embodiments have been shown and described for the purposes of illustrating the functional and structural principles of the present invention and is subject to change without departure from such principles. Therefore, this invention includes all modifications encompassed within the spirit and scope of the following claims.
Claims (12)
1. A process of manufacturing a semiconductor wafer, comprising the steps of:
(a) spacedly and alignedly forming a plurality of analog IC dies on a wafer body to define a scribe line as a margin formed between each two said dies, wherein each of said dies has an internal circuit formed therewithin and at least a terminal pad;
(b) aligning said terminal pad on said scribe line of said wafer body adjacent to said respective die;
(c) forming a conductive element on said wafer body to electrically connect said terminal pad with said internal circuit of said die; and
(d) cutting off said die from said wafer body along said scribe line thereof such that said terminal pad is removed from said die so as to keep said internal circuit within said die.
2. The process, as recited in claim 1 , wherein said terminal pad, having a comb shaped, defines a plurality of terminal teeth spacedly formed on said scribe line of said wafer body for preventing a residue of said terminal pad stayed at a cutting tip of a cutting tool when said die is cut off from said wafer body, wherein said conductive element is extended from said scribe line of said wafer body to said die so as to electrically connect said terminal teeth of said terminal pad with said internal circuit of said die.
3. The process, as recited in claim 1 , wherein said terminal pad is embodied as a trim pad formed on said scribe line of said wafer body, wherein each of said dies further has a trim fuse disposed therewithin to electrically connect with said trim pad of said terminal pad, such that said die is trimmed before said die is cut off from said wafer body.
4. The process, as recited in claim 2 , wherein said terminal pad is embodied as a trim pad formed on said scribe line of said wafer body, wherein each of said dies further has a trim fuse disposed therewithin to electrically connect with said trim pad of said terminal pad, such that said die is trimmed before said die is cut off from said wafer body.
5. The process, as recited in claim 1 , wherein said terminal pad is embodied as a test pad formed on said scribe line of said wafer body, wherein said conductive element is extended from said scribe line of said wafer body to said die so as to electrically connect said test pad of said terminal pad with said internal circuit of said die such that said die is tested before said die is cut off from said wafer body.
6. The process, as recited in claim 2 , wherein said terminal pad is embodied as a test pad formed on said scribe line of said wafer body, wherein said conductive element is extended from said scribe line of said wafer body to said die so as to electrically connect said test pad of said terminal pad with said internal circuit of said die such that said die is tested before said die is cut off from said wafer body.
7. A semiconductor wafer, as recited in claim 1 , wherein said conductive element is made of metal layer.
8. A semiconductor wafer, as recited in claim 2 , wherein said conductive element is made of metal layer.
9. A semiconductor wafer, as recited in claim 4 , wherein said conductive element is made of metal layer.
10. A semiconductor wafer, as recited in claim 1 , wherein said conductive element is made of poly layer.
11. A semiconductor wafer, as recited in claim 2 , wherein said conductive element is made of poly layer.
12. A semiconductor wafer, as recited in claim 4 , wherein said conductive element is made of poly layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/167,967 US20050282361A1 (en) | 2004-05-06 | 2005-06-27 | Semiconductor wafer and manufacturing process thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/841,035 US7075107B2 (en) | 2004-05-06 | 2004-05-06 | Semiconductor wafer and manufacturing process thereof |
US11/167,967 US20050282361A1 (en) | 2004-05-06 | 2005-06-27 | Semiconductor wafer and manufacturing process thereof |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/841,035 Division US7075107B2 (en) | 2004-05-06 | 2004-05-06 | Semiconductor wafer and manufacturing process thereof |
Publications (1)
Publication Number | Publication Date |
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US20050282361A1 true US20050282361A1 (en) | 2005-12-22 |
Family
ID=35238692
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US10/841,035 Expired - Fee Related US7075107B2 (en) | 2004-05-06 | 2004-05-06 | Semiconductor wafer and manufacturing process thereof |
US11/167,967 Abandoned US20050282361A1 (en) | 2004-05-06 | 2005-06-27 | Semiconductor wafer and manufacturing process thereof |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US10/841,035 Expired - Fee Related US7075107B2 (en) | 2004-05-06 | 2004-05-06 | Semiconductor wafer and manufacturing process thereof |
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US (2) | US7075107B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070275543A1 (en) * | 2006-03-30 | 2007-11-29 | Renesas Technology Corp. | Manufacturing method of a semiconductor device |
CN102299139A (en) * | 2010-06-24 | 2011-12-28 | 安森美半导体贸易公司 | Semiconductor integrated circuit |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4307664B2 (en) | 1999-12-03 | 2009-08-05 | 株式会社ルネサステクノロジ | Semiconductor device |
JP2007034275A (en) * | 2005-06-21 | 2007-02-08 | Canon Inc | Electronic component and manufacturing method thereof |
US7563694B2 (en) * | 2006-12-01 | 2009-07-21 | Atmel Corporation | Scribe based bond pads for integrated circuits |
US10847482B2 (en) | 2018-05-16 | 2020-11-24 | Micron Technology, Inc. | Integrated circuit structures and methods of forming an opening in a material |
US10651100B2 (en) | 2018-05-16 | 2020-05-12 | Micron Technology, Inc. | Substrates, structures within a scribe-line area of a substrate, and methods of forming a conductive line of a redistribution layer of a substrate and of forming a structure within a scribe-line area of the substrate |
Citations (8)
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US5206181A (en) * | 1991-06-03 | 1993-04-27 | Motorola, Inc. | Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing |
US5654582A (en) * | 1994-05-06 | 1997-08-05 | Texas Instruments Incorporated | Circuit wafer and TEG test pad electrode |
US5696803A (en) * | 1996-08-07 | 1997-12-09 | Motorola, Inc. | Barrel shifter and method of making same |
US5710538A (en) * | 1995-09-27 | 1998-01-20 | Micrel, Inc. | Circuit having trim pads formed in scribe channel |
US5981971A (en) * | 1997-03-14 | 1999-11-09 | Kabushiki Kaisha Toshiba | Semiconductor ROM wafer test structure, and IC card |
US6492666B2 (en) * | 2000-07-17 | 2002-12-10 | Mitsumi Electric Co., Ltd. | Semiconductor wafer with scribe lines having inspection pads formed thereon |
US20050239268A1 (en) * | 2004-04-22 | 2005-10-27 | Texas Instruments Incorporated | Integrated circuit with removable scribe street trim and test pads |
US7183623B2 (en) * | 2001-10-02 | 2007-02-27 | Agere Systems Inc. | Trimmed integrated circuits with fuse circuits |
-
2004
- 2004-05-06 US US10/841,035 patent/US7075107B2/en not_active Expired - Fee Related
-
2005
- 2005-06-27 US US11/167,967 patent/US20050282361A1/en not_active Abandoned
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5206181A (en) * | 1991-06-03 | 1993-04-27 | Motorola, Inc. | Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing |
US5654582A (en) * | 1994-05-06 | 1997-08-05 | Texas Instruments Incorporated | Circuit wafer and TEG test pad electrode |
US5710538A (en) * | 1995-09-27 | 1998-01-20 | Micrel, Inc. | Circuit having trim pads formed in scribe channel |
US5696803A (en) * | 1996-08-07 | 1997-12-09 | Motorola, Inc. | Barrel shifter and method of making same |
US5981971A (en) * | 1997-03-14 | 1999-11-09 | Kabushiki Kaisha Toshiba | Semiconductor ROM wafer test structure, and IC card |
US6492666B2 (en) * | 2000-07-17 | 2002-12-10 | Mitsumi Electric Co., Ltd. | Semiconductor wafer with scribe lines having inspection pads formed thereon |
US7183623B2 (en) * | 2001-10-02 | 2007-02-27 | Agere Systems Inc. | Trimmed integrated circuits with fuse circuits |
US20050239268A1 (en) * | 2004-04-22 | 2005-10-27 | Texas Instruments Incorporated | Integrated circuit with removable scribe street trim and test pads |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070275543A1 (en) * | 2006-03-30 | 2007-11-29 | Renesas Technology Corp. | Manufacturing method of a semiconductor device |
CN102299139A (en) * | 2010-06-24 | 2011-12-28 | 安森美半导体贸易公司 | Semiconductor integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
US7075107B2 (en) | 2006-07-11 |
US20050248000A1 (en) | 2005-11-10 |
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Legal Events
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AS | Assignment |
Owner name: ADVANCED ANALOG TECHNOLOGY, INC., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, WEI-JUNG;CHANG, YUNG-CHING;HUANG, JAW-SHIN;AND OTHERS;REEL/FRAME:016734/0629 Effective date: 20050606 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |