US20060010339A1 - Memory system and method having selective ECC during low power refresh - Google Patents
Memory system and method having selective ECC during low power refresh Download PDFInfo
- Publication number
- US20060010339A1 US20060010339A1 US10/876,796 US87679604A US2006010339A1 US 20060010339 A1 US20060010339 A1 US 20060010339A1 US 87679604 A US87679604 A US 87679604A US 2006010339 A1 US2006010339 A1 US 2006010339A1
- Authority
- US
- United States
- Prior art keywords
- data
- dram
- ecc
- syndromes
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
- G06F11/1052—Bypassing or disabling error detection or correction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/004—Error avoidance
Definitions
- This invention relates to dynamic random access memory (“DRAM”) devices and systems, and, more particularly, to a method and system for allowing DRAM cells to be refreshed at a relatively low rate to reduce power consumption.
- DRAM dynamic random access memory
- DRAM dynamic random access memory
- DRAM devices The power consumed by DRAM devices is also affected by their operating mode.
- a DRAM device for example, will generally consume a relatively large amount of power when the DRAM cells are being refreshed.
- DRAM cells each of which essentially consists of a capacitor, must be periodically refreshed to retain data stored in the DRAM device. Refresh is typically performed by essentially reading data bits from the memory cells in each row of a memory cell array and then writing those same data bits back to the same cells in the row.
- a relatively large amount of power is consumed when refreshing a DRAM because rows of memory cells in a memory cell array are being actuated in the rapid sequence.
- Refresh power can, of course, be reduced by reducing the rate at which the memory cells in a DRAM are being refreshed.
- reducing the refresh rate increases the risk of data stored in the DRAM cells being lost.
- DRAM cells are essentially capacitors, charge inherently leaks from the memory cell capacitors, which can change the value of a data bit stored in the memory cell over time.
- current leaks from capacitors at varying rates Some capacitors are essentially short-circuited and are thus incapable of storing charge indicative of a data bit. These defective memory cells can be detected during production testing, and can then be repaired by substituting non-defective memory cells using conventional redundancy circuitry.
- a DRAM refresh rate is chosen to ensure that all but a few memory cells can store data bits without data loss. This refresh rate is typically once every 64 ms. The memory cells that cannot reliably retain data bits at this refresh rate are detected during production testing and replaced by redundant memory cells.
- the rate of current leakage from DRAM cells can change after production testing, both as a matter of time and from subsequent production steps, such as in packaging DRAM chips. Current leakage, and hence the rate of data loss, can also be effected by environmental factors, such as the temperature of DRAM devices. Therefore, despite production testing, a few memory cells will typically be unable to retain stored data bits at normal refresh rates.
- ECC error correcting code
- ECC techniques during refresh could substantially reduce power consumption during refresh, it could impose significant cost penalties in both the cost and the performance of DRAM devices.
- the development cost and manufacturing cost of a DRAM device or a memory controller would be increased by the cost to develop and manufacture the additional circuitry needed to perform the ECC function.
- the increase in manufacturing cost for additional features in DRAM devices is normally manifested in a larger semiconductor die size, which reduces the yield from each semiconductor wafer.
- the performance of DRAM devices would be impaired by reduced operating speeds resulting from the need to check and possibly correct all data read from the DRAM devices as well as the need to create syndromes for all data written to the DRAM devices.
- a method and system for refreshing memory cells in a dynamic random access memory (“DRAM”) device is coupled to a processor in a computer system.
- the memory cells in the DRAM are refreshed at a reduced power rate that is sufficiently slow that data retention errors can be expected to occur during refresh.
- the expected data retention errors are corrected using ECC techniques applied only to memory cells containing essential data that should be protected from data retention errors. More specifically, prior to refreshing the memory cells at the reduced power rate, a determination is made, preferably by the processor, which memory cells are storing the essential data. ECC techniques are then used to check and correct the essential data without using ECC techniques to check and correct data stored in other memory cells.
- the essential data Prior to refreshing the memory cells at the reduced power rate, the essential data are read, and corresponding syndromes are generated and stored. When departing from the low power refresh rate, the essential data are again read, and the stored syndromes are used to check the read data for errors. If any errors are found, the syndromes are used to correct the data, and the corrected data are written to the DRAM.
- FIG. 1 is a block diagram of a computer system according to one embodiment of the invention.
- FIG. 2 is a block diagram of a computer system according to another embodiment of the invention.
- FIG. 3 is a block diagram of a DRAM device according to one embodiment of the invention.
- FIG. 4 is a schematic diagram illustrating the data structure of control data that may be stored in a control register in the DRAM of FIG. 3 .
- FIG. 5 is a block diagram of a portion of column interface circuitry used in the DRAM of FIG. 3 .
- FIG. 6 is a flow chart showing the operation of the DRAM of FIG. 3 when entering a low power refresh mode using ECC techniques to correct data retention errors for essential data.
- FIG. 7 is a flow chart showing the operation of the DRAM of FIG. 3 when exiting the low power refresh mode.
- FIG. 1 A computer system 10 according to one embodiment of the invention is shown in FIG. 1 .
- the computer system 10 includes a central processor unit (“CPU”) 14 coupled to a system controller 16 through a processor bus 18 .
- the system controller 16 is coupled to input/output (“I/O”) devices (not shown) through a peripheral bus 20 and to an I/0 controller 24 through an expansion bus 26 .
- the I/O controller 24 is also connected to various peripheral devices (not shown) through another I/0 bus 28 .
- the system controller 16 includes a memory controller 30 that is coupled to several dynamic random access memory (“DRAM”) device 32 a - c through an address bus 36 , a control bus 38 , and a data bus 42 .
- DRAM dynamic random access memory
- the locations in each of the DRAMs 32 a - c to which data are written and data are read are designated by addresses coupled to the DRAMs 32 a - c on the address bus 36 .
- the operation of the DRAMs 32 a - c are controlled by control signals coupled to the DRAMs 32 a - c on the control bus 38 .
- the memory controller 30 may be coupled to one or more memory modules (not shown) through the address bus 36 , the control bus 38 , and the data bus 42 .
- Each of the memory modules would normally contain several of the DRAMs 32 .
- the DRAMs 32 a - c each include a syndrome memory 50 , a memory array 52 and ECC logic 54 .
- the ECC logic 54 generates a syndrome from write data received from the memory controller 30 , and stores the syndrome in the syndrome memory 40 while the write data are being stored in the memory array 52 of the DRAM 32 .
- the read data are coupled from memory array 52 to the ECC logic 54 and the syndrome are coupled from the syndrome memory 40 to the ECC logic 54 .
- the ECC logic 54 uses the syndrome to determine if the read data contains an erroneous data bit, and, if more than one data bit is not in error, to correct the erroneous data bit.
- the corrected read data are then coupled to the memory controller 30 through the data bus 42 .
- the syndrome memory 50 may be a separate memory array in the DRAM 32 as shown in FIG. 1 , it may alternatively be included in the same array of DRAM cells that are used to store data, as explained in greater detail below.
- ECC allows the refresh rate of the memory cells in the memory array 52 to be reduced to a rate at which some data retention errors can occur since such errors can be corrected using the syndromes stored in the syndrome memory 50 and the ECC logic 52 .
- the DRAM 32 is able to use ECC techniques with relatively little of the costs and performance impairments associated with conventional ECC techniques because the CPU 14 uses ECC techniques to check and correct only the data stored in the memory array 52 that needs to be correct.
- conventional computer systems and other electronic systems use DRAM devices to store a variety of data types.
- a DRAM device may be used as a “scratch pad” memory or to store audio data or video data that is being coupled to a display. This type of data is usually overwritten with new data quite frequently, and is therefore generally not used after an extended refresh. Other data, such as program instructions, spreadsheet data, word processing documents, must be protected during refresh. Therefore, the CPU 14 applies ECC techniques to this type of data.
- the CPU 14 can determine which data to protect through a variety of means. For example, the CPU 14 can store essential data that needs to be protected in only certain regions of the memory array 52 , and then apply ECC techniques to these regions. The CPU 14 can also keep track of where in the memory array 52 essential data are stored, and then apply ECC techniques to these regions. Other techniques may also be used.
- the DRAMs 32 a - c perform a read and syndrome generating operation prior to each of the DRAMs 32 a - c entering a low power refresh mode. More specifically, the CPU 14 enables the ECC logic 54 by suitable means, such as by coupling a command signal to the DRAMs 32 a - c through the memory controller 30 and control bus 38 that enables a control register in the DRAM 32 . However, the CPU may enable the ECC logic 54 by other means, such as by coupling control signals directly to the ECC logic 54 , by coupling an unsupported command to the DRAM 32 , use of a specific sequence of operations, or by other means.
- suitable means such as by coupling a command signal to the DRAMs 32 a - c through the memory controller 30 and control bus 38 that enables a control register in the DRAM 32 .
- the CPU may enable the ECC logic 54 by other means, such as by coupling control signals directly to the ECC logic 54 , by coupling an unsupported command to the DRAM 32
- the CPU 14 performs a read operation to the regions of the memory array 52 that store essential data that needs to be protected.
- the read operation is preferably performed in a burst read mode to minimize the time required for the read operation. Regions of the memory array 52 that store non-essential data, such as regions used as image buffers, temporary buffers and screen buffers, are not read.
- the DRAM 32 generates syndromes from the read data, and stores the syndromes in the syndrome memory 50 .
- the DRAM 32 then enters a low power refresh mode in which the memory cells in the array 52 are refreshed at a rate that is sufficiently low that data retention errors may occur.
- the CPU 14 leaves the ECC logic 54 enabled during the low power refresh mode to correct any data retention errors as they occur. In another embodiment of the invention, the CPU 14 disables the ECC logic 54 after all of the syndromes have been stored and before entering the low power refresh mode. In this embodiment, the CPU 14 corrects any data retention errors that have occurred when exiting the low power refresh mode, as explained in greater detail below.
- the DRAMs 32 a - c When exiting the low power refresh mode, the DRAMs 32 a - c perform a read and correct operation. More specifically, the CPU 14 enables the ECC logic 54 if it was not enabled during the refresh mode. The CPU 14 then reads data from the protected regions of the memory array 52 , again preferably using a burst read mode. During these read operations, the ECC logic 54 receives the read data from the memory array 52 and the corresponding syndromes from the syndrome memory 50 . The ECC logic 54 then uses the syndromes to check the read data and to correct any errors that are found. The ECC logic 54 then writes the corrected data to the memory array 52 . Once the protected regions of the memory array 52 have been read, and the refresh rate increased to the normal refresh rate, the CPU 14 can disable the ECC logic 54 .
- the CPU 14 initiates a read operation prior to entering the low power refresh mode, but the actual reading of data from the protected areas is accomplished by sequencer logic in the DRAMs 32 or in a memory module containing the DRAMs 32 .
- the operation of the sequencer logic could be initiated by commands from the CPU 14 other than a read command, such as by issuing commands for a “dummy” operation, i.e., an operation that is not actually implemented by the DRAMs 32 .
- the data stored in ECC protected areas regions of the memory array 52 are not checked and corrected when exiting the low power refresh mode. Instead, the ECC mode remains active during normal operation, and the data stored in the ECC protected regions are checked using the stored syndromes whenever that data are read during normal operation.
- This embodiment requires that the syndrome memory 50 remain powered during normal operation, at least until all of the data stored in the protected regions have been read.
- a complicating factor is the possibility of the data stored in the protected region being changed by a write to that region without the syndrome also being changed accordingly. Of course, if the write is for a data word equal in size to the data words used to create the syndromes, there would be no problem because the protected data would be entirely replaced after exiting the low power refresh mode.
- the syndrome will no longer correspond to the modified word.
- the ECC logic 54 would report a data retention error even if the data are not in error.
- the operating system being executed by the CPU 14 could determine which stored data words will be the subject of a partial write. The CPU 14 could then check these words for errors when exiting the low power refresh mode, and correct any errors that are found. Another technique would be to check and correct each stored data word just before a partial write to the data word occurs. Other techniques may also be used.
- FIG. 2 A computer system 60 according to another embodiment of the invention is shown in FIG. 2 .
- the computer system 60 is very similar in structure and operation to the computer system 10 of FIG. 1 . Therefore, in the interests of brevity, corresponding components have been provided with the same reference numerals, and a description of their operation will not be repeated.
- the computer system 60 of FIG. 2 differs from the computer system 10 of FIG. 1 primarily in the addition of a syndrome bus 64 and the elimination of the ECC logic 54 from the DRAMs 32 .
- the ECC logic 54 is located in the memory controller 30 . Therefore, prior to entering the low power refresh mode, read data from the protected regions of the memory array 52 are coupled to the ECC logic 54 in the memory controller 30 through the data bus 42 .
- the ECC logic 54 then generates the syndromes, which are coupled to the syndrome memory 50 in the DRAMs 32 through the syndrome bus 64 .
- the read data in the protected regions are coupled to the ECC logic 54 through the data bus 42 , and the corresponding syndromes are coupled from the syndrome memory 50 to the ECC logic 54 through the syndrome bus 64 .
- the ECC logic 54 then checks the read data, corrects any errors that are found, and couples corrected data through the data bus 42 , which are written to the memory array 52 .
- the advantage of the computer system 10 of FIG. 1 over the memory device 60 is that the DRAMs 32 used in the system 10 of FIG. 1 are plug compatible with conventional DRAMs, thus making it unnecessary to physically alter the computer system to accommodate selective ECC during low power refresh.
- a synchronous DRAM 100 (“SDRAM”) is shown in FIG. 3 .
- the SDRAM 100 includes an address register 112 that receives bank addresses, row addresses and column addresses on an address bus 114 .
- the address bus 114 is coupled to the memory controller 30 ( FIG. 1 ).
- a bank address is received by the address register 112 and is coupled to bank control logic 116 that generates bank control signals, which are described further below.
- the bank address is normally coupled to the SDRAM 100 along with a row address.
- the row address is received by the address register 112 and applied to a row address multiplexer 118 .
- the row address multiplexer 118 couples the row address to row address latch & decoder circuit 120 a - d for each of several banks of memory cell arrays 122 a - d, respectively.
- Each bank 120 a - d is divided into two sections, a data second 124 that is used for storing data, and a syndrome section 126 that is used for storing syndromes.
- a separate syndrome memory 50 is not used in the SDRAM 100 of FIG. 3 .
- Each of the latch & decoder circuits 120 a - d is selectively enabled by a control signal from the bank control logic 116 depending on which bank of memory cell arrays 122 a - d is selected by the bank address.
- the selected latch & decoder circuit 120 applies various signals to its respective bank 122 as a function of the row address stored in the latch & decoder circuit 120 . These signals include word line voltages that activate respective rows of memory cells in the banks 122 .
- the row address multiplexer 118 also couples row addresses to the row address latch & decoder circuits 120 a - d for the purpose of refreshing the memory cells in the banks 122 a - d.
- the row addresses are generated for refresh purposes by a refresh counter 130 .
- the refresh counter 130 periodically begins operating at times controlled by a self-refresh timer 132 .
- the self-refresh timer 132 preferably initiates refreshes at a relatively slow rate in the low power refresh mode, as explained above.
- a column address is applied to the address register 112 .
- the address register 112 couples the column address to a column address counter/latch circuit 134 .
- the counter/latch circuit 134 stores the column address, and, when operating in a burst mode, generates column addresses that increment from the received column address. In either case, either the stored column address or incrementally increasing column addresses are coupled to column address & decoders 138 a - d for the respective banks 122 a - d.
- the column address & decoders 138 a - d apply various signals to respective sense amplifiers 140 a - d and 142 a - d through column interface circuitry 144 .
- the column interface circuitry 144 includes conventional 1 /O gating circuits, DQM mask logic, read data latches for storing read data from the memory cells in the banks 122 and write drivers for coupling write data to the memory cells in the banks 122 .
- the column interface circuitry 144 also includes an ECC generator/checker 146 that essentially performs the same function as the ECC logic 54 in the DRAMS 32 of FIGS. 1 and 2 .
- Syndromes read from the syndrome section 126 of one of the banks 122 a - d are sensed by the respective set of sense amplifiers 142 a - d and then coupled to the ECC generator checker 146 .
- Data read from the data section 124 one of the banks 122 a - d are sensed by the respective set of sense amplifiers 140 a - d and then stored in the read data latches in the column interface circuitry 144 .
- the data are then coupled to a data output register 148 , which applies the read data to a data bus 150 .
- Data to be written to the memory cells in one of the banks 122 a - d are coupled from the data bus 150 through a data input register 152 to write drivers in the column interface circuitry 144 .
- the write drivers then couple the data to the memory cells in one of the banks 122 a - d.
- a data mask signal “DQM” is applied to the column interface circuitry 144 and the data output register 148 to selectively alter the flow of data into and out of the column interface circuitry 144 , such as by selectively masking data to be read from the banks of memory cell arrays 122 a - d.
- control logic 156 which includes a command decoder 158 that receives command signals through a command bus 160 .
- These high level command signals which are generated by the memory controller 30 ( FIG. 1 ), are a clock a chip select signal CS#, a write enable signal WE#, a column address strobe signal CAS#, and a row address strobe signal RAS#, with the “#” designating the signal as active low.
- Various combinations of these signals are registered as respective commands, such as a read command or a write command.
- the control logic 156 also receives a clock signal CLK and a clock enable signal CKE#, which cause the SDRAM 100 to operate in a synchronous manner.
- the control logic 156 generates a sequence of control signals responsive to the command signals to carry out the function (e.g., a read or a write) designated by each of the command signals.
- the control logic 156 also applies signals to the refresh counter 130 to control the operation of the refresh counter 130 during refresh of the memory cells in the banks 122 .
- the control logic 156 also applies signals to the refresh timer 132 to control the refresh rate and allow the SDRAM 100 to operate in the low power refresh mode.
- the control signals generated by the control logic 156 and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted.
- the control logic 156 also includes a mode register 164 that may be programmed by signals coupled through the command bus 160 during initialization of the SDRAM 100 .
- the mode register 164 then generates mode control signals that are used by the control logic 156 to control the operation of the SDRAM 100 in various modes, such as the low power refresh mode.
- the mode register 164 may also include an ECC controller 170 that causes the control logic 156 to issue control signals to the ECC generator checker 146 and other components to generate syndromes for storage in the syndrome section 126 of the banks 122 a - d, and to check and correct data read from the data section 124 of the banks 122 a - d using syndromes stored in the sections 126 .
- the ECC controller 170 is preferably enabled and disabled by a mode signal from the mode register 164 , as explained above.
- control logic 156 may include a control register 174 that can receive control signals from the CPU 14 ( FIG. 1 ) to directly control the operation of the ECC generator checker 146 , as explained above.
- the contents of the control register 174 in one embodiment of the invention are shown in FIG. 4 .
- a first bit 180 of the control register 174 is either set or reset to enable or disable, respectively, the ECC mode.
- the next M+1 bits 184 of the control register 180 selects which memory banks 122 are to be powered, thereby allowing the CPU 14 to selectively apply power to each of the memory banks 122 .
- the final N+1 bits 188 select each region of each bank 122 that is to be ECC protected.
- the bits 188 could allow only a portion of a bank 122 to be refreshed, or all of a bank to be refreshed.
- the interfaces between the sense amplifiers 140 , 142 , the ECC generator/checker 146 and certain components in the column interface circuitry 144 are shown in greater detail in FIG. 5 .
- the sense amplifiers 142 coupled to the data sections 124 of the memory banks 122 a - d output respective data bits for respective columns, which are applied to column steering logic 190 .
- the sense amplifiers 142 output respective data bits for 8,192 columns.
- the column steering logic 190 uses the 6 most significant bits 2 - 7 of a column address to select 1 of 64 128-bit groups of data bits and couples the data bits to the ECC generator/checker 146 .
- the sense amplifiers 140 coupled to the syndrome section of the memory banks 122 a - d couple a syndrome corresponding to the read data directly to the ECC generator/checker 146 .
- the ECC generator/checker 146 includes a comparator 194 that provides an error indication in the event the read data contains an error.
- the ECC generator/checker 146 then couples the corrected 128-bit word to additional column steering logic 198 , and also couples the corrected 128-bit word back through the column steering logic 180 to the banks 122 a - d so that the banks will now contain correct data.
- the column steering logic 198 uses the 2 least significant bits 0 - 1 of a column address to select 1 of 4 32-bit groups of data bits and couples the data bits to the memory controller 30 ( FIG. 1 ), as previously explained. It is not necessary for the column steering logic 198 to couple the syndrome to the memory controller 30 in the computer system 10 of FIG. 1 so that the operation error checking and correction function is transparent to the memory controller 30 . Also, although 128 bits of write data are used to form the syndrome, it is not necessary for the DRAM 32 to include externally accessible data terminals for each of these 128 bits.
- a procedure 200 is initially in an idle state 202 prior to entering the low power refresh mode.
- the operating system for the CPU 14 determines at step 206 the regions of the memory banks 122 that are to be ECC protected. More specifically, a variable “i” designating the first region of memory that will be protected in initialized to “1”, and the last region of memory that will be protected is set to a variable “X.”
- a record of this determination is also stored at step 206 in a suitable location, such as a register internal to the CPU 14 or memory controller 30 .
- step 220 the procedure branches from step 218 to step 220 where the CPU 14 disables the ECC protection.
- This can be accomplished by the CPU 14 either writing a mode bit to the mode register 164 or resetting the bit 180 in the control register 174 , as explained above with reference to FIG. 4 .
- the CPU 14 then enters the low power refresh mode at step 224 , which is preferably a self-refresh mode, the nature of which is well-known to one skilled in the art. This can be accomplished by the CPU writing an appropriate bit to the mode register 164 .
- the control logic 156 then issues a control signal to the refresh timer 132 to reduce the refresh rate.
- the SDRAM 100 then operates in a reduced refresh rate, which substantially reduces the power consumed by the SDRAM 100 .
- a procedure 230 shown in FIG. 7 is used.
- the refresh exit procedure is initiated at step 232
- the normal refresh rate used for auto refresh is initiated at step 234 .
- the variable X identifying the regions of memory that were ECC protected is also read at step 234 .
- the CPU 14 then enables the ECC checking mode at step 238 to check the first region of memory that was ECC protected. Again, this can be accomplished by the CPU 14 either writing a mode bit to the mode register 164 or writing appropriate bits to the control register 174 .
- step 246 When data from all of the protected regions have been read, checked and corrected if necessary, the procedure branches from step 246 to step 250 in which the CPU 14 switches the SDRAM 100 to the normal operating mode. This can be accomplished by the CPU 14 either writing a mode bit to the mode register 164 or resetting the bit 180 in the control register 174 , as explained above with reference to FIG. 4 . The CPU 14 then enters the normal operating mode at step 252 .
Abstract
A computer system includes a processor coupled to a DRAM through a memory controller. The processor switches the DRAM to a low power refresh mode in which DRAM cells are refreshed at a sufficiently low rate that data retention errors may occur. Prior to switching the DRAM to the low power refresh mode, the processor identifies a region of an array of DRAM cells that contains essential data that needs to be protected from such data retention errors. The processor then reads data from the identified region, and either the DRAM or the memory controller generates error checking and correcting syndromes from the read data. The syndromes are stored in the DRAM, and the low power refresh mode is then entered. Upon exiting the low power refresh mode, the processor again reads the data from the identified region, and the read data is checked and corrected using the syndromes.
Description
- This invention relates to dynamic random access memory (“DRAM”) devices and systems, and, more particularly, to a method and system for allowing DRAM cells to be refreshed at a relatively low rate to reduce power consumption.
- As the use of electronic devices, such as personal computers, continue to increase, it is becoming ever more important to make such devices portable. The usefulness of portable electronic devices, such as notebook computers, is limited by the limited length of time batteries are capable of powering the device before needing to be recharged. This problem has been addressed by attempts to increase battery life and attempts to reduce the rate at which such electronic devices consume power.
- Various techniques have been used to reduce power consumption in electronic devices, the nature of which often depends upon the type of power consuming electronic circuits that are in the device. Electronic devices, such notebook computers, typically include dynamic random access memory (“DRAM”) devices that consume a substantial amount of power. As the data storage capacity and operating speeds of DRAM devices continues to increase, the power consumed by such devices has continued to increase in a corresponding manner. In general, the power consumed by a DRAM device increases with both the capacity and the operating speed of the DRAM devices.
- The power consumed by DRAM devices is also affected by their operating mode. A DRAM device, for example, will generally consume a relatively large amount of power when the DRAM cells are being refreshed. As is well-known in the art, DRAM cells, each of which essentially consists of a capacitor, must be periodically refreshed to retain data stored in the DRAM device. Refresh is typically performed by essentially reading data bits from the memory cells in each row of a memory cell array and then writing those same data bits back to the same cells in the row. A relatively large amount of power is consumed when refreshing a DRAM because rows of memory cells in a memory cell array are being actuated in the rapid sequence. Each time a row of memory cells is actuated, a pair of digit lines for each memory cell are switched to complementary voltages and then equilibrated. As a result, DRAM refreshes tends to be particularly power-hungry operations. Further, since refreshing memory cells must be accomplished even when the DRAM is not being used and is thus inactive, the amount of power consumed by refresh is a critical determinant of the amount of power consumed by the DRAM over an extended period. Thus many attempts to reduce power consumption in DRAM devices have focused on reducing the rate at which power is consumed during refresh.
- Refresh power can, of course, be reduced by reducing the rate at which the memory cells in a DRAM are being refreshed. However, reducing the refresh rate increases the risk of data stored in the DRAM cells being lost. More specifically, since, as mentioned above, DRAM cells are essentially capacitors, charge inherently leaks from the memory cell capacitors, which can change the value of a data bit stored in the memory cell over time. However, current leaks from capacitors at varying rates. Some capacitors are essentially short-circuited and are thus incapable of storing charge indicative of a data bit. These defective memory cells can be detected during production testing, and can then be repaired by substituting non-defective memory cells using conventional redundancy circuitry. On the other hand, current leaks from most DRAM cells at much slower rates that span a wide range. A DRAM refresh rate is chosen to ensure that all but a few memory cells can store data bits without data loss. This refresh rate is typically once every 64 ms. The memory cells that cannot reliably retain data bits at this refresh rate are detected during production testing and replaced by redundant memory cells. However, the rate of current leakage from DRAM cells can change after production testing, both as a matter of time and from subsequent production steps, such as in packaging DRAM chips. Current leakage, and hence the rate of data loss, can also be effected by environmental factors, such as the temperature of DRAM devices. Therefore, despite production testing, a few memory cells will typically be unable to retain stored data bits at normal refresh rates.
- One technique that has been used to correct data errors in DRAMs is to generate an error correcting code “ECC from each item of stored data, and then store the ECC, known as a syndrome, along with the data. The use of ECC techniques during refresh could allow the power consumed by a DRAM device to be reduced because the ability of ECC to correct data retention errors would allow the refresh rate to be slowed to such an extent that errors can occur. Significantly reducing the refresh rate of a DRAM device would result in a substantial reduction in the power consumed by the DRAM device.
- Although the use of ECC techniques during refresh could substantially reduce power consumption during refresh, it could impose significant cost penalties in both the cost and the performance of DRAM devices. In particular, the development cost and manufacturing cost of a DRAM device or a memory controller would be increased by the cost to develop and manufacture the additional circuitry needed to perform the ECC function. The increase in manufacturing cost for additional features in DRAM devices is normally manifested in a larger semiconductor die size, which reduces the yield from each semiconductor wafer. It can also be anticipated that the performance of DRAM devices would be impaired by reduced operating speeds resulting from the need to check and possibly correct all data read from the DRAM devices as well as the need to create syndromes for all data written to the DRAM devices.
- There is therefore a need for a system and method for reducing power consumption by refreshing DRAM cells at a reduced rate without incurring the cost and performance penalties needed to check and possibly correct all of the data read from the DRAM device and to create syndromes for all data written to the DRAM device.
- A method and system for refreshing memory cells in a dynamic random access memory (“DRAM”) device is coupled to a processor in a computer system. The memory cells in the DRAM are refreshed at a reduced power rate that is sufficiently slow that data retention errors can be expected to occur during refresh. However, the expected data retention errors are corrected using ECC techniques applied only to memory cells containing essential data that should be protected from data retention errors. More specifically, prior to refreshing the memory cells at the reduced power rate, a determination is made, preferably by the processor, which memory cells are storing the essential data. ECC techniques are then used to check and correct the essential data without using ECC techniques to check and correct data stored in other memory cells. Prior to refreshing the memory cells at the reduced power rate, the essential data are read, and corresponding syndromes are generated and stored. When departing from the low power refresh rate, the essential data are again read, and the stored syndromes are used to check the read data for errors. If any errors are found, the syndromes are used to correct the data, and the corrected data are written to the DRAM.
-
FIG. 1 is a block diagram of a computer system according to one embodiment of the invention. -
FIG. 2 is a block diagram of a computer system according to another embodiment of the invention. -
FIG. 3 is a block diagram of a DRAM device according to one embodiment of the invention. -
FIG. 4 is a schematic diagram illustrating the data structure of control data that may be stored in a control register in the DRAM ofFIG. 3 . -
FIG. 5 is a block diagram of a portion of column interface circuitry used in the DRAM ofFIG. 3 . -
FIG. 6 is a flow chart showing the operation of the DRAM ofFIG. 3 when entering a low power refresh mode using ECC techniques to correct data retention errors for essential data. -
FIG. 7 is a flow chart showing the operation of the DRAM ofFIG. 3 when exiting the low power refresh mode. - A
computer system 10 according to one embodiment of the invention is shown inFIG. 1 . Thecomputer system 10 includes a central processor unit (“CPU”) 14 coupled to asystem controller 16 through aprocessor bus 18. Thesystem controller 16 is coupled to input/output (“I/O”) devices (not shown) through aperipheral bus 20 and to an I/0controller 24 through anexpansion bus 26. The I/O controller 24 is also connected to various peripheral devices (not shown) through another I/0bus 28. - The
system controller 16 includes amemory controller 30 that is coupled to several dynamic random access memory (“DRAM”) device 32 a-c through anaddress bus 36, acontrol bus 38, and adata bus 42. The locations in each of the DRAMs 32 a-c to which data are written and data are read are designated by addresses coupled to the DRAMs 32 a-c on theaddress bus 36. The operation of the DRAMs 32 a-c are controlled by control signals coupled to the DRAMs 32 a-c on thecontrol bus 38. - In other embodiments of the invention, the
memory controller 30 may be coupled to one or more memory modules (not shown) through theaddress bus 36, thecontrol bus 38, and thedata bus 42. Each of the memory modules would normally contain several of the DRAMs 32. - With further reference to
FIG. 1 , the DRAMs 32 a-c each include asyndrome memory 50, amemory array 52 andECC logic 54. TheECC logic 54 generates a syndrome from write data received from thememory controller 30, and stores the syndrome in the syndrome memory 40 while the write data are being stored in thememory array 52 of the DRAM 32. When data are read from the DRAM 32, the read data are coupled frommemory array 52 to theECC logic 54 and the syndrome are coupled from the syndrome memory 40 to theECC logic 54. TheECC logic 54 then uses the syndrome to determine if the read data contains an erroneous data bit, and, if more than one data bit is not in error, to correct the erroneous data bit. The corrected read data are then coupled to thememory controller 30 through thedata bus 42. Although thesyndrome memory 50 may be a separate memory array in the DRAM 32 as shown inFIG. 1 , it may alternatively be included in the same array of DRAM cells that are used to store data, as explained in greater detail below. The use of ECC allows the refresh rate of the memory cells in thememory array 52 to be reduced to a rate at which some data retention errors can occur since such errors can be corrected using the syndromes stored in thesyndrome memory 50 and theECC logic 52. - The DRAM 32 is able to use ECC techniques with relatively little of the costs and performance impairments associated with conventional ECC techniques because the
CPU 14 uses ECC techniques to check and correct only the data stored in thememory array 52 that needs to be correct. More specifically, conventional computer systems and other electronic systems use DRAM devices to store a variety of data types. For example, a DRAM device may be used as a “scratch pad” memory or to store audio data or video data that is being coupled to a display. This type of data is usually overwritten with new data quite frequently, and is therefore generally not used after an extended refresh. Other data, such as program instructions, spreadsheet data, word processing documents, must be protected during refresh. Therefore, theCPU 14 applies ECC techniques to this type of data. - The
CPU 14 can determine which data to protect through a variety of means. For example, theCPU 14 can store essential data that needs to be protected in only certain regions of thememory array 52, and then apply ECC techniques to these regions. TheCPU 14 can also keep track of where in thememory array 52 essential data are stored, and then apply ECC techniques to these regions. Other techniques may also be used. - In operation, prior to each of the DRAMs 32 a-c entering a low power refresh mode, the DRAMs 32 a-c perform a read and syndrome generating operation. More specifically, the
CPU 14 enables theECC logic 54 by suitable means, such as by coupling a command signal to the DRAMs 32 a-c through thememory controller 30 andcontrol bus 38 that enables a control register in the DRAM 32. However, the CPU may enable theECC logic 54 by other means, such as by coupling control signals directly to theECC logic 54, by coupling an unsupported command to the DRAM 32, use of a specific sequence of operations, or by other means. In any case, once theECC logic 54 has been enabled, theCPU 14 performs a read operation to the regions of thememory array 52 that store essential data that needs to be protected. The read operation is preferably performed in a burst read mode to minimize the time required for the read operation. Regions of thememory array 52 that store non-essential data, such as regions used as image buffers, temporary buffers and screen buffers, are not read. During the read operation, the DRAM 32 generates syndromes from the read data, and stores the syndromes in thesyndrome memory 50. The DRAM 32 then enters a low power refresh mode in which the memory cells in thearray 52 are refreshed at a rate that is sufficiently low that data retention errors may occur. In one embodiment of the invention, theCPU 14 leaves theECC logic 54 enabled during the low power refresh mode to correct any data retention errors as they occur. In another embodiment of the invention, theCPU 14 disables theECC logic 54 after all of the syndromes have been stored and before entering the low power refresh mode. In this embodiment, theCPU 14 corrects any data retention errors that have occurred when exiting the low power refresh mode, as explained in greater detail below. - When exiting the low power refresh mode, the DRAMs 32 a-c perform a read and correct operation. More specifically, the
CPU 14 enables theECC logic 54 if it was not enabled during the refresh mode. TheCPU 14 then reads data from the protected regions of thememory array 52, again preferably using a burst read mode. During these read operations, theECC logic 54 receives the read data from thememory array 52 and the corresponding syndromes from thesyndrome memory 50. TheECC logic 54 then uses the syndromes to check the read data and to correct any errors that are found. TheECC logic 54 then writes the corrected data to thememory array 52. Once the protected regions of thememory array 52 have been read, and the refresh rate increased to the normal refresh rate, theCPU 14 can disable theECC logic 54. - In other embodiments of the invention, the
CPU 14 initiates a read operation prior to entering the low power refresh mode, but the actual reading of data from the protected areas is accomplished by sequencer logic in the DRAMs 32 or in a memory module containing the DRAMs 32. The operation of the sequencer logic could be initiated by commands from theCPU 14 other than a read command, such as by issuing commands for a “dummy” operation, i.e., an operation that is not actually implemented by the DRAMs 32. - In still another embodiment of the invention, the data stored in ECC protected areas regions of the
memory array 52 are not checked and corrected when exiting the low power refresh mode. Instead, the ECC mode remains active during normal operation, and the data stored in the ECC protected regions are checked using the stored syndromes whenever that data are read during normal operation. This embodiment requires that thesyndrome memory 50 remain powered during normal operation, at least until all of the data stored in the protected regions have been read. A complicating factor is the possibility of the data stored in the protected region being changed by a write to that region without the syndrome also being changed accordingly. Of course, if the write is for a data word equal in size to the data words used to create the syndromes, there would be no problem because the protected data would be entirely replaced after exiting the low power refresh mode. However, if a write occurs for part of a word used to create a stored syndrome, then the syndrome will no longer correspond to the modified word. As a result, when the word is subsequently read, theECC logic 54 would report a data retention error even if the data are not in error. There are several ways of handling this problem. For example, the operating system being executed by theCPU 14 could determine which stored data words will be the subject of a partial write. TheCPU 14 could then check these words for errors when exiting the low power refresh mode, and correct any errors that are found. Another technique would be to check and correct each stored data word just before a partial write to the data word occurs. Other techniques may also be used. - A
computer system 60 according to another embodiment of the invention is shown inFIG. 2 . Thecomputer system 60 is very similar in structure and operation to thecomputer system 10 ofFIG. 1 . Therefore, in the interests of brevity, corresponding components have been provided with the same reference numerals, and a description of their operation will not be repeated. Thecomputer system 60 ofFIG. 2 differs from thecomputer system 10 ofFIG. 1 primarily in the addition of asyndrome bus 64 and the elimination of theECC logic 54 from the DRAMs 32. In thecomputer system 60, theECC logic 54 is located in thememory controller 30. Therefore, prior to entering the low power refresh mode, read data from the protected regions of thememory array 52 are coupled to theECC logic 54 in thememory controller 30 through thedata bus 42. TheECC logic 54 then generates the syndromes, which are coupled to thesyndrome memory 50 in the DRAMs 32 through thesyndrome bus 64. When exiting the low power refresh mode, the read data in the protected regions are coupled to theECC logic 54 through thedata bus 42, and the corresponding syndromes are coupled from thesyndrome memory 50 to theECC logic 54 through thesyndrome bus 64. TheECC logic 54 then checks the read data, corrects any errors that are found, and couples corrected data through thedata bus 42, which are written to thememory array 52. The advantage of thecomputer system 10 ofFIG. 1 over thememory device 60 is that the DRAMs 32 used in thesystem 10 ofFIG. 1 are plug compatible with conventional DRAMs, thus making it unnecessary to physically alter the computer system to accommodate selective ECC during low power refresh. - A synchronous DRAM 100 (“SDRAM”) according to one embodiment of the invention is shown in
FIG. 3 . TheSDRAM 100 includes anaddress register 112 that receives bank addresses, row addresses and column addresses on anaddress bus 114. Theaddress bus 114 is coupled to the memory controller 30 (FIG. 1 ). Typically, a bank address is received by theaddress register 112 and is coupled tobank control logic 116 that generates bank control signals, which are described further below. The bank address is normally coupled to theSDRAM 100 along with a row address. The row address is received by theaddress register 112 and applied to arow address multiplexer 118. Therow address multiplexer 118 couples the row address to row address latch & decoder circuit 120 a-d for each of several banks of memory cell arrays 122 a-d, respectively. Each bank 120 a-d is divided into two sections, a data second 124 that is used for storing data, and asyndrome section 126 that is used for storing syndromes. Thus, unlike the DRAM 32 ofFIGS. 1 and 2 , aseparate syndrome memory 50 is not used in theSDRAM 100 ofFIG. 3 . - Each of the latch & decoder circuits 120 a-d is selectively enabled by a control signal from the
bank control logic 116 depending on which bank of memory cell arrays 122 a-d is selected by the bank address. The selected latch & decoder circuit 120 applies various signals to its respective bank 122 as a function of the row address stored in the latch & decoder circuit 120. These signals include word line voltages that activate respective rows of memory cells in the banks 122. Therow address multiplexer 118 also couples row addresses to the row address latch & decoder circuits 120 a-d for the purpose of refreshing the memory cells in the banks 122 a-d. The row addresses are generated for refresh purposes by arefresh counter 130. During operation in a self-refresh mode, therefresh counter 130 periodically begins operating at times controlled by a self-refresh timer 132. The self-refresh timer 132 preferably initiates refreshes at a relatively slow rate in the low power refresh mode, as explained above. - After the bank and row addresses have been applied to the
address register 112, a column address is applied to theaddress register 112. The address register 112 couples the column address to a column address counter/latch circuit 134. The counter/latch circuit 134 stores the column address, and, when operating in a burst mode, generates column addresses that increment from the received column address. In either case, either the stored column address or incrementally increasing column addresses are coupled to column address & decoders 138 a-d for the respective banks 122 a-d. The column address & decoders 138 a-d apply various signals torespective sense amplifiers 140 a-d and 142 a-d throughcolumn interface circuitry 144. Thecolumn interface circuitry 144 includes conventional 1/O gating circuits, DQM mask logic, read data latches for storing read data from the memory cells in the banks 122 and write drivers for coupling write data to the memory cells in the banks 122. Thecolumn interface circuitry 144 also includes an ECC generator/checker 146 that essentially performs the same function as theECC logic 54 in the DRAMS 32 ofFIGS. 1 and 2 . - Syndromes read from the
syndrome section 126 of one of the banks 122 a-d are sensed by the respective set ofsense amplifiers 142 a-d and then coupled to theECC generator checker 146. Data read from thedata section 124 one of the banks 122 a-d are sensed by the respective set ofsense amplifiers 140 a-d and then stored in the read data latches in thecolumn interface circuitry 144. The data are then coupled to adata output register 148, which applies the read data to adata bus 150. Data to be written to the memory cells in one of the banks 122 a-d are coupled from thedata bus 150 through adata input register 152 to write drivers in thecolumn interface circuitry 144. The write drivers then couple the data to the memory cells in one of the banks 122 a-d. A data mask signal “DQM” is applied to thecolumn interface circuitry 144 and thedata output register 148 to selectively alter the flow of data into and out of thecolumn interface circuitry 144, such as by selectively masking data to be read from the banks of memory cell arrays 122 a-d. - The above-described operation of the
SDRAM 100 is controlled bycontrol logic 156, which includes acommand decoder 158 that receives command signals through acommand bus 160. These high level command signals, which are generated by the memory controller 30 (FIG. 1 ), are a clock a chip select signal CS#, a write enable signal WE#, a column address strobe signal CAS#, and a row address strobe signal RAS#, with the “#” designating the signal as active low. Various combinations of these signals are registered as respective commands, such as a read command or a write command. Thecontrol logic 156 also receives a clock signal CLK and a clock enable signal CKE#, which cause theSDRAM 100 to operate in a synchronous manner. Thecontrol logic 156 generates a sequence of control signals responsive to the command signals to carry out the function (e.g., a read or a write) designated by each of the command signals. Thecontrol logic 156 also applies signals to therefresh counter 130 to control the operation of therefresh counter 130 during refresh of the memory cells in the banks 122. Thecontrol logic 156 also applies signals to therefresh timer 132 to control the refresh rate and allow theSDRAM 100 to operate in the low power refresh mode. The control signals generated by thecontrol logic 156, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted. - The
control logic 156 also includes amode register 164 that may be programmed by signals coupled through thecommand bus 160 during initialization of theSDRAM 100. Themode register 164 then generates mode control signals that are used by thecontrol logic 156 to control the operation of theSDRAM 100 in various modes, such as the low power refresh mode. Themode register 164 may also include anECC controller 170 that causes thecontrol logic 156 to issue control signals to theECC generator checker 146 and other components to generate syndromes for storage in thesyndrome section 126 of the banks 122 a-d, and to check and correct data read from thedata section 124 of the banks 122 a-d using syndromes stored in thesections 126. TheECC controller 170 is preferably enabled and disabled by a mode signal from themode register 164, as explained above. - In an alternative embodiment, the
control logic 156 may include acontrol register 174 that can receive control signals from the CPU 14 (FIG. 1 ) to directly control the operation of theECC generator checker 146, as explained above. The contents of thecontrol register 174 in one embodiment of the invention are shown inFIG. 4 . Afirst bit 180 of thecontrol register 174 is either set or reset to enable or disable, respectively, the ECC mode. The next M+1bits 184 of thecontrol register 180 selects which memory banks 122 are to be powered, thereby allowing theCPU 14 to selectively apply power to each of the memory banks 122. In theSDRAM 100 ofFIG. 3 , there are 4 bits bankpower control bits 184 for the respective banks 122 a-d. The final N+1bits 188 select each region of each bank 122 that is to be ECC protected. Thebits 188 could allow only a portion of a bank 122 to be refreshed, or all of a bank to be refreshed. - The interfaces between the
sense amplifiers checker 146 and certain components in thecolumn interface circuitry 144 are shown in greater detail inFIG. 5 . Thesense amplifiers 142 coupled to thedata sections 124 of the memory banks 122 a-d output respective data bits for respective columns, which are applied tocolumn steering logic 190. In the embodiment shown inFIG. 5 , thesense amplifiers 142 output respective data bits for 8,192 columns. Thecolumn steering logic 190 uses the 6 most significant bits 2-7 of a column address to select 1 of 64 128-bit groups of data bits and couples the data bits to the ECC generator/checker 146. Thesense amplifiers 140 coupled to the syndrome section of the memory banks 122 a-d couple a syndrome corresponding to the read data directly to the ECC generator/checker 146. - The ECC generator/
checker 146 includes acomparator 194 that provides an error indication in the event the read data contains an error. The ECC generator/checker 146 then couples the corrected 128-bit word to additionalcolumn steering logic 198, and also couples the corrected 128-bit word back through thecolumn steering logic 180 to the banks 122 a-d so that the banks will now contain correct data. Thecolumn steering logic 198 uses the 2 least significant bits 0-1 of a column address to select 1 of 4 32-bit groups of data bits and couples the data bits to the memory controller 30 (FIG. 1 ), as previously explained. It is not necessary for thecolumn steering logic 198 to couple the syndrome to thememory controller 30 in thecomputer system 10 ofFIG. 1 so that the operation error checking and correction function is transparent to thememory controller 30. Also, although 128 bits of write data are used to form the syndrome, it is not necessary for the DRAM 32 to include externally accessible data terminals for each of these 128 bits. - The operation of the
SDRAM 100 when entering and exiting the ECC protected low power refresh mode will now be explained with reference toFIGS. 6 and 7 . With reference toFIG. 6 , aprocedure 200 is initially in anidle state 202 prior to entering the low power refresh mode. Prior to entering the low power refresh mode, the operating system for theCPU 14 determines atstep 206 the regions of the memory banks 122 that are to be ECC protected. More specifically, a variable “i” designating the first region of memory that will be protected in initialized to “1”, and the last region of memory that will be protected is set to a variable “X.” A record of this determination is also stored atstep 206 in a suitable location, such as a register internal to theCPU 14 ormemory controller 30. When the ECC protected low power refresh mode is to be entered, theCPU 14 first enables the ECC mode atstep 210. This is accomplished by either writing a mode bit to themode register 164 or writing appropriate bits to thecontrol register 174, as explained above with reference toFIG. 4 . TheCPU 14 then reads a first region of memory (i=1) in one of the banks 122 atstep 212, and, in doing so, generates and stores syndromes for the read data. The region to be protected (“i”) is then incremented by 1 atstep 216, and a check is made atstep 218 to determine if the region currently being ECC protected is the final region that will be protected. If not, the process returns to repeat steps 210-218. - When all of the protected regions have been read, the procedure branches from
step 218 to step 220 where theCPU 14 disables the ECC protection. This can be accomplished by theCPU 14 either writing a mode bit to themode register 164 or resetting thebit 180 in thecontrol register 174, as explained above with reference toFIG. 4 . TheCPU 14 then enters the low power refresh mode atstep 224, which is preferably a self-refresh mode, the nature of which is well-known to one skilled in the art. This can be accomplished by the CPU writing an appropriate bit to themode register 164. Thecontrol logic 156 then issues a control signal to therefresh timer 132 to reduce the refresh rate. TheSDRAM 100 then operates in a reduced refresh rate, which substantially reduces the power consumed by theSDRAM 100. - When the
SDRAM 100 is to exit the low power refresh mode, aprocedure 230 shown inFIG. 7 is used. The refresh exit procedure is initiated atstep 232, and the normal refresh rate used for auto refresh is initiated atstep 234. The variable X identifying the regions of memory that were ECC protected is also read atstep 234. TheCPU 14 then enables the ECC checking mode atstep 238 to check the first region of memory that was ECC protected. Again, this can be accomplished by theCPU 14 either writing a mode bit to themode register 164 or writing appropriate bits to thecontrol register 174. TheCPU 14 then reads a first region of memory (i=1) in one of the banks 122 atstep 240, and theECC generator checker 146 checks the read data for errors and corrects any errors that are found. The corrected data is then written to the region of memory being read. The region being checked is then incremented by 1 atstep 244, and a check is made atstep 246 to determine if the region currently being checked is the final region that was protected. If not, the process returns to repeat steps 238-246. - When data from all of the protected regions have been read, checked and corrected if necessary, the procedure branches from
step 246 to step 250 in which theCPU 14 switches theSDRAM 100 to the normal operating mode. This can be accomplished by theCPU 14 either writing a mode bit to themode register 164 or resetting thebit 180 in thecontrol register 174, as explained above with reference toFIG. 4 . TheCPU 14 then enters the normal operating mode atstep 252. - Although the present invention has been described with reference to the disclosed embodiments, persons skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. Such modifications are well within the skill of those ordinarily skilled in the art. Accordingly, the invention is not limited except as by the appended claims.
Claims (47)
1. In a computer system having a processor coupled to a dynamic random access memory (“DRAM”) device, a method of reducing the power consumed by the DRAM device, comprising:
refreshing DRAM cells in the DRAM device at a first rate when the DRAM device is active;
refreshing the DRAM cells in the DRAM device at a second rate when the DRAM device is inactive, the second rate being substantially slower than the first rate;
prior to transitioning from the first rate to the second rate, transitioning to an ECC protection mode by:
determining which DRAM cells are storing data that should be protected from data retention errors;
reading data from the DRAM cells determined to be storing data that should be protected;
generating ECC syndromes corresponding to the read data; and
storing the generated syndromes; and
when transitioning from the second rate to the first rate, transitioning from the ECC protection mode by:
reading data from the DRAM cells that are storing data that should be protected;
reading the stored ECC syndromes corresponding to the read data;
using the syndromes to determine if any of the read data are in error;
correcting any read data found to be in error; and
storing the corrected data in the DRAM cells.
2. The method of claim 1 wherein the act of determining which DRAM cells are storing data that should be protected from data retention errors comprises determining which DRAM cells are storing data that should be protected from data retention errors based on a record of the location of the DRAM cells.
3. The method of claim 1 wherein the act of determining which DRAM cells are storing data that should be protected from data retention errors comprises determining which DRAM cells are storing data that should be protected from data retention errors based on a record of the data stored in the DRAM cells.
4. The method of claim 1 wherein the act of determining which DRAM cells are storing data that should be protected from data retention errors comprises using the processor to determine which DRAM cells are storing data that should be protected from data retention errors.
5. The method of claim 1 wherein the act of reading data from the DRAM cells determined to be storing data that should be protected prior to transitioning from the first rate to the second rate comprises reading the data in a burst read operation.
6. The method of claim 1 wherein the act of reading data from the DRAM cells determined to be storing data that should be protected when transitioning to the ECC protection mode comprises using the processor to read the data from the DRAM cells determined to be storing data that should be protected.
7. The method of claim 1 wherein the act of reading data from the DRAM cells determined to be storing data that should be protected when transitioning to the ECC protection mode comprises initiating and controlling a read operation from within the DRAM device without using the processor.
8. The method of claim 1 wherein the act of generating ECC syndromes corresponding to the read data comprises generating the ECC syndromes within the DRAM device.
9. The method of claim 1 wherein the system further comprises a memory controller coupling the processor to the DRAM device, and wherein the act of generating ECC syndromes corresponding to the read data comprises generating the ECC syndromes within the memory controller.
10. The method of claim 1 wherein the act of storing the generated syndromes comprises storing the generated syndromes within the DRAM device.
11. The method of claim 10 wherein the act of storing the generated syndromes within the DRAM device comprises storing the generated syndromes in DRAM cells.
12. The method of claim 1 wherein the act of reading data from the DRAM cells that are storing data that should be protected when transitioning from the ECC protection mode comprises reading the data in a burst read operation.
13. The method of claim 1 wherein the act of reading data from the DRAM cells that are storing data that should be protected when transitioning from the ECC protection mode comprises using the processor to read the data from the DRAM cells that are storing data that should be protected.
14. The method of claim 1 wherein the act of reading data from the DRAM cells that are storing data that should be protected when transitioning from the ECC protection mode comprises initiating and controlling a read operation from within the DRAM device without using the processor.
15. The method of claim 1 wherein the act of reading the stored ECC syndromes corresponding to the data read when transitioning from the ECC protection mode comprises reading the stored ECC syndromes from the DRAM device.
16. The method of claim 1 wherein the act of using the syndromes to determine if any of the read data are in error comprises determining if any of the read data are in error within the DRAM device using the syndromes.
17. The method of claim 1 wherein the system further comprises a memory controller coupling the processor to the DRAM device, and wherein the act of using the syndromes to determine if any of the read data are in error comprises determining if any of the read data are in error within the memory controller using the syndromes.
18. The method of claim 1 wherein the act of correcting any read data found to be in error comprises using the DRAM device to correct any read data found to be in error.
19. The method of claim 1 wherein the system further comprises a memory controller coupling the processor to the DRAM device, and wherein the act of correcting any read data found to be in error comprises using the memory controller to correct any read data found to be in error.
20. The method of claim 1 wherein the act of storing the corrected data in the DRAM cells comprises using the processor to store the corrected data in the DRAM cells.
21. The method of claim 1 wherein the act of storing the corrected data in the DRAM cells comprises writing the corrected data to the DRAM cells in a burst write operation.
22. The method of claim 1 wherein the act of transitioning to an ECC protection mode comprises using the processor to transition to the ECC protection mode.
23. The method of claim 1 wherein the DRAM device further comprises a mode register, and wherein the act of using the processor to transition to the ECC protection mode comprises using the processor to store a first mode control bit in the mode register, the first mode control bit corresponding to the ECC protection mode.
24. The method of claim 1 wherein the DRAM device further comprises a control register, and wherein the act of using the processor to transition to the ECC protection mode comprises using the processor to store control data in the control register, the control data comprising a first bit enabling the ECC protection mode, and a plurality of second bits that specify the DRAM cells determined to be storing data that should be protected.
25. The method of claim 1 wherein the DRAM device further comprises a mode register, and wherein the act of using the processor to transition from the ECC protection mode comprises using the processor to store a second mode control bit in the mode register, the second mode control bit corresponding to a normal operating mode.
26. The method of claim 1 wherein the DRAM device further comprises a control register, and wherein the act of using the processor to transition from the ECC protection mode comprises using the processor to store a bit disabling the ECC protection mode.
27. The method of claim 1 wherein the acts of reading data from the DRAM cells that are storing data that should be protected, reading the stored ECC syndromes corresponding to the read data, and using the syndromes to determine if any of the read data are in error when transitioning from the second rate to the first rate are performed only for the DRAM cells storing data words to which data will be written to a part of the stored data word.
28. The method of claim 27 wherein the acts of reading data from the DRAM cells that are storing data that should be protected, reading the stored ECC syndromes corresponding to the read data, using the syndromes to determine if any of the read data are in error, and correcting any read data found to be in error are performed during normal operation of the DRAM for the DRAM cells storing data words to which data will not be written to a part of the stored data word.
29. The method of claim 28 , further comprising providing a tag for each data word that should be protected, the tag indicating whether or not a valid syndrome exists for the corresponding data word.
30. The method of claim 29 , further comprising setting the tag for each word to indicate a valid syndrome does not exist for the word when data is written to a part of one of the stored data words.
31. A method of refreshing memory cells in a dynamic random access memory (“DRAM”) device, the method comprising:
refreshing the memory cells at a reduced power rate that is sufficiently slow that data retention errors can be expected to occur during refresh; and
prior to refreshing the memory cells at the reduced power rate, determining which memory cells are storing essential data that should be protected from data retention errors, and use ECC techniques to check and correct the essential data without using ECC techniques to check and correct data stored in other of the memory cells.
32. The method of claim 31 wherein the act of using ECC techniques to check and correct the essential data comprises, prior to refreshing the memory cells at the reduced power rate:
identifying the memory cells storing essential data;
reading the essential data;
generating syndromes corresponding to the read data; and
storing the generated syndromes.
33. The method of claim 32 wherein the act of using ECC techniques to check and correct the essential data comprises, when no longer refreshing the memory cells at the reduced power rate:
reading the essential data;
retrieving the stored syndromes;
using the stored syndromes to determine if any of the essential data are in error;
if any of the essential data were found to be in error, using the stored syndromes to provide corrected data; and
storing the corrected data in the memory cells.
34. The method of claim 33 wherein the DRAM is coupled to a processor, and wherein the act of reading the essential data comprises using the processor to read the essential data.
35. The method of claim 31 wherein the DRAM is coupled to a processor, and wherein the act of determining which memory cells are storing essential data that should be protected comprises using the processor to determine which memory cells are storing essential data that should be protected.
36. A processor-based system, comprising:
a memory controller;
a dynamic random access memory (“DRAM”) device coupled to the memory controller, the DRAM device having a plurality of DRAM cells that are refreshed at a relatively high rate during operation in a normal mode and a relatively low rate during operation in a low power refresh mode; and
a processor coupled to the DRAM device through the memory controller, the processor being operable to couple a first signal to the DRAM device to cause the DRAM device to operate in the low power refresh mode and to couple a second signal to the DRAM device to cause the DRAM device to operate in the normal mode, the processor being operable prior to coupling the first signal to the DRAM device to:
determine which DRAM cells are storing data that should be protected from data retention errors in the low power refresh mode;
couple signals to the DRAM device that cause data to be read from the DRAM cells determined to be storing data that should be protected, the read data being used to generate ECC syndromes corresponding to the read data and being stored for subsequent use; and
the processor being operable after coupling the second signal to the DRAM device to couple signals to the DRAM device that cause data to be read from the DRAM cells that are storing data that should be protected, the read data being checked for errors and any errors corrected using the stored syndromes, the corrected data being stored in the DRAM device.
37. The system of claim 36 wherein the DRAM device comprises:
a syndrome memory that is operable to store the syndromes; and
ECC logic that is operable to:
receive the read data from the DRAM cells;
generate ECC syndromes corresponding to the read data;
cause the generated syndromes to be stored in the DRAM;
use the stored syndromes to check and correct read data from the DRAM cells; and
cause the corrected data to be stored in the DRAM.
38. The system of claim 37 wherein the DRAM device comprises a control register that receives a control bit from the processor, the control register being operable to store the control bit and to enable the ECC logic responsive to the control bit being set.
39. The system of claim 38 wherein the control register further receives from the processor a plurality of bits identifying the DRAM cells that are storing data that should be protected from data retention errors.
40. The system of claim 37 wherein the DRAM device further comprises:
an ECC controller that is operable to controls the ECC logic; and
a mode register coupled to receive mode control signals from the processor, the mode control signals switching the DRAM device between the normal mode and the low power refresh mode, the mode control signals further enabling and disabling the ECC controller.
41. The system of claim 37 wherein the DRAM device further comprises data steering logic coupled to receive corrected data from the ECC logic, the data steering logic being operable to couple the corrected data back to the DRAM cells for storage in the DRAM device.
42. The system of claim 36 wherein the DRAM device comprises a syndrome memory that is operable to store the generated ECC syndromes corresponding to the read data.
43. The system of claim 36 wherein the memory controller comprises ECC logic that is operable to:
receive the read data from the DRAM cells;
generate ECC syndromes corresponding to the read data;
cause the generated syndromes to be stored in the DRAM;
use the stored syndromes to check and correct read data from the DRAM cells; and
cause the corrected data to be stored in the DRAM.
44. A computer system, comprising:
a memory controller;
a dynamic random access memory (“DRAM”) device coupled to the memory controller, the DRAM device having at least one array of DRAM cells that are refreshed at a relatively high rate during operation in a normal mode and a relatively low rate during operation in a low power refresh mode; and
a processor coupled to the DRAM device through the memory controller, the processor being operable to identify at least one region of the array that should be protected from data loss when the DRAM device is operating in the low power refresh mode, the processor being operable to protect the identified region using ECC techniques during the period the DRAM device is operating in the low power refresh mode without protecting regions of the array other than the identified region.
45. The computer system of claim 44 wherein the DRAM device comprises ECC logic that is operable to generate syndromes corresponding to data stored in the identified regions of the array and to use the syndromes to check and correct the data stored in the identified regions of the array.
46. The computer system of claim 44 wherein the memory controller comprises ECC logic that is operable to generate syndromes corresponding to data stored in the identified regions of the array and to use the syndromes to check and correct the data stored in the identified regions of the array.
47. The system of claim 46 wherein the DRAM device comprises a syndrome memory that is operable to store the ECC syndromes generated by the memory controller.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/876,796 US20060010339A1 (en) | 2004-06-24 | 2004-06-24 | Memory system and method having selective ECC during low power refresh |
US11/433,217 US7461320B2 (en) | 2004-06-24 | 2006-05-11 | Memory system and method having selective ECC during low power refresh |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/876,796 US20060010339A1 (en) | 2004-06-24 | 2004-06-24 | Memory system and method having selective ECC during low power refresh |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/433,217 Continuation US7461320B2 (en) | 2004-06-24 | 2006-05-11 | Memory system and method having selective ECC during low power refresh |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060010339A1 true US20060010339A1 (en) | 2006-01-12 |
Family
ID=35542711
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/876,796 Abandoned US20060010339A1 (en) | 2004-06-24 | 2004-06-24 | Memory system and method having selective ECC during low power refresh |
US11/433,217 Active 2024-08-17 US7461320B2 (en) | 2004-06-24 | 2006-05-11 | Memory system and method having selective ECC during low power refresh |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/433,217 Active 2024-08-17 US7461320B2 (en) | 2004-06-24 | 2006-05-11 | Memory system and method having selective ECC during low power refresh |
Country Status (1)
Country | Link |
---|---|
US (2) | US20060010339A1 (en) |
Cited By (66)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060075296A1 (en) * | 2004-09-30 | 2006-04-06 | Menon Sankaran M | Method, apparatus and system for data integrity of state retentive elements under low power modes |
US20060090039A1 (en) * | 2004-10-27 | 2006-04-27 | Sanjeev Jain | Method and apparatus to enable DRAM to support low-latency access via vertical caching |
US20060101209A1 (en) * | 2004-11-08 | 2006-05-11 | Lais Eric N | Prefetch miss indicator for cache coherence directory misses on external caches |
US20070014168A1 (en) * | 2005-06-24 | 2007-01-18 | Rajan Suresh N | Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies |
US20070058410A1 (en) * | 2005-09-02 | 2007-03-15 | Rajan Suresh N | Methods and apparatus of stacking DRAMs |
US20070195613A1 (en) * | 2006-02-09 | 2007-08-23 | Rajan Suresh N | Memory module with memory stack and interface with enhanced capabilities |
US20070204075A1 (en) * | 2006-02-09 | 2007-08-30 | Rajan Suresh N | System and method for reducing command scheduling constraints of memory circuits |
US20080002503A1 (en) * | 2004-07-15 | 2008-01-03 | Klein Dean A | Method and system for controlling refresh to avoid memory cell data losses |
US20080025136A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | System and method for storing at least a portion of information received in association with a first operation for use in performing a second operation |
US20080027697A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Memory circuit simulation system and method with power saving capabilities |
US20080025123A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US20080025125A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US20080025122A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Memory refresh system and method |
US20080028136A1 (en) * | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
US20080025108A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US20080025137A1 (en) * | 2005-06-24 | 2008-01-31 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
US20080028137A1 (en) * | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and Apparatus For Refresh Management of Memory Modules |
US20080028135A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Multiple-component memory interface system and method |
US20080031072A1 (en) * | 2006-07-31 | 2008-02-07 | Metaram, Inc. | Power saving system and method for use with a plurality of memory circuits |
US20080031030A1 (en) * | 2006-07-31 | 2008-02-07 | Metaram, Inc. | System and method for power management in memory systems |
US20080056014A1 (en) * | 2006-07-31 | 2008-03-06 | Suresh Natarajan Rajan | Memory device with emulated characteristics |
US20080062773A1 (en) * | 2006-07-31 | 2008-03-13 | Suresh Natarajan Rajan | System and method for simulating an aspect of a memory circuit |
US20080082763A1 (en) * | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US20080086588A1 (en) * | 2006-10-05 | 2008-04-10 | Metaram, Inc. | System and Method for Increasing Capacity, Performance, and Flexibility of Flash Storage |
US20080092016A1 (en) * | 2006-10-11 | 2008-04-17 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
US20080109705A1 (en) * | 2006-10-18 | 2008-05-08 | Pawlowski J Thomas | Memory system and method using ECC with flag bit to identify modified data |
US20080115006A1 (en) * | 2006-07-31 | 2008-05-15 | Michael John Sebastian Smith | System and method for adjusting the timing of signals associated with a memory system |
US20080126690A1 (en) * | 2006-02-09 | 2008-05-29 | Rajan Suresh N | Memory module with memory stack |
US20080162991A1 (en) * | 2007-01-02 | 2008-07-03 | International Business Machines Corporation | Systems and methods for improving serviceability of a memory system |
US20090024790A1 (en) * | 2006-07-31 | 2009-01-22 | Suresh Natarajan Rajan | Memory circuit system and method |
US20090024789A1 (en) * | 2007-07-18 | 2009-01-22 | Suresh Natarajan Rajan | Memory circuit system and method |
US20090083479A1 (en) * | 2007-08-01 | 2009-03-26 | Samsung Electronics Co., Ltd. | Multiport semiconductor memory device and associated refresh method |
US20090119443A1 (en) * | 2006-08-15 | 2009-05-07 | International Business Machines Corporation | Methods for program directed memory access patterns |
US20090249148A1 (en) * | 2008-03-25 | 2009-10-01 | Micorn Technology, Inc. | Error-correction forced mode with m-sequence |
US7669086B2 (en) | 2006-08-02 | 2010-02-23 | International Business Machines Corporation | Systems and methods for providing collision detection in a memory system |
US7685392B2 (en) | 2005-11-28 | 2010-03-23 | International Business Machines Corporation | Providing indeterminate read data latency in a memory system |
US7765368B2 (en) | 2004-07-30 | 2010-07-27 | International Business Machines Corporation | System, method and storage medium for providing a serialized memory interface with a bus repeater |
US7870459B2 (en) | 2006-10-23 | 2011-01-11 | International Business Machines Corporation | High density high reliability memory module with power gating and a fault tolerant address and command bus |
US7934115B2 (en) | 2005-10-31 | 2011-04-26 | International Business Machines Corporation | Deriving clocks in a memory system |
US20110095783A1 (en) * | 2009-06-09 | 2011-04-28 | Google Inc. | Programming of dimm termination resistance values |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US20110282963A1 (en) * | 2010-05-11 | 2011-11-17 | Hitachi, Ltd. | Storage device and method of controlling storage device |
US20110307672A1 (en) * | 2009-03-06 | 2011-12-15 | Rambus Inc. | Memory interface with interleaved control information |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8140942B2 (en) | 2004-10-29 | 2012-03-20 | International Business Machines Corporation | System, method and storage medium for providing fault detection and correction in a memory subsystem |
US8296541B2 (en) | 2004-10-29 | 2012-10-23 | International Business Machines Corporation | Memory subsystem with positional read data latency |
US20120278681A1 (en) * | 2011-04-29 | 2012-11-01 | Freescale Semiconductor, Inc. | Selective error detection and error correction for a memory interface |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US8417900B1 (en) * | 2004-10-13 | 2013-04-09 | Marvell International Ltd. | Power save module for storage controllers |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US8566672B2 (en) | 2011-03-22 | 2013-10-22 | Freescale Semiconductor, Inc. | Selective checkbit modification for error correction |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US20140289455A1 (en) * | 2013-03-25 | 2014-09-25 | Dialog Semiconductor B.V. | Memory Patching Circuit |
US20150067437A1 (en) * | 2013-08-30 | 2015-03-05 | Kuljit S. Bains | Apparatus, method and system for reporting dynamic random access memory error information |
US8990657B2 (en) | 2011-06-14 | 2015-03-24 | Freescale Semiconductor, Inc. | Selective masking for error correction |
US8990660B2 (en) | 2010-09-13 | 2015-03-24 | Freescale Semiconductor, Inc. | Data processing system having end-to-end error correction and method therefor |
US9064600B2 (en) | 2004-05-06 | 2015-06-23 | Micron Technology, Inc. | Memory controller method and system compensating for memory cell data losses |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7607031B2 (en) * | 2006-03-28 | 2009-10-20 | Advanced Micro Devices, Inc. | Power management in a communication link |
US7617404B2 (en) * | 2006-03-28 | 2009-11-10 | Advanced Micro Devices, Inc. | In-band power management in a communication link |
US7917828B2 (en) * | 2006-12-28 | 2011-03-29 | Intel Corporation | Providing error correction coding for probed data |
US20080162918A1 (en) * | 2007-01-02 | 2008-07-03 | Nokia Corporation | Hide boot |
US7483325B2 (en) * | 2007-03-20 | 2009-01-27 | International Business Machines Corporation | Retention-time control and error management in a cache system comprising dynamic storage |
US7984357B2 (en) * | 2007-04-27 | 2011-07-19 | International Business Machines Corporation | Implementing minimized latency and maximized reliability when data traverses multiple buses |
US7730346B2 (en) * | 2007-04-30 | 2010-06-01 | Globalfoundries Inc. | Parallel instruction processing and operand integrity verification |
US8738993B2 (en) | 2010-12-06 | 2014-05-27 | Intel Corporation | Memory device on the fly CRC mode |
US9612901B2 (en) | 2012-03-30 | 2017-04-04 | Intel Corporation | Memories utilizing hybrid error correcting code techniques |
DE112012006154T5 (en) * | 2012-03-30 | 2015-02-05 | Intel Corporation | Memory using hybrid error correction code techniques |
US8887014B2 (en) | 2012-12-11 | 2014-11-11 | International Business Machines Corporation | Managing errors in a DRAM by weak cell encoding |
US8898544B2 (en) * | 2012-12-11 | 2014-11-25 | International Business Machines Corporation | DRAM error detection, evaluation, and correction |
US10073731B2 (en) * | 2013-11-27 | 2018-09-11 | Intel Corporation | Error correction in memory |
US10269445B1 (en) * | 2017-10-22 | 2019-04-23 | Nanya Technology Corporation | Memory device and operating method thereof |
US11726864B2 (en) * | 2020-03-17 | 2023-08-15 | Renesas Electronics Corporation | Data processing device and data processing method |
US20230342048A1 (en) * | 2022-04-21 | 2023-10-26 | Micron Technology, Inc. | Self-Refresh Arbitration |
Citations (95)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4433211A (en) * | 1981-11-04 | 1984-02-21 | Technical Communications Corporation | Privacy communication system employing time/frequency transformation |
US4598402A (en) * | 1982-12-25 | 1986-07-01 | Fujitsu Limited | System for treatment of single bit error in buffer storage unit |
US4766573A (en) * | 1986-03-18 | 1988-08-23 | Fujitsu Limited | Semiconductor memory device with error correcting circuit |
US4858236A (en) * | 1986-04-25 | 1989-08-15 | Mitsubishi Denki Kabushiki Kaisha | Method for error correction in memory system |
US4862463A (en) * | 1987-07-20 | 1989-08-29 | International Business Machines Corp. | Error correcting code for 8-bit-per-chip memory with reduced redundancy |
US4918692A (en) * | 1987-06-03 | 1990-04-17 | Mitsubishi Denki Kabushiki Kaisha | Automated error detection for multiple block memory array chip and correction thereof |
US4937830A (en) * | 1987-05-19 | 1990-06-26 | Fujitsu Limited | Semiconductor memory device having function of checking and correcting error of read-out data |
US5127014A (en) * | 1990-02-13 | 1992-06-30 | Hewlett-Packard Company | Dram on-chip error correction/detection |
US5278796A (en) * | 1991-04-12 | 1994-01-11 | Micron Technology, Inc. | Temperature-dependent DRAM refresh circuit |
US5291498A (en) * | 1991-01-29 | 1994-03-01 | Convex Computer Corporation | Error detecting method and apparatus for computer memory having multi-bit output memory circuits |
US5313624A (en) * | 1991-05-14 | 1994-05-17 | Next Computer, Inc. | DRAM multiplexer |
US5313475A (en) * | 1991-10-31 | 1994-05-17 | International Business Machines Corporation | ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme |
US5313425A (en) * | 1992-11-23 | 1994-05-17 | Samsung Electronics Co., Ltd. | Semiconductor memory device having an improved error correction capability |
US5313464A (en) * | 1989-07-06 | 1994-05-17 | Digital Equipment Corporation | Fault tolerant memory using bus bit aligned Reed-Solomon error correction code symbols |
US5321661A (en) * | 1991-11-20 | 1994-06-14 | Oki Electric Industry Co., Ltd. | Self-refreshing memory with on-chip timer test circuit |
US5335201A (en) * | 1991-04-15 | 1994-08-02 | Micron Technology, Inc. | Method for providing synchronous refresh cycles in self-refreshing interruptable DRAMs |
US5418796A (en) * | 1991-03-26 | 1995-05-23 | International Business Machines Corporation | Synergistic multiple bit error correction for memory of array chips |
US5428630A (en) * | 1993-07-01 | 1995-06-27 | Quantum Corp. | System and method for verifying the integrity of data written to a memory |
US5432802A (en) * | 1990-02-26 | 1995-07-11 | Nec Corporation | Information processing device having electrically erasable programmable read only memory with error check and correction circuit |
US5446695A (en) * | 1994-03-22 | 1995-08-29 | International Business Machines Corporation | Memory device with programmable self-refreshing and testing methods therefore |
US5481552A (en) * | 1993-12-30 | 1996-01-02 | International Business Machines Corporation | Method and structure for providing error correction code for 8-byte data words on SIMM cards |
US5509132A (en) * | 1990-04-13 | 1996-04-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof |
US5513135A (en) * | 1994-12-02 | 1996-04-30 | International Business Machines Corporation | Synchronous memory packaged in single/dual in-line memory module and method of fabrication |
US5515333A (en) * | 1991-10-29 | 1996-05-07 | Hitachi, Ltd. | Semiconductor memory |
US5600662A (en) * | 1993-09-21 | 1997-02-04 | Cirrus Logic, Inc. | Error correction method and apparatus for headers |
US5604703A (en) * | 1994-10-24 | 1997-02-18 | Nec Corporation | Semiconductor memory device with error check-correction function permitting reduced read-out time |
US5623506A (en) * | 1994-01-28 | 1997-04-22 | International Business Machines Corporation | Method and structure for providing error correction code within a system having SIMMs |
US5631914A (en) * | 1988-07-18 | 1997-05-20 | Canon Kabushiki Kaisha | Error correcting apparatus |
US5706225A (en) * | 1995-05-18 | 1998-01-06 | Siemens Aktiengesellschaft | Memory apparatus with dynamic memory cells having different capacitor values |
US5732092A (en) * | 1996-01-25 | 1998-03-24 | Mitsubishi Denki Kabushiki Kaisha | Method of refreshing flash memory data in flash disk card |
US5740188A (en) * | 1996-05-29 | 1998-04-14 | Compaq Computer Corporation | Error checking and correcting for burst DRAM devices |
US5754753A (en) * | 1992-06-11 | 1998-05-19 | Digital Equipment Corporation | Multiple-bit error correction in computer main memory |
US5761222A (en) * | 1994-09-30 | 1998-06-02 | Sgs-Thomson Microelectronics, S.R.L. | Memory device having error detection and correction function, and methods for reading, writing and erasing the memory device |
US5765185A (en) * | 1995-03-17 | 1998-06-09 | Atmel Corporation | EEPROM array with flash-like core having ECC or a write cache or interruptible load cycles |
US5784328A (en) * | 1996-12-23 | 1998-07-21 | Lsi Logic Corporation | Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array |
US5784391A (en) * | 1996-10-08 | 1998-07-21 | International Business Machines Corporation | Distributed memory system with ECC and method of operation |
US5864569A (en) * | 1996-10-18 | 1999-01-26 | Micron Technology, Inc. | Method and apparatus for performing error correction on data read from a multistate memory |
US5878059A (en) * | 1997-09-24 | 1999-03-02 | Emc Corporation | Method and apparatus for pipelining an error detection algorithm on an n-bit word stored in memory |
US5896404A (en) * | 1997-04-04 | 1999-04-20 | International Business Machines Corporation | Programmable burst length DRAM |
US5912906A (en) * | 1997-06-23 | 1999-06-15 | Sun Microsystems, Inc. | Method and apparatus for recovering from correctable ECC errors |
US6018817A (en) * | 1997-12-03 | 2000-01-25 | International Business Machines Corporation | Error correcting code retrofit method and apparatus for multiple memory configurations |
US6041430A (en) * | 1997-11-03 | 2000-03-21 | Sun Microsystems, Inc. | Error detection and correction code for data and check code fields |
US6041001A (en) * | 1999-02-25 | 2000-03-21 | Lexar Media, Inc. | Method of increasing data reliability of a flash memory device without compromising compatibility |
US6063694A (en) * | 1997-10-01 | 2000-05-16 | Nec Corporation | Field-effect transistor with a trench isolation structure and a method for manufacturing the same |
US6085283A (en) * | 1993-11-19 | 2000-07-04 | Kabushiki Kaisha Toshiba | Data selecting memory device and selected data transfer device |
US6092231A (en) * | 1998-06-12 | 2000-07-18 | Qlogic Corporation | Circuit and method for rapid checking of error correction codes using cyclic redundancy check |
US6101614A (en) * | 1994-05-24 | 2000-08-08 | Intel Corporation | Method and apparatus for automatically scrubbing ECC errors in memory via hardware |
US6199139B1 (en) * | 1998-01-27 | 2001-03-06 | International Business Machines Corporation | Refresh period control apparatus and method, and computer |
US6212631B1 (en) * | 1999-01-15 | 2001-04-03 | Dell Usa, L.P. | Method and apparatus for automatic L2 cache ECC configuration in a computer system |
US6216247B1 (en) * | 1998-05-29 | 2001-04-10 | Intel Corporation | 32-bit mode for a 64-bit ECC capable memory subsystem |
US6216246B1 (en) * | 1996-05-24 | 2001-04-10 | Jeng-Jye Shau | Methods to make DRAM fully compatible with SRAM using error correction code (ECC) mechanism |
US6219807B1 (en) * | 1997-11-14 | 2001-04-17 | Nec Corporation | Semiconductor memory device having an ECC circuit |
US6223309B1 (en) * | 1998-10-02 | 2001-04-24 | International Business Machines Corporation | Method and apparatus for ECC logic test |
US6233717B1 (en) * | 1997-12-31 | 2001-05-15 | Samsung Electronics Co., Ltd. | Multi-bit memory device having error check and correction circuit and method for checking and correcting data errors therein |
US6262925B1 (en) * | 1999-05-19 | 2001-07-17 | Nec Corporation | Semiconductor memory device with improved error correction |
US20010013924A1 (en) * | 1996-09-24 | 2001-08-16 | Osamu Yokoyama | Projector display comprising light source units |
US6279072B1 (en) * | 1999-07-22 | 2001-08-21 | Micron Technology, Inc. | Reconfigurable memory with selectable error correction storage |
US6349068B2 (en) * | 1999-04-14 | 2002-02-19 | Fujitsu Limited | Semiconductor memory device capable of reducing power consumption in self-refresh operation |
US6349390B1 (en) * | 1999-01-04 | 2002-02-19 | International Business Machines Corporation | On-board scrubbing of soft errors memory module |
US6353910B1 (en) * | 1999-04-09 | 2002-03-05 | International Business Machines Corporation | Method and apparatus for implementing error correction coding (ECC) in a dynamic random access memory utilizing vertical ECC storage |
US6397365B1 (en) * | 1999-05-18 | 2002-05-28 | Hewlett-Packard Company | Memory error correction using redundant sliced memory and standard ECC mechanisms |
US6397357B1 (en) * | 1996-10-08 | 2002-05-28 | Dell Usa, L.P. | Method of testing detection and correction capabilities of ECC memory controller |
US6438066B1 (en) * | 1998-11-27 | 2002-08-20 | Mitsubishi Denki Kabushiki Kaisha | Synchronous semiconductor memory device allowing control of operation mode in accordance with operation conditions of a system |
US6442644B1 (en) * | 1997-08-11 | 2002-08-27 | Advanced Memory International, Inc. | Memory system having synchronous-link DRAM (SLDRAM) devices and controller |
US20030009721A1 (en) * | 2001-07-06 | 2003-01-09 | International Business Machines Corporation | Method and system for background ECC scrubbing for a memory array |
US6510537B1 (en) * | 1998-08-07 | 2003-01-21 | Samsung Electronics Co., Ltd | Semiconductor memory device with an on-chip error correction circuit and a method for correcting a data error therein |
US6526537B2 (en) * | 1997-09-29 | 2003-02-25 | Nec Corporation | Storage for generating ECC and adding ECC to data |
US6557072B2 (en) * | 2001-05-10 | 2003-04-29 | Palm, Inc. | Predictive temperature compensation for memory devices systems and method |
US6556497B2 (en) * | 2001-03-08 | 2003-04-29 | Micron Technology, Inc. | Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs |
US6560155B1 (en) * | 2001-10-24 | 2003-05-06 | Micron Technology, Inc. | System and method for power saving memory refresh for dynamic random access memory devices after an extended interval |
US20030093744A1 (en) * | 2001-11-14 | 2003-05-15 | Monilithic System Technology, Inc. | Error correcting memory and method of operating same |
US20030097608A1 (en) * | 2001-11-20 | 2003-05-22 | Rodeheffer Thomas Lee | System and method for scrubbing errors in very large memories |
US20030101405A1 (en) * | 2001-11-21 | 2003-05-29 | Noboru Shibata | Semiconductor memory device |
US6591394B2 (en) * | 2000-12-22 | 2003-07-08 | Matrix Semiconductor, Inc. | Three-dimensional memory array and method for storing data bits and ECC bits therein |
US6594796B1 (en) * | 2000-06-30 | 2003-07-15 | Oak Technology, Inc. | Simultaneous processing for error detection and P-parity and Q-parity ECC encoding |
US6601211B1 (en) * | 1996-10-15 | 2003-07-29 | Micron Technology, Inc. | Write reduction in flash memory systems through ECC usage |
US20030149855A1 (en) * | 2001-12-05 | 2003-08-07 | Elpida Memory, Inc | Unbuffered memory system |
US6609236B2 (en) * | 1996-03-08 | 2003-08-19 | Hitachi, Ltd. | Semiconductor IC device having a memory and a logic circuit implemented with a single chip |
US6678860B1 (en) * | 1999-08-11 | 2004-01-13 | Samsung Electronics Co., Ltd. | Integrated circuit memory devices having error checking and correction circuits therein and methods of operating same |
US20040008562A1 (en) * | 2002-07-11 | 2004-01-15 | Elpida Memory, Inc | Semiconductor memory device |
US6697992B2 (en) * | 2000-08-14 | 2004-02-24 | Hitachi, Ltd. | Data storing method of dynamic RAM and semiconductor memory device |
US6697926B2 (en) * | 2001-06-06 | 2004-02-24 | Micron Technology, Inc. | Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device |
US6701480B1 (en) * | 2000-03-08 | 2004-03-02 | Rockwell Automation Technologies, Inc. | System and method for providing error check and correction in memory systems |
US6704230B1 (en) * | 2003-06-12 | 2004-03-09 | International Business Machines Corporation | Error detection and correction method and apparatus in a magnetoresistive random access memory |
US6715104B2 (en) * | 2000-07-25 | 2004-03-30 | International Business Machines Corporation | Memory access system |
US6715116B2 (en) * | 2000-01-26 | 2004-03-30 | Hewlett-Packard Company, L.P. | Memory data verify operation |
US20040064646A1 (en) * | 2002-09-26 | 2004-04-01 | Emerson Steven M. | Multi-port memory controller having independent ECC encoders |
US20040083334A1 (en) * | 2002-10-28 | 2004-04-29 | Sandisk Corporation | Method and apparatus for managing the integrity of data in non-volatile memory system |
US20040098654A1 (en) * | 2002-11-14 | 2004-05-20 | Der-Kant Cheng | FIFO memory with ECC function |
US6751143B2 (en) * | 2002-04-11 | 2004-06-15 | Micron Technology, Inc. | Method and system for low power refresh of dynamic random access memories |
US20040117723A1 (en) * | 2002-11-29 | 2004-06-17 | Foss Richard C. | Error correction scheme for memory |
US6754858B2 (en) * | 2001-03-29 | 2004-06-22 | International Business Machines Corporation | SDRAM address error detection method and apparatus |
US6775190B2 (en) * | 2001-08-28 | 2004-08-10 | Renesas Technology Corp. | Semiconductor memory device with detection circuit |
US20050099868A1 (en) * | 2003-11-07 | 2005-05-12 | Jong-Hoon Oh | Refresh for dynamic cells with weak retention |
US7171605B2 (en) * | 2002-02-01 | 2007-01-30 | International Business Machines Corporation | Check bit free error correction for sleep mode data retention |
Family Cites Families (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55150192A (en) | 1979-05-08 | 1980-11-21 | Nec Corp | Memory unit |
JPS61134988A (en) | 1984-12-04 | 1986-06-23 | Toshiba Corp | Error detecting/correction function controlling system of dynamic type memory |
JPS6246357A (en) | 1985-08-23 | 1987-02-28 | Hitachi Vlsi Eng Corp | Semiconductor memory device |
US4710934A (en) | 1985-11-08 | 1987-12-01 | Texas Instruments Incorporated | Random access memory with error correction capability |
KR970003710B1 (en) | 1987-09-04 | 1997-03-21 | 미다 가쓰시게 | Low noise semiconductor memory |
JPH01201736A (en) | 1988-02-08 | 1989-08-14 | Mitsubishi Electric Corp | Microcomputer |
JPH03162800A (en) | 1989-08-29 | 1991-07-12 | Mitsubishi Electric Corp | Semiconductor memory device |
US5307356A (en) | 1990-04-16 | 1994-04-26 | International Business Machines Corporation | Interlocked on-chip ECC system |
KR950003013B1 (en) | 1992-03-30 | 1995-03-29 | 삼성전자 주식회사 | Eeprom with error correcting circuit |
US5459742A (en) | 1992-06-11 | 1995-10-17 | Quantum Corporation | Solid state disk memory using storage devices with defects |
US5369651A (en) | 1992-06-30 | 1994-11-29 | Intel Corporation | Multiplexed byte enable bus for partial word writes to ECC protected memory |
JP2816512B2 (en) | 1992-07-27 | 1998-10-27 | 三菱電機株式会社 | Semiconductor storage device |
US5588112A (en) | 1992-12-30 | 1996-12-24 | Digital Equipment Corporation | DMA controller for memory scrubbing |
JP3328093B2 (en) | 1994-07-12 | 2002-09-24 | 三菱電機株式会社 | Error correction device |
US5455801A (en) | 1994-07-15 | 1995-10-03 | Micron Semiconductor, Inc. | Circuit having a control array of memory cells and a current source and a method for generating a self-refresh timing signal |
JP3714489B2 (en) * | 1995-03-03 | 2005-11-09 | 株式会社日立製作所 | Dynamic RAM and memory module |
US5841418A (en) | 1995-06-07 | 1998-11-24 | Cirrus Logic, Inc. | Dual displays having independent resolutions and refresh rates |
US5953278A (en) | 1996-07-11 | 1999-09-14 | Texas Instruments Incorporated | Data sequencing and registering in a four bit pre-fetch SDRAM |
US5808952A (en) | 1996-10-28 | 1998-09-15 | Silicon Magic Corporation | Adaptive auto refresh |
US5961660A (en) | 1997-03-03 | 1999-10-05 | International Business Machines Corporation | Method and apparatus for optimizing ECC memory performance |
US6279134B1 (en) | 1998-03-02 | 2001-08-21 | Hitachi, Ltd. | Storage device and storage subsystem for efficiently writing error correcting code |
US6009547A (en) | 1997-12-03 | 1999-12-28 | International Business Machines Corporation | ECC in memory arrays having subsequent insertion of content |
JP3194368B2 (en) | 1997-12-12 | 2001-07-30 | 日本電気株式会社 | Semiconductor memory device and driving method thereof |
US6085334A (en) | 1998-04-17 | 2000-07-04 | Motorola, Inc. | Method and apparatus for testing an integrated memory device |
US6125467A (en) | 1998-04-21 | 2000-09-26 | International Business Machines Corporation | Method and apparatus for partial word read through ECC block |
US6134167A (en) | 1998-06-04 | 2000-10-17 | Compaq Computer Corporation | Reducing power consumption in computer memory |
JP2000137983A (en) | 1998-08-26 | 2000-05-16 | Toshiba Corp | Semiconductor storage |
JP4105819B2 (en) | 1999-04-26 | 2008-06-25 | 株式会社ルネサステクノロジ | Storage device and memory card |
KR100322530B1 (en) | 1999-05-11 | 2002-03-18 | 윤종용 | Data Input Circuit of Semiconductor memory device &Data input Method using the same |
JP4421036B2 (en) | 1999-11-17 | 2010-02-24 | 富士通マイクロエレクトロニクス株式会社 | Data writing method for semiconductor memory device and semiconductor memory device |
JP4707803B2 (en) * | 2000-07-10 | 2011-06-22 | エルピーダメモリ株式会社 | Error rate determination method and semiconductor integrated circuit device |
JP3595495B2 (en) * | 2000-07-27 | 2004-12-02 | Necマイクロシステム株式会社 | Semiconductor storage device |
US6934199B2 (en) * | 2002-12-11 | 2005-08-23 | Micron Technology, Inc. | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency |
US7894289B2 (en) * | 2006-10-11 | 2011-02-22 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
US7900120B2 (en) * | 2006-10-18 | 2011-03-01 | Micron Technology, Inc. | Memory system and method using ECC with flag bit to identify modified data |
-
2004
- 2004-06-24 US US10/876,796 patent/US20060010339A1/en not_active Abandoned
-
2006
- 2006-05-11 US US11/433,217 patent/US7461320B2/en active Active
Patent Citations (99)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4433211A (en) * | 1981-11-04 | 1984-02-21 | Technical Communications Corporation | Privacy communication system employing time/frequency transformation |
US4598402A (en) * | 1982-12-25 | 1986-07-01 | Fujitsu Limited | System for treatment of single bit error in buffer storage unit |
US4766573A (en) * | 1986-03-18 | 1988-08-23 | Fujitsu Limited | Semiconductor memory device with error correcting circuit |
US4858236A (en) * | 1986-04-25 | 1989-08-15 | Mitsubishi Denki Kabushiki Kaisha | Method for error correction in memory system |
US4937830A (en) * | 1987-05-19 | 1990-06-26 | Fujitsu Limited | Semiconductor memory device having function of checking and correcting error of read-out data |
US4918692A (en) * | 1987-06-03 | 1990-04-17 | Mitsubishi Denki Kabushiki Kaisha | Automated error detection for multiple block memory array chip and correction thereof |
US4862463A (en) * | 1987-07-20 | 1989-08-29 | International Business Machines Corp. | Error correcting code for 8-bit-per-chip memory with reduced redundancy |
US5631914A (en) * | 1988-07-18 | 1997-05-20 | Canon Kabushiki Kaisha | Error correcting apparatus |
US5313464A (en) * | 1989-07-06 | 1994-05-17 | Digital Equipment Corporation | Fault tolerant memory using bus bit aligned Reed-Solomon error correction code symbols |
US5127014A (en) * | 1990-02-13 | 1992-06-30 | Hewlett-Packard Company | Dram on-chip error correction/detection |
US5432802A (en) * | 1990-02-26 | 1995-07-11 | Nec Corporation | Information processing device having electrically erasable programmable read only memory with error check and correction circuit |
US5509132A (en) * | 1990-04-13 | 1996-04-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof |
US5291498A (en) * | 1991-01-29 | 1994-03-01 | Convex Computer Corporation | Error detecting method and apparatus for computer memory having multi-bit output memory circuits |
US5418796A (en) * | 1991-03-26 | 1995-05-23 | International Business Machines Corporation | Synergistic multiple bit error correction for memory of array chips |
US5278796A (en) * | 1991-04-12 | 1994-01-11 | Micron Technology, Inc. | Temperature-dependent DRAM refresh circuit |
US5335201A (en) * | 1991-04-15 | 1994-08-02 | Micron Technology, Inc. | Method for providing synchronous refresh cycles in self-refreshing interruptable DRAMs |
US5313624A (en) * | 1991-05-14 | 1994-05-17 | Next Computer, Inc. | DRAM multiplexer |
US5515333A (en) * | 1991-10-29 | 1996-05-07 | Hitachi, Ltd. | Semiconductor memory |
US5313475A (en) * | 1991-10-31 | 1994-05-17 | International Business Machines Corporation | ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme |
US5321661A (en) * | 1991-11-20 | 1994-06-14 | Oki Electric Industry Co., Ltd. | Self-refreshing memory with on-chip timer test circuit |
US5754753A (en) * | 1992-06-11 | 1998-05-19 | Digital Equipment Corporation | Multiple-bit error correction in computer main memory |
US5313425A (en) * | 1992-11-23 | 1994-05-17 | Samsung Electronics Co., Ltd. | Semiconductor memory device having an improved error correction capability |
US5428630A (en) * | 1993-07-01 | 1995-06-27 | Quantum Corp. | System and method for verifying the integrity of data written to a memory |
US5600662A (en) * | 1993-09-21 | 1997-02-04 | Cirrus Logic, Inc. | Error correction method and apparatus for headers |
US6085283A (en) * | 1993-11-19 | 2000-07-04 | Kabushiki Kaisha Toshiba | Data selecting memory device and selected data transfer device |
US5481552A (en) * | 1993-12-30 | 1996-01-02 | International Business Machines Corporation | Method and structure for providing error correction code for 8-byte data words on SIMM cards |
US5623506A (en) * | 1994-01-28 | 1997-04-22 | International Business Machines Corporation | Method and structure for providing error correction code within a system having SIMMs |
US5446695A (en) * | 1994-03-22 | 1995-08-29 | International Business Machines Corporation | Memory device with programmable self-refreshing and testing methods therefore |
US6101614A (en) * | 1994-05-24 | 2000-08-08 | Intel Corporation | Method and apparatus for automatically scrubbing ECC errors in memory via hardware |
US5761222A (en) * | 1994-09-30 | 1998-06-02 | Sgs-Thomson Microelectronics, S.R.L. | Memory device having error detection and correction function, and methods for reading, writing and erasing the memory device |
US5604703A (en) * | 1994-10-24 | 1997-02-18 | Nec Corporation | Semiconductor memory device with error check-correction function permitting reduced read-out time |
US5513135A (en) * | 1994-12-02 | 1996-04-30 | International Business Machines Corporation | Synchronous memory packaged in single/dual in-line memory module and method of fabrication |
US5765185A (en) * | 1995-03-17 | 1998-06-09 | Atmel Corporation | EEPROM array with flash-like core having ECC or a write cache or interruptible load cycles |
US5706225A (en) * | 1995-05-18 | 1998-01-06 | Siemens Aktiengesellschaft | Memory apparatus with dynamic memory cells having different capacitor values |
US5732092A (en) * | 1996-01-25 | 1998-03-24 | Mitsubishi Denki Kabushiki Kaisha | Method of refreshing flash memory data in flash disk card |
US6609236B2 (en) * | 1996-03-08 | 2003-08-19 | Hitachi, Ltd. | Semiconductor IC device having a memory and a logic circuit implemented with a single chip |
US6216246B1 (en) * | 1996-05-24 | 2001-04-10 | Jeng-Jye Shau | Methods to make DRAM fully compatible with SRAM using error correction code (ECC) mechanism |
US5740188A (en) * | 1996-05-29 | 1998-04-14 | Compaq Computer Corporation | Error checking and correcting for burst DRAM devices |
US20010013924A1 (en) * | 1996-09-24 | 2001-08-16 | Osamu Yokoyama | Projector display comprising light source units |
US6397357B1 (en) * | 1996-10-08 | 2002-05-28 | Dell Usa, L.P. | Method of testing detection and correction capabilities of ECC memory controller |
US5784391A (en) * | 1996-10-08 | 1998-07-21 | International Business Machines Corporation | Distributed memory system with ECC and method of operation |
US6601211B1 (en) * | 1996-10-15 | 2003-07-29 | Micron Technology, Inc. | Write reduction in flash memory systems through ECC usage |
US6178537B1 (en) * | 1996-10-18 | 2001-01-23 | Micron Technology, Inc. | Method and apparatus for performing error correction on data read from a multistate memory |
US5864569A (en) * | 1996-10-18 | 1999-01-26 | Micron Technology, Inc. | Method and apparatus for performing error correction on data read from a multistate memory |
US5784328A (en) * | 1996-12-23 | 1998-07-21 | Lsi Logic Corporation | Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array |
US5896404A (en) * | 1997-04-04 | 1999-04-20 | International Business Machines Corporation | Programmable burst length DRAM |
US5912906A (en) * | 1997-06-23 | 1999-06-15 | Sun Microsystems, Inc. | Method and apparatus for recovering from correctable ECC errors |
US6442644B1 (en) * | 1997-08-11 | 2002-08-27 | Advanced Memory International, Inc. | Memory system having synchronous-link DRAM (SLDRAM) devices and controller |
US5878059A (en) * | 1997-09-24 | 1999-03-02 | Emc Corporation | Method and apparatus for pipelining an error detection algorithm on an n-bit word stored in memory |
US6526537B2 (en) * | 1997-09-29 | 2003-02-25 | Nec Corporation | Storage for generating ECC and adding ECC to data |
US6063694A (en) * | 1997-10-01 | 2000-05-16 | Nec Corporation | Field-effect transistor with a trench isolation structure and a method for manufacturing the same |
US6041430A (en) * | 1997-11-03 | 2000-03-21 | Sun Microsystems, Inc. | Error detection and correction code for data and check code fields |
US6219807B1 (en) * | 1997-11-14 | 2001-04-17 | Nec Corporation | Semiconductor memory device having an ECC circuit |
US6018817A (en) * | 1997-12-03 | 2000-01-25 | International Business Machines Corporation | Error correcting code retrofit method and apparatus for multiple memory configurations |
US6233717B1 (en) * | 1997-12-31 | 2001-05-15 | Samsung Electronics Co., Ltd. | Multi-bit memory device having error check and correction circuit and method for checking and correcting data errors therein |
US6199139B1 (en) * | 1998-01-27 | 2001-03-06 | International Business Machines Corporation | Refresh period control apparatus and method, and computer |
US6216247B1 (en) * | 1998-05-29 | 2001-04-10 | Intel Corporation | 32-bit mode for a 64-bit ECC capable memory subsystem |
US6092231A (en) * | 1998-06-12 | 2000-07-18 | Qlogic Corporation | Circuit and method for rapid checking of error correction codes using cyclic redundancy check |
US6510537B1 (en) * | 1998-08-07 | 2003-01-21 | Samsung Electronics Co., Ltd | Semiconductor memory device with an on-chip error correction circuit and a method for correcting a data error therein |
US6223309B1 (en) * | 1998-10-02 | 2001-04-24 | International Business Machines Corporation | Method and apparatus for ECC logic test |
US6438066B1 (en) * | 1998-11-27 | 2002-08-20 | Mitsubishi Denki Kabushiki Kaisha | Synchronous semiconductor memory device allowing control of operation mode in accordance with operation conditions of a system |
US6349390B1 (en) * | 1999-01-04 | 2002-02-19 | International Business Machines Corporation | On-board scrubbing of soft errors memory module |
US6212631B1 (en) * | 1999-01-15 | 2001-04-03 | Dell Usa, L.P. | Method and apparatus for automatic L2 cache ECC configuration in a computer system |
US6041001A (en) * | 1999-02-25 | 2000-03-21 | Lexar Media, Inc. | Method of increasing data reliability of a flash memory device without compromising compatibility |
US6353910B1 (en) * | 1999-04-09 | 2002-03-05 | International Business Machines Corporation | Method and apparatus for implementing error correction coding (ECC) in a dynamic random access memory utilizing vertical ECC storage |
US6349068B2 (en) * | 1999-04-14 | 2002-02-19 | Fujitsu Limited | Semiconductor memory device capable of reducing power consumption in self-refresh operation |
US6397365B1 (en) * | 1999-05-18 | 2002-05-28 | Hewlett-Packard Company | Memory error correction using redundant sliced memory and standard ECC mechanisms |
US6262925B1 (en) * | 1999-05-19 | 2001-07-17 | Nec Corporation | Semiconductor memory device with improved error correction |
US6397290B1 (en) * | 1999-07-22 | 2002-05-28 | Micron Technology, Inc. | Reconfigurable memory with selectable error correction storage |
US6584543B2 (en) * | 1999-07-22 | 2003-06-24 | Micron Technology, Inc. | Reconfigurable memory with selectable error correction storage |
US20030070054A1 (en) * | 1999-07-22 | 2003-04-10 | Williams Brett L. | Reconfigurable memory with selectable error correction storage |
US6279072B1 (en) * | 1999-07-22 | 2001-08-21 | Micron Technology, Inc. | Reconfigurable memory with selectable error correction storage |
US6678860B1 (en) * | 1999-08-11 | 2004-01-13 | Samsung Electronics Co., Ltd. | Integrated circuit memory devices having error checking and correction circuits therein and methods of operating same |
US6715116B2 (en) * | 2000-01-26 | 2004-03-30 | Hewlett-Packard Company, L.P. | Memory data verify operation |
US6701480B1 (en) * | 2000-03-08 | 2004-03-02 | Rockwell Automation Technologies, Inc. | System and method for providing error check and correction in memory systems |
US6594796B1 (en) * | 2000-06-30 | 2003-07-15 | Oak Technology, Inc. | Simultaneous processing for error detection and P-parity and Q-parity ECC encoding |
US6715104B2 (en) * | 2000-07-25 | 2004-03-30 | International Business Machines Corporation | Memory access system |
US6697992B2 (en) * | 2000-08-14 | 2004-02-24 | Hitachi, Ltd. | Data storing method of dynamic RAM and semiconductor memory device |
US6591394B2 (en) * | 2000-12-22 | 2003-07-08 | Matrix Semiconductor, Inc. | Three-dimensional memory array and method for storing data bits and ECC bits therein |
US6556497B2 (en) * | 2001-03-08 | 2003-04-29 | Micron Technology, Inc. | Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs |
US6754858B2 (en) * | 2001-03-29 | 2004-06-22 | International Business Machines Corporation | SDRAM address error detection method and apparatus |
US6557072B2 (en) * | 2001-05-10 | 2003-04-29 | Palm, Inc. | Predictive temperature compensation for memory devices systems and method |
US6697926B2 (en) * | 2001-06-06 | 2004-02-24 | Micron Technology, Inc. | Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device |
US20030009721A1 (en) * | 2001-07-06 | 2003-01-09 | International Business Machines Corporation | Method and system for background ECC scrubbing for a memory array |
US6775190B2 (en) * | 2001-08-28 | 2004-08-10 | Renesas Technology Corp. | Semiconductor memory device with detection circuit |
US6560155B1 (en) * | 2001-10-24 | 2003-05-06 | Micron Technology, Inc. | System and method for power saving memory refresh for dynamic random access memory devices after an extended interval |
US20030093744A1 (en) * | 2001-11-14 | 2003-05-15 | Monilithic System Technology, Inc. | Error correcting memory and method of operating same |
US20030097608A1 (en) * | 2001-11-20 | 2003-05-22 | Rodeheffer Thomas Lee | System and method for scrubbing errors in very large memories |
US20030101405A1 (en) * | 2001-11-21 | 2003-05-29 | Noboru Shibata | Semiconductor memory device |
US20030149855A1 (en) * | 2001-12-05 | 2003-08-07 | Elpida Memory, Inc | Unbuffered memory system |
US7171605B2 (en) * | 2002-02-01 | 2007-01-30 | International Business Machines Corporation | Check bit free error correction for sleep mode data retention |
US6751143B2 (en) * | 2002-04-11 | 2004-06-15 | Micron Technology, Inc. | Method and system for low power refresh of dynamic random access memories |
US20040008562A1 (en) * | 2002-07-11 | 2004-01-15 | Elpida Memory, Inc | Semiconductor memory device |
US20040064646A1 (en) * | 2002-09-26 | 2004-04-01 | Emerson Steven M. | Multi-port memory controller having independent ECC encoders |
US20040083334A1 (en) * | 2002-10-28 | 2004-04-29 | Sandisk Corporation | Method and apparatus for managing the integrity of data in non-volatile memory system |
US20040098654A1 (en) * | 2002-11-14 | 2004-05-20 | Der-Kant Cheng | FIFO memory with ECC function |
US20040117723A1 (en) * | 2002-11-29 | 2004-06-17 | Foss Richard C. | Error correction scheme for memory |
US6704230B1 (en) * | 2003-06-12 | 2004-03-09 | International Business Machines Corporation | Error detection and correction method and apparatus in a magnetoresistive random access memory |
US20050099868A1 (en) * | 2003-11-07 | 2005-05-12 | Jong-Hoon Oh | Refresh for dynamic cells with weak retention |
Cited By (157)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9064600B2 (en) | 2004-05-06 | 2015-06-23 | Micron Technology, Inc. | Memory controller method and system compensating for memory cell data losses |
US20080002503A1 (en) * | 2004-07-15 | 2008-01-03 | Klein Dean A | Method and system for controlling refresh to avoid memory cell data losses |
US8279683B2 (en) | 2004-07-15 | 2012-10-02 | Micron Technology, Inc. | Digit line comparison circuits |
US8446783B2 (en) | 2004-07-15 | 2013-05-21 | Micron Technology, Inc. | Digit line comparison circuits |
US7898892B2 (en) | 2004-07-15 | 2011-03-01 | Micron Technology, Inc. | Method and system for controlling refresh to avoid memory cell data losses |
US7765368B2 (en) | 2004-07-30 | 2010-07-27 | International Business Machines Corporation | System, method and storage medium for providing a serialized memory interface with a bus repeater |
US20060075296A1 (en) * | 2004-09-30 | 2006-04-06 | Menon Sankaran M | Method, apparatus and system for data integrity of state retentive elements under low power modes |
US8417900B1 (en) * | 2004-10-13 | 2013-04-09 | Marvell International Ltd. | Power save module for storage controllers |
US7325099B2 (en) * | 2004-10-27 | 2008-01-29 | Intel Corporation | Method and apparatus to enable DRAM to support low-latency access via vertical caching |
US20060090039A1 (en) * | 2004-10-27 | 2006-04-27 | Sanjeev Jain | Method and apparatus to enable DRAM to support low-latency access via vertical caching |
US8140942B2 (en) | 2004-10-29 | 2012-03-20 | International Business Machines Corporation | System, method and storage medium for providing fault detection and correction in a memory subsystem |
US8589769B2 (en) | 2004-10-29 | 2013-11-19 | International Business Machines Corporation | System, method and storage medium for providing fault detection and correction in a memory subsystem |
US8296541B2 (en) | 2004-10-29 | 2012-10-23 | International Business Machines Corporation | Memory subsystem with positional read data latency |
US7669010B2 (en) | 2004-11-08 | 2010-02-23 | International Business Machines Corporation | Prefetch miss indicator for cache coherence directory misses on external caches |
US20060101209A1 (en) * | 2004-11-08 | 2006-05-11 | Lais Eric N | Prefetch miss indicator for cache coherence directory misses on external caches |
US20080195820A1 (en) * | 2004-11-08 | 2008-08-14 | International Business Machines Corporation | Prefetch miss indicator for cache coherence directory misses on external caches |
US7395375B2 (en) * | 2004-11-08 | 2008-07-01 | International Business Machines Corporation | Prefetch miss indicator for cache coherence directory misses on external caches |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US20080025137A1 (en) * | 2005-06-24 | 2008-01-31 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US20070014168A1 (en) * | 2005-06-24 | 2007-01-18 | Rajan Suresh N | Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies |
US8615679B2 (en) | 2005-06-24 | 2013-12-24 | Google Inc. | Memory modules with reliability and serviceability functions |
US8386833B2 (en) | 2005-06-24 | 2013-02-26 | Google Inc. | Memory systems and memory modules |
US20070050530A1 (en) * | 2005-06-24 | 2007-03-01 | Rajan Suresh N | Integrated memory core and memory interface circuit |
US20080027702A1 (en) * | 2005-06-24 | 2008-01-31 | Metaram, Inc. | System and method for simulating a different number of memory circuits |
US20070058410A1 (en) * | 2005-09-02 | 2007-03-15 | Rajan Suresh N | Methods and apparatus of stacking DRAMs |
US20070058471A1 (en) * | 2005-09-02 | 2007-03-15 | Rajan Suresh N | Methods and apparatus of stacking DRAMs |
US8582339B2 (en) | 2005-09-02 | 2013-11-12 | Google Inc. | System including memory stacks |
US20080170425A1 (en) * | 2005-09-02 | 2008-07-17 | Rajan Suresh N | Methods and apparatus of stacking drams |
US8619452B2 (en) | 2005-09-02 | 2013-12-31 | Google Inc. | Methods and apparatus of stacking DRAMs |
US8811065B2 (en) | 2005-09-02 | 2014-08-19 | Google Inc. | Performing error detection on DRAMs |
US7934115B2 (en) | 2005-10-31 | 2011-04-26 | International Business Machines Corporation | Deriving clocks in a memory system |
US8151042B2 (en) | 2005-11-28 | 2012-04-03 | International Business Machines Corporation | Method and system for providing identification tags in a memory system having indeterminate data response times |
US8145868B2 (en) | 2005-11-28 | 2012-03-27 | International Business Machines Corporation | Method and system for providing frame start indication in a memory system having indeterminate read data latency |
US7685392B2 (en) | 2005-11-28 | 2010-03-23 | International Business Machines Corporation | Providing indeterminate read data latency in a memory system |
US8327105B2 (en) | 2005-11-28 | 2012-12-04 | International Business Machines Corporation | Providing frame start indication in a memory system having indeterminate read data latency |
US8495328B2 (en) | 2005-11-28 | 2013-07-23 | International Business Machines Corporation | Providing frame start indication in a memory system having indeterminate read data latency |
US8797779B2 (en) | 2006-02-09 | 2014-08-05 | Google Inc. | Memory module with memory stack and interface with enhanced capabilites |
US8566556B2 (en) | 2006-02-09 | 2013-10-22 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US20080126690A1 (en) * | 2006-02-09 | 2008-05-29 | Rajan Suresh N | Memory module with memory stack |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US20080109595A1 (en) * | 2006-02-09 | 2008-05-08 | Rajan Suresh N | System and method for reducing command scheduling constraints of memory circuits |
US9542353B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US9727458B2 (en) | 2006-02-09 | 2017-08-08 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US20070204075A1 (en) * | 2006-02-09 | 2007-08-30 | Rajan Suresh N | System and method for reducing command scheduling constraints of memory circuits |
US20070195613A1 (en) * | 2006-02-09 | 2007-08-23 | Rajan Suresh N | Memory module with memory stack and interface with enhanced capabilities |
US20080120443A1 (en) * | 2006-02-09 | 2008-05-22 | Suresh Natarajan Rajan | System and method for reducing command scheduling constraints of memory circuits |
US8595419B2 (en) | 2006-07-31 | 2013-11-26 | Google Inc. | Memory apparatus operable to perform a power-saving operation |
US8972673B2 (en) | 2006-07-31 | 2015-03-03 | Google Inc. | Power management of memory circuits by virtual memory simulation |
US20080025136A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | System and method for storing at least a portion of information received in association with a first operation for use in performing a second operation |
US20080027697A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Memory circuit simulation system and method with power saving capabilities |
US20080104314A1 (en) * | 2006-07-31 | 2008-05-01 | Rajan Suresh N | Memory device with emulated characteristics |
US20080025123A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US20080027703A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Memory circuit simulation system and method with refresh capabilities |
US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US7730338B2 (en) | 2006-07-31 | 2010-06-01 | Google Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US7761724B2 (en) | 2006-07-31 | 2010-07-20 | Google Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US20090024790A1 (en) * | 2006-07-31 | 2009-01-22 | Suresh Natarajan Rajan | Memory circuit system and method |
US20100271888A1 (en) * | 2006-07-31 | 2010-10-28 | Google Inc. | System and Method for Delaying a Signal Communicated from a System to at Least One of a Plurality of Memory Circuits |
US20080025125A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US20080037353A1 (en) * | 2006-07-31 | 2008-02-14 | Metaram, Inc. | Interface circuit system and method for performing power saving operations during a command-related latency |
US20080025122A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Memory refresh system and method |
US20080239858A1 (en) * | 2006-07-31 | 2008-10-02 | Suresh Natarajan Rajan | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US20080239857A1 (en) * | 2006-07-31 | 2008-10-02 | Suresh Natarajan Rajan | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US20080056014A1 (en) * | 2006-07-31 | 2008-03-06 | Suresh Natarajan Rajan | Memory device with emulated characteristics |
US20080062773A1 (en) * | 2006-07-31 | 2008-03-13 | Suresh Natarajan Rajan | System and method for simulating an aspect of a memory circuit |
US8019589B2 (en) | 2006-07-31 | 2011-09-13 | Google Inc. | Memory apparatus operable to perform a power-saving operation |
US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US20080031030A1 (en) * | 2006-07-31 | 2008-02-07 | Metaram, Inc. | System and method for power management in memory systems |
US20080028136A1 (en) * | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
US20080025108A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US9047976B2 (en) | 2006-07-31 | 2015-06-02 | Google Inc. | Combined signal delay and power saving for use with a plurality of memory circuits |
US8566516B2 (en) | 2006-07-31 | 2013-10-22 | Google Inc. | Refresh management of memory modules |
US8671244B2 (en) | 2006-07-31 | 2014-03-11 | Google Inc. | Simulating a memory standard |
US20080123459A1 (en) * | 2006-07-31 | 2008-05-29 | Metaram, Inc. | Combined signal delay and power saving system and method for use with a plurality of memory circuits |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US8868829B2 (en) | 2006-07-31 | 2014-10-21 | Google Inc. | Memory circuit system and method |
US8112266B2 (en) | 2006-07-31 | 2012-02-07 | Google Inc. | Apparatus for simulating an aspect of a memory circuit |
US20080103753A1 (en) * | 2006-07-31 | 2008-05-01 | Rajan Suresh N | Memory device with emulated characteristics |
US20080126687A1 (en) * | 2006-07-31 | 2008-05-29 | Suresh Natarajan Rajan | Memory device with emulated characteristics |
US20080126689A1 (en) * | 2006-07-31 | 2008-05-29 | Suresh Natarajan Rajan | Memory device with emulated characteristics |
US20080126688A1 (en) * | 2006-07-31 | 2008-05-29 | Suresh Natarajan Rajan | Memory device with emulated characteristics |
US8154935B2 (en) | 2006-07-31 | 2012-04-10 | Google Inc. | Delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US20080028137A1 (en) * | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and Apparatus For Refresh Management of Memory Modules |
US8601204B2 (en) | 2006-07-31 | 2013-12-03 | Google Inc. | Simulating a refresh operation latency |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US20080126692A1 (en) * | 2006-07-31 | 2008-05-29 | Suresh Natarajan Rajan | Memory device with emulated characteristics |
US8280714B2 (en) | 2006-07-31 | 2012-10-02 | Google Inc. | Memory circuit simulation system and method with refresh capabilities |
US20080115006A1 (en) * | 2006-07-31 | 2008-05-15 | Michael John Sebastian Smith | System and method for adjusting the timing of signals associated with a memory system |
US20080028135A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Multiple-component memory interface system and method |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US20080109206A1 (en) * | 2006-07-31 | 2008-05-08 | Rajan Suresh N | Memory device with emulated characteristics |
US20080031072A1 (en) * | 2006-07-31 | 2008-02-07 | Metaram, Inc. | Power saving system and method for use with a plurality of memory circuits |
US8340953B2 (en) | 2006-07-31 | 2012-12-25 | Google, Inc. | Memory circuit simulation with power saving capabilities |
US8745321B2 (en) | 2006-07-31 | 2014-06-03 | Google Inc. | Simulating a memory standard |
US8631220B2 (en) | 2006-07-31 | 2014-01-14 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US7669086B2 (en) | 2006-08-02 | 2010-02-23 | International Business Machines Corporation | Systems and methods for providing collision detection in a memory system |
US20090119443A1 (en) * | 2006-08-15 | 2009-05-07 | International Business Machines Corporation | Methods for program directed memory access patterns |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US20080082763A1 (en) * | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US8370566B2 (en) | 2006-10-05 | 2013-02-05 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US8751732B2 (en) | 2006-10-05 | 2014-06-10 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US20080086588A1 (en) * | 2006-10-05 | 2008-04-10 | Metaram, Inc. | System and Method for Increasing Capacity, Performance, and Flexibility of Flash Storage |
US8977806B1 (en) | 2006-10-05 | 2015-03-10 | Google Inc. | Hybrid memory module |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8359517B2 (en) | 2006-10-11 | 2013-01-22 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
US20080092016A1 (en) * | 2006-10-11 | 2008-04-17 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
US8832522B2 (en) | 2006-10-11 | 2014-09-09 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
US20110138251A1 (en) * | 2006-10-11 | 2011-06-09 | Pawlowski J Thomas | Memory system and method using partial ecc to achieve low power refresh and fast access to data |
US9286161B2 (en) | 2006-10-11 | 2016-03-15 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
US7894289B2 (en) | 2006-10-11 | 2011-02-22 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
US8413007B2 (en) | 2006-10-18 | 2013-04-02 | Micron Technology, Inc. | Memory system and method using ECC with flag bit to identify modified data |
US20080109705A1 (en) * | 2006-10-18 | 2008-05-08 | Pawlowski J Thomas | Memory system and method using ECC with flag bit to identify modified data |
US8880974B2 (en) | 2006-10-18 | 2014-11-04 | Micron Technology, Inc. | Memory system and method using ECC with flag bit to identify modified data |
US7900120B2 (en) | 2006-10-18 | 2011-03-01 | Micron Technology, Inc. | Memory system and method using ECC with flag bit to identify modified data |
US8601341B2 (en) | 2006-10-18 | 2013-12-03 | Micron Technologies, Inc. | Memory system and method using ECC with flag bit to identify modified data |
US7870459B2 (en) | 2006-10-23 | 2011-01-11 | International Business Machines Corporation | High density high reliability memory module with power gating and a fault tolerant address and command bus |
US8446781B1 (en) | 2006-11-13 | 2013-05-21 | Google Inc. | Multi-rank partial width memory modules |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8760936B1 (en) | 2006-11-13 | 2014-06-24 | Google Inc. | Multi-rank partial width memory modules |
US20080162991A1 (en) * | 2007-01-02 | 2008-07-03 | International Business Machines Corporation | Systems and methods for improving serviceability of a memory system |
US7721140B2 (en) * | 2007-01-02 | 2010-05-18 | International Business Machines Corporation | Systems and methods for improving serviceability of a memory system |
US20090024789A1 (en) * | 2007-07-18 | 2009-01-22 | Suresh Natarajan Rajan | Memory circuit system and method |
US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
US20090083479A1 (en) * | 2007-08-01 | 2009-03-26 | Samsung Electronics Co., Ltd. | Multiport semiconductor memory device and associated refresh method |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
US8675429B1 (en) | 2007-11-16 | 2014-03-18 | Google Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US8705240B1 (en) | 2007-12-18 | 2014-04-22 | Google Inc. | Embossed heat spreader |
US8730670B1 (en) | 2007-12-18 | 2014-05-20 | Google Inc. | Embossed heat spreader |
US8631193B2 (en) | 2008-02-21 | 2014-01-14 | Google Inc. | Emulation of abstracted DIMMS using abstracted DRAMS |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US20090249148A1 (en) * | 2008-03-25 | 2009-10-01 | Micorn Technology, Inc. | Error-correction forced mode with m-sequence |
US8627163B2 (en) * | 2008-03-25 | 2014-01-07 | Micron Technology, Inc. | Error-correction forced mode with M-sequence |
US8762675B2 (en) | 2008-06-23 | 2014-06-24 | Google Inc. | Memory system for synchronous data transmission |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US8819356B2 (en) | 2008-07-25 | 2014-08-26 | Google Inc. | Configurable multirank memory system with interface circuit |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US20110307672A1 (en) * | 2009-03-06 | 2011-12-15 | Rambus Inc. | Memory interface with interleaved control information |
US20110095783A1 (en) * | 2009-06-09 | 2011-04-28 | Google Inc. | Programming of dimm termination resistance values |
US8169233B2 (en) | 2009-06-09 | 2012-05-01 | Google Inc. | Programming of DIMM termination resistance values |
US20110282963A1 (en) * | 2010-05-11 | 2011-11-17 | Hitachi, Ltd. | Storage device and method of controlling storage device |
US8990660B2 (en) | 2010-09-13 | 2015-03-24 | Freescale Semiconductor, Inc. | Data processing system having end-to-end error correction and method therefor |
US8566672B2 (en) | 2011-03-22 | 2013-10-22 | Freescale Semiconductor, Inc. | Selective checkbit modification for error correction |
US20120278681A1 (en) * | 2011-04-29 | 2012-11-01 | Freescale Semiconductor, Inc. | Selective error detection and error correction for a memory interface |
US8607121B2 (en) * | 2011-04-29 | 2013-12-10 | Freescale Semiconductor, Inc. | Selective error detection and error correction for a memory interface |
US8990657B2 (en) | 2011-06-14 | 2015-03-24 | Freescale Semiconductor, Inc. | Selective masking for error correction |
US20140289455A1 (en) * | 2013-03-25 | 2014-09-25 | Dialog Semiconductor B.V. | Memory Patching Circuit |
US20150067437A1 (en) * | 2013-08-30 | 2015-03-05 | Kuljit S. Bains | Apparatus, method and system for reporting dynamic random access memory error information |
Also Published As
Publication number | Publication date |
---|---|
US7461320B2 (en) | 2008-12-02 |
US20060206769A1 (en) | 2006-09-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7461320B2 (en) | Memory system and method having selective ECC during low power refresh | |
US8880974B2 (en) | Memory system and method using ECC with flag bit to identify modified data | |
US8832522B2 (en) | Memory system and method using partial ECC to achieve low power refresh and fast access to data | |
US7184352B2 (en) | Memory system and method using ECC to achieve low power refresh | |
US7526713B2 (en) | Low power cost-effective ECC memory system and method | |
US8446783B2 (en) | Digit line comparison circuits | |
US7428687B2 (en) | Memory controller method and system compensating for memory cell data losses |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KLEIN, DEAN A.;REEL/FRAME:015523/0964 Effective date: 20040604 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |