US20060019467A1 - Methods of fabricating integrated circuit chips for multi-chip packaging and wafers and chips formed thereby - Google Patents

Methods of fabricating integrated circuit chips for multi-chip packaging and wafers and chips formed thereby Download PDF

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Publication number
US20060019467A1
US20060019467A1 US11/147,677 US14767705A US2006019467A1 US 20060019467 A1 US20060019467 A1 US 20060019467A1 US 14767705 A US14767705 A US 14767705A US 2006019467 A1 US2006019467 A1 US 2006019467A1
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Prior art keywords
electrically insulating
holes
chip
semiconductor
insulating layer
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Abandoned
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US11/147,677
Inventor
In-Young Lee
Sung-min Sim
Dong-Hyeon Jang
Hyun-Soo Chung
Young-hee Song
Myeong-Soon Park
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority to JP2005204665A priority Critical patent/JP2006041512A/en
Priority to DE102005036646A priority patent/DE102005036646B4/en
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHUNG, HYUN-SOO, JANG, DONG-HYEON, LEE, IN-YOUNG, PARK, MYEONG-SOON, SIM, SUNG-MIN, SONG, YOUNG-HEE
Publication of US20060019467A1 publication Critical patent/US20060019467A1/en
Abandoned legal-status Critical Current

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Definitions

  • the present invention relates to methods of fabricating integrated circuit chips and, more particularly, to methods of fabricating integrated circuit chips suitable for multi-chip packaging.
  • Multi-chip package (MCP) technologies typically include methods of fabricating integrated circuit chips that may be combined side-by-side or stacked together within a single integrated circuit package or module.
  • MCP Multi-chip package
  • the use of MCP technologies can significantly increase the integration density of integrated circuits, including those that are used in hand-held and other small devices (e.g., cellular phones).
  • An example of an MCP technology that uses wiring plugs within penetrant apertures that extent through an integrated circuit chip is disclosed in U.S. Pat. No. 6,429,096 to Yanagida. These wiring plugs support the electrical interconnection of a plurality of chips that can be stacked vertically within a single integrated circuit package.
  • Another example of an MCP technology that uses through-holes is disclosed in U.S. Pat. No. 6,566,232 to Hara et al.
  • CSP chip scale packaging
  • CSP wafer-level chip-scale packaging
  • PCB printed circuit board
  • BGA ball-grid array
  • the principle advantage of WLCSP is that the IC-to-PC board inductance is minimized and the secondary advantages are the reduction in package size and manufacturing cycle time and the enhanced thermal conduction characteristics.
  • Another type of CSP technology which describes initially forming partial through-holes in a semiconductor substrate and then removing an underside surface of the substrate to expose the through-holes, is disclosed in Korean Laid Open Patent Application No. 2003-0023040.
  • FIG. 1 illustrates a cross-sectional view of a vertical stack 20 of first and second integrated circuit chips 10 a and 10 b that are electrically connected together.
  • This vertical stack 20 has some similarities to the vertical stack of chips illustrated at FIG. 12 of the aforementioned Korean Laid Open Patent Application No. 2003-0023040.
  • the first chip 10 a is illustrated as including a first semiconductor substrate 12 a having a first through-hole 17 a therein.
  • the first through-hole 17 a extends from an upper surface of the substrate 12 a to a lower surface of the substrate 12 a .
  • a first passivation layer 13 a is provided on the upper surface of the substrate 12 a .
  • This first passivation layer 13 a has an opening therein that exposes a first chip pad 11 a .
  • a first insulating layer 18 a is also provided. This first insulating layer 18 a extends on the first passivation layer 13 a and directly on sidewalls of the first through-hole 17 a .
  • a first metal layer 21 a is provided directly on the first chip pad 11 a and forms an electrical connection therewith. As illustrated, this first metal layer 21 a also extends on the first insulating layer 18 a and into the first through-hole 17 a .
  • the first through-hole 17 a is filled with a first electrode metal layer 22 a , which is electrically coupled to the first chip pad 11 a by the first metal layer 21 a .
  • the second chip 10 b is illustrated as including a second semiconductor substrate 12 b having a second through-hole 17 b therein.
  • the second through-hole 17 b extends from an upper surface of the substrate 12 b to a lower surface of the substrate 12 b .
  • a second passivation layer 13 b is provided on the upper surface of the substrate 12 b .
  • This second passivation layer 13 b has an opening therein that exposes a second chip pad 11 b .
  • a second insulating layer 18 b is also provided. This second insulating layer 18 b extends on the second passivation layer 13 b and directly on sidewalls of the second through-hole 17 b .
  • a second metal layer 21 b is provided directly on the second chip pad 11 b .
  • This second metal layer 21 b also extends on the second insulating layer 18 b and into the second through-hole 17 b .
  • the second through-hole 17 b is filled by a second electrode metal layer 22 b , which is electrically coupled to the second chip pad 11 b by the second metal layer 21 b.
  • An electrical interconnection is provided between the first and second integrated circuit chips 10 a and 10 b and the first and second chip pads 11 a and 11 b .
  • This electrical interconnection is provided by a first metal bump 24 a (e.g., solder ball), which electrically connects the first electrode metal layer 22 a to the second electrode metal layer 22 b .
  • a second metal bump 24 b is also provided to electrically connect the second electrode metal layer 22 b to an underlying chip, package or printed circuit board (not shown).
  • the first and second integrated circuit chips 10 a and 10 b may be formed from a common semiconductor wafer (not shown) containing integrated circuits therein and a plurality of chip pads thereon, which are partially covered by a passivation layer (shown as 13 a and 13 b in FIG. 1 ).
  • the first and second through-holes 17 a and 17 b may be formed in the semiconductor wafer using a laser drilling technique.
  • an insulating layer (shown as 18 a and 18 b in FIG. 1 ) is formed on the passivation layer and along sidewalls of the through-holes. This insulating layer may then be patterned to expose the chip pads.
  • a metal layer-(shown as 21 a and 21 b in FIG. 1 ) and an electrode metal layer (shown as 22 a and 22 b in FIG. 1 ) are then deposited in sequence on the insulating layer.
  • the electrode metal layer is deposited to a thickness sufficient to fill the through-holes.
  • the semiconductor wafer may be thinned by removing a portion of a bottom surface of the semiconductor wafer. This thinning operation may include conventional grinding, polishing and wet etching techniques that result in an exposure of the electrode metal layer within the through-holes.
  • the conventional fabrication step of laser drilling to form through-holes in a semiconductor wafer is a relatively lengthy process step that may require each hole to be formed one-at-a-time in sequence.
  • the drilling of holes may damage the semiconductor wafer and result in through-holes with tapered sidewall profiles.
  • the formation of tapered sidewall profiles may lead to the formation of electrode metal layers that are susceptible to defects (e.g., electrical disconnection).
  • a semiconductor substrate is provided having upper and lower faces thereon that extend to an outer edge thereof. At least a first contact pad is provided on a portion of the upper face extending adjacent the outer edge.
  • An electrically insulating region is provided on the outer edge of the semiconductor substrate. This electrically insulating region, which may surround an entire periphery of the semiconductor substrate, includes at least one through-hole that extends vertically through an entire thickness of the electrically insulating region and has a longitudinal axis that is substantially parallel to the outer edge of the semiconductor substrate.
  • a connection electrode is also provided.
  • connection electrode extends through the through-hole and is electrically connected to the first contact pad.
  • the electrically insulating layer may have a lower surface that is coplanar with the lower face of the semiconductor substrate and an upper surface that is above the upper face of the semiconductor substrate, which results in a length of the through-hole being greater than a thickness of the semiconductor substrate.
  • the electrically insulating layer may wrap around the outer edge and extend onto a passivation layer covering the semiconductor substrate.
  • Additional embodiments of the invention include a semiconductor chip having a peripheral edge defined by an electrically insulating region having interconnect through-holes therein.
  • the semiconductor chip includes a semiconductor substrate having upper and lower faces thereon that extend to an outer edge thereof.
  • An electrically insulating region is provided on the outer edge of the semiconductor substrate.
  • the electrically insulating region has a through-hole therein that is filled within a connection electrode.
  • a solder bump is also provided. The solder bump is electrically connected to a portion of the connection electrode extending adjacent a bottom of the through-hole.
  • Still further embodiments of the invention include methods of fabricating a plurality of integrated circuit chips from a semiconductor wafer. These methods include forming a plurality of crisscrossing grooves in a semiconductor wafer having a plurality of contact pads thereon. The criss-crossing grooves are then filled with an electrically insulating layer. The electrically insulating layer is patterned to define at least first and second through-holes therein, which extend into a first one of the criss-crossing groves. The first and second through-holes are filled with first and second through-chip connection electrodes, respectively. The semiconductor wafer is then diced into a plurality of integrated circuit chips. This dicing step may be performed by cutting through the electrically insulating layer in a criss-crossing pattern that overlaps with the locations of the crisscrossing grooves.
  • the dicing step is preceded by the step of removing an underside of the semiconductor wafer to thereby expose the first and second through-chip connection electrodes and the electrically insulating layer.
  • the step of filling the first and second through-holes may also include depositing a base metal layer that extends on the electrically insulating layer and lines the first and second through-holes and then electroplating the first and second through-chip connection electrodes into the first and second through-holes using the base metal layer as an electroplating electrode.
  • the base metal layer may then be etched back using the first and second through-chip connection electrodes as an etching mask.
  • FIG. 1 is a cross-sectional view of a stack of integrated circuit chips that is compatible with chip scale packaging technologies, according to the prior art.
  • FIG. 2 is a plan view of a semiconductor wafer that may be processed in accordance with the methods of FIGS. 3-14 herein.
  • FIGS. 3-14 are cross-sectional views of intermediate structures that illustrate methods of forming integrated circuit chips according to embodiments of the present invention.
  • FIG. 15 is a cross-sectional view of a stack of integrated circuit chips formed in accordance with the methods of FIGS. 3-14 .
  • FIG. 2 a semiconductor wafer 30 is illustrated.
  • This semiconductor wafer 30 includes a semiconductor substrate 32 (e.g., silicon substrate) having a primary surface 35 thereon, which is also described herein as an upper face of the substrate 32 .
  • a plurality of semiconductor chips 34 may be formed from the semiconductor wafer 30 by dicing the semiconductor wafer 30 along crisscrossing scribe lanes 36 (a/k/a dicing streets) to thereby form a plurality of separate semiconductor chips 34 .
  • FIG. 3 is a plan view of a portion of the semiconductor wafer 30 of FIG. 2 and FIG. 4 is a cross-sectional view of the portion of FIG. 3 , taken along line 4 - 4 ′.
  • FIG. 3 illustrates peripheral portions of adjacent integrated circuit devices that are separated from each other by a scribe lane 36 .
  • Each integrated circuit device includes respective contact pads 31 on the primary surface 35 . These pads 31 are illustrated as extending adjacent one side of each of the illustrated integrated circuit devices. In other embodiments of the present invention, other pads (not shown) may also be provided adjacent other sides of the integrated circuit devices.
  • a surface passivation layer 33 is also illustrated as extending across the primary surface 35 of the semiconductor wafer 30 .
  • the pads 31 may be made of aluminum or copper, for example, and the passivation layer 33 may be made of electrically insulating materials such as silicon oxide, silicon nitride and silicon oxynitride.
  • This passivation layer 33 may be formed as a relatively thick electrically insulating layer that covers multiple underlying layers of metallization, interconnects, interlayer insulating layers and active devices (not shown), for example.
  • FIG. 4 also illustrates the position of a scribe lane 36 , which extends between two portions of the substrate 32 that will ultimately constitute separate semiconductor chips 34 after a final wafer dicing step is performed.
  • a series of deep criss-crossing grooves 37 are formed along the scribe lanes 36 .
  • These grooves 37 may have a width equal to about the width of the scribe lanes 36 .
  • the depth of these grooves 37 may be a function of the amount of the underside surface 39 of the semiconductor wafer 30 that is to be removed prior to wafer dicing. In some embodiments of the invention, the depth of the grooves 37 may be in the range from about 30 microns to about 300 microns.
  • These grooves 37 may be formed using a wafer sawing technique and/or a wafer etching technique.
  • a relatively thick electrically insulating layer 38 is then formed as a blanket layer on the primary surface of the semiconductor wafer 30 .
  • This electrically insulating layer 38 is of sufficient thickness to completely fill the grooves 37 and cover adjacent portions of the substrate 32 , as illustrated by FIG. 6 .
  • the electrically insulating layer 38 may be formed as a silicon oxide layer or as a polyimide layer, for example.
  • the electrically insulating layer 38 is selectively removed to define a plurality of through-holes 41 therein (i.e., connection holes), which are located in the scribe lanes 36 and sufficiently deep to expose the bottoms of the grooves 37 , and expose the contact pads 31 .
  • This removal step may be performed as a photolithographically-defined etching step, which results in through-holes 41 having substantially vertical sidewalls and uniform diameters.
  • These through-holes 41 may have diameters in a range from about 10 microns to about 50 microns.
  • the electrically insulating layer 38 is also formed of a material that has good adhesive strength to the substrate 32 , which inhibits detachment and/or delamination of the insulating layer 38 during subsequent processing and packaging. Moreover, by using a selective etching step that processes the entire wafer 30 at the same time, significant process time savings can be achieved because all of the through-holes 41 may be formed at the same time and all of the contact pads 31 may be exposed at the same time.
  • a blanket base metal layer 42 may be deposited on the wafer 30 . As illustrated by FIG. 8 , this base metal layer 42 is illustrated as contacting upper surfaces of the exposed contact pads 31 and lining the bottoms and sidewalls of the through-holes 41 .
  • the base metal layer 42 which should be chosen to have good adhesive properties with the underlying electrically insulating layer 38 , may be formed using a sputtering technique, for example, and may have a thickness in a range from about 0.05 microns to about 1 micron. In some embodiments of the present invention, the base metal layer 42 may be a composite of two or more metal layers.
  • the first of these metal layers within the composite may be chromium, titanium or other metal layer having good adhesive properties with the electrically insulating layer 38 and the second of these metal layers may be silver, gold, copper, nickel, palladium, platinum or other metal layer having good adhesive properties with a subsequently formed connection electrode.
  • a blanket layer of photoresist material is deposited and patterned to define a photoresist mask 51 having a plurality of openings 52 therein. These openings 52 expose portions of the base metal layer 42 extending over each contact pad 31 and its corresponding through-hole 41 .
  • electrode metal layers 43 are formed to completely fill respective openings 52 in the photoresist mask 51 .
  • These electrode metal layers 43 may be formed using an electroplating technique, which includes using the base metal layer 42 as a plating electrode, or another selective deposition technique.
  • Electrode metal layers 43 which represent respective connection electrodes, may be formed of silver, gold, copper, nickel, palladium, platinum and alloys thereof or other suitable high conductivity materials.
  • the photoresist mask 51 is then removed to thereby expose portions of the base metal layer 42 .
  • These exposed portions of the base metal layer 42 are then selectively removed using an etching step and the electrode metal layers 43 as etching masks. This etching step causes portions of the electrically insulating layer 38 to be exposed and the electrode metal layers 43 to become electrically disconnected from each other.
  • a wafer thinning step is performed to expose portions of the electrode metal layers 43 extending to the bottoms of the through-holes 41 .
  • This wafer thinning step may be performed using a grinding wheel 53 to remove a portion of the underside surface 39 of the semiconductor wafer 30 .
  • wet etching may be used to remove portions of the underside surface 39 of the semiconductor wafer 30 .
  • the portion of the underside surface 39 of the semiconductor wafer 30 that is removed may be substantial. For example, if the semiconductor wafer 30 has a thickness of about 700 microns prior to wafer thinning, it may only have a thickness of about 100 microns (or less) after wafer thinning.
  • each electrode metal layer 43 and corresponding base metal layer 42 provide a high conductivity electrical path from a corresponding contact pad 31 to an underside of the semiconductor wafer 30 .
  • the wafer thinning step may be followed by the step of applying an adhesive tape 54 (e.g., ultraviolet adhesive tape) to the entire underside surface 39 of the thinned semiconductor wafer 30 .
  • This tape 54 preserves the integrity of the semiconductor wafer 30 during subsequent processing steps (e.g., wafer dicing).
  • the semiconductor wafer 30 is then diced into a plurality of separate integrated circuit chips 60 by sawing the wafer along the center of the scribe lanes 36 using a cutting tool 55 .
  • a cross-sectional view of a stack 70 of integrated circuit chips 60 a and 60 b formed in accordance with the methods of FIGS. 3-14 uses a first metallic (e.g., solder) bump 45 a to electrically connect an upper connection electrode 43 a associated with an upper chip 60 a to a lower connection electrode 43 b associated with a lower chip 60 b .
  • a second metallic bump 45 b may also be provided to support mounting and electrical connection of the stack 70 to a printed circuit board (PCB) (not shown). In this manner, the second metallic bump 45 b operates as a terminal to the stack 70 .
  • These first and second metallic bumps 45 a and 45 b may be formed using an electroplating or other metal bump forming technique.

Abstract

Methods of forming integrated circuit chips include forming a plurality of criss-crossing grooves in a semiconductor wafer having a plurality of contact pads thereon and filling the criss-crossing grooves with an electrically insulating layer. The electrically insulating layer is then patterned to define at least first and second through-holes therein that extend in a first one of the criss-crossing groves. The first and second through-holes are then filled with first and second through-chip connection electrodes, respectively. The semiconductor wafer is then diced into a plurality of integrated circuit chips by cutting through the electrically insulating layer in a criss-crossing pattern that overlaps with the locations of the criss-crossing grooves.

Description

    REFERENCE TO PRIORITY APPLICATION
  • This application claims priority to Korean Application Serial No. 2004-58689, filed Jul. 23, 2004, the disclosure of which is hereby incorporated herein by reference.
    • FIELD OF THE INVENTION
  • The present invention relates to methods of fabricating integrated circuit chips and, more particularly, to methods of fabricating integrated circuit chips suitable for multi-chip packaging.
    • BACKGROUND OF THE INVENTION
  • Multi-chip package (MCP) technologies typically include methods of fabricating integrated circuit chips that may be combined side-by-side or stacked together within a single integrated circuit package or module. The use of MCP technologies can significantly increase the integration density of integrated circuits, including those that are used in hand-held and other small devices (e.g., cellular phones). An example of an MCP technology that uses wiring plugs within penetrant apertures that extent through an integrated circuit chip is disclosed in U.S. Pat. No. 6,429,096 to Yanagida. These wiring plugs support the electrical interconnection of a plurality of chips that can be stacked vertically within a single integrated circuit package. Another example of an MCP technology that uses through-holes is disclosed in U.S. Pat. No. 6,566,232 to Hara et al.
  • Other packaging technologies that seek to increase the integration densities of integrated circuit chips on a substrate (e.g., printed circuit board (PCB)) include chip scale packaging (CSP) technologies. These CSP technologies seek to increase integration levels using packages that have very small form factors and are nearly the same size as the integrated circuit chip(s) they enclose. One commonly accepted requirement of a CSP package requires that it have a lateral footprint that is no greater than about 1.2 times the size of the semiconductor chip it encloses. An example of a CSP packaging technology is disclosed in U.S. Pat. No. 6,774,475 to Blackshear et al. One type of CSP technology includes wafer-level chip-scale packaging (WLCSP), which enables an integrated circuit chip to be mounted face-down to a printed circuit board (PCB), with the chip's pads connected to the board's pads through individual solder balls without needing any underfill material. This technology differ from other ball-grid array (BGA) technologies because there is typically no bond wires or interposer connections. The principle advantage of WLCSP is that the IC-to-PC board inductance is minimized and the secondary advantages are the reduction in package size and manufacturing cycle time and the enhanced thermal conduction characteristics. Another type of CSP technology, which describes initially forming partial through-holes in a semiconductor substrate and then removing an underside surface of the substrate to expose the through-holes, is disclosed in Korean Laid Open Patent Application No. 2003-0023040.
  • FIG. 1 illustrates a cross-sectional view of a vertical stack 20 of first and second integrated circuit chips 10 a and 10 b that are electrically connected together. This vertical stack 20 has some similarities to the vertical stack of chips illustrated at FIG. 12 of the aforementioned Korean Laid Open Patent Application No. 2003-0023040. The first chip 10 a is illustrated as including a first semiconductor substrate 12 a having a first through-hole 17 a therein. The first through-hole 17 a extends from an upper surface of the substrate 12 a to a lower surface of the substrate 12 a. A first passivation layer 13 a is provided on the upper surface of the substrate 12 a. This first passivation layer 13 a has an opening therein that exposes a first chip pad 11 a. A first insulating layer 18 a is also provided. This first insulating layer 18 a extends on the first passivation layer 13 a and directly on sidewalls of the first through-hole 17 a. A first metal layer 21 a is provided directly on the first chip pad 11 a and forms an electrical connection therewith. As illustrated, this first metal layer 21 a also extends on the first insulating layer 18 a and into the first through-hole 17 a. The first through-hole 17 a is filled with a first electrode metal layer 22 a, which is electrically coupled to the first chip pad 11 a by the first metal layer 21 a.
  • Similarly, the second chip 10 b is illustrated as including a second semiconductor substrate 12 b having a second through-hole 17 b therein. The second through-hole 17 b extends from an upper surface of the substrate 12 b to a lower surface of the substrate 12 b. A second passivation layer 13 b is provided on the upper surface of the substrate 12 b. This second passivation layer 13 b has an opening therein that exposes a second chip pad 11 b. A second insulating layer 18 b is also provided. This second insulating layer 18 b extends on the second passivation layer 13 b and directly on sidewalls of the second through-hole 17 b. A second metal layer 21 b is provided directly on the second chip pad 11 b. This second metal layer 21 b also extends on the second insulating layer 18 b and into the second through-hole 17 b. The second through-hole 17 b is filled by a second electrode metal layer 22 b, which is electrically coupled to the second chip pad 11 b by the second metal layer 21 b.
  • An electrical interconnection is provided between the first and second integrated circuit chips 10 a and 10 b and the first and second chip pads 11 a and 11 b. This electrical interconnection is provided by a first metal bump 24 a (e.g., solder ball), which electrically connects the first electrode metal layer 22 a to the second electrode metal layer 22 b. A second metal bump 24 b is also provided to electrically connect the second electrode metal layer 22 b to an underlying chip, package or printed circuit board (not shown).
  • As will be understood by those skilled in the art, the first and second integrated circuit chips 10 a and 10 b may be formed from a common semiconductor wafer (not shown) containing integrated circuits therein and a plurality of chip pads thereon, which are partially covered by a passivation layer (shown as 13 a and 13 b in FIG. 1). The first and second through- holes 17 a and 17 b may be formed in the semiconductor wafer using a laser drilling technique. After formation of the through-holes, an insulating layer (shown as 18 a and 18 b in FIG. 1) is formed on the passivation layer and along sidewalls of the through-holes. This insulating layer may then be patterned to expose the chip pads. A metal layer-(shown as 21 a and 21 b in FIG. 1) and an electrode metal layer (shown as 22 a and 22 b in FIG. 1) are then deposited in sequence on the insulating layer. The electrode metal layer is deposited to a thickness sufficient to fill the through-holes. Following these steps, the semiconductor wafer may be thinned by removing a portion of a bottom surface of the semiconductor wafer. This thinning operation may include conventional grinding, polishing and wet etching techniques that result in an exposure of the electrode metal layer within the through-holes.
  • Unfortunately, the conventional fabrication step of laser drilling to form through-holes in a semiconductor wafer is a relatively lengthy process step that may require each hole to be formed one-at-a-time in sequence. Moreover, the drilling of holes may damage the semiconductor wafer and result in through-holes with tapered sidewall profiles. The formation of tapered sidewall profiles may lead to the formation of electrode metal layers that are susceptible to defects (e.g., electrical disconnection). Thus, notwithstanding these conventional techniques for forming integrated circuit chips that may be stacked together to provide high levels of integration, there continues to be a need for improved methods of forming through-holes in semiconductor wafers and chips.
    • SUMMARY OF THE INVENTION
  • Semiconductor chips according to embodiments of the present invention use outer edge insulating layers with through-holes therein that provide reliable interconnection vias when the chips are used in stacked multi-chip packaging applications. In some of these embodiments, a semiconductor substrate is provided having upper and lower faces thereon that extend to an outer edge thereof. At least a first contact pad is provided on a portion of the upper face extending adjacent the outer edge. An electrically insulating region is provided on the outer edge of the semiconductor substrate. This electrically insulating region, which may surround an entire periphery of the semiconductor substrate, includes at least one through-hole that extends vertically through an entire thickness of the electrically insulating region and has a longitudinal axis that is substantially parallel to the outer edge of the semiconductor substrate. A connection electrode is also provided. This connection electrode extends through the through-hole and is electrically connected to the first contact pad. The electrically insulating layer may have a lower surface that is coplanar with the lower face of the semiconductor substrate and an upper surface that is above the upper face of the semiconductor substrate, which results in a length of the through-hole being greater than a thickness of the semiconductor substrate. In particular, the electrically insulating layer may wrap around the outer edge and extend onto a passivation layer covering the semiconductor substrate.
  • Additional embodiments of the invention include a semiconductor chip having a peripheral edge defined by an electrically insulating region having interconnect through-holes therein. The semiconductor chip includes a semiconductor substrate having upper and lower faces thereon that extend to an outer edge thereof. An electrically insulating region is provided on the outer edge of the semiconductor substrate. The electrically insulating region has a through-hole therein that is filled within a connection electrode. A solder bump is also provided. The solder bump is electrically connected to a portion of the connection electrode extending adjacent a bottom of the through-hole.
  • Still further embodiments of the invention include methods of fabricating a plurality of integrated circuit chips from a semiconductor wafer. These methods include forming a plurality of crisscrossing grooves in a semiconductor wafer having a plurality of contact pads thereon. The criss-crossing grooves are then filled with an electrically insulating layer. The electrically insulating layer is patterned to define at least first and second through-holes therein, which extend into a first one of the criss-crossing groves. The first and second through-holes are filled with first and second through-chip connection electrodes, respectively. The semiconductor wafer is then diced into a plurality of integrated circuit chips. This dicing step may be performed by cutting through the electrically insulating layer in a criss-crossing pattern that overlaps with the locations of the crisscrossing grooves.
  • In additional embodiments of the invention, the dicing step is preceded by the step of removing an underside of the semiconductor wafer to thereby expose the first and second through-chip connection electrodes and the electrically insulating layer. The step of filling the first and second through-holes may also include depositing a base metal layer that extends on the electrically insulating layer and lines the first and second through-holes and then electroplating the first and second through-chip connection electrodes into the first and second through-holes using the base metal layer as an electroplating electrode. The base metal layer may then be etched back using the first and second through-chip connection electrodes as an etching mask.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view of a stack of integrated circuit chips that is compatible with chip scale packaging technologies, according to the prior art.
  • FIG. 2 is a plan view of a semiconductor wafer that may be processed in accordance with the methods of FIGS. 3-14 herein.
  • FIGS. 3-14 are cross-sectional views of intermediate structures that illustrate methods of forming integrated circuit chips according to embodiments of the present invention.
  • FIG. 15 is a cross-sectional view of a stack of integrated circuit chips formed in accordance with the methods of FIGS. 3-14.
    • DESCRIPTION OF PREFERRED EMBODIMENTS
  • The present invention now will be described more fully herein with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity of description. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like elements throughout.
  • Methods of forming integrated circuit chips according to embodiments of the present invention will now be described with reference to FIGS. 2-14. In FIG. 2, a semiconductor wafer 30 is illustrated. This semiconductor wafer 30 includes a semiconductor substrate 32 (e.g., silicon substrate) having a primary surface 35 thereon, which is also described herein as an upper face of the substrate 32. As described more fully hereinbelow with respect to FIGS. 3-14, a plurality of semiconductor chips 34 may be formed from the semiconductor wafer 30 by dicing the semiconductor wafer 30 along crisscrossing scribe lanes 36 (a/k/a dicing streets) to thereby form a plurality of separate semiconductor chips 34.
  • FIG. 3 is a plan view of a portion of the semiconductor wafer 30 of FIG. 2 and FIG. 4 is a cross-sectional view of the portion of FIG. 3, taken along line 4-4′. In particular, FIG. 3 illustrates peripheral portions of adjacent integrated circuit devices that are separated from each other by a scribe lane 36. Each integrated circuit device includes respective contact pads 31 on the primary surface 35. These pads 31 are illustrated as extending adjacent one side of each of the illustrated integrated circuit devices. In other embodiments of the present invention, other pads (not shown) may also be provided adjacent other sides of the integrated circuit devices. In FIG. 4, a surface passivation layer 33 is also illustrated as extending across the primary surface 35 of the semiconductor wafer 30. The pads 31 may be made of aluminum or copper, for example, and the passivation layer 33 may be made of electrically insulating materials such as silicon oxide, silicon nitride and silicon oxynitride. This passivation layer 33 may be formed as a relatively thick electrically insulating layer that covers multiple underlying layers of metallization, interconnects, interlayer insulating layers and active devices (not shown), for example. FIG. 4 also illustrates the position of a scribe lane 36, which extends between two portions of the substrate 32 that will ultimately constitute separate semiconductor chips 34 after a final wafer dicing step is performed.
  • As illustrated by FIGS. 5-6, a series of deep criss-crossing grooves 37 are formed along the scribe lanes 36. These grooves 37 may have a width equal to about the width of the scribe lanes 36. As illustrated more fully by FIG. 12, the depth of these grooves 37 may be a function of the amount of the underside surface 39 of the semiconductor wafer 30 that is to be removed prior to wafer dicing. In some embodiments of the invention, the depth of the grooves 37 may be in the range from about 30 microns to about 300 microns. These grooves 37 may be formed using a wafer sawing technique and/or a wafer etching technique. A relatively thick electrically insulating layer 38 is then formed as a blanket layer on the primary surface of the semiconductor wafer 30. This electrically insulating layer 38 is of sufficient thickness to completely fill the grooves 37 and cover adjacent portions of the substrate 32, as illustrated by FIG. 6. The electrically insulating layer 38 may be formed as a silicon oxide layer or as a polyimide layer, for example.
  • Referring now to FIG. 7, the electrically insulating layer 38 is selectively removed to define a plurality of through-holes 41 therein (i.e., connection holes), which are located in the scribe lanes 36 and sufficiently deep to expose the bottoms of the grooves 37, and expose the contact pads 31. This removal step may be performed as a photolithographically-defined etching step, which results in through-holes 41 having substantially vertical sidewalls and uniform diameters. These through-holes 41 may have diameters in a range from about 10 microns to about 50 microns. The electrically insulating layer 38 is also formed of a material that has good adhesive strength to the substrate 32, which inhibits detachment and/or delamination of the insulating layer 38 during subsequent processing and packaging. Moreover, by using a selective etching step that processes the entire wafer 30 at the same time, significant process time savings can be achieved because all of the through-holes 41 may be formed at the same time and all of the contact pads 31 may be exposed at the same time.
  • After the through-holes 41 have been formed, a blanket base metal layer 42 may be deposited on the wafer 30. As illustrated by FIG. 8, this base metal layer 42 is illustrated as contacting upper surfaces of the exposed contact pads 31 and lining the bottoms and sidewalls of the through-holes 41. The base metal layer 42, which should be chosen to have good adhesive properties with the underlying electrically insulating layer 38, may be formed using a sputtering technique, for example, and may have a thickness in a range from about 0.05 microns to about 1 micron. In some embodiments of the present invention, the base metal layer 42 may be a composite of two or more metal layers. The first of these metal layers within the composite may be chromium, titanium or other metal layer having good adhesive properties with the electrically insulating layer 38 and the second of these metal layers may be silver, gold, copper, nickel, palladium, platinum or other metal layer having good adhesive properties with a subsequently formed connection electrode.
  • Referring now to FIGS. 9-11, a blanket layer of photoresist material is deposited and patterned to define a photoresist mask 51 having a plurality of openings 52 therein. These openings 52 expose portions of the base metal layer 42 extending over each contact pad 31 and its corresponding through-hole 41. Then, as illustrated best by FIG. 10, electrode metal layers 43 are formed to completely fill respective openings 52 in the photoresist mask 51. These electrode metal layers 43 may be formed using an electroplating technique, which includes using the base metal layer 42 as a plating electrode, or another selective deposition technique. These electrode metal layers 43, which represent respective connection electrodes, may be formed of silver, gold, copper, nickel, palladium, platinum and alloys thereof or other suitable high conductivity materials. As illustrated by FIG. 11, the photoresist mask 51 is then removed to thereby expose portions of the base metal layer 42. These exposed portions of the base metal layer 42 are then selectively removed using an etching step and the electrode metal layers 43 as etching masks. This etching step causes portions of the electrically insulating layer 38 to be exposed and the electrode metal layers 43 to become electrically disconnected from each other.
  • Referring now to FIG. 12, a wafer thinning step is performed to expose portions of the electrode metal layers 43 extending to the bottoms of the through-holes 41. This wafer thinning step may be performed using a grinding wheel 53 to remove a portion of the underside surface 39 of the semiconductor wafer 30. In addition to grinding, wet etching may be used to remove portions of the underside surface 39 of the semiconductor wafer 30. The portion of the underside surface 39 of the semiconductor wafer 30 that is removed may be substantial. For example, if the semiconductor wafer 30 has a thickness of about 700 microns prior to wafer thinning, it may only have a thickness of about 100 microns (or less) after wafer thinning. Accordingly, the depth of the through-holes 41 and the grooves 37 should be greater than about 100 microns to guarantee, exposure of the electrode metal layers 43. When this relationship is present, each electrode metal layer 43 and corresponding base metal layer 42 provide a high conductivity electrical path from a corresponding contact pad 31 to an underside of the semiconductor wafer 30.
  • As illustrated by FIGS. 13-14, the wafer thinning step may be followed by the step of applying an adhesive tape 54 (e.g., ultraviolet adhesive tape) to the entire underside surface 39 of the thinned semiconductor wafer 30. This tape 54 preserves the integrity of the semiconductor wafer 30 during subsequent processing steps (e.g., wafer dicing). The semiconductor wafer 30 is then diced into a plurality of separate integrated circuit chips 60 by sawing the wafer along the center of the scribe lanes 36 using a cutting tool 55.
  • Referring now to FIG. 15, a cross-sectional view of a stack 70 of integrated circuit chips 60 a and 60 b formed in accordance with the methods of FIGS. 3-14 uses a first metallic (e.g., solder) bump 45 a to electrically connect an upper connection electrode 43 a associated with an upper chip 60 a to a lower connection electrode 43 b associated with a lower chip 60 b. A second metallic bump 45 b may also be provided to support mounting and electrical connection of the stack 70 to a printed circuit board (PCB) (not shown). In this manner, the second metallic bump 45 b operates as a terminal to the stack 70. These first and second metallic bumps 45 a and 45 b may be formed using an electroplating or other metal bump forming technique.
  • In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims (20)

1. A semiconductor chip, comprising:
a semiconductor substrate having upper and lower faces thereon that extend to an outer edge thereof and at least a first contact pad on a portion of the upper face extending adjacent the outer edge;
an electrically insulating region on the outer edge of said semiconductor substrate, said electrically insulating region having through-hole therein; and
a connection electrode that extends through said through-hole and is electrically connected to the first contact pad.
2. The semiconductor chip of claim 1, wherein said electrically insulating layer has a lower surface that is coplanar with the lower face of said semiconductor substrate.
3. The semiconductor chip of claim 1, wherein a length of the through-hole is greater than a thickness of said semiconductor substrate.
4. The semiconductor chip of claim 3, wherein a longitudinal axis of the through-hole is substantially parallel to the outer edge of said semiconductor substrate.
5. The semiconductor chip of claim 1, further comprising a passivation layer extending on the upper face and having an opening therein that exposes the first contact pad; and wherein said electrically insulating region wraps around the outer edge and extends onto the passivation layer.
6. The semiconductor chip of claim 5, wherein said electrically insulating region extends between the upper face and said connection electrode.
7. The semiconductor chip of claim 1, wherein an outer edge of said electrically insulating region represents an outer edge of the semiconductor chip.
8. A semiconductor chip, comprising:
a semiconductor substrate having upper and lower faces thereon that extend to an outer edge thereof;
an electrically insulating region on the outer edge of said semiconductor substrate, said electrically insulating region having through-hole therein with a length greater than a thickness of said semiconductor substrate;
a connection electrode extending through the through-hole; and
a solder bump electrically connected to a portion of said connection electrode extending adjacent a bottom of the through-hole.
9. The semiconductor chip of claim 8, wherein an outer edge of said electrically insulating region represents an outer edge of the semiconductor chip.
10. A method of fabricating a plurality of integrated circuit chips, comprising the steps of:
forming a plurality of criss-crossing grooves in a semiconductor wafer having a plurality of contact pads thereon;
filling the crisscrossing grooves with an electrically insulating layer;
patterning the electrically insulating layer to define at least first and second through-holes therein that extend in a first one of the criss-crossing groves;
filling the first and second through-holes with first and second through-chip connection electrodes, respectively; and
dicing the semiconductor wafer into a plurality of integrated circuit chips by cutting through the electrically insulating layer in a crisscrossing pattern that overlaps with the locations of the criss-crossing grooves.
11. The method of claim 10, wherein said dicing step is preceded by the step of removing an underside of said semiconductor wafer to thereby expose the first and second through-chip connection electrodes and the electrically insulating layer.
12. The method of claim 11, wherein said step of filling the first and second through-holes comprises the steps of:
depositing a base metal layer that extends on the electrically insulating layer and lines the first and second through-holes;
electroplating the first and second through-chip connection electrodes into the first and second through-holes; and
etching back the base metal layer using the first and second through-chip connection electrodes as an etching mask.
13. The method of claim 10, wherein said step of filling the first and second through-holes comprises the steps of:
depositing a base metal layer that extends on the electrically insulating layer and lines the first and second through-holes;
electroplating the first and second through-chip connection electrodes into the first and second through-holes; and
etching back the base metal layer using the first and second through-chip connection electrodes as an etching mask.
14. The method of claim 13, wherein said electroplating step comprises electroplating the first and second through-chip connection electrodes into the first and second through-holes using the base metal layer as an electroplating electrode.
15. The method of claim 14, wherein said electroplating step is preceded by the step of patterning an electroplating mask on the base metal layer.
16. A method of fabricating an integrated circuit chip, comprising the steps of:
forming a groove in a semiconductor substrate;
filling the groove with an electrically insulating region;
forming first and second through-holes in the electrically insulating region;
filling the first and second through-holes with first and second connection electrodes, respectively;
removing an underside of the semiconductor substrate to thereby expose the electrically insulating region and the first and second connection electrodes; and
dicing the semiconductor substrate into first and second semiconductor chips by cutting through the electrically insulating region at a location extending between the first and second connection electrodes.
17. The method of claim 16, wherein said step of filling the first and second through-holes comprises electroplating first and second connection electrodes into the first and second through-holes.
18. A method of processing a semiconductor wafer, comprising the steps of:
forming a plurality of criss-crossing grooves in a semiconductor wafer;
filling the criss-crossing grooves with an electrically insulating layer;
removing an underside of the semiconductor wafer to thereby expose a surface of the electrically insulating layer having a criss-crossing pattern; and
dicing the semiconductor wafer into a plurality of integrated circuit chips having electrically insulating edges by cutting through the electrically insulating region at locations defined by the criss-crossing pattern.
19. The method of claim 18, wherein said removing step is preceded by the steps of:
forming a plurality of through-holes in the electrically insulating layer; and
filling the plurality of through-holes with a corresponding plurality of connection electrodes.
20. The method of claim 19, wherein said removing step comprises removing an underside of the semiconductor wafer to thereby expose a surface of the electrically insulating layer and the plurality of connection electrodes.
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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060234475A1 (en) * 2005-04-15 2006-10-19 Hynix Semiconductor Inc. Method for manufacturing semiconductor device
US20070045836A1 (en) * 2005-08-31 2007-03-01 Samsung Electronics Co., Ltd. Stacked chip package using warp preventing insulative material and manufacturing method thereof
US20070246826A1 (en) * 2006-04-21 2007-10-25 Samsung Electronics Co. Ltd. Wafer level semiconductor module and method for manufacturing the same
US20080153265A1 (en) * 2006-12-21 2008-06-26 Texas Instruments Incorporated Semiconductor Device Manufactured Using an Etch to Separate Wafer into Dies and Increase Device Space on a Wafer
US20080150089A1 (en) * 2006-11-06 2008-06-26 Yong-Chai Kwon Semiconductor device having through vias and method of manufacturing the same
US20090305502A1 (en) * 2008-06-10 2009-12-10 Ho-Jin Lee Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein and Chips Formed Thereby
US7847416B2 (en) 2006-05-22 2010-12-07 Samsung Electronics Co., Ltd. Wafer level package and method of fabricating the same
US20110042821A1 (en) * 2009-08-21 2011-02-24 Micron Technology, Inc. Vias and conductive routing layers in semiconductor substrates
US20110124156A1 (en) * 2007-05-04 2011-05-26 Stats Chippac, Ltd. Method of Fabricating Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die
US20110204526A1 (en) * 2006-05-22 2011-08-25 Micron Technology, Inc. Methods of Determining X-Y Spatial Orientation of a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Positioning a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Processing a Semiconductor Substrate, and Semiconductor Devices
US20120034777A1 (en) * 2008-03-27 2012-02-09 Stats Chippac, Ltd. Through Hole Vias at Saw Streets Including Protrusions or Recesses for Interconnection
US20120073871A1 (en) * 2008-08-27 2012-03-29 Advanced Semiconductor Engineering, Inc. Multi-layered substrate
US20120218728A1 (en) * 2009-08-24 2012-08-30 Epcos Ag Carrier Device, Arrangement Comprising such a Carrier Device, and Method for Patterning a Layer Stack Comprising at Least One Ceramic Layer
US20130299975A1 (en) * 2008-05-27 2013-11-14 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Through Vias with Reflowed Conductive Material
US20140008769A1 (en) * 2010-02-03 2014-01-09 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Cavity Adjacent to Sensitive Region of Semiconductor Die Using Wafer-Level Underfill Material
US20180096952A1 (en) * 2016-09-30 2018-04-05 Intel IP Corporation Methods and structures for dicing integrated circuits from a wafer
US10741504B2 (en) * 2017-01-10 2020-08-11 Renesas Electronics Corporation Semiconductor device manufacturing method and semiconductor wafer

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2875624A1 (en) * 2004-09-23 2006-03-24 St Microelectronics Sa DETERMINISTIC GENERATION OF AN IDENTIFIER NUMBER OF AN INTEGRATED CIRCUIT
JP2007299968A (en) * 2006-05-01 2007-11-15 Matsushita Electric Ind Co Ltd Semiconductor device
JP4731394B2 (en) * 2006-05-09 2011-07-20 Ｏｋｉセミコンダクタ株式会社 Electronic component built-in substrate and manufacturing method thereof
KR100794658B1 (en) 2006-07-07 2008-01-14 삼성전자주식회사 Method of forming semiconductor chip, the semiconductor chip so formed and chip stack package having the same
KR100761468B1 (en) 2006-07-13 2007-09-27 삼성전자주식회사 Semiconductor device and method of forming the same
JP2008091777A (en) * 2006-10-04 2008-04-17 Sumitomo Electric Ind Ltd Optical transceiver
JP4312786B2 (en) * 2006-11-02 2009-08-12 Ｏｋｉセミコンダクタ株式会社 Manufacturing method of semiconductor chip
KR100843214B1 (en) * 2006-12-05 2008-07-02 삼성전자주식회사 Planar multi semiconductor chip with the memory chip connected to processor chip by through electrode and method for fabricating the same
US8110899B2 (en) * 2006-12-20 2012-02-07 Intel Corporation Method for incorporating existing silicon die into 3D integrated stack
US7884481B2 (en) * 2007-08-02 2011-02-08 Mediatek Inc. Semiconductor chip package and method for designing the same
KR101465948B1 (en) * 2007-12-27 2014-12-10 삼성전자주식회사 A wafer level stack package and method of manufacturing a wafer level stack package
US8823179B2 (en) 2008-05-21 2014-09-02 Chia-Lun Tsai Electronic device package and method for fabricating the same
US7846772B2 (en) * 2008-06-23 2010-12-07 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US7868442B2 (en) * 2008-06-30 2011-01-11 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8384417B2 (en) * 2008-09-10 2013-02-26 Qualcomm Incorporated Systems and methods utilizing redundancy in semiconductor chip interconnects
KR101064757B1 (en) 2008-11-25 2011-09-15 한국전자통신연구원 Method of forming the through wafer via having thick insulation layer
JP2011009645A (en) * 2009-06-29 2011-01-13 Toshiba Corp Semiconductor device and method of manufacturing the same
KR101078740B1 (en) * 2009-12-31 2011-11-02 주식회사 하이닉스반도체 Stack package and method for fabricating the same
US8796863B2 (en) * 2010-02-09 2014-08-05 Samsung Electronics Co., Ltd. Semiconductor memory devices and semiconductor packages
KR20110135299A (en) * 2010-06-10 2011-12-16 삼성전자주식회사 Semiconductor memory device
US8598695B2 (en) 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
CN103579192A (en) * 2012-07-26 2014-02-12 中芯国际集成电路制造(上海)有限公司 Novel through hole chain testing structure and testing method thereof
DE102012108522A1 (en) 2012-09-12 2014-03-13 Ams Ag Method for manufacturing semiconductor stack for stacking semiconductor chips with components for three-dimensional integration of electronic circuit, involves arranging through-contacts in aperture after connecting stack components
US9059053B2 (en) * 2013-10-03 2015-06-16 Nanya Technology Corporation Multi-die stack structure
CN104952827A (en) * 2014-03-26 2015-09-30 中芯国际集成电路制造(上海)有限公司 Pad structure and manufacturing method thereof
US10699948B2 (en) 2017-11-13 2020-06-30 Analog Devices Global Unlimited Company Plated metallization structures

Citations (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4499655A (en) * 1981-03-18 1985-02-19 General Electric Company Method for making alignment-enhancing feed-through conductors for stackable silicon-on-sapphire
US5677569A (en) * 1994-10-27 1997-10-14 Samsung Electronics Co., Ltd. Semiconductor multi-package stack
US5688721A (en) * 1994-03-15 1997-11-18 Irvine Sensors Corporation 3D stack of IC chips having leads reached by vias through passivation covering access plane
US5818107A (en) * 1997-01-17 1998-10-06 International Business Machines Corporation Chip stacking by edge metallization
US6002177A (en) * 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6107121A (en) * 1996-06-24 2000-08-22 International Business Machines Corporation Method of making interconnections between a multi-layer chip stack to a printed circuit board in a ceramic package
US6117299A (en) * 1997-05-09 2000-09-12 Mcnc Methods of electroplating solder bumps of uniform height on integrated circuit substrates
US6124149A (en) * 1997-11-19 2000-09-26 Hyundai Electronics Industries Co., Ltd. Method of making stackable semiconductor chips to build a stacked chip module
US6177721B1 (en) * 1998-10-21 2001-01-23 Hyundai Electronics Industries Co., Ltd Chip stack-type semiconductor package and method for fabricating the same
US6188129B1 (en) * 1997-03-24 2001-02-13 Hyundai Electronics Industries Co., Ltd. Stacked semiconductor chip package having external terminal pads and stackable chips having a protection layer
US6338980B1 (en) * 1999-08-13 2002-01-15 Citizen Watch Co., Ltd. Method for manufacturing chip-scale package and manufacturing IC chip
US6344683B1 (en) * 1999-03-09 2002-02-05 Hyundai Electronics Industries Co., Ltd. Stacked semiconductor package with flexible tape
US6406937B1 (en) * 1999-09-10 2002-06-18 Infineon Technologies Ag Method for producing an electrical connection between the front and rear sides of semiconductor chips
US6429096B1 (en) * 1999-03-29 2002-08-06 Sony Corporation Method of making thinned, stackable semiconductor device
US6506632B1 (en) * 2002-02-15 2003-01-14 Unimicron Technology Corp. Method of forming IC package having downward-facing chip cavity
US6555902B2 (en) * 2000-07-17 2003-04-29 Siliconware Precision Industries Co., Ltd. Multiple stacked-chip packaging structure
US6562647B2 (en) * 1999-09-13 2003-05-13 Vishay Intertechnology, Inc. Chip scale surface mount package for semiconductor device and process of fabricating the same
US6566232B1 (en) * 1999-10-22 2003-05-20 Seiko Epson Corporation Method of fabricating semiconductor device
US6590291B2 (en) * 2000-01-31 2003-07-08 Shinko Electric Industries Co., Ltd. Semiconductor device and manufacturing method therefor
US6607938B2 (en) * 2001-07-19 2003-08-19 Samsung Electronics Co., Ltd. Wafer level stack chip package and method for manufacturing same
US20030173678A1 (en) * 2002-03-18 2003-09-18 Fujitsu Limited Semiconductor device and method for fabricating the same
US20030194860A1 (en) * 2002-04-16 2003-10-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device manufacturing method and electronic equipment using same
US20040043535A1 (en) * 2002-08-28 2004-03-04 Jeung Boon Suan Castellation wafer level packaging of integrated circuit chips
US6732913B2 (en) * 2001-04-26 2004-05-11 Advanpack Solutions Pte Ltd. Method for forming a wafer level chip scale package, and package formed thereby
US6737300B2 (en) * 2001-01-24 2004-05-18 Advanced Semiconductor Engineering, Inc. Chip scale package and manufacturing method
US6737295B2 (en) * 2001-02-27 2004-05-18 Chippac, Inc. Chip scale package with flip chip interconnect
US6757968B2 (en) * 2000-02-16 2004-07-06 The Boeing Company Chip scale packaging on CTE matched printed wiring boards
US6759307B1 (en) * 2000-09-21 2004-07-06 Micron Technology, Inc. Method to prevent die attach adhesive contamination in stacked chips
US6768190B2 (en) * 2002-01-25 2004-07-27 Advanced Semiconductor Engineering, Inc. Stack type flip-chip package
US6768195B2 (en) * 2001-08-29 2004-07-27 Sun Microsystems, Inc. Multi-chip semiconductor device
US6774475B2 (en) * 2002-01-24 2004-08-10 International Business Machines Corporation Vertically stacked memory chips in FBGA packages
US6780746B2 (en) * 2000-06-02 2004-08-24 Micron Technology, Inc. Method for fabricating a chip scale package using wafer level processing and devices resulting therefrom
US6781240B2 (en) * 2001-06-26 2004-08-24 Samsung Electronics Co., Ltd. Semiconductor package with semiconductor chips stacked therein and method of making the package
US6787395B2 (en) * 2000-07-07 2004-09-07 Renesas Technology Corp. Method of manufacturing a multi-chip module
US6791178B2 (en) * 2001-05-31 2004-09-14 Hitachi, Ltd. Multi-chip module including semiconductor devices and a wiring substrate for mounting the semiconductor devices
US6798061B2 (en) * 1999-11-15 2004-09-28 Koninklijke Philips Electronics N.V. Multiple semiconductor chip (multi-chip) module for use in power applications
US6803252B2 (en) * 2001-11-21 2004-10-12 Sierra Monolithics, Inc. Single and multiple layer packaging of high-speed/high-density ICs
US6809416B1 (en) * 2002-05-28 2004-10-26 Intersil Corporation Package for integrated circuit with thermal vias and method thereof
US20050046002A1 (en) * 2003-08-26 2005-03-03 Kang-Wook Lee Chip stack package and manufacturing method thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100311035B1 (en) * 1997-11-21 2002-02-28 윤종용 Semiconductor memory device with efficiently disposed pads
KR100608611B1 (en) 1999-06-02 2006-08-09 삼성전자주식회사 Wafer level chip scale package using via hole and manufacturing method for the same
KR100584003B1 (en) 1999-12-02 2006-05-29 삼성전자주식회사 Method for manufacturing stack chip package
US6800169B2 (en) * 2001-01-08 2004-10-05 Fujitsu Limited Method for joining conductive structures and an electrical conductive article
KR100830347B1 (en) 2001-09-11 2008-05-20 페어차일드코리아반도체 주식회사 Direct chip attaching package, manufacturing method thereof and stacked direct chip attaching package
JP2003188263A (en) 2001-12-17 2003-07-04 Sharp Corp Method for producing semiconductor integrated circuit chip and semiconductor package using semiconductor integrated circuit chip
JP2006073821A (en) * 2004-09-02 2006-03-16 Sharp Corp Semiconductor integrated circuit device

Patent Citations (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4499655A (en) * 1981-03-18 1985-02-19 General Electric Company Method for making alignment-enhancing feed-through conductors for stackable silicon-on-sapphire
US5688721A (en) * 1994-03-15 1997-11-18 Irvine Sensors Corporation 3D stack of IC chips having leads reached by vias through passivation covering access plane
US5677569A (en) * 1994-10-27 1997-10-14 Samsung Electronics Co., Ltd. Semiconductor multi-package stack
US6002177A (en) * 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6107121A (en) * 1996-06-24 2000-08-22 International Business Machines Corporation Method of making interconnections between a multi-layer chip stack to a printed circuit board in a ceramic package
US5818107A (en) * 1997-01-17 1998-10-06 International Business Machines Corporation Chip stacking by edge metallization
US6188129B1 (en) * 1997-03-24 2001-02-13 Hyundai Electronics Industries Co., Ltd. Stacked semiconductor chip package having external terminal pads and stackable chips having a protection layer
US6117299A (en) * 1997-05-09 2000-09-12 Mcnc Methods of electroplating solder bumps of uniform height on integrated circuit substrates
US6124149A (en) * 1997-11-19 2000-09-26 Hyundai Electronics Industries Co., Ltd. Method of making stackable semiconductor chips to build a stacked chip module
US6177721B1 (en) * 1998-10-21 2001-01-23 Hyundai Electronics Industries Co., Ltd Chip stack-type semiconductor package and method for fabricating the same
US6528353B2 (en) * 1998-10-21 2003-03-04 Hyundai Electronics Industries Co., Ltd. Chip stack-type semiconductor package and method for fabricating the same
US6344683B1 (en) * 1999-03-09 2002-02-05 Hyundai Electronics Industries Co., Ltd. Stacked semiconductor package with flexible tape
US6429096B1 (en) * 1999-03-29 2002-08-06 Sony Corporation Method of making thinned, stackable semiconductor device
US6338980B1 (en) * 1999-08-13 2002-01-15 Citizen Watch Co., Ltd. Method for manufacturing chip-scale package and manufacturing IC chip
US6406937B1 (en) * 1999-09-10 2002-06-18 Infineon Technologies Ag Method for producing an electrical connection between the front and rear sides of semiconductor chips
US6562647B2 (en) * 1999-09-13 2003-05-13 Vishay Intertechnology, Inc. Chip scale surface mount package for semiconductor device and process of fabricating the same
US6566232B1 (en) * 1999-10-22 2003-05-20 Seiko Epson Corporation Method of fabricating semiconductor device
US6798061B2 (en) * 1999-11-15 2004-09-28 Koninklijke Philips Electronics N.V. Multiple semiconductor chip (multi-chip) module for use in power applications
US6590291B2 (en) * 2000-01-31 2003-07-08 Shinko Electric Industries Co., Ltd. Semiconductor device and manufacturing method therefor
US6757968B2 (en) * 2000-02-16 2004-07-06 The Boeing Company Chip scale packaging on CTE matched printed wiring boards
US6780746B2 (en) * 2000-06-02 2004-08-24 Micron Technology, Inc. Method for fabricating a chip scale package using wafer level processing and devices resulting therefrom
US6787395B2 (en) * 2000-07-07 2004-09-07 Renesas Technology Corp. Method of manufacturing a multi-chip module
US6555902B2 (en) * 2000-07-17 2003-04-29 Siliconware Precision Industries Co., Ltd. Multiple stacked-chip packaging structure
US6759307B1 (en) * 2000-09-21 2004-07-06 Micron Technology, Inc. Method to prevent die attach adhesive contamination in stacked chips
US6737300B2 (en) * 2001-01-24 2004-05-18 Advanced Semiconductor Engineering, Inc. Chip scale package and manufacturing method
US6737295B2 (en) * 2001-02-27 2004-05-18 Chippac, Inc. Chip scale package with flip chip interconnect
US6732913B2 (en) * 2001-04-26 2004-05-11 Advanpack Solutions Pte Ltd. Method for forming a wafer level chip scale package, and package formed thereby
US6791178B2 (en) * 2001-05-31 2004-09-14 Hitachi, Ltd. Multi-chip module including semiconductor devices and a wiring substrate for mounting the semiconductor devices
US6781240B2 (en) * 2001-06-26 2004-08-24 Samsung Electronics Co., Ltd. Semiconductor package with semiconductor chips stacked therein and method of making the package
US6607938B2 (en) * 2001-07-19 2003-08-19 Samsung Electronics Co., Ltd. Wafer level stack chip package and method for manufacturing same
US6768195B2 (en) * 2001-08-29 2004-07-27 Sun Microsystems, Inc. Multi-chip semiconductor device
US6803252B2 (en) * 2001-11-21 2004-10-12 Sierra Monolithics, Inc. Single and multiple layer packaging of high-speed/high-density ICs
US6774475B2 (en) * 2002-01-24 2004-08-10 International Business Machines Corporation Vertically stacked memory chips in FBGA packages
US6768190B2 (en) * 2002-01-25 2004-07-27 Advanced Semiconductor Engineering, Inc. Stack type flip-chip package
US6506632B1 (en) * 2002-02-15 2003-01-14 Unimicron Technology Corp. Method of forming IC package having downward-facing chip cavity
US20030173678A1 (en) * 2002-03-18 2003-09-18 Fujitsu Limited Semiconductor device and method for fabricating the same
US20030194860A1 (en) * 2002-04-16 2003-10-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device manufacturing method and electronic equipment using same
US6809416B1 (en) * 2002-05-28 2004-10-26 Intersil Corporation Package for integrated circuit with thermal vias and method thereof
US20040043535A1 (en) * 2002-08-28 2004-03-04 Jeung Boon Suan Castellation wafer level packaging of integrated circuit chips
US20050046002A1 (en) * 2003-08-26 2005-03-03 Kang-Wook Lee Chip stack package and manufacturing method thereof

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7524738B2 (en) * 2005-04-15 2009-04-28 Hynix Semiconductor Inc. Method for manufacturing semiconductor device
US20060234475A1 (en) * 2005-04-15 2006-10-19 Hynix Semiconductor Inc. Method for manufacturing semiconductor device
US20070045836A1 (en) * 2005-08-31 2007-03-01 Samsung Electronics Co., Ltd. Stacked chip package using warp preventing insulative material and manufacturing method thereof
US20070048969A1 (en) * 2005-08-31 2007-03-01 Samsung Electronics Co., Ltd. Stacked chip package using photosensitive polymer and manufacturing method thereof
US20070246826A1 (en) * 2006-04-21 2007-10-25 Samsung Electronics Co. Ltd. Wafer level semiconductor module and method for manufacturing the same
US20100032807A1 (en) * 2006-04-21 2010-02-11 Hyun-Soo Chung Wafer level semiconductor module and method for manufacturing the same
US8110922B2 (en) 2006-04-21 2012-02-07 Samsung Electronics Co., Ltd. Wafer level semiconductor module and method for manufacturing the same
US20110204526A1 (en) * 2006-05-22 2011-08-25 Micron Technology, Inc. Methods of Determining X-Y Spatial Orientation of a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Positioning a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Processing a Semiconductor Substrate, and Semiconductor Devices
US7847416B2 (en) 2006-05-22 2010-12-07 Samsung Electronics Co., Ltd. Wafer level package and method of fabricating the same
US8531046B2 (en) * 2006-05-22 2013-09-10 Micron Technology, Inc. Semiconductor substrates comprising through substrate interconnects that are visible on the substrate backside
US20080150089A1 (en) * 2006-11-06 2008-06-26 Yong-Chai Kwon Semiconductor device having through vias and method of manufacturing the same
US7602047B2 (en) * 2006-11-06 2009-10-13 Samsung Electronics Co., Ltd. Semiconductor device having through vias
US20080153265A1 (en) * 2006-12-21 2008-06-26 Texas Instruments Incorporated Semiconductor Device Manufactured Using an Etch to Separate Wafer into Dies and Increase Device Space on a Wafer
US8815643B2 (en) * 2007-05-04 2014-08-26 Stats Chippac, Ltd. Method of fabricating semiconductor die with through-hole via on saw streets and through-hole via in active area of die
US20110124156A1 (en) * 2007-05-04 2011-05-26 Stats Chippac, Ltd. Method of Fabricating Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die
US20120244661A9 (en) * 2007-05-04 2012-09-27 Stats Chippac, Ltd. Method of Fabricating Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die
US20120034777A1 (en) * 2008-03-27 2012-02-09 Stats Chippac, Ltd. Through Hole Vias at Saw Streets Including Protrusions or Recesses for Interconnection
US8940636B2 (en) * 2008-03-27 2015-01-27 STATS ChipPAC, Ltc. Through hole vias at saw streets including protrusions or recesses for interconnection
US20130299975A1 (en) * 2008-05-27 2013-11-14 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Through Vias with Reflowed Conductive Material
US9331002B2 (en) * 2008-05-27 2016-05-03 Stats Chippac, Ltd. Semiconductor device and method of forming through vias with reflowed conductive material
US9219035B2 (en) 2008-06-10 2015-12-22 Samsung Electronics Co., Ltd. Integrated circuit chips having vertically extended through-substrate vias therein
US8629059B2 (en) 2008-06-10 2014-01-14 Samsung Electronics Co., Ltd. Methods of forming integrated circuit chips having vertically extended through-substrate vias therein
US20090305502A1 (en) * 2008-06-10 2009-12-10 Ho-Jin Lee Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein and Chips Formed Thereby
US7875552B2 (en) 2008-06-10 2011-01-25 Samsung Electronics Co., Ltd. Methods of forming integrated circuit chips having vertically extended through-substrate vias therein and chips formed thereby
US20120073871A1 (en) * 2008-08-27 2012-03-29 Advanced Semiconductor Engineering, Inc. Multi-layered substrate
US9799562B2 (en) * 2009-08-21 2017-10-24 Micron Technology, Inc. Vias and conductive routing layers in semiconductor substrates
US20110042821A1 (en) * 2009-08-21 2011-02-24 Micron Technology, Inc. Vias and conductive routing layers in semiconductor substrates
US10600689B2 (en) 2009-08-21 2020-03-24 Micron Technology, Inc. Vias and conductive routing layers in semiconductor substrates
US9001523B2 (en) * 2009-08-24 2015-04-07 Epcos Ag Carrier device, arrangement comprising such a carrier device, and method for patterning a layer stack comprising at least one ceramic layer
US20120218728A1 (en) * 2009-08-24 2012-08-30 Epcos Ag Carrier Device, Arrangement Comprising such a Carrier Device, and Method for Patterning a Layer Stack Comprising at Least One Ceramic Layer
US20140008769A1 (en) * 2010-02-03 2014-01-09 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Cavity Adjacent to Sensitive Region of Semiconductor Die Using Wafer-Level Underfill Material
US9679881B2 (en) * 2010-02-03 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material
US20180096952A1 (en) * 2016-09-30 2018-04-05 Intel IP Corporation Methods and structures for dicing integrated circuits from a wafer
US10325861B2 (en) * 2016-09-30 2019-06-18 Intel IP Corporation Methods and structures for dicing integrated circuits from a wafer
US10741504B2 (en) * 2017-01-10 2020-08-11 Renesas Electronics Corporation Semiconductor device manufacturing method and semiconductor wafer

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US7595559B2 (en) 2009-09-29

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