US20060033211A1 - Power gridding scheme - Google Patents
Power gridding scheme Download PDFInfo
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- US20060033211A1 US20060033211A1 US11/203,849 US20384905A US2006033211A1 US 20060033211 A1 US20060033211 A1 US 20060033211A1 US 20384905 A US20384905 A US 20384905A US 2006033211 A1 US2006033211 A1 US 2006033211A1
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- solder bumps
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Abstract
An electrical device includes electrical contact pads, a supply voltage bus and an interconnection circuit. The electrical contact pads receive a supply voltage, and the bus is electrically connected to the electrical contact pads. For each electrical contact pad, the interconnection circuit forms a redundant connection between the bus and the electrical contact pad. The electrical device may include a passivation layer that includes windows to establish electrical contact between the electrical contact pads and the supply voltage bus. This window may be elongated in a path that is generally aligned with the path along which the supply voltage bus extends.
Description
- This application is a divisional of U.S. Pat. No. 6,930,379, granted Aug. 16, 2005, which is a divisional of U.S. patent application Ser. No. 10/022,700, filed on Oct. 30, 2001.
- The invention generally relates to a power gridding scheme.
- Microprocessors are being fabricated with increasingly higher speeds and device density. As a result, the power that is consumed by a microprocessor continues to increase from one generation to the next. This increase in power usage, in turn, may present several challenges.
- For example, the microprocessor has a finite number of external contacts (positive and negative supply voltage contacts, for example) to communicate power to the microprocessor. For example, these external contacts may be solder bumps that are part of a ball and grid package, a package in which the solder bumps are arranged in a rectangular grid, or array. In this array, the distances between adjacent solder bumps typically decreases from one generation microprocessor to the next in an attempt to increase the number of solder bumps that are available to communicate power. However, the increase in bump density does not track the corresponding increase in the speed and scaling of devices in the microprocessor. As a result, there is a net reduction in the number of solder bumps for power per device in the microprocessor. Thus, the net result of the increased power density for these solder bumps is that the current densities of some solder bumps may be large enough to possibly cause premature failure of these solder bumps due to the process of electromigration (EM).
- Thus, there is a continuing need for an arrangement that addresses one or more of the problems that are stated above.
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FIG. 1 is a partial schematic diagram of an integrated circuit package depicting an arrangement of solder bumps according to an embodiment of the invention. -
FIG. 2 is a cross-sectional view of the package taken along line 2-2 ofFIG. 1 . -
FIG. 3 is an exploded perspective view of a portion of the package according to an embodiment of the invention. -
FIG. 4 is a top view of an interconnection layer ofFIG. 3 according to an embodiment of the invention. -
FIG. 5 is a cross-sectional view of a semiconductor package according to an embodiment of the invention. -
FIG. 6 is a top view of an integrated circuit die according to an embodiment of the invention. -
FIG. 7 is a schematic diagram depicting electrical connections between buses and solder bumps according to an embodiment of the invention. -
FIGS. 8, 9 and 10 are exploded perspective views of portions of semiconductor packages according to different embodiments of the invention. -
FIG. 11 is a cross-sectional view of a portion of a semiconductor package according to an embodiment of the invention. - Referring to
FIG. 1 , an integrated circuit package (a microprocessor, as an example) in accordance with an embodiment of the invention includessolder bumps 22 that are located on the outside of thepackage 10 to form external contacts. In this manner, thepackage 10 may be a ball grid package, and thesolder bumps 22 may be part of a grid, or array. Thesolder bumps 22 form contacts for communicating power and signals to and from circuitry of theintegrated circuit package 10. As an example, some of thesolder bumps 22 may designated to communicate positive and negative supply voltages to theintegrated circuit package 10. - More particularly,
FIG. 1 depicts, as examples,specific solder bumps circuit package 10. For this example, thesolder bumps solder bumps buses 17 of the integratedcircuit package 10. In this manner, thesolder bumps supply voltage bus 17 a of theintegrated circuit package 10, and thesolder bump 22 c may be electrically connected to another positivesupply voltage bus 17 b of theintegrated circuit package 10. - Although the positive
supply voltage buses 17 are described below in connection with thesolder bumps supply voltage bus 18, for example. - To establish both an electrical and mechanical connection between a
particular solder bump 22 and circuitry inside theintegrated circuit package 10, a window may be formed in a passivation layer of the semiconductor die that is encased in thepackage 10. This passivation layer forms an outer insulating layer of thedie 11 and is located between the closest internal metal layer of thepackage 10 and thesolder bumps 22. As a more specific example, referring also toFIG. 2 , theintegrated circuit package 10 may include apassivation layer 16 that generally covers an upper metal layer 62 (a metal six layer, as an example) of thedie 11. Themetal layer 62 is exposed for contact with thesolder bumps 22 at several locations at which contact windows are formed in thepassivation layer 16. - One of these
windows 15 is depicted inFIG. 2 . As shown, thewindow 15 exposes a solder bumpmetal contact pad 66 that is part of theupper metal layer 62. Thus, the associatedsolder bump 22 a extends through thewindow 15 to bond to themetal pad 66. Thismetal pad 66, in turn, is electrically connected to thesupply voltage bus 17 a, and thus, the contact of thesolder bump 22 a to themetal pad 66 electrically connects thesolder bump 22 a to thebus 17 a. As an example of the interconnection between themetal pad 66 and thebus 17 a, thepad 66 may be connected to ametal pad 70 of alower metal layer 64 by way of avia 67, and thismetal pad 70 may be connected to thebus 17 by way of another via 71. - The size of the
window 15 limits the current carrying capability of thesolder bump 22, as the size of thewindow 15 defines the area of thesolder bump 22 that contacts the solderbump contact pad 66. For purposes of increasing the extent of contact between thesolder bump 22 and thecontact pad 66, in accordance with an embodiment of the invention, thewindow 15 is elongated. This elongation permits more contact area betweensolder bump 22 and its associatedcontact pad 66. Thus, selected windows of theintegrated circuit package 10 may be elongated for purposes of increasing the current carrying capabilities ofsolder bumps 22 that communicate positive and negative supply voltages. - As a more specific example, referring back to
FIG. 1 , in some embodiments of the invention, thewindow 15 may be a substantially rectangular pad, a pad that is elongated such that the longest dimension of thewindow 15 is aligned with thebus 17 that lies underneath thatwindow 15 and is electrically connected to thesolder bump 22 that extends through thewindow 15. Thus, the major axis of therectangular window 15 is aligned with and located directly above thebus 17 that extends immediately below thewindow 15. - In contrast to the elongated shape of the
window 15, awindow 14 of the prior art, also depicted inFIG. 1 for purposes of comparison, typically is square. In this manner, in conventional integrated circuits, the size of the square window is limited by the dimension (of the square window 14) that is transverse to thebus 17. In contrast, unlike conventional arrangements, in theintegrated circuit 10, although the transverse direction governs the width of thewindow 15, the length of thewindow 15 is elongated along thebus 17 in a direction to permit more contact between the associatedsolder bump 22 andcontact pad 66. - As a more specific example, in some embodiments of the invention, the
window 15 may have a dimension of approximately 80 by 40 micrometers (μm, or microns), and in other embodiments of the invention may have dimensions of 100 by 150 microns. - It is noted that it is not essential that the
window 15 has a rectangular shape. In this manner, in other embodiments of the invention, thewindow 15 may have different elongated shapes (an oval shape, for example). - As depicted in
FIG. 1 , in some embodiments of the invention, the windows that are formed in thepassivation layer 16 are sized differently. In this manner, the windows, in some embodiments of the invention, are selectively sized, in that larger windows are formed for use with somesolder bumps 22 and smaller windows are formed for use withother solder bumps 22. Such an arrangement permits larger windows to be formed forsolder bumps 22 that carry relatively high levels of currents, thereby increasing the current carrying capabilities of thesesolder bumps 22; and permits smaller windows to be formed forsolder bumps 22 that do not carry such high levels of current. - As an example of this selective sizing,
FIG. 1 depicts therectangular windows 15 that are relatively large and are used to increase the current carrying capabilities ofsolder bumps hexagonal windows 11 that are used bysolder bumps 22 d and 22 e. Thehexagonal window 11 is smaller than thewindow 15 in that thewindow 11 exposes less area of the upper metal layer for contact with the associatedsolder bump 22 than thewindow 15. Thus, thesolder bumps 22 d and 22 e may be associated with lower currents than thesolder bumps - In some embodiments of the invention, as an example of this selective sizing, some of the windows may be approximately square and have dimensions of approximately 40 by 40 microns; and other larger windows (sized to impart a higher current capability to their associated solder bumps 22) may have dimensions of approximately 80 by 40 microns. As another example, in other embodiments of the invention, some of the windows may be approximately square and have dimensions of approximately 100 by 100 microns; and other larger windows (sized to impart a higher current capability to their associated solder bumps 22) may have dimensions of approximately 100 by 150 microns. Other variations, size differences and shapes of the windows are contemplated and are within the scope of the appended claims.
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FIG. 3 depicts anotherembodiment 200 for the integrated circuit package. In this embodiment, thepackage 10 includes different features to increase the current carrying capability of the solder bumps 22. In this arrangement, theintegrated circuit 10 includes aninterconnection layer 26 to establish separate and redundant connections between the solder bumps 22 and thebuses 17. For example, in some embodiments of the invention, theinterconnection layer 26 may form bridges (such as bridges that form atriangle 30, as more clearly depicted in a top view inFIG. 4 ) that form redundant connection points 23 between the solder bumps 22 a, 22 b and 22 c. As depicted inFIG. 3 , these bridges may be part of a metal layer that is located between the solder bumps 22 and a metal layer in which thebuses 17 are formed. However, in other embodiments of the invention, theinterconnection layer 26 may be formed out of the same metal layer as thebuses 17. -
FIG. 5 depicts a cross-sectional view of theintegrated circuit 200, depicting theinterconnection layer 26 as being part of theupper metal layer 62. More particularly,FIG. 5 depicts aportion 208 of themetal layer 62 that forms redundant connections between solder bumps 22 (twosolder bumps 22 being depicted inFIG. 5 ). In this manner, eachsolder bump 22 is also connected to thebus 17 that is formed in the lowerlevel metal layer 65. Theintegrated circuit 200 may have additional metal layers that are disposed between the metal layers 62 and 65, such as ametal layer 64 that is depicted inFIG. 5 . In this manner, themetal layer 64 may includemetal pads 212 that are connected to themetal portion 208 throughvias 210, and themetal pads 212 may be connected to thebus 17 throughother vias 214. - Referring to
FIG. 7 , the electrical path between asolder bump 22 for a supply voltage and the correspondingbus 17 may be electrically represented by aresistor 100. However, unlike conditional arrangements, theinterconnection layer 26 forms redundant connections (depicted by theelectrical connections 102 between the solder bumps 22), thereby effectively shorting the solder bumps 22 together near the top of the die to form a lower resistance between eachsolder bump 22 and its associatedbus 17. - Although the
interconnection layer 26 has been described above in connection with an integrated circuit package that includes solder bumps 22, other arrangements are possible. For example,FIG. 6 depicts a top surface of a die 40 that includesbond pads 44 for communicating supply voltage to and from thedie 40. The interconnection layer may be formed, for example, bymetal lines 50, or bonding wire, that connectsvarious bond pads 44 together. For example, the bond pads denoted by the reference numeral “44 b” are connected together via the conductive traces 50. Other arrangements are possible. -
FIG. 8 depicts anintegrated circuit package 400 in which theinterconnection layer 26 is formed fromconductive traces Vertical vias 160 form connections between thetraces buses 17. -
FIG. 9 depicts anintegrated circuit package 450 in which theinterconnection layer 26 is formed in the same metal layer as thebuses 17. For example, in some embodiments of the invention, theinterconnection layer 26 may be formed by aconductive trace 120 that connects two of thebuses 17 together, and anotherconductive trace 122 that connects theother bus 17 to the two connected buses. Other arrangements are possible. -
FIG. 10 depicts another integratedcircuit package 500. In thepackage 500, theinterconnection layer 26 contains circuitry other than hard-wired conductive traces. In this manner, in some embodiments of the invention, theinterconnection layer 26 may include switches, such as metal-oxide-semiconductor field-effect-transistors (MOSFETs) 500, that have their drain-source paths coupled between various solder bumps 22 to selectively form connection points 23 near the solder bumps 22. Thus, due to this arrangement, theMOSFETs 500 may be selectively closed to couple groups of the solder bumps 22 together. This arrangement may have various advantages, such as permitting grouping of the solder bumps 22 after fabrication of a particular integrated circuit. In this manner, it may be determined that certain solder bumps 22 require higher current densities than other solder bumps 22. Thus, the solder bumps 22 that require higher densities are connected together to effectively impart a higher current carrying capability to each of thesebumps 22. - Other embodiments are within the scope of the following claims. For example,
FIG. 11 depicts an arrangement in which an extra metal layer 533 (a metal seven layer, for example) is created on top of the passivation layer 16 (i.e., on the opposite side of thepassivation layer 16 from the other metal layers) for purposes of forming part or all of theinterconnection layer 26. In this manner, the metal for themetal layer 533 may be deposited on top of thepassivation layer 16. Next, a mask is used to form an etching pattern for purposes of permitting subsequent etching to remove metal from themetal layer 533 while leaving conductive traces (thetrace 534 depicted inFIG. 11 , as an example) to selectively form connections between the solder bumps 22. As depicted inFIG. 11 , in an example, twosolder bumps conductive trace 534 of themetal layer 533. The solder bumps 22 f and 22 g extend through respective windows to contactrespective metal pads 540 of the nextlower metal layer 62. Other variations are possible. - While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
Claims (8)
1-19. (canceled)
20. A method usable with a semiconductor device, comprising:
electrical connecting external contacts of a semiconductor device to internal buses of the semiconductor device;
establishing redundant connections between the buses and the external contacts.
21-24. (canceled)
25. A method usable with a semiconductor device, comprising:
electrical connecting external contacts of a semiconductor device to internal buses of the semiconductor device;
establishing redundant connections between the buses and the external contacts;
forming a passivation layer;
providing contacts that are exposed for external connections with the semiconductor device on one side of the passivation layer; and
forming the redundant connections on said one side.
26. The method of claim 25 , wherein the forming comprises:
depositing a metal layer on said one side; and
selectively etching the metal layer to form the redundant connections.
27. The method of claim 25 , wherein the semiconductor device comprises a microprocessor.
28. The method of claim 25 , wherein the external connections comprise solder bumps.
29. The method of claim 25 , wherein the external connections comprise bond pads.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/203,849 US20060033211A1 (en) | 2001-10-30 | 2005-08-15 | Power gridding scheme |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US10/022,700 US6979896B2 (en) | 2001-10-30 | 2001-10-30 | Power gridding scheme |
US10/680,772 US6930379B2 (en) | 2001-10-30 | 2003-10-07 | Power gridding scheme |
US11/203,849 US20060033211A1 (en) | 2001-10-30 | 2005-08-15 | Power gridding scheme |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/680,772 Division US6930379B2 (en) | 2001-10-30 | 2003-10-07 | Power gridding scheme |
Publications (1)
Publication Number | Publication Date |
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US20060033211A1 true US20060033211A1 (en) | 2006-02-16 |
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Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
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US10/022,700 Expired - Lifetime US6979896B2 (en) | 2001-10-30 | 2001-10-30 | Power gridding scheme |
US10/680,772 Expired - Lifetime US6930379B2 (en) | 2001-10-30 | 2003-10-07 | Power gridding scheme |
US11/203,849 Abandoned US20060033211A1 (en) | 2001-10-30 | 2005-08-15 | Power gridding scheme |
US11/203,724 Expired - Lifetime US7511370B2 (en) | 2001-10-30 | 2005-08-15 | Power gridding scheme |
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Application Number | Title | Priority Date | Filing Date |
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US10/022,700 Expired - Lifetime US6979896B2 (en) | 2001-10-30 | 2001-10-30 | Power gridding scheme |
US10/680,772 Expired - Lifetime US6930379B2 (en) | 2001-10-30 | 2003-10-07 | Power gridding scheme |
Family Applications After (1)
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US11/203,724 Expired - Lifetime US7511370B2 (en) | 2001-10-30 | 2005-08-15 | Power gridding scheme |
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US (4) | US6979896B2 (en) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6979896B2 (en) * | 2001-10-30 | 2005-12-27 | Intel Corporation | Power gridding scheme |
US7566964B2 (en) * | 2003-04-10 | 2009-07-28 | Agere Systems Inc. | Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures |
US20050046016A1 (en) * | 2003-09-03 | 2005-03-03 | Ken Gilleo | Electronic package with insert conductor array |
WO2005024912A2 (en) * | 2003-09-09 | 2005-03-17 | Intel Corporation | Methods of processing thick ild layers using spray coating or lamination for c4 wafer level thick metal integrated flow |
US7906424B2 (en) | 2007-08-01 | 2011-03-15 | Advanced Micro Devices, Inc. | Conductor bump method and apparatus |
US20090032941A1 (en) * | 2007-08-01 | 2009-02-05 | Mclellan Neil | Under Bump Routing Layer Method and Apparatus |
JP2009252805A (en) * | 2008-04-01 | 2009-10-29 | Nec Electronics Corp | Semiconductor integrated circuit, its layout method and layout program |
US8314474B2 (en) * | 2008-07-25 | 2012-11-20 | Ati Technologies Ulc | Under bump metallization for on-die capacitor |
US8247906B2 (en) | 2009-07-06 | 2012-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Supplying power to integrated circuits using a grid matrix formed of through-silicon vias |
US8237274B1 (en) * | 2010-05-13 | 2012-08-07 | Xilinx, Inc. | Integrated circuit package with redundant micro-bumps |
US11469198B2 (en) | 2018-07-16 | 2022-10-11 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device manufacturing method and associated semiconductor die |
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US5083187A (en) * | 1990-05-16 | 1992-01-21 | Texas Instruments Incorporated | Integrated circuit device having bumped power supply buses over active surface areas and method of manufacture thereof |
US5583376A (en) * | 1995-01-03 | 1996-12-10 | Motorola, Inc. | High performance semiconductor device with resin substrate and method for making the same |
US5591941A (en) * | 1993-10-28 | 1997-01-07 | International Business Machines Corporation | Solder ball interconnected assembly |
US6414248B1 (en) * | 2000-10-04 | 2002-07-02 | Honeywell International Inc. | Compliant attachment interface |
US6657130B2 (en) * | 2001-09-20 | 2003-12-02 | International Business Machines Corporation | Electrical and physical design integration method and apparatus for providing interconnections on first level ceramic chip carrier packages |
US6930379B2 (en) * | 2001-10-30 | 2005-08-16 | Intel Corporation | Power gridding scheme |
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US5629840A (en) * | 1992-05-15 | 1997-05-13 | Digital Equipment Corporation | High powered die with bus bars |
US6396136B2 (en) * | 1998-12-31 | 2002-05-28 | Texas Instruments Incorporated | Ball grid package with multiple power/ground planes |
US6538314B1 (en) * | 2002-03-29 | 2003-03-25 | International Business Machines Corporation | Power grid wiring for semiconductor devices having voltage islands |
-
2001
- 2001-10-30 US US10/022,700 patent/US6979896B2/en not_active Expired - Lifetime
-
2003
- 2003-10-07 US US10/680,772 patent/US6930379B2/en not_active Expired - Lifetime
-
2005
- 2005-08-15 US US11/203,849 patent/US20060033211A1/en not_active Abandoned
- 2005-08-15 US US11/203,724 patent/US7511370B2/en not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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US5083187A (en) * | 1990-05-16 | 1992-01-21 | Texas Instruments Incorporated | Integrated circuit device having bumped power supply buses over active surface areas and method of manufacture thereof |
US5591941A (en) * | 1993-10-28 | 1997-01-07 | International Business Machines Corporation | Solder ball interconnected assembly |
US5583376A (en) * | 1995-01-03 | 1996-12-10 | Motorola, Inc. | High performance semiconductor device with resin substrate and method for making the same |
US6414248B1 (en) * | 2000-10-04 | 2002-07-02 | Honeywell International Inc. | Compliant attachment interface |
US6657130B2 (en) * | 2001-09-20 | 2003-12-02 | International Business Machines Corporation | Electrical and physical design integration method and apparatus for providing interconnections on first level ceramic chip carrier packages |
US6930379B2 (en) * | 2001-10-30 | 2005-08-16 | Intel Corporation | Power gridding scheme |
Also Published As
Publication number | Publication date |
---|---|
US7511370B2 (en) | 2009-03-31 |
US20030080406A1 (en) | 2003-05-01 |
US6979896B2 (en) | 2005-12-27 |
US20060033197A1 (en) | 2006-02-16 |
US20040065948A1 (en) | 2004-04-08 |
US6930379B2 (en) | 2005-08-16 |
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