US20060057403A1 - Use of thin SOI to inhibit relaxation of SiGe layers - Google Patents
Use of thin SOI to inhibit relaxation of SiGe layers Download PDFInfo
- Publication number
- US20060057403A1 US20060057403A1 US11/268,096 US26809605A US2006057403A1 US 20060057403 A1 US20060057403 A1 US 20060057403A1 US 26809605 A US26809605 A US 26809605A US 2006057403 A1 US2006057403 A1 US 2006057403A1
- Authority
- US
- United States
- Prior art keywords
- layer
- sige
- present
- relaxation
- metastable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 239000000463 material Substances 0.000 claims description 32
- 238000009792 diffusion process Methods 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 25
- 229910045601 alloy Inorganic materials 0.000 abstract description 18
- 239000000956 alloy Substances 0.000 abstract description 18
- 230000007547 defect Effects 0.000 description 25
- 230000004888 barrier function Effects 0.000 description 22
- 239000012212 insulator Substances 0.000 description 19
- 150000002500 ions Chemical class 0.000 description 16
- 238000010438 heat treatment Methods 0.000 description 15
- 230000012010 growth Effects 0.000 description 10
- 239000007943 implant Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 7
- 238000002513 implantation Methods 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 230000006911 nucleation Effects 0.000 description 4
- 238000010899 nucleation Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- -1 i.e. Substances 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 238000002441 X-ray diffraction Methods 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- POIUWJQBRNEFGX-XAMSXPGMSA-N cathelicidin Chemical compound C([C@@H](C(=O)N[C@@H](CCCNC(N)=N)C(=O)N[C@@H](CCCCN)C(=O)N[C@@H](CO)C(=O)N[C@@H](CCCCN)C(=O)N[C@@H](CCC(O)=O)C(=O)N[C@@H](CCCCN)C(=O)N[C@@H]([C@@H](C)CC)C(=O)NCC(=O)N[C@@H](CCCCN)C(=O)N[C@@H](CCC(O)=O)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)N[C@@H](CCCCN)C(=O)N[C@@H](CCCNC(N)=N)C(=O)N[C@@H]([C@@H](C)CC)C(=O)N[C@@H](C(C)C)C(=O)N[C@@H](CCC(N)=O)C(=O)N[C@@H](CCCNC(N)=N)C(=O)N[C@@H]([C@@H](C)CC)C(=O)N[C@@H](CCCCN)C(=O)N[C@@H](CC(O)=O)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CCCNC(N)=N)C(=O)N[C@@H](CC(N)=O)C(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](C(C)C)C(=O)N1[C@@H](CCC1)C(=O)N[C@@H](CCCNC(N)=N)C(=O)N[C@@H]([C@@H](C)O)C(=O)N[C@@H](CCC(O)=O)C(=O)N[C@@H](CO)C(O)=O)NC(=O)[C@H](CC=1C=CC=CC=1)NC(=O)[C@H](CC(O)=O)NC(=O)CNC(=O)[C@H](CC(C)C)NC(=O)[C@@H](N)CC(C)C)C1=CC=CC=C1 POIUWJQBRNEFGX-XAMSXPGMSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000224 chemical solution deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/52—Alloys
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
- C30B31/02—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor by contacting with diffusion materials in the solid state
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
Definitions
- the present invention relates to a method of fabricating SiGe-on-insulator substrate materials, and more particular to a method of fabricating SiGe-on-insulator substrate materials in which the SiGe alloy layer is metastable, yet very resistant to relaxation.
- the present invention also relates to the SiGe-on-insulator substrate materials produced using the method of the present invention.
- CMOS complementary metal oxide semiconductor
- Relaxation of SiGe alloy layers can occur when the thickness of the layer exceeds a certain value (called the critical thickness) for a given Ge concentration in the alloy.
- the relaxation of strained SiGe alloy layers that are thicker than the critical thickness occurs primarily through the formation of strain-relieving misfit dislocations.
- Strained SiGe layers that are grown thicker than the critical thickness, but remain strained and defect-free, are said to be metastable. In fact, any strained layer whose total film energy (including the strain, thickness and defect components) is not minimized with respect to defect production is, by definition, metastable.
- Metastable-strained SiGe layers can be defect free if the growth conditions are chosen correctly. Specifically, relaxation by defect formation almost always occurs at local microscopic defect sites at the strained Si/SiGe interface. The growth of metastable SiGe layers, then, is most successful when the growth surface is atomically clean and free of existing defects. Once a metastable SiGe layer is grown, it can relax if the layers are annealed at a high enough temperature. The nucleation and growth rate of misfit dislocations are strongly temperature dependent. Relaxation occurs by defect production and growth until 1) there is not enough strain energy within the film to create another dislocation, and 2) the existing dislocations stall, become pinned, or get trapped by some other mechanism.
- thermodynamically stable SiGe layer is grown on a silicon-on-insulator (SOI) substrate and subsequently oxidized at high temperatures (on the order of about 1200° C. or greater), the final SGOI material formed will generally remain fully strained. This is because the only mechanism available to relieve strain at the substrate level is through defects; and since there is not enough strain energy to form defects, no relaxation occurs. If a metastable SiGe layer is grown on an SOI substrate and oxidized at high temperatures, the layer will tend towards a minimum film energy condition with respect to the residual SiGe film strain and the extent of lattice relaxation (by defect generation). In some applications, it is advantageous to form SGOI that remain fully strained, i.e., no relaxation, rather than a relaxed SiGe layer.
- SOI silicon-on-insulator
- the applicants of the present application have determined that when high-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 ⁇ or less, the SiGe layers can remain substantially strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures.
- the present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.
- the present method has applications to, for example, 1) the selective relaxation of SiGe on a given substrate surface or 2) having fully strained SGOI with SiGe thickness greater than the critical value for a given Ge fraction.
- the method of the present invention which is useful in fabricating high-quality metastable SiGe-on-insulators, comprises the steps of:
- a Ge-containing layer on a surface of a top Si-containing layer having a thickness of about 500 ⁇ or less and being located on a barrier layer that is resistant to Ge diffusion;
- the metastable, strained single crystal layer SiGe layer formed using the method of the present invention can be a continuous layer that is present atop the entire substrate, or it can be present as a patterned region atop the substrate.
- the present invention also provides a SiGe-on-insulator substrate material that is formed using the above-mentioned processing steps.
- the inventive substrate material comprises a Si-containing substrate, an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate, and a substantially metastable SiGe layer which is resistant to relaxation present atop the insulating region.
- FIGS. 1A-1D are pictorial representations (through cross-sectional views) showing the basic processing steps that are employed in the present invention in fabricating a high-quality, substantially metastable SiGe-on-insulator substrate material wherein the initial substrate includes an unpatterned diffusion barrier region.
- FIGS. 2 A-D are pictorial representations (through cross-sectional views) showing the basic processing steps that are employed in an alternative embodiment of the present invention in fabricating a high-quality, substantially metastable SiGe-on-insulator substrate material wherein the initial substrate includes a patterned diffusion barrier region.
- FIGS. 3A-3B are pictorial representations (through cross-sectional views) showing an alternative embodiment of the present invention wherein a Si cap layer is formed atop a Ge-containing layer which is formed on an unpatterned ( 3 A) or patterned ( 3 B) substrate.
- FIGS. 4A-4B are pictorial representations (through cross-sectional views) showing an alternative embodiment of the present invention in which selective ion implantation is performed to form regions of metastable and strained SiGe and relaxed SiGe atop a barrier layer that is resistant to Ge diffusion.
- FIG. 5 is a graph plotting final SGOI Relaxation (%) vs. starting SOI thickness ( ⁇ ).
- FIG. 1A and FIG. 2A show initial substrate materials that can be employed in the present invention.
- the initial substrate materials illustrated in FIGS. 1A and 2A each comprise Si-containing semiconductor substrate 10 , barrier layer 12 which is resistant to Ge diffusion (hereinafter “barrier layer”) present atop a surface of Si-containing semiconductor substrate 10 and a top Si-containing layer 14 present atop the barrier layer 12 .
- barrier layer which is resistant to Ge diffusion
- FIG. 1A the barrier layer 12 is present continuously throughout the entire structure
- the barrier layer 12 is present as discrete and isolated regions or islands that are surrounded by semiconductor material, i.e., layers 10 and 14 .
- the initial structure shown in FIG. 1A thus includes an unpatterned barrier layer
- the initial structure of FIG. 2A includes a patterned barrier layer.
- the initial structure may be a conventional silicon-on-insulator (SOI) substrate material wherein region 12 is a buried oxide region which electrically isolates top Si-containing layer 14 from the Si-containing substrate semiconductor substrate 10 .
- the top Si-containing layer 14 can be referred to as the SOI layer.
- Si-containing denotes a single crystal semiconductor material that includes at least silicon.
- Illustrative examples include, but are not limited to: Si, SiGe, SiC, SiGeC, Si/Si, Si/SiC, Si/SiGeC, and preformed silicon-on-insulators which may include any number of buried oxide (continuous, non-continuous or mixtures of continuous and non-continuous) regions present therein.
- the SOI substrate may be formed utilizing conventional SIMOX (separation by ion implantation of oxygen) processes well-known to those skilled in the art, as well as the various SIMOX processes mentioned in co-assigned U.S. patent application Ser. No. 09/861,593, filed May 21, 2001; Ser. No. 09/861,594, filed May 21, 2001; Ser. No. 09/861,590, filed May 21, 2001; Ser. No. 09/861,596, filed May 21, 2001; and Ser. No. 09/884,670, filed Jun. 19, 2001 as well as U.S. Pat. No. 5,930,634 to Sadana, et al., the entire contents of each are being incorporated herein by reference. Note that the process disclosed in the '590 application can be employed herein to fabricate the patterned substrate shown in FIG. 2A . Alternatively, the SOI substrate material may be made using other conventional processes including, for example, a thermal bonding and layer transfer process.
- the initial substrates shown in FIGS. 1A and 2A may be a non-SOI substrate that is made using conventional deposition processes as well as lithography and etching (employed when fabricating a patterned substrate).
- the initial structure is formed by depositing a crystalline Ge diffusion barrier layer atop a surface of a Si-containing substrate, via conventional deposition, thermal growing processes or atomic layer deposition (ALD); optionally patterning the barrier layer by employing conventional lithography and etching; and thereafter forming a Si-containing layer atop the barrier layer using conventional deposition processes including chemical vapor deposition (CVD), plasma-assisted CVD, sputtering, evaporation, chemical solution deposition or epitaxial Si growth.
- CVD chemical vapor deposition
- CVD chemical vapor deposition
- sputtering evaporation
- chemical solution deposition or epitaxial Si growth chemical solution deposition
- Barrier layer 12 of the initial structure shown in FIGS. 1A and 2A comprises any insulating material that is highly resistant to Ge diffusion.
- insulating and Ge diffusion resistant materials include, but are not limited to: crystalline or non-crystalline oxides or nitrides.
- the top Si-containing layer 14 of the initial structure is a relatively thin layer.
- the term “relatively thin” is used in the present invention to denote a top Si-containing layer 14 thickness of about 500 ⁇ or less, with a thickness of from about 10 to about 350 ⁇ being more highly preferred.
- the thin top Si-containing layer 14 can be obtained by cutting, proper choice of implantation conditions, proper choice of deposition conditions, etching, planarization or oxidation-based thinning of thicker SOI layers.
- barrier layer 12 i.e., Ge diffusion resistant layer
- that layer may have a thickness of from about 1 to about 1000 nm, with a thickness of from about 20 to about 200 nm being more highly preferred.
- the thickness of the Si-containing substrate layer, i.e., layer 10 is inconsequential to the present invention.
- FIGS. 1B and 2B illustrate the structure that is formed after Ge-containing layer 16 is formed atop the top Si-containing layer 14 .
- the Ge-containing layer 16 can be comprised of pure Ge or a SiGe alloy layer.
- the term “SiGe alloy layer” includes SiGe alloys that comprise up to 99.99 atomic percent Ge, more preferably alloys where the Ge content is from about 0.1 to about 99.9 atomic percent. Even more preferably, the SiGe alloys used in the present invention have a Ge atomic percent of from about 10 to about 35.
- the Ge-containing layer 16 is formed atop first Si-containing layer 14 using any conventional epitaxial growth method that is known to those skilled in the art that is capable of growing a SiGe alloy or pure Ge layer that is metastable and substantially free from defects, i.e., misfit and threading dislocations.
- epitaxial growing processes that are capable of growing metastable and substantially defect free films include, but are not limited to: low-pressure chemical vapor deposition (LPCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), molecular beam (MBE) epitaxy and plasma-enhanced chemical vapor deposition (PECVD).
- the thickness of the Ge-containing layer 16 formed at this point of the present invention may vary, but typically layer 16 has a thickness of from about 10 to about 500 nm, with a thickness of from about 20 to about 200 nm being more highly preferred.
- optional cap layer 18 is formed atop the Ge-containing layer 16 prior to performing the heating step of the present invention.
- the optional cap layer 18 employed in the present invention comprises any Si material including, but not limited to: epitaxial silicon (epi-Si), amorphous silicon (a:Si), single or polycrystalline Si or any combination thereof including multilayers.
- the cap layer is comprised of epi Si. It is noted that layers 16 and 18 may, or may not, be formed in the same reaction chamber.
- the optional cap layer 18 has a thickness of from about 1 to about 100 nm, with a thickness of from about 1 to about 30 nm being more highly preferred.
- the optional cap layer 18 is formed utilizing any known deposition process including the epitaxial growth processes mentioned above.
- a pure Ge or SiGe alloy (15 to 20 atomic percent Ge) layer having a thickness of from about 1 to about 500 nm on the surface of a Si-containing layer, and thereafter forming a Si cap layer having a thickness of from about 1 to about 100 nm atop the Ge-containing layer.
- the structure shown in either FIG. 1B, 2B , 3 A or 3 B is then heated, i.e., annealed, at a temperature which permits interdiffusion of Ge throughout top Si-containing layer 14 , Ge-containing layer 16 and, if present, the optional Si cap 18 thereby forming a substantially metastable, single crystal SiGe layer 20 that is highly resistant to relaxation atop the barrier layer.
- a surface oxide layer 22 is formed atop the SiGe layer 20 .
- the surface oxide layer 22 is typically, but not always, removed from the structure after the heating step using a conventional wet etch process wherein a chemical etchant such as HF that has a high selectivity for removing oxide as compared to SiGe is employed.
- a chemical etchant such as HF that has a high selectivity for removing oxide as compared to SiGe is employed.
- FIGS. 1C and 2C show the structure that is formed after the heating steps has been performed.
- a single crystal Si layer can be formed atop layer 20 and the above processing steps of the present invention may be repeated any number of times to produce a multilayered substantially metastable SiGe substrate material.
- the surface oxide layer 22 formed after the heating step of the present invention has a variable thickness which may range from about 10 to about 1000 nm, with a thickness of from about 20 to about 500 nm being more highly preferred.
- the heating step of the present invention is an annealing step that is performed at a temperature of from about 900° to about 1350° C., with a temperature of from about 1200° to about 1335° C. being more highly preferred.
- the heating step of the present invention is carried out in an oxidizing ambient which includes at least one oxygen-containing gas such as O 2 , NO, N 2 O, ozone, air and other like oxygen-containing gases.
- the oxygen-containing gas may be admixed with each other (such as an admixture of O 2 and NO), or the gas may be diluted with an inert gas such as He, Ar, N 2 , Xe, Kr, or Ne.
- the heating step of the present invention may be carried out for a variable period of time that typically ranges from about 10 to about 1800 minutes, with a time period of from about 60 to about 600 minutes being more highly preferred.
- the heating step may be carried out at a single targeted temperature, or various ramp and soak cycles using various ramp rates and soak times can be employed.
- the heating step is performed under an oxidizing ambient to achieve the presence of a surface oxide layer 22 , which acts as a diffusion barrier to Ge atoms. Therefore, once the oxide layer is formed on the surface of the structure, Ge becomes trapped between barrier layer 12 and surface oxide layer 22 . As the surface oxide increases in thickness, the Ge becomes more uniformly distributed throughout layers 14 , 16 , and optionally 18 , but it is continually and efficiently rejected from the encroaching oxide layer. So as the (now homogenized) layers are thinned during this heating step, the relative Ge fraction increases. Efficient thermal mixing is achieved in the present invention when the heating step is carried out at a temperature of from about 1200° to about 1320° C. in a diluted oxygen-containing gas.
- the role of the heating step of the present invention is to allow Ge atoms to diffuse more quickly thereby maintaining a homogeneous distribution during annealing.
- the structure includes a uniform and substantially metastable SiGe alloy layer 20 , sandwiched between barrier layer 12 and surface oxide layer 22 . Because the initial Si-containing layer was thin, the thus formed SiGe alloy layer is frustrated since it is not permitted to relax because the usual mechanisms responsible for nucleation and growth of strain-relieving dislocations have, in some way, changed.
- the measured relaxation of the substantially metastable SiGe layer is between 0 to 85% of the relaxation value measured on similar SiGe layers formed using thicker starting SOI layers (greater than 500 ⁇ ). More typically, the measured value of relaxation is between 5 to 50% of the value that is measured on equivalent SiGe layers formed using thicker starting SOI layers; the resistance to relaxation is a function of the SOI thickness as shown in FIG. 5 .
- the SiGe layer 20 has a thickness of about 2000 nm or less, with a thickness of from about 10 to about 100 nm being more highly preferred. Note that the SiGe layer 20 formed in the present invention is thin.
- the SiGe layer 20 formed in the present invention has a final Ge content of from about 0.1 to about 99.9 atomic percent, with an atomic percent of Ge of from about 10 to about 35 being more highly preferred. Another characteristic feature of SiGe layer 20 is that it is a strained layer.
- the surface oxide layer 22 may be stripped at this point of the present invention so as to provide the SiGe-on-insulator substrate material shown, for example, in FIGS. 1D or 2 D (note that the substrate material does not include the cap layer since that layer has been used in forming the SiGe layer).
- ions are implanted into predetermined portions of the top Si-containing layer 14 prior to annealing. Specifically after forming the Ge-containing layer 16 (with or without the optional cap layer 18 ) atop the initial structure, the structure is then subjected to an ion implantation step wherein ions that are capable of forming or nucleating strain-relieving defects within the top Si-containing layer 14 or near the interface between the top Si-containing layer 14 and the Ge-containing layer 16 is performed.
- the implant may be performed with an implantation mask that is located on the surface of the structure or some distance from the structure.
- FIG. 4A The structure after this implantation step is shown in FIG. 4A (without optional cap layer).
- reference numeral 19 denotes the defect regions formed by the ion implantation step and reference numeral 17 denotes the interface between the top Si-containing layer 14 and the Ge-containing layer 16 .
- the defect regions solve the problem of defect production in the Ge-containing layer/Si-containing layer bilayer by allowing formation or nucleation and growth of strain-relieving defects in said regions.
- Implantation conditions for a particular ion are chosen to place the ion peak concentration within or near the Si-containing layer 14 .
- Highly preferred ions are those that are compatible with modern CMOS manufacturing: H, B, C, N, O, Si, P, Ge, As or any of the inert gas ions.
- Example ions used in the present invention are hydrogen ions (H + ). It is noted that other species of hydrogen such as H 2 + are also contemplated herein.
- the implant step of the present invention is conducted at approximately room temperature, i.e., a temperature of from about 283 K to about 303 K, using a beam current density of from about 0.01 to about 10 microamps/cm 2 . Implantation at different temperatures and/or using other beam current densities may affect defect formation.
- the concentration of the implant species used in forming the platelet defects may vary depending upon the type of implant species employed. Typically, however, the concentration of implanted ions (H) used at this point of the present invention is below 3E16 cm ⁇ 2 , with an ion concentration of from about 1E16 to about 2.99E16 cm ⁇ 2 being more highly preferred.
- the energy of this implant may also vary depending upon the type of ion that is being implanted, with the proviso that the implant energy must be capable of positioning ions within layer 14 or near the interface between layers 14 and 16 . For example, when hydrogen is employed as the implant ion, the energy used to ensure defect formation within layer 14 or near the interface between layers 14 and 16 is from about 1 to about 100 keV, with an energy of from about 3 to about 20 keV being more highly preferred.
- the optional cap may be formed atop the Ge-containing alloy layer.
- the implanted structure is heated, i.e., annealed, using the conditions described above.
- FIG. 4B illustrates the structure that is formed after the annealing step.
- the substantially metastable and strained SiGe portions are labeled as 20
- substantially relaxed SiGe portions that received the above described ion implant are labeled as 23 .
- the measured relaxation of the substantially relaxed SiGe region 23 is between 90 to 110% of the relaxation value measured on SiGe layers with equivalent film thickness and Ge concentration formed using thicker starting SOI layer 14 (greater than 500 ⁇ ) without ion implantation.
- the possibility of relaxed SiGe region 23 having greater than 100% of the relaxation value of equivalent SiGe layers is due to the fact that ion-implanted strained layers tend to relax more efficiently because of the random nature of the defect nucleation.
- a Si layer can be formed atop the SiGe layer (relaxed and/or metastable) using a conventional epitaxial deposition process well-known in the art.
- the thickness of the epi-Si layer may vary, but typically, the epi-Si layer has a thickness of from about 1 to about 100 nm, with a thickness of from about 1 to about 50 nm being more highly preferred.
- additional SiGe can be formed atop SiGe layer (relaxed and/or metastable) utilizing the above-mentioned processing steps, and thereafter an epi-Si layer may be formed. Because the relaxed SiGe layer has a large in-plane lattice parameter as compared to the epi-Si layer, the epi-layer will be strained in a tensile manner.
- the present invention also contemplates superlattice structures as well as lattice mismatched structures which include at least the SiGe-on-insulator substrate material of the present invention.
- superlattice structures such structures would include at least the SiGe-on-insulator substrate material of the present invention, and alternating layers Si and SiGe formed atop the SiGe layer of the substrate material.
- GaAs, GaP or other like compound would be formed atop the SiGe layer of the inventive SiGe-on-insulator substrate material.
- the final SGOI relaxation for samples having various SOI starting thickness were determined. Specifically, the measured relaxation of SGOI layers made by growing 600 ⁇ -17% SiGe on SOI substrates with a top SOI layer having a thickness ranging from 1450 ⁇ down to 200 ⁇ was determined. All of the structures were then converted into approximately 380 ⁇ -28% SiGe SGOI using the method described above. Specifically, the initial SiGe/Si bilayer is oxidized at a high temperature of about 1200° C. allowing Ge to diffuse uniformly throughout the layers while being rejected from the growing surface oxide layer. This way, the total Ge content is retained as the (homogenized) SGOI layer is thinned by the oxidation process. The SOI thickness reported in FIG.
- FIG. 5 does not take into account the thin Si buffer layer that is grown before the SiGe layer is grown which is part of the low-temperature epitaxial process.
- FIG. 5 clearly shows a rapid decrease in the measured relaxation (using X-ray diffraction) of the final SGOI with decreasing initial top SOI layer thickness. It is the region in FIG. 5 below 500 ⁇ starting SOI thickness that the inventive highly metastable and relaxation-resistant silicon-germanium-on-insulator is realized.
Abstract
Description
- The present invention relates to a method of fabricating SiGe-on-insulator substrate materials, and more particular to a method of fabricating SiGe-on-insulator substrate materials in which the SiGe alloy layer is metastable, yet very resistant to relaxation. The present invention also relates to the SiGe-on-insulator substrate materials produced using the method of the present invention.
- In the semiconductor industry, there has recently been a high-level of activity using strained Si-based heterostructures to achieve high mobility structures for complementary metal oxide semiconductor (CMOS) applications. In such heterostructures, the strained Si is typically formed atop a relaxed SiGe alloy layer.
- Relaxation of SiGe alloy layers can occur when the thickness of the layer exceeds a certain value (called the critical thickness) for a given Ge concentration in the alloy. The relaxation of strained SiGe alloy layers that are thicker than the critical thickness occurs primarily through the formation of strain-relieving misfit dislocations. Strained SiGe layers that are grown thicker than the critical thickness, but remain strained and defect-free, are said to be metastable. In fact, any strained layer whose total film energy (including the strain, thickness and defect components) is not minimized with respect to defect production is, by definition, metastable.
- Metastable-strained SiGe layers can be defect free if the growth conditions are chosen correctly. Specifically, relaxation by defect formation almost always occurs at local microscopic defect sites at the strained Si/SiGe interface. The growth of metastable SiGe layers, then, is most successful when the growth surface is atomically clean and free of existing defects. Once a metastable SiGe layer is grown, it can relax if the layers are annealed at a high enough temperature. The nucleation and growth rate of misfit dislocations are strongly temperature dependent. Relaxation occurs by defect production and growth until 1) there is not enough strain energy within the film to create another dislocation, and 2) the existing dislocations stall, become pinned, or get trapped by some other mechanism.
- The above physical properties of metastable strained SiGe layers put limitations on what initial SiGe layers can be applied to the thermal mixing method of fabricating SiGe-on-insulator (SGOI) substrate materials. The thermal mixing method is disclosed, for example, in co-pending and co-assigned U.S. patent application Ser. No. 10/055,138, filed Jan. 23, 2002, entitled “Method to Create High-Quality SiGe-On-Insulator for Strained Si CMOS Applications”.
- If a thermodynamically stable SiGe layer is grown on a silicon-on-insulator (SOI) substrate and subsequently oxidized at high temperatures (on the order of about 1200° C. or greater), the final SGOI material formed will generally remain fully strained. This is because the only mechanism available to relieve strain at the substrate level is through defects; and since there is not enough strain energy to form defects, no relaxation occurs. If a metastable SiGe layer is grown on an SOI substrate and oxidized at high temperatures, the layer will tend towards a minimum film energy condition with respect to the residual SiGe film strain and the extent of lattice relaxation (by defect generation). In some applications, it is advantageous to form SGOI that remain fully strained, i.e., no relaxation, rather than a relaxed SiGe layer.
- In view of the above, it would seem that the fabrication of fully strained SiGe-on-insulators is only possible by using thermodynamically stable SiGe layers. Such a method however places constraints on the total SGOI film thickness for a given Ge concentration.
- Despite the current state of the art, applicants are unaware of any ongoing effort to create a “frustrated” SGOI film in which the SiGe layer is metastable, yet very resistant to relaxation.
- The applicants of the present application have determined that when high-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.
- The present method has applications to, for example, 1) the selective relaxation of SiGe on a given substrate surface or 2) having fully strained SGOI with SiGe thickness greater than the critical value for a given Ge fraction. In case 1) above, one can use a method of implanting ions into the thin Si layer to create dislocations that allow relaxation to occur in regions in which the implantation is performed.
- In broad terms, the method of the present invention, which is useful in fabricating high-quality metastable SiGe-on-insulators, comprises the steps of:
- forming a Ge-containing layer on a surface of a top Si-containing layer having a thickness of about 500 Å or less and being located on a barrier layer that is resistant to Ge diffusion; and
- heating said layers at a temperature which permits interdiffusion of Ge throughout said top Si-containing layer and said Ge-containing layer thereby forming a substantially metastable, SiGe layer that is resistant to relaxation atop said barrier layer.
- The metastable, strained single crystal layer SiGe layer formed using the method of the present invention can be a continuous layer that is present atop the entire substrate, or it can be present as a patterned region atop the substrate.
- The present invention also provides a SiGe-on-insulator substrate material that is formed using the above-mentioned processing steps. Specifically, the inventive substrate material comprises a Si-containing substrate, an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate, and a substantially metastable SiGe layer which is resistant to relaxation present atop the insulating region.
-
FIGS. 1A-1D are pictorial representations (through cross-sectional views) showing the basic processing steps that are employed in the present invention in fabricating a high-quality, substantially metastable SiGe-on-insulator substrate material wherein the initial substrate includes an unpatterned diffusion barrier region. - FIGS. 2A-D are pictorial representations (through cross-sectional views) showing the basic processing steps that are employed in an alternative embodiment of the present invention in fabricating a high-quality, substantially metastable SiGe-on-insulator substrate material wherein the initial substrate includes a patterned diffusion barrier region.
-
FIGS. 3A-3B are pictorial representations (through cross-sectional views) showing an alternative embodiment of the present invention wherein a Si cap layer is formed atop a Ge-containing layer which is formed on an unpatterned (3A) or patterned (3B) substrate. -
FIGS. 4A-4B are pictorial representations (through cross-sectional views) showing an alternative embodiment of the present invention in which selective ion implantation is performed to form regions of metastable and strained SiGe and relaxed SiGe atop a barrier layer that is resistant to Ge diffusion. -
FIG. 5 is a graph plotting final SGOI Relaxation (%) vs. starting SOI thickness (Å). - The present invention, which provides a method of fabricating high-quality, substantially metastable SiGe-on-insulator substrate materials in which the SiGe layer is resistant to relaxation, will now be described in greater detail by referring to the drawings the accompany the present application. In the drawings, like and/or corresponding elements are referred to by like reference numerals.
- Reference is first made to
FIG. 1A andFIG. 2A which show initial substrate materials that can be employed in the present invention. Specifically, the initial substrate materials illustrated inFIGS. 1A and 2A each comprise Si-containingsemiconductor substrate 10,barrier layer 12 which is resistant to Ge diffusion (hereinafter “barrier layer”) present atop a surface of Si-containingsemiconductor substrate 10 and a top Si-containinglayer 14 present atop thebarrier layer 12. The difference between the two initial structures depicted in the drawings is that, inFIG. 1A , thebarrier layer 12 is present continuously throughout the entire structure, whereas inFIG. 2A , thebarrier layer 12 is present as discrete and isolated regions or islands that are surrounded by semiconductor material, i.e.,layers FIG. 1A thus includes an unpatterned barrier layer, whereas the initial structure ofFIG. 2A includes a patterned barrier layer. - Notwithstanding whether the barrier layer is patterned or unpatterned, the initial structure may be a conventional silicon-on-insulator (SOI) substrate material wherein
region 12 is a buried oxide region which electrically isolates top Si-containinglayer 14 from the Si-containingsubstrate semiconductor substrate 10. The top Si-containinglayer 14 can be referred to as the SOI layer. The term “Si-containing” as used herein denotes a single crystal semiconductor material that includes at least silicon. Illustrative examples include, but are not limited to: Si, SiGe, SiC, SiGeC, Si/Si, Si/SiC, Si/SiGeC, and preformed silicon-on-insulators which may include any number of buried oxide (continuous, non-continuous or mixtures of continuous and non-continuous) regions present therein. - The SOI substrate may be formed utilizing conventional SIMOX (separation by ion implantation of oxygen) processes well-known to those skilled in the art, as well as the various SIMOX processes mentioned in co-assigned U.S. patent application Ser. No. 09/861,593, filed May 21, 2001; Ser. No. 09/861,594, filed May 21, 2001; Ser. No. 09/861,590, filed May 21, 2001; Ser. No. 09/861,596, filed May 21, 2001; and Ser. No. 09/884,670, filed Jun. 19, 2001 as well as U.S. Pat. No. 5,930,634 to Sadana, et al., the entire contents of each are being incorporated herein by reference. Note that the process disclosed in the '590 application can be employed herein to fabricate the patterned substrate shown in
FIG. 2A . Alternatively, the SOI substrate material may be made using other conventional processes including, for example, a thermal bonding and layer transfer process. - In addition to SOI substrates, the initial substrates shown in
FIGS. 1A and 2A may be a non-SOI substrate that is made using conventional deposition processes as well as lithography and etching (employed when fabricating a patterned substrate). Specifically, when non-SOI substrates are employed, the initial structure is formed by depositing a crystalline Ge diffusion barrier layer atop a surface of a Si-containing substrate, via conventional deposition, thermal growing processes or atomic layer deposition (ALD); optionally patterning the barrier layer by employing conventional lithography and etching; and thereafter forming a Si-containing layer atop the barrier layer using conventional deposition processes including chemical vapor deposition (CVD), plasma-assisted CVD, sputtering, evaporation, chemical solution deposition or epitaxial Si growth. -
Barrier layer 12 of the initial structure shown inFIGS. 1A and 2A comprises any insulating material that is highly resistant to Ge diffusion. Examples of such insulating and Ge diffusion resistant materials include, but are not limited to: crystalline or non-crystalline oxides or nitrides. - In accordance with the present invention, the top Si-containing
layer 14 of the initial structure is a relatively thin layer. The term “relatively thin” is used in the present invention to denote a top Si-containinglayer 14 thickness of about 500 Å or less, with a thickness of from about 10 to about 350 Å being more highly preferred. The thin top Si-containinglayer 14 can be obtained by cutting, proper choice of implantation conditions, proper choice of deposition conditions, etching, planarization or oxidation-based thinning of thicker SOI layers. - In the case of barrier layer 12 (i.e., Ge diffusion resistant layer), that layer may have a thickness of from about 1 to about 1000 nm, with a thickness of from about 20 to about 200 nm being more highly preferred. The thickness of the Si-containing substrate layer, i.e.,
layer 10, is inconsequential to the present invention. -
FIGS. 1B and 2B illustrate the structure that is formed after Ge-containinglayer 16 is formed atop the top Si-containinglayer 14. The Ge-containinglayer 16 can be comprised of pure Ge or a SiGe alloy layer. The term “SiGe alloy layer” includes SiGe alloys that comprise up to 99.99 atomic percent Ge, more preferably alloys where the Ge content is from about 0.1 to about 99.9 atomic percent. Even more preferably, the SiGe alloys used in the present invention have a Ge atomic percent of from about 10 to about 35. - In accordance with the present invention, the Ge-containing
layer 16 is formed atop first Si-containinglayer 14 using any conventional epitaxial growth method that is known to those skilled in the art that is capable of growing a SiGe alloy or pure Ge layer that is metastable and substantially free from defects, i.e., misfit and threading dislocations. Illustrative examples of such epitaxial growing processes that are capable of growing metastable and substantially defect free films include, but are not limited to: low-pressure chemical vapor deposition (LPCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), molecular beam (MBE) epitaxy and plasma-enhanced chemical vapor deposition (PECVD). - The thickness of the Ge-containing
layer 16 formed at this point of the present invention may vary, but typicallylayer 16 has a thickness of from about 10 to about 500 nm, with a thickness of from about 20 to about 200 nm being more highly preferred. - In an alternative embodiment of the present invention, see
FIGS. 3A-3B ,optional cap layer 18 is formed atop the Ge-containinglayer 16 prior to performing the heating step of the present invention. Theoptional cap layer 18 employed in the present invention comprises any Si material including, but not limited to: epitaxial silicon (epi-Si), amorphous silicon (a:Si), single or polycrystalline Si or any combination thereof including multilayers. In a preferred embodiment, the cap layer is comprised of epi Si. It is noted thatlayers - When present, the
optional cap layer 18 has a thickness of from about 1 to about 100 nm, with a thickness of from about 1 to about 30 nm being more highly preferred. Theoptional cap layer 18 is formed utilizing any known deposition process including the epitaxial growth processes mentioned above. - In one embodiment of the present invention, it is preferred to form a pure Ge or SiGe alloy (15 to 20 atomic percent Ge) layer having a thickness of from about 1 to about 500 nm on the surface of a Si-containing layer, and thereafter forming a Si cap layer having a thickness of from about 1 to about 100 nm atop the Ge-containing layer.
- After forming the Ge-containing layer 16 (and optional cap layer 18) atop the initial structure, the structure shown in either
FIG. 1B, 2B , 3A or 3B is then heated, i.e., annealed, at a temperature which permits interdiffusion of Ge throughout top Si-containinglayer 14, Ge-containinglayer 16 and, if present, theoptional Si cap 18 thereby forming a substantially metastable, singlecrystal SiGe layer 20 that is highly resistant to relaxation atop the barrier layer. During the heating step, asurface oxide layer 22 is formed atop theSiGe layer 20. Thesurface oxide layer 22 is typically, but not always, removed from the structure after the heating step using a conventional wet etch process wherein a chemical etchant such as HF that has a high selectivity for removing oxide as compared to SiGe is employed.FIGS. 1C and 2C show the structure that is formed after the heating steps has been performed. - Note that when the surface oxide layer 24 is removed, a single crystal Si layer can be formed atop
layer 20 and the above processing steps of the present invention may be repeated any number of times to produce a multilayered substantially metastable SiGe substrate material. - The
surface oxide layer 22 formed after the heating step of the present invention has a variable thickness which may range from about 10 to about 1000 nm, with a thickness of from about 20 to about 500 nm being more highly preferred. - Specifically, the heating step of the present invention is an annealing step that is performed at a temperature of from about 900° to about 1350° C., with a temperature of from about 1200° to about 1335° C. being more highly preferred. Moreover, the heating step of the present invention is carried out in an oxidizing ambient which includes at least one oxygen-containing gas such as O2, NO, N2O, ozone, air and other like oxygen-containing gases. The oxygen-containing gas may be admixed with each other (such as an admixture of O2 and NO), or the gas may be diluted with an inert gas such as He, Ar, N2, Xe, Kr, or Ne.
- The heating step of the present invention may be carried out for a variable period of time that typically ranges from about 10 to about 1800 minutes, with a time period of from about 60 to about 600 minutes being more highly preferred. The heating step may be carried out at a single targeted temperature, or various ramp and soak cycles using various ramp rates and soak times can be employed.
- The heating step is performed under an oxidizing ambient to achieve the presence of a
surface oxide layer 22, which acts as a diffusion barrier to Ge atoms. Therefore, once the oxide layer is formed on the surface of the structure, Ge becomes trapped betweenbarrier layer 12 andsurface oxide layer 22. As the surface oxide increases in thickness, the Ge becomes more uniformly distributed throughoutlayers - It is also contemplated herein to use a tailored heat cycle that is based upon the melting point of the SiGe layer. In such an instance, the temperature is adjusted to tract at or near the melting point of the SiGe layer. This procedure is disclosed, for example, in co-pending and co-assigned U.S. patent application Ser. No. 10/448,948, filed May 30, 2003. The content of the aforementioned U.S. application is incorporated herein by reference.
- If the oxidation occurs too rapidly, Ge cannot diffuse away from the surface oxide/SiGe interface fast enough and is either transported through the oxide (and lost) or the interfacial concentration of Ge becomes so high that the alloy melting temperature will be reached.
- The role of the heating step of the present invention is to allow Ge atoms to diffuse more quickly thereby maintaining a homogeneous distribution during annealing. After this heating step has been performed, the structure includes a uniform and substantially metastable
SiGe alloy layer 20, sandwiched betweenbarrier layer 12 andsurface oxide layer 22. Because the initial Si-containing layer was thin, the thus formed SiGe alloy layer is frustrated since it is not permitted to relax because the usual mechanisms responsible for nucleation and growth of strain-relieving dislocations have, in some way, changed. The measured relaxation of the substantially metastable SiGe layer is between 0 to 85% of the relaxation value measured on similar SiGe layers formed using thicker starting SOI layers (greater than 500 Å). More typically, the measured value of relaxation is between 5 to 50% of the value that is measured on equivalent SiGe layers formed using thicker starting SOI layers; the resistance to relaxation is a function of the SOI thickness as shown inFIG. 5 . - In accordance with the present invention, the
SiGe layer 20 has a thickness of about 2000 nm or less, with a thickness of from about 10 to about 100 nm being more highly preferred. Note that theSiGe layer 20 formed in the present invention is thin. - The
SiGe layer 20 formed in the present invention has a final Ge content of from about 0.1 to about 99.9 atomic percent, with an atomic percent of Ge of from about 10 to about 35 being more highly preferred. Another characteristic feature ofSiGe layer 20 is that it is a strained layer. - As stated above, the
surface oxide layer 22 may be stripped at this point of the present invention so as to provide the SiGe-on-insulator substrate material shown, for example, inFIGS. 1D or 2D (note that the substrate material does not include the cap layer since that layer has been used in forming the SiGe layer). - In some embodiments of the present invention, it is possible to form a substrate material wherein portions of the SiGe layer are substantially relaxed and other portions of the SiGe layer are substantially metastable and strained. Such an embodiment is depicted in
FIGS. 4A-4B . In this embodiment, ions are implanted into predetermined portions of the top Si-containinglayer 14 prior to annealing. Specifically after forming the Ge-containing layer 16 (with or without the optional cap layer 18) atop the initial structure, the structure is then subjected to an ion implantation step wherein ions that are capable of forming or nucleating strain-relieving defects within the top Si-containinglayer 14 or near the interface between the top Si-containinglayer 14 and the Ge-containinglayer 16 is performed. Almost any ions can be used to form or nucleate strain-relieving defects because dislocations can nucleate from a wide range of crystalline imperfections such as vacancy clusters, point defects, platelet defects and bubble or void defects. The implant may be performed with an implantation mask that is located on the surface of the structure or some distance from the structure. - The structure after this implantation step is shown in
FIG. 4A (without optional cap layer). In this figure,reference numeral 19 denotes the defect regions formed by the ion implantation step andreference numeral 17 denotes the interface between the top Si-containinglayer 14 and the Ge-containinglayer 16. The defect regions solve the problem of defect production in the Ge-containing layer/Si-containing layer bilayer by allowing formation or nucleation and growth of strain-relieving defects in said regions. - Implantation conditions for a particular ion are chosen to place the ion peak concentration within or near the Si-containing
layer 14. Highly preferred ions are those that are compatible with modern CMOS manufacturing: H, B, C, N, O, Si, P, Ge, As or any of the inert gas ions. Example ions used in the present invention are hydrogen ions (H+). It is noted that other species of hydrogen such as H2 + are also contemplated herein. - The implant step of the present invention is conducted at approximately room temperature, i.e., a temperature of from about 283 K to about 303 K, using a beam current density of from about 0.01 to about 10 microamps/cm2. Implantation at different temperatures and/or using other beam current densities may affect defect formation.
- The concentration of the implant species used in forming the platelet defects may vary depending upon the type of implant species employed. Typically, however, the concentration of implanted ions (H) used at this point of the present invention is below 3E16 cm−2, with an ion concentration of from about 1E16 to about 2.99E16 cm−2 being more highly preferred. The energy of this implant may also vary depending upon the type of ion that is being implanted, with the proviso that the implant energy must be capable of positioning ions within
layer 14 or near the interface betweenlayers layer 14 or near the interface betweenlayers - After the implant step, and if not previously formed on the structure, the optional cap may be formed atop the Ge-containing alloy layer. Next, the implanted structure is heated, i.e., annealed, using the conditions described above.
FIG. 4B illustrates the structure that is formed after the annealing step. In this drawing, the surface oxide layer has been removed. The substantially metastable and strained SiGe portions are labeled as 20, while substantially relaxed SiGe portions that received the above described ion implant are labeled as 23. The measured relaxation of the substantiallyrelaxed SiGe region 23 is between 90 to 110% of the relaxation value measured on SiGe layers with equivalent film thickness and Ge concentration formed using thicker starting SOI layer 14 (greater than 500 Å) without ion implantation. The possibility ofrelaxed SiGe region 23 having greater than 100% of the relaxation value of equivalent SiGe layers is due to the fact that ion-implanted strained layers tend to relax more efficiently because of the random nature of the defect nucleation. - A Si layer can be formed atop the SiGe layer (relaxed and/or metastable) using a conventional epitaxial deposition process well-known in the art. The thickness of the epi-Si layer may vary, but typically, the epi-Si layer has a thickness of from about 1 to about 100 nm, with a thickness of from about 1 to about 50 nm being more highly preferred.
- In some instances, additional SiGe can be formed atop SiGe layer (relaxed and/or metastable) utilizing the above-mentioned processing steps, and thereafter an epi-Si layer may be formed. Because the relaxed SiGe layer has a large in-plane lattice parameter as compared to the epi-Si layer, the epi-layer will be strained in a tensile manner.
- As stated above, the present invention also contemplates superlattice structures as well as lattice mismatched structures which include at least the SiGe-on-insulator substrate material of the present invention. In the case of superlattice structures, such structures would include at least the SiGe-on-insulator substrate material of the present invention, and alternating layers Si and SiGe formed atop the SiGe layer of the substrate material.
- In the case of lattice mismatched structures, GaAs, GaP or other like compound would be formed atop the SiGe layer of the inventive SiGe-on-insulator substrate material.
- The following example is provided to illustrate the method of the present ion as well as some advantages that may be obtained therefrom.
- In this example, the final SGOI relaxation for samples having various SOI starting thickness were determined. Specifically, the measured relaxation of SGOI layers made by growing 600 Å-17% SiGe on SOI substrates with a top SOI layer having a thickness ranging from 1450 Å down to 200 Å was determined. All of the structures were then converted into approximately 380 Å-28% SiGe SGOI using the method described above. Specifically, the initial SiGe/Si bilayer is oxidized at a high temperature of about 1200° C. allowing Ge to diffuse uniformly throughout the layers while being rejected from the growing surface oxide layer. This way, the total Ge content is retained as the (homogenized) SGOI layer is thinned by the oxidation process. The SOI thickness reported in
FIG. 5 does not take into account the thin Si buffer layer that is grown before the SiGe layer is grown which is part of the low-temperature epitaxial process.FIG. 5 clearly shows a rapid decrease in the measured relaxation (using X-ray diffraction) of the final SGOI with decreasing initial top SOI layer thickness. It is the region inFIG. 5 below 500 Å starting SOI thickness that the inventive highly metastable and relaxation-resistant silicon-germanium-on-insulator is realized. - While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the scope and spirit of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/268,096 US20060057403A1 (en) | 2003-09-03 | 2005-11-07 | Use of thin SOI to inhibit relaxation of SiGe layers |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/654,232 US6989058B2 (en) | 2003-09-03 | 2003-09-03 | Use of thin SOI to inhibit relaxation of SiGe layers |
US11/268,096 US20060057403A1 (en) | 2003-09-03 | 2005-11-07 | Use of thin SOI to inhibit relaxation of SiGe layers |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/654,232 Division US6989058B2 (en) | 2003-09-03 | 2003-09-03 | Use of thin SOI to inhibit relaxation of SiGe layers |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060057403A1 true US20060057403A1 (en) | 2006-03-16 |
Family
ID=34218049
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/654,232 Expired - Lifetime US6989058B2 (en) | 2003-09-03 | 2003-09-03 | Use of thin SOI to inhibit relaxation of SiGe layers |
US11/268,096 Abandoned US20060057403A1 (en) | 2003-09-03 | 2005-11-07 | Use of thin SOI to inhibit relaxation of SiGe layers |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/654,232 Expired - Lifetime US6989058B2 (en) | 2003-09-03 | 2003-09-03 | Use of thin SOI to inhibit relaxation of SiGe layers |
Country Status (5)
Country | Link |
---|---|
US (2) | US6989058B2 (en) |
JP (1) | JP4732725B2 (en) |
KR (1) | KR100602534B1 (en) |
CN (1) | CN100350561C (en) |
TW (1) | TWI304622B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060214257A1 (en) * | 2005-03-25 | 2006-09-28 | Sumco Corporation | Production method of strained silicon-SOI substrate and strained silicon-SOI substrate produced by same |
US20090169843A1 (en) * | 2008-01-02 | 2009-07-02 | Tetsuya Mishima | Low-Defect-Density Crystalline Structure and Method for Making Same |
US20160351397A1 (en) * | 2014-02-12 | 2016-12-01 | International Business Machines Corporation | Silicon germanium-on-insulator formation by thermal mixing |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003098664A2 (en) * | 2002-05-15 | 2003-11-27 | The Regents Of The University Of California | Method for co-fabricating strained and relaxed crystalline and poly-crystalline structures |
US7169226B2 (en) * | 2003-07-01 | 2007-01-30 | International Business Machines Corporation | Defect reduction by oxidation of silicon |
US7084460B2 (en) * | 2003-11-03 | 2006-08-01 | International Business Machines Corporation | Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates |
KR100739099B1 (en) * | 2005-12-21 | 2007-07-12 | 주식회사 실트론 | Epitaxial wafer and maufacturing method thereof |
KR100738459B1 (en) * | 2005-12-30 | 2007-07-11 | 주식회사 실트론 | Method of fabricating Germanium-On-Insulator Substrate Using A SOI substrate |
US7563702B2 (en) * | 2006-04-28 | 2009-07-21 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device |
KR100792433B1 (en) | 2006-04-28 | 2008-01-10 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
DE102006058820A1 (en) * | 2006-12-13 | 2008-06-19 | Siltronic Ag | Method of making SGOI and GeOI semiconductor structures |
US8486776B2 (en) | 2010-09-21 | 2013-07-16 | International Business Machines Corporation | Strained devices, methods of manufacture and design structures |
TWI521600B (en) * | 2011-06-03 | 2016-02-11 | 應用材料股份有限公司 | Method of forming high growth rate, low resistivity germanium film on silicon substrate(1) |
US8828851B2 (en) * | 2012-02-01 | 2014-09-09 | Stmicroeletronics, Inc. | Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering |
CN106611697B (en) * | 2015-10-26 | 2019-11-05 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
US9728642B2 (en) | 2015-11-04 | 2017-08-08 | International Business Machines Corporation | Retaining strain in finFET devices |
US10453750B2 (en) * | 2017-06-22 | 2019-10-22 | Globalfoundries Inc. | Stacked elongated nanoshapes of different semiconductor materials and structures that incorporate the nanoshapes |
CN110660654B (en) * | 2019-09-30 | 2022-05-03 | 闽南师范大学 | Preparation method of ultra-high-quality SOI (silicon on insulator) -based bonded Ge film |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5759898A (en) * | 1993-10-29 | 1998-06-02 | International Business Machines Corporation | Production of substrate for tensilely strained semiconductor |
US5930634A (en) * | 1997-04-21 | 1999-07-27 | Advanced Micro Devices, Inc. | Method of making an IGFET with a multilevel gate |
US20020185686A1 (en) * | 2001-06-12 | 2002-12-12 | International Business Machines Corporation | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
US20030139000A1 (en) * | 2002-01-23 | 2003-07-24 | International Business Machines Corporation | Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications |
US6841457B2 (en) * | 2002-07-16 | 2005-01-11 | International Business Machines Corporation | Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion |
US6861158B2 (en) * | 2003-05-30 | 2005-03-01 | International Business Machines Corporation | Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2998330B2 (en) * | 1991-09-19 | 2000-01-11 | 日本電気株式会社 | SIMOX substrate and method of manufacturing the same |
JP3712599B2 (en) * | 2000-08-25 | 2005-11-02 | 株式会社東芝 | Semiconductor device and semiconductor substrate |
JP2002305293A (en) * | 2001-04-06 | 2002-10-18 | Canon Inc | Method of manufacturing semiconductor member, and method of manufacturing semiconductor device |
JP2003158250A (en) * | 2001-10-30 | 2003-05-30 | Sharp Corp | CMOS OF SiGe/SOI AND ITS MANUFACTURING METHOD |
JP3970011B2 (en) * | 2001-12-11 | 2007-09-05 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
US6515335B1 (en) * | 2002-01-04 | 2003-02-04 | International Business Machines Corporation | Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same |
JP4064682B2 (en) * | 2002-02-15 | 2008-03-19 | セイコーインスツル株式会社 | Integrated circuit |
JP3873012B2 (en) * | 2002-07-29 | 2007-01-24 | 株式会社東芝 | Manufacturing method of semiconductor device |
-
2003
- 2003-09-03 US US10/654,232 patent/US6989058B2/en not_active Expired - Lifetime
-
2004
- 2004-08-06 KR KR1020040061937A patent/KR100602534B1/en not_active IP Right Cessation
- 2004-08-30 TW TW093126077A patent/TWI304622B/en not_active IP Right Cessation
- 2004-08-31 CN CNB2004100683692A patent/CN100350561C/en not_active Expired - Fee Related
- 2004-09-02 JP JP2004256027A patent/JP4732725B2/en not_active Expired - Fee Related
-
2005
- 2005-11-07 US US11/268,096 patent/US20060057403A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5759898A (en) * | 1993-10-29 | 1998-06-02 | International Business Machines Corporation | Production of substrate for tensilely strained semiconductor |
US5930634A (en) * | 1997-04-21 | 1999-07-27 | Advanced Micro Devices, Inc. | Method of making an IGFET with a multilevel gate |
US20020185686A1 (en) * | 2001-06-12 | 2002-12-12 | International Business Machines Corporation | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
US20030139000A1 (en) * | 2002-01-23 | 2003-07-24 | International Business Machines Corporation | Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications |
US6841457B2 (en) * | 2002-07-16 | 2005-01-11 | International Business Machines Corporation | Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion |
US6861158B2 (en) * | 2003-05-30 | 2005-03-01 | International Business Machines Corporation | Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060214257A1 (en) * | 2005-03-25 | 2006-09-28 | Sumco Corporation | Production method of strained silicon-SOI substrate and strained silicon-SOI substrate produced by same |
US20090169843A1 (en) * | 2008-01-02 | 2009-07-02 | Tetsuya Mishima | Low-Defect-Density Crystalline Structure and Method for Making Same |
US7923098B2 (en) * | 2008-01-02 | 2011-04-12 | The Board Of Regents Of The University Of Oklahoma | Low-defect-density crystalline structure and method for making same |
US20160351397A1 (en) * | 2014-02-12 | 2016-12-01 | International Business Machines Corporation | Silicon germanium-on-insulator formation by thermal mixing |
US20160359023A1 (en) * | 2014-02-12 | 2016-12-08 | International Business Machines Corporation | Silicon germanium-on-insulator formation by thermal mixing |
US10249737B2 (en) * | 2014-02-12 | 2019-04-02 | International Business Machines Corporation | Silicon germanium-on-insulator formation by thermal mixing |
US10396182B2 (en) * | 2014-02-12 | 2019-08-27 | International Business Machines Corporation | Silicon germanium-on-insulator formation by thermal mixing |
US20190267475A1 (en) * | 2014-02-12 | 2019-08-29 | International Business Machines Corporation | Silicon germanium-on-insulator formation by thermal mixing |
Also Published As
Publication number | Publication date |
---|---|
TWI304622B (en) | 2008-12-21 |
JP4732725B2 (en) | 2011-07-27 |
KR100602534B1 (en) | 2006-07-19 |
JP2005079601A (en) | 2005-03-24 |
US6989058B2 (en) | 2006-01-24 |
CN1601701A (en) | 2005-03-30 |
TW200512841A (en) | 2005-04-01 |
US20050048778A1 (en) | 2005-03-03 |
CN100350561C (en) | 2007-11-21 |
KR20050025261A (en) | 2005-03-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20060057403A1 (en) | Use of thin SOI to inhibit relaxation of SiGe layers | |
US6841457B2 (en) | Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion | |
US7679141B2 (en) | High-quality SGOI by annealing near the alloy melting point | |
US6805962B2 (en) | Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications | |
US7816664B2 (en) | Defect reduction by oxidation of silicon | |
US7358166B2 (en) | Relaxed, low-defect SGOI for strained Si CMOS applications | |
US6855436B2 (en) | Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal | |
US7141115B2 (en) | Method of producing silicon-germanium-on-insulator material using unstrained Ge-containing source layers |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |