Búsqueda Imágenes Maps Play YouTube Noticias Gmail Drive Más »
Iniciar sesión
Usuarios de lectores de pantalla: deben hacer clic en este enlace para utilizar el modo de accesibilidad. Este modo tiene las mismas funciones esenciales pero funciona mejor con el lector.

Patentes

  1. Búsqueda avanzada de patentes
Número de publicaciónUS20060070885 A1
Tipo de publicaciónSolicitud
Número de solicitudUS 11/295,014
Fecha de publicación6 Abr 2006
Fecha de presentación6 Dic 2005
Fecha de prioridad17 Sep 1999
También publicado comoCN1238891C, CN1433572A, EP1218937A2, US6355153, US6905588, US7147766, US20020033342, US20030164302, WO2001020647A2, WO2001020647A3
Número de publicación11295014, 295014, US 2006/0070885 A1, US 2006/070885 A1, US 20060070885 A1, US 20060070885A1, US 2006070885 A1, US 2006070885A1, US-A1-20060070885, US-A1-2006070885, US2006/0070885A1, US2006/070885A1, US20060070885 A1, US20060070885A1, US2006070885 A1, US2006070885A1
InventoresCyprian Uzoh, Homayoun Talieh, Bulent Basol
Cesionario originalUzoh Cyprian E, Homayoun Talieh, Bulent Basol
Exportar citaBiBTeX, EndNote, RefMan
Enlaces externos: USPTO, Cesión de USPTO, Espacenet
Chip interconnect and packaging deposition methods and structures
US 20060070885 A1
Resumen
The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.
Imágenes(15)
Previous page
Next page
Reclamaciones(25)
1. A method of forming an annealed overburden conductive layer with a planar upper surface on a substrate having a barrier layer and a seed layer formed thereon, the method comprising:
depositing a conductive material at a depositing rate in cavities of the substrate while simultaneously applying a pad to remove material at a removal rate from field regions of the substrate, the pad being attached to an anode, the field regions being between the cavities, wherein the depositing rate and the removal rate are substantially the same;
increasing the depositing rate above the removal rate after the cavities are completely filled with the conductive material;
forming an overburden conductive layer on the substrate with the conductive material, the overburden conductive layer having a substantially planar upper surface; and
annealing the overburden conductive layer.
2. The method of claim 1, wherein a thickness of the overburden conductive layer ranges from 0.1 to 10000 Å.
3. The method of claim 1, further comprising the step of processing the annealed overburden conductive layer using chemical mechanical polishing.
4. The method of claim 1, wherein the annealing is conducted at a temperature in the range of 60-450° C.
5. The method of claim 2, wherein the annealing is conducted at a temperature in the range of 60-450° C.
6. The method of claim 3, wherein the annealing is conducted at a temperature in the range of 60-450° C.
7. The method of claim 1, wherein the annealing is performed in one of an inert atmosphere, a reducing atmosphere, and a vacuum.
8. A method of forming an optimized planar conductive layer on a substrate having a surface and cavities formed in the surface, the surface and the cavities being lined with a conductive film, the method comprising:
electrodepositing a conductive material onto the surface and into the cavities to form a planar conductive layer that fills the cavities and extends on the surface; and
annealing the planar conductive layer to thereby form the optimized planar conductive layer on the substrate.
9. The method of claim 8, further comprising processing the optimized planar conductive layer using chemical mechanical polishing.
10. The method of claim 8, wherein a thickness of the planar conductive layer is in the range of 0.1 to 10000 Å.
11. The method of claim 8, wherein the annealing is conducted at a temperature in the range of 60-450° C.
12. The method of claim 9, wherein the annealing is conducted at a temperature in the range of 60-450° C.
13. The method of claim 10, wherein the annealing is conducted at a temperature in the range of 60-450° C.
14. The method of claim 8, wherein the annealing is performed in one of an inert atmosphere, a reducing atmosphere, and a vacuum.
15. The method of claim 8, wherein the electrodepositing is conducted while polishing the surface.
16. The method of claim 15, wherein the polishing is performed using a pad material.
17. A method of forming a planar layer on a substrate having a surface and cavities formed in the surface, the surface and the cavities being lined with a conductive film, the method comprising:
depositing a planar conductive layer on the surface and the cavities, wherein the planar conductive layer fills the cavities and extends on the surface; and
annealing the planar conductive layer to thereby form an optimized planar conductive layer on the substrate.
18. The method of claim 17, wherein depositing comprises electrodepositing a conductor on the surface and the cavities while polishing the surface.
19. The method of claim 17, further comprising processing the optimized planar conductive layer using chemical mechanical polishing.
20. The method of claim 17, wherein a thickness of the planar conductive layer is in the range of 0.1 to 10000 Å.
21. The method of claim 17, wherein the annealing is conducted at a temperature in the range of 60-450° C.
22. The method of claim 19, wherein the annealing is conducted at a temperature in the range of 60-450° C.
23. The method of claim 20, wherein the annealing is conducted at a temperature in the range of 60-450° C.
24. The method of claim 21, wherein the annealing is performed in one of an inert atmosphere, a reducing atmosphere, and a vacuum.
25. The method of claim 18, wherein the polishing is performed using a pad material.
Descripción
    REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This application is a continuation application of, and claims priority to, co-pending U.S. patent application Ser. No. 10/407,892, filed Apr. 4, 2003, which is a continuation of U.S. patent application Ser. No. 09/905,335, filed Jul. 13, 2001, now U.S. Pat. No. 6,905,588, which is a divisional of U.S. patent application Ser. No. 09/398,258, filed Sep. 17, 1999, now U.S. Pat. No. 6,355,153. The disclosures of all of the foregoing patents and applications are hereby incorporated by reference in their entireties.
  • FIELD OF THE INVENTION
  • [0002]
    The present invention relates to a method for fabricating high performance chip interconnects and packages. More particularly, the present invention is directed to a method for insitu-selectively removing portions of a seed layer from a top surface of a substrate while preventing removal of the seed layer from the cavities formed therein. Moreover, the present invention discloses methods for depositing a conductive material in cavities of a substrate.
  • BACKGROUND OF THE INVENTION
  • [0003]
    Depositing a metal/conductive material in cavities (trenches, holes, and vias) of a substrate or workpiece has important and broad application in the semiconductor and non-semiconductor industries. Conductive materials are deposited in cavities of the substrate to interconnect layers and components contained therein. In recent times, there is great interest in fabricating chips and devices with very high aspect ratio and sub micron level features (e.g., below 0.25 um). As a result, copper is the preferred conductive material of choice as it provides better conductivity and reliability than, for example, aluminum or aluminum alloys.
  • [0004]
    FIGS. 1A-1C illustrate one conventional method for depositing a conductive material in the cavities of a substrate (e.g., workpiece). FIG. 1A illustrates a cross sectional view of a substrate having various layers disposed thereon. This figure illustrates a silicon dioxide layer (SiO2) 2 (dielectric layer) having deposited thereon a barrier or adhesive layer 4 and a seed layer 6.
  • [0005]
    The dielectric layer 2 is generally etched with cavities before the barrier layer 4 and the seed layer 6 are deposited thereon. The cavities in the dielectric layer 2 are generally etched using a reactive ion etching (RIE) method. The barrier layer 4 may be tantalum (Ta), titanium (Ti), tungsten (W), titanium-tungsten (TiW), titanium nitride (TiN), Nb, CuWP, CoWP, or other materials or combinations thereof that are commonly used in this field. The barrier layer 4 is generally deposited on the dielectric layer 2 using any of the various sputtering methods, chemical vapor deposition (CVD), electro-deposition or electrolyte/electroless plating method. Thereafter, the seed layer 6 is deposited over the barrier layer 4. The seed layer 6 may be deposited on the barrier layer 4 again using various sputtering methods, CVD, or electroless deposition or combinations thereof. The seed layer 6 thickness, depending on the substrate topography, may vary from 20 to 4,000 Å.
  • [0006]
    After depositing the seed layer 6, a conductive material 8 (e.g., copper) is generally used to fill the cavities of the dielectric layer 2. This is illustrated in FIG. 1B. The conductive material 8 may be formed on the seed layer 6 by CVD, sputtering, electroless plating, electrodeposition, or combinations thereof. The conductive material 8 and the seed layer 6 are generally the same material. The cavities are typically overfilled with the conductive material 8 as shown.
  • [0007]
    Once the conductive material 8 is formed in the cavities of the substrate, the substrate is typically transferred to another equipment for polishing/planarizing the top surface of the substrate as illustrated in FIG. 1C. Typically, the substrate is planarized using a conventional chemical mechanical polishing (CMP) device. The conductive material 8 overburden can be removed using a conventional CMP method. Portions of the seed layer 6 and the barrier layer 4 on the top surface of the substrate are also polished to electrically isolate the various structures. The remaining seed layer 6 in the cavities is embodied in the conductive material 8 as illustrated in FIG. 1C.
  • [0008]
    Referring back to FIGS. 1A-1B, the depth 9 c of the cavities in the dielectric layer 2 can range from 0.2 to 5 um for interconnects and up to 50 um or more for packages. When depositing the conductive material 8 over the substrate, it is desirable to overfill the cavities to, for example, 50 to 200% of the depth 9 c in order to minimize defects in the wiring structure. For example, for the structure of FIG. 1A, assume that the depth 9 a is about 0.5 um and the width 9 b is about 10.0 um. Thus, the larger cavity includes the width 9 b of 10.0 um and a total depth of about 1.0 um (measured from the bottom of the cavity to the top of the substrate). To completely fill the larger cavity, a minimum depth of at least 1.0 um of the conductive material 8 must be deposited therein. Further, an additional amount of the conductive material 8 is overfilled in the larger cavity to make certain that the cavity is completely filled and to minimize wiring defects. Thus, the additional amount (i.e., 50%) of the conductive material 8 over the larger cavity should be at a depth 9 e of at least 0.5 um. In this case, when the depth 9 e is about 0.5 um, the conductive material 8 formed over the field regions will be at a depth 9 d of about 1.5 um. In other words, an overburden of at least 1.5 um of the conductive material 8 will be deposited over most of the field regions of the substrate while a smaller overburden of at least 0.5 um will be deposited over the larger cavities. Thus, the overburden of 0.5 to 1.5 um of the conductive material 8 will be deposited over the various features of the substrate.
  • [0009]
    The disparity of the conductive material 8 overburden across the substrate results in longer polishing time and higher costs using the conventional CMP process. Thus, there is a need for a deposition process that minimizes the amount of the conductive material 8 overburden across the substrate, as well as to minimize the disparity of the overburden depths on the surface of the substrate.
  • [0010]
    FIGS. 2A-2F illustrate another conventional method for depositing a conductive material in the cavities of a substrate. FIG. 2A illustrates a dielectric (SiO2) layer 2 that is etched with cavities and having a barrier layer 4 and a seed layer 6 deposited thereon, similar to the structure of FIG. 1A. Again, the cavities in the dielectric layer 2 are typically etched using an RIE method.
  • [0011]
    FIG. 2B illustrates a photoresist material 12 coated on top of the seed layer 6. Using a positive photoresist process, a mask (not shown) is used such that ultraviolet light is applied only to the photoresist material 12 that is formed in the cavities of the substrate. The photoresist that is exposed to the ultraviolet light (photoresist in the cavities) is degraded as the ultraviolet light breaks down the molecular structure of the photoresist. The degraded photoresist is then removed from the cavities of the substrate using an appropriate solvent or RIE method, resulting in the structure as illustrated in FIG. 2C. Although a positive photoresist process is described herein, a negative photoresist process can also be used to form the structure of FIG. 2C.
  • [0012]
    For substrates having large cavities of, for example, width 9 b greater than 2 um, photoresist removal from the cavities may require additional steps. For example, the photoresist material 12 in the cavities may interact with the seed layer 6 such that using a solvent to remove the photoresist material 12 may be inadequate. In this case, after applying the solvent for photoresist dissolution, the substrate is exposed to oxygen plasmas in order to ash away/strip off the remaining photoresist material 12 from the seed layer 6 in the cavities of the substrate.
  • [0013]
    When exposing a copper seed layer to oxygen plasma, copper oxides, copper sulfides, or copper-oxide-sulfide compounds may be formed on the copper seed layer, particularly when the photoresist material contains sulfur-bearing elements. These compounds that are formed on the copper seed layer is generally resistive to a conductive material, and should be removed before any conductive material is deposited on the seed layer. Thus, a second stripping process may be required to remove the oxides, sulfides, or oxide-sulfides.
  • [0014]
    In many wiring structures having submicron features, the copper seed layer in the cavities may be deposited to a thickness between 15 to 1000 Ao. In other cases, particularly when feature size is below 0.5 um and the aspect ratio is greater than 1.5, the copper seed layer in the cavities may be very thin or even discontinuous. In this case, applying the photoresist material on the discontinuous seed layer in the cavities may result in portions of the seed layer being consumed by the photoresist material, thereby resulting in a substrate having a large number of defects. In FIG. 2D, a conductive material 8 (e.g., copper) is deposited in the cavities from a suitable electroplating or electroless bath, while the remaining photoresist 12 prevents the conductive material 8 from being formed on the top surface of the substrate. After depositing the conductive material 8 in the cavities, the entire photoresist is removed using appropriate solvent or RIE, resulting in the structure of FIG. 2E. Thereafter, portions of the seed layer 6 and the barrier layer 4 on the top surface of the substrate are etched or polished using conventional methods (e.g., CMP, RIE, or combinations thereof), resulting in the structure illustrated in FIG. 2F.
  • [0015]
    Using an alternative conventional method, the photoresist material 12 and the seed layer 6 on the top surface of the substrate as shown in FIG. 2B may be removed using a CMP equipment and an abrasive slurry. Using this method, some abrasive particulates will be trapped in the cavities, where the abrasives become mechanically attached to the sidewalls of the cavities. When the abrasives are attached to the sidewalls of the cavities, they are often very difficult to remove, thereby resulting in substrates have various defects when the conductive material is deposited in the cavities.
  • [0016]
    The conventional methods described above for fabricating chip interconnects and packages require multiple steps and/or equipments. The time and effort needed during this phase of the fabrication process can be improved and simplified. Accordingly, there is a need for methods that can deposit a conductive material in the cavities of a substrate in a more efficient and effective manner. The present invention overcomes these and other disadvantages of prior art methods.
  • SUMMARY OF THE INVENTION
  • [0017]
    It is an object of the present invention to provide a method that removes the seed layer from a top surface of a substrate while preventing or minimizing removal of the seed layer from the cavities of the substrate.
  • [0018]
    It is another object of the present invention to provide a method that deposits a conductive material in the cavities of a substrate after selectively removing the seed layer from the top surface of the substrate.
  • [0019]
    It is a further object of the present invention to provide a method that removes a seed layer from a top surface of a substrate using a pad type material while preventing removal of the seed layer from the cavities of the substrate.
  • [0020]
    It is yet another object of the present invention to provide a method that removes the seed layer from a top surface of a substrate while depositing a conductive material in the cavities of the substrate.
  • [0021]
    It is another object of the present invention to provide a method that reduces and minimizes the conductive material overburden across a substrate while depositing the conductive material in the cavities of the substrate.
  • [0022]
    It is yet another object of the present invention to provide a method that minimizes the disparity of the conductive material overburden across a substrate while depositing the conductive material in the cavities of the substrate.
  • [0023]
    It is a further object of the present invention to provide a method for forming a multi-layered structure having cavities with capped conductive materials.
  • [0024]
    It is yet a further object of the present invention to provide a method for depositing a conductive material in cavities of the substrate after forming an oxide layer on the top surface of the substrate.
  • [0025]
    The present invention discloses methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. One method according to the present invention includes selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. A pad type material that is attached to an anode is used to polish the seed layer from the top surface of the substrate. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses the structures that are formed using the methods described herein.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0026]
    These and other objects and advantages of the present invention will become apparent and more readily appreciated from the following detailed description of the presently preferred exemplary embodiments of the invention taken in conjunction with the accompanying drawings, of which:
  • [0027]
    FIGS. 1A-1C illustrate cross sectional views of one conventional method for depositing a conductive material in the cavities of a substrate;
  • [0028]
    FIGS. 2A-2F illustrate cross sectional views of another conventional method for depositing a conductive material in the cavities of a substrate;
  • [0029]
    FIGS. 3A-3D illustrate cross sectional views of methods for depositing a conductive material in the cavities of a substrate in accordance with the preferred embodiment of the present invention;
  • [0030]
    FIGS. 4A-4E illustrate cross sectional views of a method for forming a multi-layered structure having capped conductive materials in accordance with the preferred embodiment of the present invention;
  • [0031]
    FIGS. 5A-5F illustrate cross sectional views of another method for forming a multi-layered structure having capped conductive materials in accordance with the preferred embodiment of the present invention;
  • [0032]
    FIGS. 6A-6C illustrate cross sectional views of another method for depositing a conductive material in the cavities of a substrate in accordance with the preferred embodiment of the present invention;
  • [0033]
    FIGS. 7A-7C illustrate cross sectional views of a method for forming an insulating material in cavities of a substrate in accordance with the preferred embodiment of the present invention; and
  • [0034]
    FIGS. 8A-8F illustrate cross sectional views of yet another method for depositing a conductive material in the cavities of a substrate in accordance with the preferred embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0035]
    The preferred embodiments of the present invention will now be described with reference to FIGS. 3-8, wherein like structures and materials are designated by like reference numerals throughout the various figures. The inventors of the present invention disclose herein methods for depositing a conductive material, preferably copper, in cavities of a substrate. The present invention can be used with any substrate or workpiece such as a wafer, flat panel, magnetic film head, integrated circuit, device, chip, and packaging substrate including lead-tin solder alloys, or lead free solderable alloys. Further, specific processing parameters provided herein are intended to be explanatory rather than limiting.
  • [0036]
    FIGS. 3A-3D illustrate cross sectional views of methods for fabricating chip interconnects and packages in accordance with the present invention. In other words, FIGS. 3A-3D disclose methods for depositing a material, preferably a conductive material/solution such as copper, in the cavities of a substrate. In another embodiment, the conductive material can be deposited in the cavities while selectively removing the seed layer from the top surface of the substrate.
  • [0037]
    The methods shown in FIGS. 3A-3D include the step depositing a conductive material in the cavities of the substrate using an apparatus having a pad type material attached to an anode. Such apparatus is described in greater detail in the co-pending U.S. application Ser. No. 09/373,681, filed Aug. 13, 1999, entitled “Method and Apparatus for Depositing and Controlling the Texture of A Thin Film”, commonly owned by the assignee of the present invention, the contents of which are expressly incorporated herein by reference.
  • [0038]
    FIG. 3A illustrates a dielectric or SiO.sub.2 layer 2 having deposited thereon a barrier or adhesive layer 4 and a seed layer 6, similar to that described above with reference to FIGS. 1A and 2A. Again, the top surface of the SiO.sub.2 layer 2 is patterned/etched with cavities before the barrier layer 4 and seed layer 6 are deposited thereon. Although SiO.sub.2 is presented herein as the dielectric layer 2, it is understood that other materials that are commonly used as the dielectric layer may be used in accordance with the present invention.
  • [0039]
    In FIG. 3Bi, a porous pad type material 20 with or without fixed abrasive particles (not shown) is used to selectively polish the seed layer 6 from the top surface (field regions) of the substrate. The pad type material 20 that is attached to an anode 22 may be rotated in a circular motion, vibrated, moved side to side or vertically and is brought into contact with the seed layer 6. The pad type material 20 and the anode 22 further include outlet channels 21 for channeling a conductive material/solution to the substrate. In the preferred embodiment, the anode 22, the pad type material 20, and the substrate may rotate between 50 to 2000 rpm, but preferably between 100 to 1200 rpm, during the selective removal of the seed layer 6. The seed layer 6 on the top surface of the substrate is polished when such operation occurs for 2 to 60 seconds, but preferably for about 5 to 25 seconds.
  • [0040]
    When such contact is made, the pad type material 20 polishes the seed layer 6 residing on the top surface of the substrate without removing the seed layer 6 in the cavities. During this removal step, the pad type material 20 makes contact with the seed layer 6 at a pressure that may range from 0.05 to 5 psi. Further, the conductive solution containing for example, copper, may emanate from the outlet channels 21 of the pad type material 20 and may be applied to the substrate at 0.01 to 5 gallons per minute (gpm), but preferably between 0.05 to 3 gpm. When an electric potential is applied between the anode 22 and the conducting substrate, a small amount of conductive film 14 may be deposited within the cavities of the substrate, while the pad type material 20 is selectively removing the seed layer 6 and the conductive solution from the top surface of the substrate. The purpose of applying the electrical potential between the anode 22 and the conducting substrate and generating an electric current is to avoid the dissolution of the seed layer 6 in the cavities during the process of polishing the top surface of the substrate. During this step, a substrate holder (not shown) that is capable of rotating in a circular motion, and moving side to side or vertically, guides the substrate in proper position/movement.
  • [0041]
    In an alternative embodiment, the conductive (protective or sacrificial) film 14 may be redissolved in an electrolyte solution to momentarily protect the original seed layer 6, while removing the conductive film from the field regions and before a copper conductive material is deposited in the cavities of the substrate. After removing the seed layer 6 from the field regions, the electrodes may be de-energized for a short period of time (i.e., 2-10 seconds) for the electrolyte solution to dissolve the protective or sacrificial film 14. Also, the substrate may be rendered anodic momentarily to improve the seed layer removal process from the field regions.
  • [0042]
    During the selective removal process of the seed layer 6 from the top surface of the substrate, an electrical current density between 0.05 to 15 mA/cm.sup.2, but preferably between 0.1 to 10 mA/cm.sup.2, (depending on the nature of the bath chemistry) is applied to the substrate. This electric current density range prevents seed layer 6 dissolution in the cavities and may allow a small amount of the conductive film 14 to be deposited thereon, as described above. It is important to note that during this process, the seed layer 6 on the top surface of the substrate is removed while the seed layer 6 within the cavities remains. The seed layer 6 remaining in the cavities of the substrate allows for a more efficient and effective deposition of a conductive material because it has a lower resistance than the barrier layer 4 to the conductive material.
  • [0043]
    After removing the seed layer 6 from the top surface of the substrate, the deposition current density may be increased to fill the cavities with the conductive material 8, resulting in the structure as shown in FIG. 3Ci. The conductive material 8 can be deposited in the cavities of the substrate since the remaining seed layer 6 in the cavities provides less resistance than the barrier layer 4 on top of the substrate. As a result, the conductive material 8 is more efficiently deposited on the seed layer 6 in the cavities than on the barrier layer 4 on the top surface of the substrate. In other words, the conductive material 8 will tend to form in the cavities of the substrate rather than on the barrier layer 4 on the top surface of the substrate. The conductive film 14 and the remaining seed layer 6 in the cavities are embodied in the conductive material 8.
  • [0044]
    The conductive material 8 can be deposited in the cavities using the anode 22 and the pad type material 20 via outlet channels 21. After polishing the seed layer 6 from the top surface of the substrate, the pad type material 20 can be positioned such that it is spaced apart from the top surface of the substrate between 1 micron to 2 millimeters. Electric current density can be increased to the anode 22 and the substrate between 5 to 250 mA/cm.sup.2, but preferably between 7 to 150 mA/cm.sup.2, in order to deposit the conductive material 8 in the cavities. Increasing the current density allows the conductive material 8 to fill the cavities of the substrate in a timely manner. The conducting barrier layer 4 is used to conduct the deposition current. Alternatively, the conductive material 8 can be deposited in the cavities while the pad type material 20 is actually making contact with the top surface of the substrate.
  • [0045]
    In an alternate embodiment, after selectively removing the seed layer 4, instead of electrodeposition, as described above, the cavities may be filled by electroless plating or selective metal CVD. In this case, the substrate is transferred to an electroless plating cell, and the conductive material is deposited accordingly.
  • [0046]
    Referring back to FIG. 3Ci, after depositing the conductive material 8 in the cavities, the barrier layer 4 can be removed by conventional polishing or RIE. After selectively removing the barrier layer 4 and planarizing/polishing the top surface of the substrate, the structure as illustrated in FIG. 3D is formed.
  • [0047]
    In an alternative embodiment, instead of depositing the conductive material as shown in FIG. 3Ci, the deposition time for depositing the conductive material may be increased, resulting in the structure as illustrated in FIG. 3Ciia. FIG. 3Ciia illustrates a packaging structure having a conductive material 16 deposited in the cavities. In packaging applications, lead-tin solder alloy or other solderable alloys 16 may be selectively deposited into the cavities using electrodeposition, evaporation, or other known methods. After the deposition step, portions of the barrier layer 4 are removed by RIE, using the conductive material 16 as a mask, to form the structure in FIG. 3Ciib.
  • [0048]
    In yet another embodiment of the present invention, different layers of conductive materials can be deposited in the cavities of the substrate after forming the structure illustrated in FIG. 3A.
  • [0049]
    For example, FIGS. 3Biia-3Biid illustrate a method for depositing one or more conductive materials in the cavities of a substrate. In FIG. 3Biia, using the anode 22 and the pad type material 20 (see FIG. 3Bi), a first conductive material 24 is deposited over the substrate for a period of, for example, 15-60 seconds at a current density of 5-35 mA/cm.sup.2 using a highly leveling electroplating solution to partially fill in the cavities. Alternatively, the cavities can be partially filled using electroless or CVD methods.
  • [0050]
    The first conductive material 24 is generally filled to a level of 10 to 60% of the depth of the widest cavity on the substrate. The seed layer 6 is embodied in the first conductive material 24. After the first conductive material 24 is deposited over the substrate, the top surface of the substrate may be planarized/polished, resulting in the structure of FIG. 3Biib. The top surface of the substrate can be planarized using the pad type material 20.
  • [0051]
    Alternatively, the substrate can be transferred to a CMP cell for polishing the top surface of the substrate. A CMP pad having fixed abrasive particles and a polishing solution applied thereto is used to polish/rub against the substrate for a period of 3-60 seconds, but preferably between 5-30 seconds. It is important to note that the barrier layer 4 remains on the substrate and is not polished during this process.
  • [0052]
    After polishing the first conductive material 24 overburden, a second conductive material 26 is deposited in the cavities over the first conductive material 24, as illustrated in FIG. 3Biic. Second conductive material 26 deposition may be performed using the anode 22 and the pad type material 20 or alternatively, in another deposition cell using electroless or CVD methods. For example, the first conductive material 24 may be deposited on the substrate using electro-deposition, while the second conductive material 26 may be deposited by electroless or CVD methods. After depositing the second conductive material 26 on the first conductive material 24, the second conductive material 26 can be planarized/polished using CMP or RIE to form the structure as illustrated in FIG. 3Biid.
  • [0053]
    The process described above with reference to FIGS. 3Biia-3Biid illustrate one combination of steps that may be performed to filled the cavities with various conductive materials. In another embodiment, the following chronological steps may be performed: (1) depositing a first conductive material partially in the cavities and the field regions; (2) polishing the first conductive material from the field regions; (3) annealing the substrate; (4) selectively depositing a second conductive material in the cavities; and (5) polishing/planarizing the substrate. Alternatively, the conductive materials can be deposited using the following sequence of steps: (1) depositing a first conductive material partially in the cavities and the field regions; (2) annealing the substrate; (3) polishing the first conductive material from the field regions; (4) selectively depositing a second conductive material in the cavities; and (5) polishing/planarizing the substrate. Other combination of the above steps may be implemented in the present invention.
  • [0054]
    In more detail, the first and second conductive materials 24, 26, may be the same or different material. For example, the first conductive material 24 may be Cu and the second conductive material 26 may be Cu—Sn, Cu—In, or other suitable copper alloys. Preferably, the second conductive material 26 should be a material that will enhance corrosion resistance and electromigration, while providing excellent adhesion to the first conductive material 24 and to other subsequently deposited materials that may be formed thereon. Further, the second conductive material 26 may have an electrical resistivity that is very similar to the first conductive material 24, preferably within 90-200% of that of the first conductive material 24.
  • [0055]
    When the first and second conductive materials 24, 26 are the same material, a distinct boundary between them may not exist. On the other hand, when the first and second conductive materials 24, 26 are different, a distinct boundary between them may exist before any subsequent thermal process is performed. The distinct boundary layer can be used so that intermixing between the first and second conductive materials 24, 26 is discouraged. For example, a thin adhesive or barrier layer (e.g., alpha Tantalum, chrome layer, CoP, WCOP) may be deposited in between the first and second conductive materials 24, 26 to prevent intermixing between the two materials when such intermixing is undesired. In other embodiments, more than two conductive materials can be formed in the cavities of the substrate using the process disclosed herein.
  • [0056]
    Referring back to the various methods described in FIGS. 3A-3D, the inventors of the present invention now disclose a novel conductive solution (i.e., conductive material 8, 16, 24, 26) that is suitable for electro-depositing a copper material in the cavities while polishing the copper material from the top surface of the substrate. Using this solution, a conductive material such as copper can be deposited in the cavities of the substrate, while the same material is polished from the field regions of the substrate. The conductive solution, which may be acidic or alkaline, includes at least the following elements/compounds/sources: (1) source for metal ions; (2) source of current carriers; (3) source for chloride ions; (4) source for highly leveling bath additives; (5) metal oxidizing agents; (6) passivating agents; and (7) surfactants.
  • [0057]
    First, the conductive solution of the present invention contains a concentration of metal ions (i.e., Cu) from, for example, a sulfate, nitrate, or a pyrophosphate source. The metal ion concentration should range from ½ to 40 g/L, but preferably between 2 to 25 g/L.
  • [0058]
    Second, the conductive solution includes a source of current carriers besides the copper ions, which may include organic/inorganic acids and compounds such as sulfuric acid, phosphoric acid, acetic acid, butylacetic acid, propronic acid, butyric acid, ammonium sulfate, potassium hydroxide, tetra methyl, ammonium hydroxide, and the like. The acid concentration should range from 0.05 to 18% by volume, but most preferably, between 0.2 to 15% by volume.
  • [0059]
    For acidic baths, a third source of chloride ions, either organic or inorganic, is also included in the conductive solution of the present invention. The chloride ion concentration should range from 2-180 ppm, but preferably 10-170 ppm. For alkaline baths, ammonium may be used, about 0.5 to 3 ml/L.
  • [0060]
    The fourth element in the conductive material is a source of a highly leveling bath additives and various combinations thereof. These additives include commercial additives such as Cubath MD, Cubath ML and Cubath SC replenisher from Enthone-OMI, and/or Ultra fill additive A2001 and S2001 from Shipley. Other additives such as copper wafer additives 200B and 2000C from Technic, Inc., various mercapto compounds such as 2-mercapto ethanesulfonic acid or salt, 2-mercapto benzothiazole, 2-0mercapto-5-benzimidazole sulfonic acid or salt, 2-mercapto benzimidazole, mercapto benzotriazole, tartaric acid or salt may also be used. The additive concentration should range from 0.01 to 4% by volume, but preferably between 0.05 to 3% by volume. For alkaline baths, Kupralume 501 and 502 additives manufactured from Alchem Corporation may be used.
  • [0061]
    The fifth element/compound of the conductive material includes a metal oxidizing agent such as organic and inorganic oxidizing agents. These agents may include inorganic and organic peroxides, persulfates, nitrates, nitrites, thiosulfates, salts of nitrobenzene sulfonates, and the like. What is important from this example is that any component of the oxidizing agent should not adversely affect the deposited material. Organic peroxides such as butopronoxyl, tert-butyl hydroperoxide, tert-butyl peroxide, butyl nitrite, etc. may also be used. The peroxides (i.e. hydrogen peroxide) may be stabilized using small amounts of phenol sulformates or primary diols (i.e., 1,4 butanediol). The concentration of the oxidizing agent may range from 0.1 to 60 g/L, but preferably between 0.2 to 40 g/L. Other suitable oxidants may be used for the redox reactions.
  • [0062]
    The sixth element/compound of the conductive material is an agent that passivates or enhances the passivation of copper or other metal materials. These agents may include benzotriazole, or combinations of benzotriazole with organic triazoles, such as benzotriazole-1-acetonitrid-e, benzotriazole-5-carboxylic acid, O-benzotriazole-1-yl-N,N′,N′-bis (tetramethylene) uronium hexafluoro phosphate and combinations thereof. The concentration of the passivating agents should range from 0.0005M to 0.1M, but preferably between 0.001 M to 0.2 M. Also, the highly leveling additives and the corresponding inhibitors describe above may be used as passivating agents. What is important from this example is that the concentration of the passivating agent is adequate for the CMP process and is also below the threshold level that allows for conductive material deposition. Above this threshold level, hydrogen can be deposited at the cathode instead of the conductive material.
  • [0063]
    Besides the passivating agent, surfactants such as Duponol (Dupont Chem.) may be used, where the concentration of surfactant may range from 20 to 800 ppm, but most preferably between 40 to 600 ppm. In addition, pentose sugar such as xylose, arabinose, etc., may be added for oxygen scavenging in the deposited conductive material at a concentration of 0.05 to 10 grams per liter. Water can also be used to balance the conductive solution described herein.
  • [0064]
    Such a conductive solution disclosed above allows for the simultaneous metal deposition within the cavities of a substrate while a pad type material removes all or most of the metal deposited over the field regions of the substrate. Such a formulation used in a plate and polish apparatus eliminates or minimizes the large amount of metal overburden as described in FIG. 1B.
  • [0065]
    In other applications, a uniform overburden of the conductive material may be desirable by controlling the deposition and polishing rates on the structure shown in FIG. 3A. For example, using a pad type material (i.e., pad 20 of FIG. 3Bi) and a plating and polishing electrolyte formulation, the conductive material 8 deposition and removal rates may be 10 mA/cm.sup.2. Thus, the conductive material 8 begins to fill the cavities of the substrate while the same material is being polished from the field regions. When the cavities are filled with the conductive material 8, the deposition rate is increased slightly higher than the polishing rate such that a uniform overburden of the conductive material can be deposited on the substrate. The deposition and polishing rates can be adjusted by changing the current density, rate of rotation, period of rotation, etc. For example, for depositing the uniform conductive material overburden, the current density can range from 5 to 30 mA/cm.sup.2 for a period of 10 to 90 seconds.
  • [0066]
    By depositing at a current density slightly higher than 10 mA/cm.sup.2 (i.e., 10.5 mA/cm), a thin continuous uniform overburden is formed over the entire top surface of the substrate. The depth of the overburden may range from 0.1-10000 A.sup.0, or even higher, depending on the desired structure. Thus, by varying the deposition rate and/or the polish rate, any uniform conductive material 8 overburden may be obtained as shown in FIG. 3Biii.
  • [0067]
    As can be appreciated, the methods disclosed herein reduce the number of steps and simplifies the process of fabricating chip interconnects and packages. Portions of the seed layer are selectively removed from the top surface of the substrate while other portions of the seed layer remain in the cavities. One or more conductive materials can then be deposited in the cavities where the seed layer remains.
  • [0068]
    As described above, the preferred method according to the present invention is to selectively remove the seed layer and deposit the conductive material in the cavities in one chamber/cell. However, another method is to use a CMP apparatus and cell to first remove the seed layer and then to transfer the substrate to another different cell for deposition.
  • [0069]
    In another embodiment, the seed layer can be selectively removed from the top surface of the substrate using electroless plating. The electroless solution can emanate within the channels in the pad type material that is close proximity to an anode and the top surface of the substrate. The cavities are selectively filled with the conductive material while the seed layer is being removed from the top surface of the substrate by the pad type material having abrasive particles.
  • [0070]
    One of the overriding condition in these processes is that the removal rate of the seed layer is about 2 to 100 times faster than the deposition rate of the conductive material in the cavities. Thus, in the case of electroless and electrodeposition, after the seed layer removal from the top surface of the substrate, the substrate may be moved away from the pad type material, where the deposition process is performed, or alternatively, deposition is performed while maintaining physical contact between the top surface of the substrate and the pad type material.
  • [0071]
    In other embodiments, the removal rate of the seed layer from the top surface of the substrate may be the same as the deposition rate of the conductive material in the cavities of the substrate. In this case, the seed layer on the top surface is removed while simultaneously depositing the conductive material in the cavities.
  • [0072]
    In yet another embodiment, an initial alloy layer may be deposited in the cavities of the substrate while selectively removing the seed layer from the top surface of the substrate. For example, during the initial stage of selectively removing the seed layer from the top surface of the substrate (FIG. 3B), an electrolyte solution such as an alloy material may be deposited on the seed layer in the cavities to form an initial thin alloy layer. In the case where the conductive material is copper, the thin alloy film containing indium, cadmium, tin, and the like can be used.
  • [0073]
    After selectively removing the seed layer and depositing the thin alloy layer (reference number 14 of FIG. 3B) in the cavities, the substrate and/or the anode are de-energized so that the substrate may be spray rinsed. After rinsing the substrate, the cavities in the substrate may be selectively filled with copper using a suitable source such as an electroless or electroplating bath.
  • [0074]
    For optimum interconnect performance, it is highly desirable to stabilize the structure by annealing the deposited copper. Annealing may be allowed to occur at room temperature for over a period of three days or longer, or may be annealed in a suitable oven or tube furnace for faster annealing of 15 seconds to 2 hours. The annealing temperature may range from 60.degree. to 450.degree. C. in an inert ambient such as nitrogen or in a reducing ambient, or even in a vacuum chamber.
  • [0075]
    The thin alloy layer in the cavities is used to enhance the mechanical, corrosion, and electro-migration properties of the chip interconnect. The alloy layer is intermixed with the deposited conductive material in the cavities, where upon annealing the substrate, the alloy material enhances the structural properties of the chip interconnect.
  • [0076]
    FIGS. 4A-4E illustrate cross sectional views of a method for forming a multi-layered structure having capped conductive materials in accordance with the preferred embodiment of the present invention. The filled cavities as shown in FIG. 3Ci may be selectively capped using a suitable barrier material. For example, a capping layer 32 such as CoP, NiP, WCoP, or combinations thereof can be formed on the copper material 8 using known methods, resulting in the structure as illustrated in FIG. 4A. The capping layer 32 prevents conductive material oxidation, acts as a barrier layer, and enhances adhesion.
  • [0077]
    After forming the capping layer 32 on top of the conductive material 8, the barrier layer 4 formed on the top surface of the substrate may be selectively removed by RIE, as illustrated in FIG. 4B. After removing the barrier layer 4 from the top surface of the substrate, portions of the first dielectric material 2 may also be removed using RIE, resulting in the structure of FIG. 4C. For example, in the case where the first dielectric material is SiO.sub.2, the depth of the cavities may range from 0.3 to 2.5 um. The amount of the first dielectric material 2 removed may range from 10 to 120% of the cavity depth, but most preferably, between 30 to 95%. Enough dielectric material 2 remains in order to support the nearly free-standing cavities.
  • [0078]
    Next, a second dielectric material 30 may be deposited by CVD or spin-on process over the substrate of FIG. 4C to form the structure of FIG. 4D. The second dielectric material 30 is then planarized/etched to expose the capped layer 32, as shown in FIG. 4Ei. The second dielectric material 30 may be a low or high dielectric material.
  • [0079]
    In another embodiment of the present invention, the second dielectric material 30 as shown in FIG. 4D may be patterned by lithographic methods. The dielectric material 30 can then be etched using RIE to form additional cavities. After barrier and seed layer depositions on the second dielectric material 30, the seed layer is again selectively removed from the top surface of the second dielectric material 30 and a second conductive material 28 is deposited in the cavities of the second dielectric layer 30, resulting in a structure of FIG. 4Eii.
  • [0080]
    FIGS. 5A-5F illustrate cross sectional views of another method for forming a multi-layered structure in accordance with the preferred embodiment of the present invention. A through-mask deposition method either by CVD, electroless or electrodeposition may be used to deposit a second conductive material on the first conductive material. FIG. 5A illustrates the structure of FIG. 3D.
  • [0081]
    FIG. 5B illustrates a photoresist material 50 that has been coated on the substrate, where portions of the photoresist 50 have been removed such that a second conductive material may be deposited on the first conductive material 8. The second conductive material 58 is deposited in those portions where the photoresist 50 have been removed as shown in FIG. 5C. The first and second conductive layers may be the same or different materials. The photoresist 50 and portions of the barrier layer 4 are removed using conventional methods, resulting in the structure of FIG. 5D. The second conductive material 58 remains free standing.
  • [0082]
    The second conductive material 58 is then selectively capped by electroless deposition methods before removing portions of the barrier layer 4 and the first dielectric layer 2. In this case, portions of the barrier layer 4 may be removed together with portions of the dielectric layer 2 as described earlier herein to form the structure as illustrated in FIG. 5E. The capped layer 60 coats the new structure of FIG. 5E with either a low or high dielectric material. Next, a second dielectric layer 70 may be formed and planarized to form the structure of FIG. 5F.
  • [0083]
    FIGS. 6A-6C illustrate another method for depositing a conductive material in the cavities of the substrate without depositing the same material on the top surface of the substrate. This is accomplished by insulating only the top surface of the substrate. For example, FIG. 6A illustrates a structure showing a SiO.sub.2 layer 2 having deposited thereon a barrier layer 4. The barrier layer 4 can be one of the well known materials such as Ta, W, or TaN as described earlier herein. These materials are known to form surface oxide layers that are uniform, which may be formed electrolitically by anodization.
  • [0084]
    Using the anodization technique, the material of interest is dipped into an electrolyte solution and a positive voltage is applied thereto with respect to a cathode, which is also in contact with the electrolyte solution. A surface oxide forms on the anodized material and the thickness of the surface oxide is dependent on the nature of the electrolyte solution and the applied voltage. Generally, higher anodization voltages lead to thicker surface oxide films. In FIG. 6B, after anodization, a thin oxide layer 66 is formed on the barrier layer 4 only on the top surface of the substrate. Once the thin oxide layer 66 is formed, a conductive material such as copper can be used to fill the cavities by electroplating without the conductive material forming on the oxide layer 66, thereby forming the structure as illustrated in FIG. 6C. The structure of FIG. 6C is formed because the oxide layer 66 has a very high resistance to the conductive material, and thus the conductive material is formed in the cavities of the substrate.
  • [0085]
    Referring back to FIG. 6B, the anodization should be performed such that there remains some appreciable barrier layer 4 directly underneath the oxide layer 66. This is important because if all of the top surface barrier layer 4 is oxidized, electroplating the conductive material 68 into the cavities can not be carried out because no current would pass through the completely oxidized surface layers.
  • [0086]
    In another embodiment, a thin seed layer (not shown) may be formed over the barrier layer 4 in the structure of FIG. 6A. In this case, the seed layer on the top surface of the substrate would be dissolved during anodization and the barrier layer 4 would oxidize, thereby forming an the oxide layer 66. Portions of the seed layer remain in the cavities over the barrier layer.
  • [0087]
    To fabricate the structure of FIG. 6C, the cavities as illustrated in FIG. 6A need to be electrically isolated during anodization. Otherwise, anodization would affect the entire substrate, including the cavities and the top surface. The isolation can be achieved through various means. For example, if the cavities are narrow and deep, the substrate can be lowered into the anodization electrolyte solution with the cavities facing downward. Gas/air trapped in the cavities can keep the electrolyte solution from reaching into the cavities and thus can act as an insulator.
  • [0088]
    Alternately, an insulating material can be filled into the cavities before exposing the top surface of the substrate to the anodization electrolyte solution. For example, FIG. 7A illustrates a liquid chamber 74 having an electrolyte solution 70 contained therein. In FIG. 7B, an insulating solution 72, which is lighter in weight than the anodization electrolyte solution 70 and which does not mix with the electrolyte solution 70 is placed in the chamber 74 on top of the anodization electrolyte solution 70. In FIG. 7C, the chamber 74 is raised such that the top surface of the substrate (the side having the open end of the cavities) first makes contact with the insulating solution 72. Using this technique, the cavities are first filled with the insulating solution 72 as the liquid chamber 74 is raised. As the chamber 74 is further raised, the remaining top surface of the substrate (portions outside the cavities) is anodized as the top surface of the substrate makes contact with the electrolyte solution 70. Therefore, when anodization is performed on the top surface of the substrate, portions of the barrier layer 4 outside the cavities would form an oxide layer. The insulating solution 72 in the cavities prevents the oxide layer from forming in the cavities.
  • [0089]
    It should be noted that the approach described in FIGS. 7A-7C can also be employed to remove the seed layer from the top surface of a substrate. In this case, there would be a barrier layer and a seed layer on the original substrate. The anodization electrolyte solution 70 would be replaced with an etching electrolyte solution that would touch the seed layer on the top surface of the substrate and chemically etch the seed layer. However, the seed layer within the cavities would be protected by the insulating solution 72. Once the seed layer at the top surface is etched away, the substrate can be removed from the chamber. The insulating solution 72 can be removed from the cavities such that a conductive material can then be deposited in the cavities of the substrate.
  • [0090]
    FIGS. 8A-8F illustrate yet another embodiment of the present invention for depositing a conductive material in the cavities of a substrate. FIG. 8A illustrates a dielectric layer 2 deposited thereon a barrier layer 4 and a seed layer 6, similar to the structure as shown in FIG. 3A.
  • [0091]
    In FIG. 8B, a sacrificial or protective layer 84 of, for example chrome (Cr), is deposited on the seed layer 6 at a thickness of 25-1000 A.sup.0. Thereafter, a hard glossy layer 86 made of SiO.sub.2, cross linked epoxies, UV cured, etc. is coated over the Cr layer 84, resulting in the structure of FIG. 8C.
  • [0092]
    In FIG. 8D, the top surface of the substrate is then planarized using for example, an abrasive pad or solution, thereby removing the hard glossy layer 86, the Cr layer 84, and the seed layer 6 residing over the field regions. The hard glossy layer 86 in the cavities of the substrate is then removed using for example, a dilute HF, resulting in the structure of FIG. 8E. The remaining Cr layer within the cavities may be stripped away using an appropriate solvent as known in the art. Thereafter, a conductive material 88 may be deposited in the cavities of the substrate via electroplating, electroless, and the like.
  • [0093]
    Along with using copper and its alloys as the conductive material, other conductive materials such as aluminum, iron, nickel, chromium, indium, lead, tin, lead-tin alloys, nonleaded solderable alloys, silver, zinc, cadmium, titanium, tungsten molybdenum, ruthenium, gold, paladium, cobalt, rhondium, platinum, their respective alloys and various combinations of above material with oxygen, nitrogen, hydrogen and phosphorous may be used in the present invention.
  • [0094]
    In the previous descriptions, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., to provide a thorough understanding of the present invention. However, as one having ordinary skill in the art would recognize, the present invention can be practiced without resorting to the details specifically set forth.
  • [0095]
    Although various preferred embodiments have been described in detail above, those skilled in the art will readily appreciate that many modifications of the exemplary embodiment are possible without materially departing from the novel teachings and advantages of this invention. Background of the Invention
Citas de patentes
Patente citada Fecha de presentación Fecha de publicación Solicitante Título
US2540602 *3 Jul 19466 Feb 1951Lockheed Aircraft CorpMethod and apparatus for the surface treatment of metals
US2708181 *17 May 195110 May 1955Indiana Steel & Wire Company IElectroplating process
US3328273 *15 Ago 196627 Jun 1967Udylite CorpElectro-deposition of copper from acidic baths
US3448023 *20 Ene 19663 Jun 1969Hammond Machinery Builders IncBelt type electro-chemical (or electrolytic) grinding machine
US3595089 *23 Sep 196927 Jul 1971Jirik Frank JRotary grain sampler device
US3637468 *25 Abr 196925 Ene 1972Dalic SaElectrodes for electrolytic processes
US3959089 *30 Dic 197425 May 1976Watts John DawsonSurface finishing and plating method
US4024029 *16 Oct 197517 May 1977National Research Development CorporationElectrodeposition
US4080513 *3 Nov 197521 Mar 1978Metropolitan Circuits Incorporated Of CaliforniaMolded circuit board substrate
US4315985 *28 Dic 197716 Feb 1982International Business Machines CorporationFine-line circuit fabrication and photoresist application therefor
US4339319 *10 Dic 198013 Jul 1982Seiichiro AigoApparatus for plating semiconductor wafers
US4391684 *2 Jul 19815 Jul 1983Rolls-Royce LimitedMethod of manufacture of an article having internal passages
US4430173 *16 Jul 19827 Feb 1984Rhone-Poulenc Specialties ChimiquesAdditive composition, bath and process for acid copper electroplating
US4431501 *22 Jul 198114 Feb 1984Outokumpu OyApparatus for electrolytic polishing
US5024735 *15 Feb 198918 Jun 1991Kadija Igor VMethod and apparatus for manufacturing interconnects with fine lines and spacing
US5084071 *23 Feb 199028 Ene 1992International Business Machines CorporationMethod of chemical-mechanical polishing an electronic component substrate and polishing slurry therefor
US5096550 *15 Oct 199017 Mar 1992The United States Of America As Represented By The United States Department Of EnergyMethod and apparatus for spatially uniform electropolishing and electrolytic etching
US5292399 *8 Ene 19928 Mar 1994Applied Materials, Inc.Plasma etching apparatus with conductive means for inhibiting arcing
US5316974 *30 Abr 199031 May 1994Texas Instruments IncorporatedIntegrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
US5436504 *19 May 199325 Jul 1995The Boeing CompanyInterconnect structures having tantalum/tantalum oxide layers
US5486234 *19 Ene 199523 Ene 1996The United States Of America As Represented By The United States Department Of EnergyRemoval of field and embedded metal by spin spray etching
US5486282 *30 Nov 199423 Ene 1996Ibm CorporationElectroetching process for seed layer removal in electrochemical fabrication of wafers
US5512131 *4 Oct 199330 Abr 1996President And Fellows Of Harvard CollegeFormation of microstamped patterns on surfaces and derivative articles
US5516412 *16 May 199514 May 1996International Business Machines CorporationVertical paddle plating cell
US5605637 *15 Dic 199425 Feb 1997Applied Materials Inc.Adjustable dc bias control in a plasma reactor
US5714707 *13 May 19963 Feb 1998Talon Manufacturing Company, Inc.Process and apparatus for demilitarization of small caliber primed cartridge cases
US5723387 *22 Jul 19963 Mar 1998Industrial Technology Research InstituteMethod and apparatus for forming very small scale Cu interconnect metallurgy on semiconductor substrates
US5755859 *24 Ago 199526 May 1998International Business Machines CorporationCobalt-tin alloys and their applications for devices, chip interconnections and packaging
US5762544 *24 Abr 19969 Jun 1998Applied Materials, Inc.Carrier head design for a chemical mechanical polishing apparatus
US5770095 *11 Jul 199523 Jun 1998Kabushiki Kaisha ToshibaPolishing agent and polishing method using the same
US5772833 *17 Nov 199430 Jun 1998Tokyo Electron LimitedPlasma etching apparatus
US5773364 *21 Oct 199630 Jun 1998Motorola, Inc.Method for using ammonium salt slurries for chemical mechanical polishing (CMP)
US5858813 *10 May 199612 Ene 1999Cabot CorporationChemical mechanical polishing slurry for metal layers and films
US5862605 *22 May 199726 Ene 1999Ebara CorporationVaporizer apparatus
US5863412 *17 Oct 199626 Ene 1999Canon Kabushiki KaishaEtching method and process for producing a semiconductor element using said etching method
US5884990 *14 Oct 199723 Mar 1999International Business Machines CorporationIntegrated circuit inductor
US5897375 *20 Oct 199727 Abr 1999Motorola, Inc.Chemical mechanical polishing (CMP) slurry for copper and method of use in integrated circuit manufacture
US5911619 *26 Mar 199715 Jun 1999International Business Machines CorporationApparatus for electrochemical mechanical planarization
US5922091 *16 May 199713 Jul 1999National Science Council Of Republic Of ChinaChemical mechanical polishing slurry for metallic thin film
US6027631 *13 Nov 199722 Feb 2000Novellus Systems, Inc.Electroplating system with shields for varying thickness profile of deposited layer
US6063506 *8 Jun 199816 May 2000International Business Machines CorporationCopper alloys for chip and package interconnections
US6066030 *4 Mar 199923 May 2000International Business Machines CorporationElectroetch and chemical mechanical polishing equipment
US6071388 *29 May 19986 Jun 2000International Business Machines CorporationElectroplating workpiece fixture having liquid gap spacer
US6074544 *22 Jul 199813 Jun 2000Novellus Systems, Inc.Method of electroplating semiconductor wafer using variable currents and mass transfer to obtain uniform plated layer
US6074546 *21 Ago 199713 Jun 2000Rodel Holdings, Inc.Method for photoelectrochemical polishing of silicon wafers
US6176992 *1 Dic 199823 Ene 2001Nutool, Inc.Method and apparatus for electro-chemical mechanical deposition
US6187152 *17 Jul 199813 Feb 2001Cutek Research, Inc.Multiple station processing chamber and method for depositing and/or removing material on a substrate
US6210554 *21 Dic 19993 Abr 2001Mitsubishi Denki Kabushiki KaishaMethod of plating semiconductor wafer and plated semiconductor wafer
US6217734 *23 Feb 199917 Abr 2001International Business Machines CorporationElectroplating electrical contacts
US6224737 *19 Ago 19991 May 2001Taiwan Semiconductor Manufacturing CompanyMethod for improvement of gap filling capability of electrochemical deposition of copper
US6228231 *27 Sep 19998 May 2001International Business Machines CorporationElectroplating workpiece fixture having liquid gap spacer
US6245676 *22 Feb 199912 Jun 2001Nec CorporationMethod of electroplating copper interconnects
US6251235 *30 Mar 199926 Jun 2001Nutool, Inc.Apparatus for forming an electrical contact with a semiconductor substrate
US6251236 *30 Nov 199826 Jun 2001Applied Materials, Inc.Cathode contact ring for electrochemical deposition
US6334937 *31 Ago 19991 Ene 2002Semitool, Inc.Apparatus for high deposition rate solder electroplating on a microelectronic workpiece
US6346479 *14 Jun 200012 Feb 2002Advanced Micro Devices, Inc.Method of manufacturing a semiconductor device having copper interconnects
US6353623 *4 Ene 19995 Mar 2002Uniphase Telecommunications Products, Inc.Temperature-corrected wavelength monitoring and control apparatus
US6354916 *6 Abr 200012 Mar 2002Nu Tool Inc.Modified plating solution for plating and planarization and process utilizing same
US6355153 *17 Sep 199912 Mar 2002Nutool, Inc.Chip interconnect and packaging deposition methods and structures
US6368484 *9 May 20009 Abr 2002International Business Machines CorporationSelective plating process
US6375823 *9 Feb 200023 Abr 2002Kabushiki Kaisha ToshibaPlating method and plating apparatus
US6395163 *13 Oct 199828 May 2002Atotech Deutschland GmbhProcess for the electrolytic processing especially of flat items and arrangement for implementing the process
US6402925 *14 Dic 200011 Jun 2002Nutool, Inc.Method and apparatus for electrochemical mechanical deposition
US6506103 *21 Jul 200014 Ene 2003RikenELID centerless grinding apparatus
US6521285 *15 Jun 200018 Feb 2003International Business Machines CorporationMethod for printing a catalyst on substrates for electroless deposition
US6534116 *18 Dic 200018 Mar 2003Nutool, Inc.Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence
US6537133 *28 Sep 200025 Mar 2003Applied Materials, Inc.Method for in-situ endpoint detection for chemical mechanical polishing operations
US6582767 *1 Nov 200024 Jun 2003Shin-Etsu Chemical Co., Ltd.Metal pattern forming method
US6676822 *29 Jun 200013 Ene 2004Nutool, Inc.Method for electro chemical mechanical deposition
US6709565 *28 Sep 200123 Mar 2004Novellus Systems, Inc.Method and apparatus for uniform electropolishing of damascene ic structures by selective agitation
US6756307 *29 Jul 200229 Jun 2004Novellus Systems, Inc.Apparatus for electrically planarizing semiconductor wafers
US6848970 *16 Sep 20021 Feb 2005Applied Materials, Inc.Process control in electrochemically assisted planarization
US6858121 *31 Jul 200122 Feb 2005Nutool, Inc.Method and apparatus for filling low aspect ratio cavities with conductive material at high rate
US6867136 *22 Jul 200215 Mar 2005Nutool, Inc.Method for electrochemically processing a workpiece
US6902659 *9 Sep 20027 Jun 2005Asm Nutool, Inc.Method and apparatus for electro-chemical mechanical deposition
US6905588 *13 Jul 200114 Jun 2005Asm Nutool, Inc.Packaging deposition methods
US7059948 *20 Dic 200113 Jun 2006Applied MaterialsArticles for polishing semiconductor substrates
US7182677 *14 Ene 200527 Feb 2007Applied Materials, Inc.Chemical mechanical polishing pad for controlling polishing slurry distribution
US7189647 *24 Oct 200313 Mar 2007Novellus Systems, Inc.Sequential station tool for wet processing of semiconductor wafers
US7211174 *28 Oct 20021 May 2007Novellus Systems, Inc.Method and system to provide electrical contacts for electrotreating processes
US7211186 *28 Oct 20021 May 2007Novellus Systems, Inc.Method and system to provide electrical contacts for electrotreating processes
US7220166 *29 Ago 200222 May 2007Micron Technology, Inc.Methods and apparatus for electromechanically and/or electrochemically-mechanically removing conductive material from a microelectronic substrate
US7329335 *10 Jun 200312 Feb 2008Novellus Systems, Inc.Device providing electrical contact to the surface of a semiconductor workpiece during processing
US7341649 *12 Nov 200211 Mar 2008Novellus Systems, Inc.Apparatus for electroprocessing a workpiece surface
US7491308 *5 May 200517 Feb 2009Novellus Systems, Inc.Method of making rolling electrical contact to wafer front surface
US7517444 *26 Jul 200514 Abr 2009Novellus Systems, Inc.Plating method and apparatus for controlling deposition on predetermined portions of a workpiece
US7531079 *23 Feb 200512 May 2009Novellus Systems, Inc.Method and apparatus for uniform electropolishing of damascene IC structures by selective agitation
US7550070 *3 Feb 200623 Jun 2009Novellus Systems, Inc.Electrode and pad assembly for processing conductive layers
US7691250 *28 Abr 20066 Abr 2010E.I. Du Pont De Nemours And CompanyMembrane-mediated electropolishing with topographically patterned membranes
US20030070930 *22 Nov 200217 Abr 2003Homayoun TaliehDevice providing electrical contact to the surface of a semiconductor workpiece during metal plating and method of providing such contact
US20030116440 *21 Dic 200126 Jun 2003Texas Instruments IncorporatedElectroplater and method
US20050069645 *29 Abr 200431 Mar 2005Johns Hopkins UniversityMethod of electrolytically depositing materials in a pattern directed by surfactant distribution
US20050126919 *4 Nov 200416 Jun 2005Makoto KubotaPlating method, plating apparatus and a method of forming fine circuit wiring
US20060006060 *13 Sep 200512 Ene 2006Basol Bulent MMethod and apparatus for processing a substrate with minimal edge exclusion
US20060118425 *30 Ene 20068 Jun 2006Basol Bulent MProcess to minimize and/or eliminate conductive material coating over the top surface of a patterned substrate
US20070105377 *24 Oct 200610 May 2007Novellus Systems, Inc.Fabrication of semiconductor interconnect structure
US20070141818 *19 Dic 200521 Jun 2007Bulent BasolMethod of depositing materials on full face of a wafer
US20080003485 *30 Jun 20063 Ene 2008Ramkumar KrishnanFuel cell having patterned solid proton conducting electrolytes
US20080102251 *31 Oct 20071 May 2008Novellus Systems, IncPlating method and apparatus for controlling deposition on predetermined portions of a workpiece
Citada por
Patente citante Fecha de presentación Fecha de publicación Solicitante Título
US79471636 Ago 200724 May 2011Novellus Systems, Inc.Photoresist-free metal deposition
US823616024 May 20107 Ago 2012Novellus Systems, Inc.Plating methods for low aspect ratio cavities
US8435887 *2 Jun 20117 May 2013International Business Machines CorporationCopper interconnect formation
US850098513 Jul 20076 Ago 2013Novellus Systems, Inc.Photoresist-free metal deposition
US8829680 *25 Nov 20139 Sep 2014Tessera, Inc.Reliable packaging and interconnect structures
US935968317 Ago 20077 Jun 2016Applied Materials, Inc.Method of forming metal and metal alloy features
US938503611 Jul 20145 Jul 2016Invensas CorporationReliable packaging and interconnect structures
US95482735 May 201517 Ene 2017Invensas CorporationIntegrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies
US9634412 *15 Jul 201125 Abr 2017Tessera, Inc.Connector structures and methods
US971140128 Jun 201618 Jul 2017Tessera, Inc.Reliable packaging and interconnect structures
US20080041727 *18 Ago 200621 Feb 2008Semitool, Inc.Method and system for depositing alloy composition
US20080067072 *17 Ago 200720 Mar 2008Semitool, Inc.Method and system for depositing alloy composition
US20080237048 *30 Mar 20072 Oct 2008Ismail EmeshMethod and apparatus for selective electrofilling of through-wafer vias
US20090277801 *6 Ago 200712 Nov 2009Novellus Systems, Inc.Photoresist-free metal deposition
US20090280243 *13 Jul 200712 Nov 2009Novellus Systems, Inc.Photoresist-free metal deposition
US20100224501 *24 May 20109 Sep 2010Novellus Systems, Inc.Plating methods for low aspect ratio cavities
US20130014979 *15 Jul 201117 Ene 2013Tessera, Inc.Connector Structures and Methods
US20140084485 *25 Nov 201327 Mar 2014Tessera, Inc.Reliable packaging and interconnect structures
WO2008022316A2 *17 Ago 200721 Feb 2008Semitool, Inc.Method and system for depositing alloy composition
WO2008022316A3 *17 Ago 20073 Abr 2008Semitool IncMethod and system for depositing alloy composition
Eventos legales
FechaCódigoEventoDescripción
30 Ene 2006ASAssignment
Owner name: ASM NUTOOL, INC., CALIFORNIA
Free format text: CHANGE OF NAME;ASSIGNOR:NUTOOL, INC.;REEL/FRAME:017497/0979
Effective date: 20040729
19 Abr 2006ASAssignment
Owner name: ASM NUTOOL, INC., CALIFORNIA
Free format text: CHANGE OF NAME;ASSIGNOR:NUTOOL, INC.;REEL/FRAME:017518/0555
Effective date: 20040729
Owner name: ASM NUTOOL, INC.,CALIFORNIA
Free format text: CHANGE OF NAME;ASSIGNOR:NUTOOL, INC.;REEL/FRAME:017518/0555
Effective date: 20040729
12 Mar 2007ASAssignment
Owner name: NOVELLUS SYSTEMS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ASM NUTOOL, INC.;REEL/FRAME:019000/0080
Effective date: 20061204
Owner name: NOVELLUS SYSTEMS, INC.,CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ASM NUTOOL, INC.;REEL/FRAME:019000/0080
Effective date: 20061204