US20060098721A1

US20060098721A1 - Method and apparatus for receiving GPS/GLONASS signals

Info

Publication number: US20060098721A1
Application number: US11/302,548
Authority: US
Inventors: Alain Rabaeijs; Eric Aardoom; Bert Gyselinckx; Marc Engels
Original assignee: Individual
Current assignee: Individual
Priority date: 1997-11-19
Filing date: 2005-12-13
Publication date: 2006-05-11
Also published as: ATE323890T1; DE69834235D1; EP0924532B1; EP0924532A3; US6967992B1; DK0924532T3; DE69834235T2; EP0924532A2; US20050276316A1; EP1674881A3; EP1674881A2

Abstract

A method of processing received L1 and L2 spread spectrum signals is disclosed. In one embodiment, the method comprises i) locally generating replicas of a known P-code, wherein each of the received signals includes a unique frequency carrier with the known pseudo-random P-code and an unknown code modulated thereon, ii) making the code replicas available at different relative phases, iii) demodulating the received L1 and L2 signals with replicas of the P-code, iv) repetitively and separately integrating the demodulated L1 and L2 signals over time periods related to the unknown code, and v) correlating an integration result for one of the L1 and L2 signals with an integration result for the other of the L1 and L2 signals.

Description

RELATED APPLICATIONS

This application is a continuation application which claims priority under 35 U.S.C. §120 from U.S. patent application Ser. No. 11/139,128, filed May 26, 2005, and which is incorporated by reference. U.S. patent application Ser. No. 11/139,128 also claimed priority from U.S. patent application Ser. No. 09/196,658, filed Nov. 19, 1998, now U.S. Pat. No. 6,967,992, issued Nov. 22, 2005, and which is also incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to an electronic system and its components and to methods of operating the system and its components for receiving spread spectrum signals, for example, signals from a global positioning system such as Global Positioning System (GPS) and/or Global Orbiting Navigation Satellite System (GLONASS).
2. Description of the Related Technology
An increasing number of applications and systems for communicating information nowadays make use of the spread spectrum technique. The spread spectrum technique is a digital modulation technique in which a digital signal is spread over a wide frequency band so that it has a noise-like spectrum. This can be done by breaking up or “chopping” each data bit of the digital signal into multiple sub-bits (commonly called chips) that are then modulated and up-converted to a carrier frequency. The chopping may be done by multiplying the digital information signal with a so-called pseudo-random code or PN code. By using orthogonal codes for different communication links, the same frequency band can be used for different simultaneous communication links.
Using the same PN code as the transmitter, a receiver can correlate the received, spread signal and reconstruct the data signal while other receivers that use other codes or other transmission techniques cannot. One of the advantages of using the spread spectrum communication technique is the robustness to narrow band interference signals. Because spread-spectrum receivers are rapidly being introduced in applications and systems meant for the consumer markets, the cost of the receiver system is a major determining factor in order to remain competitive.
A specific class of spread spectrum systems are devices and receivers for position determination. Such devices are gaining importance for both the consumer market and for high precision applications. Most of the existing systems are based on the American Global Positioning System (GPS). Because this is also a military system, a precise position determination can be made difficult by the satellite operator deliberately introducing errors (called “anti-spoofing”). Moreover, in many areas the number of visible satellites can be too limited to determine an accurate position. These two problems can be reduced by also using a second positioning system such as the Russian Global Orbiting Navigation Satellite System (GLONASS) system.
Combined GPS and GLONASS receivers have been reported, e.g., S. Riley, N. Howard, E. Aardoom, R. Daly, and P. Silvestrin, in “A combined GPS/GLONASS high precision receiver for space applications,” ION-GPS 95, Palm Springs, USA, September 1995, or Japanese patent application JP 7128423-950519, “Receiver Common to GPS and GLONASS.”
A GPS receiver is disclosed in U.S. Pat. No. 5,293,170 that can be used with P-code modulated signals, which have been modulated with an unknown code. Implementations of this known device require a lot of registers.
U.S. Pat. No. 5,600,670 describes a GPS receiver that includes a hierarchical chain of channel modules which includes slave modules and a master module. The known system does not provide sufficient flexibility.

SUMMARY OF CERTAIN INVENTIVE ASPECTS

One aspect of the invention provides a method of processing received L1 and L2 spread spectrum signals, wherein each of the signals includes a unique frequency carrier with a known pseudo-random code modulated thereon, each L1 and L2 signal being converted into a plurality of digital signals, the method comprising: i) locally generating a single replica of the known code, ii) making the code replica available at different relative phases, iii) first demodulating the converted L1 and L2 signals with the single replica of the known code without any substantial delay, the first demodulated signal being associated with the L1 signal, iv) second demodulating the converted L1 and L2 signals with the generated replica of the known code from one of the taps of the delay line, the second demodulated signal being associated with the L2 signal, v) selectably switching the converted L1 and L2 signals for the first demodulation and selectably switching the converted L1 and L2 signals for the second demodulation, vi) repetitively and separately integrating the demodulated L1 and L2 signals over a time period, and vii) adjusting the phases of the locally generated code replicas relative to the incoming L1 and L2 signals in order to maximize the power of the integrated demodulated L1 and L2 signals.
Another aspect of the invention provides an apparatus for processing received L1 and L2 spread spectrum signals, wherein each of the signals includes a unique frequency carrier with a known pseudo-random P-code and an unknown code modulated thereon, the apparatus comprising: i) a generator of replicas of the known P-code, ii) a delay line configured to make the known P-code replicas available at different relative phases, iii) a first demodulator, connected to the generator, configured to demodulate one of the received L1 and L2 signals with one of the known P-code replicas, iv) a second demodulator configured to demodulate the other of the received L1 and L2 signals with one of the known P-code replicas, v) a first integrator configured to repetitively and separately integrate the demodulated one of the L1 and L2 signals over time periods related to the unknown code, vi) a second integrator configured to repetitively and separately integrate the demodulated other of the L1 and L2 signals over time periods related to the unknown code, and vii) a correlator configured to correlate the first integrator output with the second integrator output.
Another aspect of the invention provides an apparatus for processing received L1 and L2 spread spectrum signals, wherein each of the signals includes a unique frequency carrier with a known pseudo-random code modulated thereon, each L1 and L2 signal being converted into a plurality of digital signals, the apparatus comprising: i) a generator configured to locally generate a single replica of the known code, ii) a delay line wherefrom the known P-code replicas are available at different relative phases thereof, wherein the single replica of the known code is applied to the delay line, iii) a first demodulator configured to first demodulate the converted L1 and L2 signals with the single replica of the known code without any substantial delay, the first demodulated signal being associated with the L1 signal, iv) a second demodulator configured to second demodulate the converted L1 and L2 signals with the generated replica of the known code from one of the taps of the delay line, the second demodulated signal being associated with the L2 signal, v) a switch configured to selectably switch the converted L1 and L2 signals for the first demodulation and selectably switch the converted L1 and L2 signals for the second demodulation, vi) an integrator configured to repetitively and separately integrate the demodulated L1 and L2 signals over a time period, and vii) a phase adjuster configured to adjust the phases of the locally generated code replicas relative to the incoming L1 and L2 signals in order to maximize the power of the integrated demodulated L1 and L2 signals.
Still another aspect of the invention provides a method of processing received L1 and L2 spread spectrum signals, wherein each of the signals includes a unique frequency carrier with a known pseudo-random P-code and an unknown code modulated thereon, the method comprising: i) locally generating replicas of the known P-code, ii) making the code replicas available at different relative phases, iii) demodulating the received L1 and L2 signals with replicas of the P-code, iv) repetitively and separately integrating the demodulated L1 and L2 signals over time periods related to the unknown code, and v) correlating an integration result for one of the L1 and L2 signals with an integration result for the other of the L1 and L2 signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram showing the major components of a spread spectrum receiver according to one embodiment of the present invention.
FIG. 2 illustrates a schematic representation of a part of the correlator unit in accordance with one embodiment of the present invention.
FIG. 3 illustrates a schematic representation of a channel matrix in accordance with an embodiment of the present invention.
FIG. 4 illustrates a schematic representation of a CA-channel module in accordance with an embodiment of the present invention.
FIG. 5 illustrates a schematic representation of a hierarchical chain of CA-channel modules in accordance with an embodiment of the present invention.
FIG. 6 illustrates a schematic representation of a dual frequency channel in accordance with an embodiment of the present invention.
FIGS. 7 a and 7 b illustrate schematic representations of slaving control circuits for a CA-channel module and a CaP-channel module, respectively, in accordance with an embodiment of the present invention.
FIG. 8 illustrates a schematic representation of a code delay line unit in accordance with an embodiment of the present invention.
FIGS. 9 a and 9 b illustrate two examples of three channel modules with slaved code delay lines in accordance with an embodiment of the present invention.
FIG. 10 illustrates a schematic representation of a correlator unit in accordance with an embodiment of the present invention.
FIG. 11 illustrates a schematic representation of a CA-code integrator module in accordance with an embodiment of the present invention.
FIG. 12 illustrates a schematic representation of a CaP-code integrator module in accordance with an embodiment of the present invention.
FIG. 13 illustrates a schematic representation of a CaP-code integrator module including a Y-code estimator in accordance with an embodiment of the present invention.
FIG. 14 illustrates a schematic representation of a Y-code estimator in accordance with an embodiment of the present invention.
FIG. 15 illustrates schematic representation of a P-code unit in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF CERTAIN INVENTIVE EMBODIMENTS

Definitions
Channel: The functionality or hardware required to track one pseudo-noise code on a single frequency, e.g., a navigation code such as CA on L1 of SV3 or P on L2 of SV19. For example, not all channels of the Advanced GPS/GLONASS receiver (AGGR) need be identical in functionality. For instance, some may only be able to track the CA-code, others also the P-code. Some can operate as a master in a master-slave configuration, and some not.
Dual-frequency channel: The functionality and hardware needed to track all three ranging signals transmitted by one GPS or GLONASS satellite are placed on one carrier (L1) and the same P-code is placed on a second carrier (P on L2). A dual-frequency channel is formed by grouping three single-frequency channels.
Observables: Information read from the AGGR, except the correlation values (i.e. carrier frequency cycle counter, phase and code carrier frequency cycle counter and phase for each channel).
Pseudorange measurements: Synonym for code-phase measurements.
RF conditioning input: The input to which the antenna is connected.
Measurement epoch signal: Periodic strobe signal which controls updating of observables, common to all channels.
Integration epoch signal: Periodic strobe signal which controls updating of frequency and/or phase of internal code and carrier replica signals, individual for each channel. This signal also updates correlator output registers.
Antenna switch epoch signal: Strobe signal which controls updating of correlator output registers.
Code epoch signal: Periodic strobe signal which indicates a unique pattern (corresponding to the all-ones state of the code generator shift register) in the generated or received pseudo-random noise code.
GNSS signals: Combination of GPS, GLONASS and various augmentation signals, e.g., EGNOS, WAAS, MTSAT.
Complex signal: A signal split into in-phase (I) and quadrature (Q) components.
Interchannel bias: Mean error between two channels tracking the same satellite signal.
Bit numbering and naming conventions: Bussed signals are indexed from the least significant (LSB) to the most significant bit (MSB). The LSB has index 0 while the MSB of a vector of length N has index N-1. A suffix of “N” to a signal name indicates that a signal is active low. For example, ResetN is an active low signal.
List of Abbreviations:

- ADC: Analogue to Digital Converter
- ADSP21020: Analog Devices Digital Signal Processor 21020
- AGC: Automatic Gain Control
- AGGR: Advanced GPS/GLONASS receiver
- AGGA: Advanced GPS/GLONASS ASIC
- AOCS: Attitude and Orbit Control System
- AS: Anti-Spoofing, technique by which the GPS P-code is encrypted
- ASIC: Application Specific Integrated Circuit
- CA-code: Coarse Acquisition code
- CaP-channel: Channel that can process CA- and P-codes
- CDMA: Code Division Multiple Access
- DAC: Digital to Analogue Converter
- DSP: Digital Signal Processing
- E: Early correlation
- EGNOS: European Geostationary Navigation Overlay System
- EOW: End of Week
- ERC32: Embedded Real-time Core, 32-bit Sparc microprocessor
- GLONASS: Global Orbiting Navigation Satellite System
- GNSS: Global Navigation Satellite Systems
- GPS: Global Positioning System
- I: In-phase
- IF: Intermediate Frequency
- IO: Input-Output
- L: Late correlation
- L1: Carrier frequency (1575.42 MHz for GPS, 1602.0+ 9/16*ch MHz for GLONASS)
- L2: Carrier frequency (1227.6 MHz for GPS, 1246.0+ 7/16*ch MHz for GLONASS)
- LFSR: Linear Feedback Shift Register
- LSB: Least Significant Bit
- MSB: Most Significant Bit
- MSPS: Mega Samples Per Second
- MTSAT: Mobile Transport Satellite system
- NCO: Numerically Controlled Oscillator
- P: Punctual correlation
- PCB: Printed Circuit Board
- P-code: Precision code
- PLL: Phase-Locked Loop
- PN-code: Pseudo-Noise code
- POD: Precise Orbit Determination
- PRN: Pseudo-Random Noise
- Q: Quadrature
- RF: Radio-Frequency
- SA: Selective Availability
- SM: Sign/Magnitude
- SNR: Signal-to-Noise Ratio
- SV: Space Vehicle
- W-code: Code used to encrypt the GPS P-code to form the Y-code
- WAAS: Wide Area Augmentation System
- Y-code: Encrypted GPS P-code
  Description of Certain Embodiments

The present invention will be described with reference to specific embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. Further, the present invention will mainly be described with reference to global positioning and navigation systems such as GLONASS or GPS but the present invention is not limited thereto but only by the claims. In particular, the present invention may find application with spread spectrum communications systems generally, in particular with direct sequence CDMA (DS-CDMA) systems. In particular, the functional specification for the design of an advanced GPS and/or GLONASS receiver (AGGR) is disclosed. The AGGR is preferably fabricated including at least one sub-system implemented as an application specific integrated circuit (ASIC). The ASIC implementation of the AGGR will be referred to as the AGGA. The AGGR and particularly the ASIC (AGGA) may be used in a variety of combined GPS/GLONASS receivers for a multitude of applications including, as a non-limiting list, synchronization of mobile telephone systems, personal location devices, high precision scientific instruments and satellite attitude and orbit control systems.
The main functional units of an AGGR 100 in accordance with an embodiment of the present invention are shown schematically in FIG. 1. The AGGR 100 may comprise a linear arrangement of a microprocessor 101, a digital correlator 102, an analog front-end 103 and an antenna or antennae, e.g., an antenna array, 104. The microprocessor 101 runs the applications software and controls the operation of the AGGR 100. The correlator 102 comprises a number of channels or channel modules which can acquire and/or track spread spectrum signals, e.g., those received from a global positioning satellite. The correlator 102 may have the capability of multipath mitigation and/or calibration and/or fast acquisition. The front-end 103 converts the RF signals captured by the antenna 104 into time-discrete digital signals which can be used by the correlator 102. A suitable front-end unit 103 is known from co-pending European Patent Application No. 97870164.7 “Method and Apparatus for receiving a converting spread spectrum signals” which is incorporated hereby by reference.
In accordance with one embodiment of the present invention, the correlator 102 may include an AGGA 10 but the present invention is not limited thereto and other forms of circuits may be used, e.g., PCB's. A schematic functional block diagram of an AGGA 10 in accordance with one embodiment of the present invention is shown in FIG. 2. The AGGA 10 comprises eight main functional blocks: a front-end interface 2 which interfaces with the front end 103, a channel matrix 3, a time base generator 4, a clock generator 5, and a microprocessor interface 6 which interfaces with the receiver microprocessor 101, an interrupt controller 7, a general purpose 10 port 8 and an antenna switch controller 9. The ResetN input signal is distributed to all modules 1-9. The modules 1-9 may be connected together via an internal bus I.
In the following description reference may be made to registers. These registers are not shown in the drawings but may be located on-chip, i.e., on the same chip as the AGGA 10 ASIC. A memory map may be provided so that the address location of each register may be known to the microprocessor 101 independent of the specific design of this microprocessor 101.
The front-end interface 2 accepts digitized Intermediate Frequency (IF) input signals ADCIn0-7 from the analog front-end 103. The IF signal, for instance, can be real or complex. When real, the signal may be transformed into an In-Phase (I) and a Quadrature (Q) value and down-converted by a fixed frequency equal to a quarter of the sampling frequency. When the input IF signal is complex, it is represented as an In-Phase (I) and Quadrature (Q) value on two adjacent inputs. The down-conversion stage is then bypassed. AGGA 10 may be adapted to support a multitude of input formats, e.g., sign/magnitude, unsigned, two's complement and three-level comparator output. Furthermore, an estimate of the input energy (signal-plus-noise) may be measured to be used for automatic gain control (AGC) purposes, for instance, a signal level detector (not shown) may estimate the signal-plus-noise power of the I or Q branch of a complex signal and may be time shared by all inputs.
The channel matrix 3 contains a plurality (N) of independent channels, and may find general use in despreading spread-spectrum signals. In particular, in accordance with one embodiment of the present invention, each channel may be capable of L1 or L2 CA-code processing. These channels can also be configured into groups of three to form up to N/3 independent dual-frequency tracking channels capable of tracking CA-code on L1 or L2 and P-code on L1 and L2. Furthermore, channels can be grouped in several other ways to support functions such as fast acquisition, attitude determination by means of interferometric carrier phase measurements and multipath mitigation.
The number of channels N in an AGGA 10 is determined by how many can be integrated in the chosen technology. Each channel can be configured independently to track a GNSS signal. Dual-frequency channels support P-code and Y-code tracking. At the end of each measurement epoch, carrier and code phase values for all channels are latched into a set of observable registers (not shown). At the end of the integration epoch (individual for each channel) the code correlation values are latched into a set of correlation registers (not shown). The correlation values are used by the receiver firmware to close the tracking loops, including carrier and code phase error computations, application of loop filters, and estimation of signal and noise amplitude. The observables are used by the receiver firmware to derive the position, time, velocity and in some cases attitude. The measure epoch is provided by the time base generator 4 and is common for all channels.
The time base generator 4 preferably produces three periodic strobe signals EpochClk, MEO and OnePPS for accurate receiver time-keeping and observable measurements. The EpochClk output has a nominal frequency of 1 kHz and is the clock signal for the integration level epoch generation, the measurement epoch generation and the antenna switch controller. The measurement epoch output MEO is asserted to indicate the end of each measurement epoch. The measurement epoch input MEI accepts the MEO strobe from another AGGA 10 to enable synchronization of the observable measurements in configurations with more than one AGGA 10. The time base generator 4 also generates a one-pulse-per-second (OnePPS) signal to which external equipment can be synchronized.
The clock generator 5 produces one internal clock signal CoreClk and three external clock signals SampleClk, GenClk and ProcClk, all derived from an external clock. For instance, the AGGA 10 can generate clock signals for the ADC's and the internal channel matrix 3, a GP2010 front-end as made by GEC Plessey Semiconductors, UK and the receiver microprocessor 101. The different clock frequencies can be programmed individually. Three dedicated inputs are provided to program the clock division ratio of the microprocessor clock.
A microprocessor 101 can access the AGGA 10 through the microprocessor interface 6. The AGGA 10 may behave as a generic memory-mapped peripheral. An internal address decode (not shown) may be provided in the microprocessor interface 6, which allows the microprocessor 101 to address up to 4 AGGA's 10 using only a single chip select line. Two dedicated inputs are provided to select the valid address range of the AGGA 10. The interface 6 is preferably directly compatible with the Analog Devices ADSP21020 and the ERC32 Spare chip set. It is 32-bit wide and does not require wait-states at the specified processor clock frequencies of 20 MHz and 14 MHz for the ADSP21020 and ERC32, respectively, under the condition that the CoreClk frequency of the AGGA 10 exceeds the microprocessor clock frequency. Otherwise, the microprocessor 101 must insert wait-states to ensure that a read or write operation exceeds the CoreClk cycle time.
When various modules within the AGGA 10 require action by the microprocessor 101, this can be signaled through interrupt requests. The AGGA interrupt controller 7 receives these interrupt requests, stores them in an interrupt status register (not shown) and generates an external interrupt request. To connect multiple AGGA's 10 with a single interrupt signal to the microprocessor 101 the interrupt controller 7 may have two external interrupt inputs, allowing a number of AGGA's 10 to be connected, e.g., as a binary tree.
The parallel IO interface 8 supports functionality such as system monitoring and control functions, e.g., monitoring lock indicators of the external down-converter frequency synthesizers, or power-down of external circuitry. The output port 8 can, for example, be used for controlling parallel DACs for the front-end AGC functions. All IO pins are preferably uni-directional to prevent accidental short-circuits due to incorrect programming of the direction of IO drivers.
The antenna switch controller 9 provides means to control antenna switching for up to four antenna units 104, for instance, in a hybrid parallel-multiplex attitude determination GNSS receiver 100. It also produces an antenna switch epoch strobe which signals an antenna switch event and which is used to store correlator readings of all channels configured as slave channels. In configurations with more than one AGGA 10 only the antenna switch controller 9 of one master AGGA 10 need be enabled, while all other slave AGGA's 10 preferably use the Antenna Switch Epoch Output (ASE) of the master AGGA 10 to control their respective correlators 102.
A structure of the channel matrix 3 in accordance with one embodiment of the present invention is shown schematically in FIG. 3. The channel matrix 3 includes a plurality of processing channels 30 to 41. Twelve channels are shown but the invention is not limited thereto. All channels 30 to 41 preferably have identical functionality for CA-code tracking. Any channel 30-41 can also be configured to process unmodulated input signals, a feature which is provided for the calibration of RF front-end group delay variations. Channels 30, 33, 36, 39 which can only track the CA-code are called CA-channels, while CaP- channels 31, 32, 34, 35, 37, 38, 40, and 41 have additional functionality to enable them to track also P-code or Y-code modulated signals. A separate P-code unit 42-45 per dual-frequency channel generates the replica P-code for the pair of CaP-channels, e.g., 37, 38, when one CA-channel 36 and two CaP- channels 37, 38 are grouped to form a dual-frequency channel (one column of the channel matrix 3 as shown).
The channels 30-41 can be selectively slaved as indicated by the dashed or solid lines in FIG. 3. Slaving means at least that certain signals or signal parameters generated by the master channel (usually a CA-channel) are used by the next channel in the sequence or chain. Channels may be hierarchically chained together. For instance, for rapid acquisition all the CA- channels 30, 33, 36, 39 may be slaved together, the timing for the despreading operation used by one channel being passed on to the next channel in the sequence which adds a delay, attempts a correlation with the received signal and passes the delayed timing to the next channel and so on. By slaving, unnecessary re-calculation of signal parameters already calculated or used in the channel before may be avoided. In particular the speed of acquisition can be increased.
The operation of the channel matrix 3 is preferably entirely controlled by the external microprocessor 101. The basic functions of each channel 30-41 are: selection of one of eight complex output signals IQ0-7 from the front-end interface 2, down-conversion of the selected complex sign-magnitude signals IQ0-7 to baseband, despreading of the complex baseband signals with the on-chip generated CA or P replica code and integration over a programmable time interval. The result of these integrations is the correlation values. Together with the observables, which are the carrier and code frequency and phase measurements, they are the outputs of the channels 30-41.
A CA- channel 30, 33, 36, 39 preferably can process L1 or L2 CA-code modulated GNSS signals but not P-code or Y-code modulated signals. A block diagram of a CA-channel 30 in accordance with an embodiment of the present invention is shown schematically in FIG. 4. An input selector 302 selects one of the eight complex front-end interface output signals IQ0-7 with sample rate equal to the CoreClk rate. In an image reject mixer 305 any residual carrier frequency is removed by rotating the selected complex signal by an angle determined by a carrier generator 304, resulting in a complex baseband signal. A correlator unit 307 then despreads this signal using three CA-code sequence combinations E, P and L (early, punctual and late) and integrates the result during a programmable integration period. Hence, the correlator unit 307 includes six accumulators: three for each of the I and Q branches (not shown). The outputs of the correlator unit 307 are the correlation values. In the case of hybrid parallel-multiplex attitude determination, the integration period can be controlled by the antenna switch epoch (ASE) strobe.
The three CA-code sequence E, P and L are derived from a single CA-code sequence generated by the CA-code unit 306. The delays between the E, the P and the L sequences are determined by the settings of the CA-code delay-line unit 308. The CA-code chip rate is determined by the code numerically controlled oscillator (NCO, not shown) of the CA-code unit 306. The CA-code unit 306 also controls the length of the integration interval. The observables are sampled on the MEO strobe. The data and the address buses D and A are used by the microprocessor 101 to access the registers in the channel.
Within one AGGA 101 each CA- channel 30, 33, 36, 39, or CaP- channel 31, 32, 34, 35, 37, 38, 40, 41, operating as a CA only channel, can be slaved to another channel as shown by the dashed or dotted lines in FIG. 3. The signals which can be used in slaving are preferably AngleExt, CodeExt and CorrCtlExt (carrier rotation angle, the locally generated code and associated correlator control signals), respectively. It is preferred in accordance with the present invention if not every channel can be slaved with any other channel as this is wasteful of resources and brings little processing gain. The slave channel selection rule for the channels shown in FIG. 3 may be summarized as follows: any channel Cε(0 . . . N−1) may be slaved to a channel which satisfies (C−1 mod N) or (C−3 mod N). This means that a channel may either be a slave of its previous neighbor in the same column (or the bottom of the previous column if C is at the top of a column) or be a slave of the channel in the corresponding position in the previous column (or in the last column if C is in the first column). The ability of the receiver in accordance with the present invention to select one of at least two candidate channel modules for the next module in a chain is a significant advantage over the known receiver of U.S. Pat. No. 5,600,670.
FIG. 5 shows schematically an embodiment of the present invention having one master 30 and two slave channels 33, 36 tracking CA-code only modulated signals. Each of the CA- channel 30, 33, 36 may be identical, components of the channels not used in this embodiment are not shown for clarity purposes. Alternatively, one or more of the channels 30, 33, 36 may be CaP- channels 31, 32, 34, 35, 37, 38, 40, 41 of which only the components are shown required for CA-code acquisition. This configuration can be used for fast CA-code acquisition and for differential carrier phase measurements in attitude determination applications. The carrier rotation angle (AngleOut) for all channels is generated by the master carrier NCO unit 304 and distributed to all slave channels 33, 36. Likewise, the code (CodeOut) and associated correlator control signals (CorrCtlOut) for all channels 30-36 are generated by the master code unit 306 and distributed to the code delay line unit 338 of the first slave channel 33, which distributes these signals further down the chain.
In accordance with one embodiment of the present invention the replica CA-code sequences may or may not be delayed by the code delay- line units 308, 338, 368 of the master and slave channels 30, 33, 36 depending on the application. In accordance with one embodiment of the present invention, the code delay- line units 308, 338, 368 may be programmed differently or fast acquisition and attitude determination, respectively. For fast acquisition, front- end input selector 302, 332, 362 of all channels 30, 33, 36 are set to the same output of the front-end 103 and all delay- line units 308, 338, 368 are programmed to ½ or 1 CA-code chip delay. The correlator units 307, 337, 367 correlate the individually delayed CA-code sequences with the received signal—the more channels process the same signal simultaneously, the faster synchronization will be achieved. In accordance with one aspect of the present invention, the same signals from the front end 103 are processed by a selectable number of channels up to the maximum number of channels which can be assigned to the task of acquisition, hence resulting in rapid acquisition.
On the other hand, for attitude determination, all input selectors 302, 332, 362 are set to a different front-end output (i.e., they all receive the same basic signal but each one from a different antenna 104) and the delay- line units 308, 338, 368 are programmed for zero delay, such that all slave channels 33, 36 receive CA-code sequences from the master CA-code unit 306 with identical phase. In one embodiment, the delay-line units such as 308 are selectable for one of a plurality of pre-determined delays or for no delay depending upon the application.
As shown schematically in FIG. 6, a combined CA and P (CaP) channel, e.g., 31 or 32 contains all the functionality for CA-code operation as described above with respect to FIGS. 3-5, e.g., the use of the image reject mixers 315, 325, with additional enhancements to the correlator unit (L1 demodulator) 317 and the correlator unit (L2 demodulator) 327 for P-code and Y-code operation. A separate P-code unit 42-45 per dual-frequency channel generates the GPS and GLONASS P-codes and their associated integration control signals. Each CaP- code correlator unit 317, 327 is specially adapted for the integration of P-code and Y-code signals. More detail will be provided later with respect to codeless acquisition of the Y-coded signals in accordance with one embodiment of the present invention.
Normally a CA-channel such as 30 provides the carrier rotation angle for the L1 P-channel such as 31. However, the L1 P-channel 31 can also use its internal carrier generator (not shown in FIG. 6 for 31 but similar to 324 of 32) to generate the carrier rotation angle (this may be advantageous for better carrier phase performance in the presence of multipath). The correlator units 317, 327 of the CaP- channels 31, 32 are controlled by the CA-channel IntEpoch output signal, which is part of the CorrCtl bus. Hence the correlator units 307, 317, 327 of the CA-channel, the L1 P-channel and the L2 P-channel, respectively, of a dual-frequency channel integrate over the same time period. The IntEpoch signal is also used for triggering the P-code generator during P-code acquisition and is therefore also input directly into the P-code unit 42. The rate at which the P-code for the L1 and L2 channels 31, 32 is generated is programmed in the code NCO's of the CA- code units 316, 326 of the L1 P-channel 31 and of an L2 P-channel 32, respectively.
In accordance with one embodiment of the present invention, only two dual-frequency channels can be slaved in accordance with the rules defined by the dotted lines in FIG. 3. Such slaving doubles the number of correlator units available for tracking the P-code on L1 and the P-code on L2, a feature which is provided for multipath mitigation (at the cost of halving the number of available channels).
Some hardware is provided in accordance with the present invention to allow different groups of channels to be slaved together. The more possibilities that are allowed for grouping together channels, the larger the overhead on signal lines and multiplexers. Further, with current clock frequencies, the sum of all delays which can be tolerated is limited by the repetition rate of the received signals. Hence, the channel slaving requirements within one AGGA 10 in accordance with one embodiment of the present invention are preferably up to four single-frequency channels or up to two dual-frequency channels. If a channel is configured to accept external carrier phase angle, code and correlator control signals, the slaving multiplexers of the channel matrix 3 are preferably programmable to select the desired slaving sources. Selection may be done by means of multiplexers or selector gates as shown schematically in FIGS. 7 a and 7 b. With reference to FIG. 4, the rotational angle for correction of the carrier phase may be supplied internally or externally, the selection being made by a selector circuit, e.g., a multiplexer 304. The external Angle signal may come from one of two other previous channels depending on how the connection in the slaving chain is formed, either the previous neighbor (C−1) or the one three back (C−3). Hence, as shown in FIG. 7 a, a selector circuit is provided, e.g., a multiplexer 29, which selects between the Angle signal supplied by either the C−1 or C−3 channel depending upon the AngleSel signal. Similarly, the selection between external or internal Code signals in FIG. 3 is made by a selector circuit, e.g., a multiplexer 303. Which external Code signal is selected for the channel 30 is determined by a selector circuit, e.g., a multiplexer 28 depending upon the CodeSel signal. The signals that can preferably be slaved are Angle, Code (CA- or P-code) and various control signals grouped into CorrCtl, as shown in FIGS. 7 a and b. Two related signals, DoubleChipRate and IntEpoch, are grouped as part of the CorrCtl bus to simplify the block diagrams.
The control circuitry shown in FIG. 7 b for a Ca-P channel module resembles that of FIG. 7 a, e.g., selectors 26 and 27 are equivalent to selectors 29 and 28 respectively. In one embodiment, a selector 25 selects whether the P-code is taken from a P-code unit or is received in slaving mode. In one embodiment, a selector 24 controls whether the SignInSec is external or local. This signal will be described later with respect to the extraction of Y-coded signals.
The code delay-line units such as 308 may produce Early (E), Punctual (P) and late (L) versions of the replica code and optionally a version of IntEpoch. The code delay units in accordance with the present invention such as 308 may find general use in spread spectrum systems, e.g., in direct sequence CDMA. In accordance with an embodiment of the present invention, the delays between the E, the P and the L code outputs are programmable. The three code output sequences are used by the correlator units such as 307 to despread the complex baseband signal.
FIG. 8 shows schematically a code delay-line block diagram in accordance with an embodiment of the present invention. A code delay-line unit, e.g., 308, selects three code phases E, P, L from a 13-stage delay-line 52. The output sequences are spaced by multiples of either half a code chip or one CoreClk period. The former is only valid for code chip rates lower than one-quarter of the CoreClk rate. The clock source is selected by a selector 54 to be either CoreClk or DoubleChipRate. The P version of the Code is taken from one tap of the delay line 52. The delay from the input Code signal to the P version thereof is at least two DLClock periods and at most seven DLClock periods (default value). CodeOut (passed to the next channel module in the chain if one exists) is either a non-delayed or a delayed version of the code and is used for channel slaving. The selection between non-delayed and delayed is made in the selector circuit 56. For configuring channels for attitude determination a zero delay between Code and CodeOut is selectable. By selective operation of the two selector circuits 51 and 53 the delay from Code to the delayed version of CodeOut can vary between two and thirteen DLClock periods. By selective operation of selector circuits 51 and 55, the delay from Code to E can vary between one and six DLClock periods.
Delay-line units such as 308 from several channels can be cascaded to produce code sequences with delays larger than those possible with a single delay-line 52. This feature is provided for rapid acquisition and multipath mitigation. A switch control module 58 supports the time-multiplexing of code sequences at different code spacings. This technique can be used for multipath mitigation measuring of the correlation profile. It is however not preferred in applications with high-dynamics.
The ChipSpacingPL field of the DelayLineMode register (e.g., part of on-chip memory) sets the chip spacing between the P and L code sequences. The following chip spacings between the E and P sequences or the P and L sequences can be programmed using the selectors 51, 55, 57: T, 2T, 4T, 6T, and ½ chip, 1 chip, 2 chips or 3 chips, where T is the CoreClk period. As a consequence the following chip spacings between E and L sequences can be programmed: 2T, 3T, 4T, 5T, 6T, 7T, 8T, 10T, 12T and 1 chip, 1.5 chips, 2 chips, 2.5 chips, 3 chips, 3.5 chips, 4 chips, 5 chips or 6 chips. The spacing in chips can only be used when the CoreClk frequency is at least four times the ChipRate. If this is not the case the chip spacing in multiples of the CoreClk period is preferably used.
The input selector 51 is used for cascading code delay-lines of slaved channels. Its purpose is to provide a programmable delay between the correlation measurements of the slaved channels. Specifically, it enables a programmable chip spacing for fast acquisition and multipath mitigation. The input code sequence can be fed into tap 0 to 5 of the delay-line 52. For correct behavior, the input selector 51 should select a delay-line tap with a number lower than or equal to the number of the tap selected for the E sequence.
The cascading output CodeOut can be connected to one of taps 6 to 12 of the delay-line 51 or directly to the Code input. By connecting the output selection of one code delay-line unit to the input of another delay-line unit, a single long delay line consisting of several slaved delay-lines of different channels can be created. This output can be programmed independently of the chip spacing.
In accordance with one embodiment of the present invention, a switch control functionality is used for time-sharing of a single correlator over different code sequences. This allows the correlation profile to be measured without the need of extra correlators and is generally applicable to the despreading of spread spectrum signals. When this technique is used a different chip spacing (advance timing with respect to P) is selected for the E sequence by the selector circuit 55 at every IntEpoch interval but a single correlator is used to accumulate the results from each selection. The ability to selectively determine timing difference, i.e., the delay or advance, between the E and P or P and L sequences for each integration period is a significant advantage of one embodiment of the present invention. One advantage of this method is that the number of separate correlators required to measure the correlation profile is reduced. The timing sequence is controlled by the switch control module 58. It is preferably fully programmable to sequence over two to four cycle periods. This includes the number of time multiplexed taps (1 to 4) as well as the tap sequence. For example, for a switch sequence of three, the switch control sequence can be programmed to be T, 2T and 4T or T, 4T and 6T etc. The setting is buffered into a register on an IntEpoch strobe so that the microprocessor 101 can read to which E-P spacing the integration values correspond. The IntEpoch strobe is used to synchronize the transitions to the next switch setting to the integration interval. The provision of a programmable switch 58 is a significant advantage of the present invention as it allows the sequential determination of correlation values for the E sequences at a different advanced timing with respect to the P sequence, hence allowing generation of a correlation profile without requiring a separate correlator for each different advanced timing of the E sequence. Although embodiments of the present invention have been described with reference to the switch control module 58 controlling the operation of the early delay line 55, another embodiment of the present invention includes a switch control module for controlling the operation of the late delay line 57 in a similar way.
FIGS. 9 a and 9 b show two examples of the slaving capability of the AGGA in accordance with the present invention. FIG. 9 a shows a possible configuration with three channels configured for fast-acquisition. The delay lines 52, 52′ and 52″ are clocked by the DoubleChipRate signal. Nine complex integrators are configured to correlate nine code sequences spaced by 0.5, 1, 1.5, 2, 2.5, 3, 3.5 and 4 code chips relative to the first E output tap. FIG. 9 b shows three delay lines 52, 52′ and 52″ slaved for multipath mitigation. The nine correlators are configured to correlate nine code sequences being ET3, EE, E, E-L, P, L, LL, LT3, and LT4. With a CoreClk rate of 30 MHz, the E-L spacing is about 8/3 GPS P-code chips or 8/30 GPS CA-code chips.
The delay-line units such as 308 in accordance with one embodiment of the present invention support multipath mitigation in two ways: channel slaving and time-multiplexing. Channel slaving allows multiple correlators to be cascaded such that more samples of the correlation function can be obtained, FIG. 9 b shows an example of three channels with slaved code delay-lines. The spacing between two adjacent sequences is 4T. With a CoreClk of 20 MHz this is equivalent to 2 P-code chips. The right-most part of FIG. 9 b is performed in a despreader module of a correlator unit.
A correlator unit block diagram in accordance with an embodiment of the present invention is shown in FIG. 10. A correlator unit such as 307 in accordance with the present invention consists of a complex despreader module 62 and three complex integrator modules 64, 66, 68. The despreader module 62 multiplies the complex image reject mixer output signal (DataIn) with three code sequences. Each integrator module 62, 64, 66 integrates a despread data-sequence over a programmable integration interval equal for all integrators 62, 64, 66 of a correlator unit 307.
The despreader module 62 multiplies the complex baseband signal by three code sequences. Each code sequence is a combination of the three spreading code sequences E, P and L. Valid combinations of the code sequences E, P and L are: (P,E,L), (P,E-L,Off), (P,E-L,E), (P,E-L,L), (P,P,Off) and B,Off,Off) with Off representing “not used” and B representing “bypassed.” The principal usage for the different combinations of code sequences are:

- (P,E,L): This combination is used for fast acquisition or for measuring absolute correlation values of a data sequence despread with E, P and L code sequences e.g. for multipath mitigation techniques. Also tracking with separate E and L measurements uses this combination.
- (P,E-L,Off): This combination is used in tracking mode and when no information about the absolute E or L correlation values is needed.
- (P,E-L,E): This combination is used in tracking mode for multipath identification. An extra E measurement is obtained when three channels are slaved equivalent to FIG. 9(b).
- (P,E-L,L): This combination is used in tracking mode for multipath identification. An extra L measurement is obtained when three channels are slaved as shown in FIG. 9(b).
- (P,P,Off): This combination only uses the P sequence. This is used in the slave channel configured for hybrid parallel-multiplex attitude determination mode.
- (B,Off,Off): This combination is used in calibration mode. The despreader 62 is bypassed and only the first integrator is used.
  The output of the despreader module 62 are three complex sequences of despread data DesprValue1-3. The I and Q value of DesprValue is either −3, −1, 0, 1 or 3. The value 0 will only occur in E-L configuration, in which case the correlation values are also divided by two.

An integrator module 64, 66, 68 in accordance with one embodiment of the present invention is a complex integrator. In one embodiment, the integrator module 64, 66, 68 may find general application in the despreading of spread spectrum signals, e.g., in direct sequence CDMA receivers. The correlator unit of a CA-channel contains CA-code integrators while the correlator unit of a CaP-channel contains CaP-code integrators. A block diagram of the CA-code integrator module 70 in accordance with one embodiment of the present invention is shown in FIG. 11.
In one embodiment, a CA-code integrator acts as a 22-bit adder. In another embodiment, the CA-code integrator is a two-stage integrator consisting of a low number of bits accumulator, e.g., a 9-bit two's complement primary accumulator 72 and a full number of bits accumulator, e.g., a 22-bit two's complement secondary accumulator 74. The result of the primary accumulator 72 is dumped at a rate equal to the CA-code chip rate into a first integration buffer 73. The second accumulator 74 integrates the dumped contents of the first accumulator 72 over a longer period, e.g., one IntEpoch period. The result is double buffered in a second integration buffer 75 and kept until the end of the next integration period, when it will be overwritten by the new integrator value. One advantage of this two-stage integration is the fact that the power consumption can be reduced dramatically. Only the small primary accumulator 72 is operating at the high clock rate, while the large secondary accumulator 74 is only running at the chip rate. The use of a two-stage integrator for the CA-code is one of the major advantages of the present invention compared to the known integrators of EP 508 621.
In hybrid parallel-multiplex attitude determination mode, the integration values can also be stored into the secondary accumulator integration buffers 75 on an ASE strobe. Together with the selection of the (P,P,Off) code sequence combination in the despreader module 62, one complex integrator 64, 66, 68 will be programmed to update the secondary accumulator integration buffers 75 on an IntEpoch strobe while the other enabled complex integrator 64, 66, 68 will update the integration buffers on an ASE strobe. The integrators themselves are then reset at both IntEpoch and ASE strobes.
A CaP-code integrator module 80 in accordance with one embodiment of the present invention can be configured to accumulate CA-code modulated signals, P-code modulated signals or encrypted P-code modulated signals, i.e., Y-code modulated signals. A block diagram of the CaP-code integrator module according to this embodiment is shown in FIG. 12. A CaP-code integrator 80 in accordance with one embodiment of the present invention consists of a low number of bits primary accumulator, e.g., a 9-bit two's complement primary accumulator 82 and a full number of bits secondary accumulator, e.g., a 22-bit two's complement secondary accumulator 84. In normal operation both accumulators 82, 84 will never overflow and no data will be lost between the primary and secondary accumulator. The following operational modes can be distinguished:
CA-mode: the CaP-code integrator 80 is configured to track CA-code modulated signals and behaves identically to the CA-code integrator module 70 described above. The primary accumulator 82 results are dumped at a rate equal to the CA-code chip rate into an integration buffer 83. The secondary accumulator 84 is configured to be an adder only and is always enabled.
Attitude determination mode: In attitude determination mode, the CaP-code integrator 80 is rest both on the IntEpoch and ASE strobe. This mode corresponds to the (P,P,Off) despreader mode.
P-mode: The CaP-code integrator 80 is configured to track P-code modulated signals. The only difference between the CA-mode and the P-mode is the control of the primary dump logic 81. The SecondaryEnable strobe controls the transfer of the primary accumulator contents to the secondary accumulator 84, while the WChipEdge strobe controls buffering and reset of the primary accumulator 82. The secondary accumulator 84 is configured to be an adder only and is always enabled (EnableSel is 0). The secondary accumulator integration buffers 85 are updated on the command of the IntEpoch strobe.
Y-mode: In the Y-mode, a signal is received which consists of a P-code modulated with an unknown W-code. An exact despreading is not possible, hence one embodiment of the invention estimates the W-code sufficiently to obtain the timing and phase data of the received signals. To decode such a signal, a W-code estimation capability is provided between the primary and secondary accumulator 82, 84 of a dual-frequency channel in accordance with one embodiment of the present invention, as shown schematically in FIG. 13. There are several modes in which the CA-P integrator module 80 can process W-coded and P-coded signals each of which is an embodiment of the present invention.
Generally, the primary accumulator 82L1, 82L2 of each channel L1 and L2 integrates the incoming data (possibly despread with the known P-code) over one W chip period (generated in the W-rate generator described later). Based on this result, the W-Code Estimation unit 86 estimates the corresponding value of the W-rate.
Codeless Squaring: Functionally the CaP-Code integrator 80 operates as a single adder which adds a sequence of samples over an IntEpoch period. This codeless squaring technique requires a circuit (not shown) that squares the incoming signal before the adding operations. Incoming samples which have not be despread by the locally generated P-code replica sequence are integrated in the primary accumulators 82L1, 82L2 over a time period, e.g. one W-code interval (assumed known) signaled by WchipEdge. The primary and secondary accumulators 82, 84 (82L1, 82L2; 84L1, 84L2) are configured in add mode and are always enabled. The secondary integration buffers 85 are updated on IntEpoch strobes.
Coded Squaring: Functionally the primary accumulator 82 operates as an adder which adds a sequence of despread (with a locally generated replica of the P-code) samples over one W-code interval signaled by WchipEdge. The secondary accumulator 84 operates as an adder which adds the absolute values of the primary accumulator 82. The secondary accumulator 84 is configured to add absolute primary accumulation values by selecting the SignInSec input bit (this is a kind of “squaring”). This bit is preferably the sign bit of the value from the Q-branch of the complex primary accumulator 82 which is processing the “punctual” code replica (P of E, P, L) of the first integrator 82 (this branch normally has the highest strength of the relevant signal but the present invention is not limited thereto). The secondary accumulator integration buffers 85 are updated on IntEpoch strobes.
Coded cross-correlation: Functionally the primary accumulator 82 operates as an adder which adds a sequence of despread (with a locally generated replica of the P-code) samples over one W-code interval signaled by WchipEdge. The secondary accumulator 84 operates as an adder which adds the primary values of an L1 (alternatively L2) channel multiplied by the sign bit of the L2 (alternative L1) primary accumulator. The secondary accumulator 84 is configured to add absolute primary accumulation values by selecting the SignInSec input bit. For an L1 (L2) channel this bit is the sign bit of the Q-branch of the complex primary accumulator value of the first integrator 82 of the L2 (L1) channel. The secondary accumulator 84 is enabled by the SecondaryEnable strobe generated by the P-code generator unit. The secondary accumulator integration buffers 85 are updated on IntEpoch strobes.
Combined Y-code estimate: In a further embodiment of the present invention, the primary accumulator 82 operates functionally as an adder which adds a sequence of despread (with a locally generated replica of the P-code) samples over one W-code interval signaled by WchipEdge. The secondary accumulator 84 operates as a combiner which combines the primary values of the primary accumulator 82 and the estimated W-code chip. One method of combining includes summing the values output by the primary accumulator 82 multiplied by the estimated W-code chip value. However, one embodiment of the present invention includes other methods of combining. For instance, one embodiment includes combining the outputs of the primary accumulator 82 in dependence upon a confidence level in each output from accumulator 82. The estimated W-code chip is obtained by comparing the absolute values of the primary accumulator of the Q-branch of the complex primary accumulator value of the first integrator 82 of the L1 and L2 channel. The estimated W-code chip value (or Y-code value) is the sign bit of the largest value from this comparison. Because of the lower transmit power, a scaling value may be applied to the L2 signal which is usually more powerful than the L1 signal. A value of 0.75 is suitable. The secondary accumulator integration buffers 85 are updated on IntEpoch strobes. FIG. 14 shows one embodiment of the selection logic required to provide the Y-code estimate indicated above. The outputs of the primary accumulators 82L1 and 82L2 for the L1 and L2 channels, respectively are applied to absolute value circuits 861, 862, respectively, whereas the sign of each of these primary accumulated outputs is transferred to a Y-code estimate selector (or W-code chip estimate selector) 865. In the absolute value circuits 861, 862 the absolute value of the respective primary accumulator value is determined. The absolute value output from circuit 862 may be modified to allow for received power differences between the L1 and L2 signals, e.g., it can be multiplied by a factor such as 0.75 (multiplier 864). The modified absolute values are input to a comparator 864 which compares the two absolute values and outputs a signal to a Y-code estimate selector 865 indicating which of the signals from L1 or L2 has the largest absolute value. The selector 865 selects the sign of the signal with the largest absolute value as the value for the W-code chip or, optionally, an alternative value. The optional alternative value may be zero, e.g., when the confidence in the result is low. The output for the Y-code estimate selector 865 is combined with each of the primary accumulated values of the L1 and L2 accumulators 82L1 and 82L2 for use in the secondary accumulators 84L1 and 84L2 respectively.
A P-code unit such as 42 in accordance with one embodiment of the present invention has two main functions: generating the replicas of the GPS and GLONASS P-code sequences for L1 and L2 and generating the W-code integration control strobe signals (WChipEdge) for L1 and L2. The latter is used for tracking the GPS Y-code signal with the coded squaring, the coded cross-correlation technique and other techniques described above particularly the combined Y-code estimate embodiment of the present invention. One P-code unit 42-45 is provided per dual-frequency channel.
The P-code sequence and the sequence of W-code integration control strobes are the same for L1 and L2 but with a relative delay due to different ionospheric and front-end group delays at the two frequencies L1 and L2. The total group delay difference between L1 and L2 does not exceed 1 microsecond. This delay is the sum of the maximum specified ionospheric group delay of 800 ns between L2 lagging L1 and 200 ns due to front-end group delays. L1 can only lag L2 due to different front-end group delays. Hence the total group delay between L1 and L2 can vary between −200 ns and 1 microsecond. A delay of 1 microsecond is equivalent to 10 GPS P-code chips or 5 GLONASS P-code chips, while 200 ns corresponds to 2 GPS P-code chips or 1 GLONASS P-code chip. These numbers are a factor of 10 lower for CA-code chips.
A P-code unit block diagram in accordance with an embodiment of the present invention is shown in FIG. 15. Its main modules are the P-code generator 92, the W-rate generator 94, the cycle difference counter and switch controller 96, the P-code and WChipEdge delay- lines 91, 93 and the sequence switches 95, 97, 99. The P-code generator 92 contains functionality for generating replicas of the GPS and GLONASS P-code sequences, P-code observables, and functionality to initialize the P code and perform P-code handover which controls the enabling of the P-code. Because both code sequences are delayed versions of the same code, a single P-code generator 92 and a single W-Rate generator 94 with additional delay-line 93, and control and switching logic is used to produce both sequences for L1 and L2. The lagging sequence is obtained from a delay- line 91, 93 controlled by the cycle difference counter 96 while the other is taken directly from the generator output which is the replica of the P-code and the W chip edge, respectively. The cycle difference counter 96 records the phase difference between the L1 P-code sequence and the L2 P-code sequence as an integer number of code chips. This phase difference is the same for the L1, L2 W chip edges. An initial difference is programmed by the microprocessor 101 and represents the relative delay of the L1 and the L2 sequences. It is the accurate determination of this difference which needs to be performed by the acquisition software. The switch control and the switches 95, 97, 99 enable the microprocessor 101 to select which of the two L1 or L2 sequences of P-code and W chip edges is lagging the other.
The GLONASS P-code is a binary sequence with a nominal chip rate of 5.11 MHz generated by the code NCO and a sequence duration of precisely one second. The P-code is the tenth tap of a 25-tap linear feedback shift register (LFSR) with generating polynomial defined as:
G _P=1+X ³ +X ²⁵
The code sequence is short-cycled to a length of 5,110,000 chips, this corresponds to the LFSR state of “0CBE669” hexadecimal. The initial state of the P-code generator is a vector of 25 ones. This state coincides with the one-second mark in the GLONASS navigation message.
The GPS P-code is a binary sequence with a nominal chip rate of 10.23 MHz generated by the code NCO and a sequence duration of precisely one week. The GPS P-code is a modulo-2 addition of two sequences, the X1 sequence and the X2 sequence. The code for SV is obtained by delaying the X2 sequence by chips prior to modulo-2 addition to the X1 sequence, where is a value ranging from 1 to 37. The X1 code is generated by the modulo-2 addition of two short-cycled maximum-length sequences, whose generating polynomials are defined as:
X1A=1+X ⁶ +X ⁸ +X ¹¹ +X ¹²
X1B=1+X ¹ +X ² +X ⁵ +X ⁸ +X ¹⁰ +X ¹¹ +X ¹²
The X1A sequence is short-cycled to a length of 4092, while the X1B sequence is short-cycled to a length of 4093. The X1 sequence has a period of 3750 X1A periods, which is equal to 15,345,000 P-code chips or 1.5 seconds. When the X1B LFSR completes its 3749th period it is halted for the duration of 343 chip periods (until the X1A LFSR completes its 3750th period). On completion of each X1 period both X1 LFSRs are reset to their initial states as defined in table 1. The X1 epoch indicates the end of each X1 period.
Similar to the X1 code, the X2 code is generated by the modulo-2 addition of two short-cycled maximum-length sequences, whose generating polynomials are defined as:
X2A=1+X ¹ +X ³ +X ⁴ +X ⁵ +X ⁷ +X ⁸ +X ⁹ +X ¹⁰ +X ¹¹ +X ¹²
X2B=1+X ² +X ³ +X ⁴ +X ⁸ +X ⁹ +X ¹²
The X2A sequence is short-cycled to a length of 4092, while the X2B sequence is short-cycled to a length of 4093. Similar to the X1 sequence, the X2 period contains 3750 X2A periods. When the X2B LFSR completes its 3749th period it is initially halted for the duration of 343 P-code chip periods. When the X2A LFSR completes its 3750th period it is also halted. Subsequently, both X2A and X2B LFSRs are halted for a further duration of 37 P-code chip periods, causing the X2 period to be 37 chip periods longer than the X1 period. After this delay, the X2A and X2B LFSRs are reset to the initial states shown in Table 1.

TABLE 1

LFSR initial state

X1A 001001001000

X1B 010101010100

X2A 100100100101

X2B 010101010100
The Z counter which is located in the P-code units such as 42, is a 19-bit counter with a valid range of 0 to 403,199 (period of 403,200). This counter counts the number of elapsed X1 epochs since the start of the week, commonly referred to as the Z count. In its final state the Z counter signals End Of Week (EOW). During the last X1A period of a week, and after reaching their final state, the X1B, X2A and X2B generators will be halted until the X1A generator reaches its final state. The final X1A epoch causes all generators to be restarted from their respective initial states and the Z count to be reset to 0.
When the initialization process of the P-code generator 92 is triggered, the X1 generator is initialized to the initial states shown in table 1. To establish the correct relative phase between the X1 and X2 sequences corresponding to the programmed Z count, the X1 generator is automatically clocked for 37 times the Z count. After the X1 generator reaches its correct state the X2 generator is initialized to the initial states shown in table 1. Subsequently, both generators are clocked until the occurrence of an X1 epoch and then halted. This initialization process takes a number of cycles equivalent to exactly a full X1 period of 1.5 s, i.e., 15,345,000 cycles.
After the P-code generator 92 has been initialized the P-code handover starts the generation of a P-code sequence at the correct time instance. This mechanism requires hardware-firmware interaction. After initialization, the P-code generator 92 should not be enabled until the first bit of the preamble of the next subframe has been received. As decoding of the navigation data is a firmware task, this event must be signaled by the firmware. The P-code generator 92 is then enabled on the following active IntEpoch. After hand-over the setting is automatically reset.
The P-code observable is used to find a high-precision pseudorange. It is obtained from a 24-bit counter, which counts the number of P-code chips. It is reset after reaching a count equal to the nominal number of P-code chips per second for GLONASS and per 1.5 seconds for GPS. This number is equal to 5,110,000 GLONASS P-code chips or 15,345,000 GPS P-code chips. At the end of each measurement epoch the P-code chip count is stored in an observable register. The P-code chip counter is reset at P-code hand-over.
The W-rate generator 94 generates the control strobes for dumping the primary accumulator stages of the CaP-integrator modules 80. It is a programmable 5-bit decrementer which counts P-code chips. Each time the decrementer reaches 0, a WChipEdge strobe is generated and the decrementer is reloaded. M strobes are generated with a period of A P-code chips followed by N strobes at a rate of B P-code chips. The sequence is repeated until an X1A-epoch, generated by the P-code generator. The start of a new sequence can be delayed by S P-code chips.
The cycle difference counter 96 is a 5-bit counter that keeps track of the delay between the L1 and L2 P-codes, expressed in P-code chips. In conjunction with the variable delay- line 91, 93, it derives a delayed version of a P-code sequence. Similar to the P-code, L1 and L2 W-code chip edges are generated from a single W rate generator 94. The switch controller 96 keeps track of which sequence L1 or L2 is lagging the other. The change in phase difference is further controlled indirectly by programming the frequency and phase of the code NCO's driving the P-code generator 92, which are the clock signals triggering the cycle difference counter and the switch controller 96. When the L1 code NCO (not shown, located in the CA-Code generators) produces a clock pulse a programmable counter is incremented and when the L2 code NCO products a clock pulse it is decremented. When both NCOs generate a clock pulse the counter is inhibited. To prevent incorrect control of the delay- line 91, 93 the cycle difference counter is inhibited when it reaches its maximum delay of 10.
Due to front-end group delay differences between the L1 and L2 RF sections, the L2 P-code may lead the L1 P-code. Therefore, it is possible to delay the L1 P-code relative to the L2 P-code by interchanging the L1 and L2 inputs and associated outputs whenever the L1-L2 delay crosses zero. This functionality is controlled by the switch controller 96 and the associated switches 95, 97. The use of delay line 91 with only delayed timings and the switch 95 to switch between the L1 and L2 signals reduces the size of delay line 91 compared to conventional designs which is a significant advantage compared with the correlator known from EP 508 621.
The cycle difference counter 96 is programmed on an IntEpoch strobe. The value of the cycle difference counter 96 is an observable which is stored at the end of each measurement interval, i.e., at the same time as the other code and carrier phase observable registers. The L1-L2 delay observable is obtained by summing the contents of this observable and the difference of the L1 and L2 code NCO phase registers.
In each P-code unit 90, there is one P-code delay line 91 and one W-rate delay line 93 of length 10. Both delay lines 91, 93 are clocked by the chip rate of the leading sequence shifting the bits in the delay- line 91, 93 similar to a first-in-first-out buffer. Its input is a P-code chip for the P-code delay line 91 and a W-edge for the W-rate delay line 93. The output is a tap of 1 to 10 controlled by the cycle difference counter 96. A cycle difference counter value of zero selects the input of the delay line 91, 93.
While the above description has pointed out novel features of the invention as applied to various embodiments, the skilled person will understand that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made without departing from the scope of the invention. Therefore, the scope of the invention is defined by the appended claims rather than by the foregoing description. All variations coming within the meaning and range of equivalency of the claims are embraced within their scope.

Claims

1. A method of processing received L1 and L2 spread spectrum signals, wherein each of the signals includes a unique frequency carrier with a known pseudo-random code modulated thereon, each L1 and L2 signal being converted into a plurality of digital signals, the method comprising:

locally generating a single replica of the known code;

making the code replica available at different relative phases;

first demodulating the converted L1 and L2 signals with the single replica of the known code without any substantial delay, the first demodulated signal being associated with the L1 signal;

second demodulating the converted L1 and L2 signals with the generated replica of the known code from one of the taps of the delay line, the second demodulated signal being associated with the L2 signal;

selectably switching the converted L1 and L2 signals for the first demodulation and selectably switching the converted L1 and L2 signals for the second demodulation;

repetitively and separately integrating the demodulated L1 and L2 signals over a time period; and

adjusting the phases of the locally generated code replicas relative to the incoming L1 and L2 signals in order to maximize the power of the integrated demodulated L1 and L2 signals.

2. The method according to claim 1, wherein the resulting locally generated code phases are useable to determine information of the location of a receiving position with high accuracy.

3. The method according to claim 1, wherein the frequency carriers are also modulated with an unknown code and the phase adjustment includes:

correlating an integration result for one of the L1 and L2 signals with an integration result for the other of the L1 and L2 signals; and

adjusting the phases of the locally generated known code replicas relative to the incoming L1 and L2 signals in order to maximize the power of the correlated L1 and L2 signals, wherein the resulting locally generated known code phases are useable to determine information of the location of a receiving position.

4. The method according to claim 1, wherein the integrating of the demodulated L1 and L2 signals comprises:

first integrating the demodulated signals over a first predetermined period of time; and

second integrating the first integrated signals over a second predetermined period of time longer than the first predetermined period of time.

5. The method according to claim 1, wherein the received L1 and L2 spread spectrum signals are received from at least one of a Global Positioning System (GPS) and Global Orbiting Navigation Satellite System (GLONASS).

6. An apparatus for processing received L1 and L2 spread spectrum signals, wherein each of the signals includes a unique frequency carrier with a known pseudo-random P-code and an unknown code modulated thereon, the apparatus comprising:

a generator of replicas of the known P-code;

a delay line configured to make the known P-code replicas available at different relative phases;

a first demodulator, connected to the generator, configured to demodulate one of the received L1 and L2 signals with one of the known P-code replicas;

a second demodulator configured to demodulate the other of the received L1 and L2 signals with one of the known P-code replicas;

a first integrator configured to repetitively and separately integrate the demodulated one of the L1 and L2 signals over time periods related to the unknown code;

a second integrator configured to repetitively and separately integrate the demodulated other of the L1 and L2 signals over time periods related to the unknown code; and

a correlator configured to correlate the first integrator output with the second integrator output.

7. The apparatus according to claim 6, wherein the correlator includes:

a comparator configured to compare the absolute values of the integrated demodulated L1 and L2 signals;

a combiner configured to individually combine the values of the integrated demodulated L1 and L2 signals with a unitary value having the largest value as output by the comparator;

a first accumulator configured to individually and separately accumulate the combined values for the demodulated one of the L1 and L2 signals; and

a second accumulator configured to individually and separately accumulate the combined values for the demodulated other of the L1 and L2 signals.

8. The apparatus according to claim 7, further comprising a phase adjuster configured to adjust the phases of the locally generated P-code replicas relative to the incoming L1 and L2 signals in order to maximize the power of the correlated L1 and L2 signals.

9. The apparatus according to claim 7, wherein the combiner comprises a multiplier.

10. The apparatus according to claim 7, wherein the first accumulator operates functionally as an adder and the second accumulator operates as a combiner.

11. The apparatus according to claim 6, wherein the apparatus is for use with at least one of a Global Positioning System (GPS) and Global Orbiting Navigation Satellite System (GLONASS).

12. An apparatus for processing received L1 and L2 spread spectrum signals, wherein each of the signals includes a unique frequency carrier with a known pseudo-random code modulated thereon, each L1 and L2 signal being converted into a plurality of digital signals, the apparatus comprising:

a generator configured to locally generate a single replica of the known code;

a delay line wherefrom the known P-code replicas are available at different relative phases thereof, wherein the single replica of the known code is applied to the delay line;

a first demodulator configured to first demodulate the converted L1 and L2 signals with the single replica of the known code without any substantial delay, the first demodulated signal being associated with the L1 signal;

a second demodulator configured to second demodulate the converted L1 and L2 signals with the generated replica of the known code from one of the taps of the delay line, the second demodulated signal being associated with the L2 signal;

a switch configured to selectably switch the converted L1 and L2 signals for the first demodulation and selectably switch the converted L1 and L2 signals for the second demodulation;

an integrator configured to repetitively and separately integrate the demodulated L1 and L2 signals over a time period; and

a phase adjuster configured to adjust the phases of the locally generated code replicas relative to the incoming L1 and L2 signals in order to maximize the power of the integrated demodulated L1 and L2 signals.

13. A method of processing received L1 and L2 spread spectrum signals, wherein each of the signals includes a unique frequency carrier with a known pseudo-random P-code and an unknown code modulated thereon, the method comprising:

locally generating replicas of the known P-code;

making the code replicas available at different relative phases;

demodulating the received L1 and L2 signals with replicas of the P-code;

repetitively and separately integrating the demodulated L1 and L2 signals over time periods related to the unknown code; and

correlating an integration result for one of the L1 and L2 signals with an integration result for the other of the L1 and L2 signals.

14. The method according to claim 13, further comprising adjusting the phases of the locally generated P-code replicas relative to the incoming L1 and L2 signals in order to maximize the power of the correlated L1 and L2 signals.

15. The method according to claim 14, wherein the correlating comprises:

comparing the absolute values of the integrated demodulated L1 and L2 signals;

individually combining the values of the integrated demodulated L1 and L2 signals with a unitary value having the largest value as determined in the comparing; and

individually and separately accumulating the combined values.

16. The method according to claim 15, wherein the combining comprises multiplying.

17. The method according to claim 13, wherein the received L1 and L2 spread spectrum signals are received from at least one of a Global Positioning System (GPS) and Global Orbiting Navigation Satellite System (GLONASS).

18. The method according to claim 13, wherein the resulting locally generated P-code phases are useable to determine information of the location of a receiving position.

19. A system for processing received L1 and L2 spread spectrum signals, wherein each of the signals includes a unique frequency carrier with a known pseudo-random code modulated thereon, each L1 and L2 signal being converted into a plurality of digital signals, the system comprising:

means for locally generating a single replica of the known code;

means for making the code replica available at different relative phases;

means for first demodulating the converted L1 and L2 signals with the single replica of the known code without any substantial delay, the first demodulated signal being associated with the L1 signal;

means for second demodulating the converted L1 and L2 signals with the generated replica of the known code from one of the taps of the delay line, the second demodulated signal being associated with the L2 signal;

means for selectably switching the converted L1 and L2 signals for the first demodulation and selectably switching the converted L1 and L2 signals for the second demodulation;

means for repetitively and separately integrating the demodulated L1 and L2 signals over a time period; and

means for adjusting the phases of the locally generated code replicas relative to the incoming L1 and L2 signals in order to maximize the power of the integrated demodulated L1 and L2 signals.