US20060108667A1 - Method for manufacturing a small pin on integrated circuits or other devices - Google Patents
Method for manufacturing a small pin on integrated circuits or other devices Download PDFInfo
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- US20060108667A1 US20060108667A1 US11/285,525 US28552505A US2006108667A1 US 20060108667 A1 US20060108667 A1 US 20060108667A1 US 28552505 A US28552505 A US 28552505A US 2006108667 A1 US2006108667 A1 US 2006108667A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/068—Patterning of the switching material by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
- H10N70/8265—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices on sidewalls of dielectric structures, e.g. mesa or cup type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/50—Resistive cell structure aspects
- G11C2213/52—Structure characterized by the electrode material, shape, etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
Definitions
- the present invention relates to methods for manufacturing integrated circuits and other devices, and more particularly to methods for making very small pin-shaped structures.
- phase change materials can be caused to change phase by application of electrical current. This property has generated interest in using phase change materials to form nonvolatile memory circuits.
- phase change memory cell in which the phase change element comprises a side wall on an electrode/dielectric/electrode stack.
- Data is stored by causing transitions in the phase change material between amorphous and crystalline states using current. Current heats the material and causes transitions between the states.
- the change from the amorphous to the crystalline state is generally a lower current operation.
- the change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from crystalline state to amorphous state.
- the magnitude of the reset current needed for reset can be reduced by reducing the size of the phase change material element in the cell and of the contact area between electrodes and the phase change material.
- the present invention includes methods to form a narrow side wall spacer or pin.
- a method of forming a memory cell based on such a narrow side wall spacer or pin is described which comprises forming a stack comprising a first electrode, an insulating layer over the first electrode, and a second electrode over the insulating layer, with a side wall on at least the insulating layer of the stack.
- a side wall spacer comprising a programmable resistive material in electrical communication with the first and second electrodes is formed.
- the side wall spacer has a length extending from the first electrode to the second electrode along the side wall, a width generally orthogonal to the length, and a thickness determined by the thickness of a layer of programmable resistive material used to form the side wall spacer.
- the side wall spacer is formed by depositing a layer of programmable resistive material over the side wall of the stack, anisotropically etching the layer of programmable resistive material to remove it in areas away from the side wall, and selectively etching the programmable resistive material according to a pattern to define the width of the side wall spacer.
- the width is less than 50 nanometers, and more preferably about 40 nanometers or less.
- one technique includes forming an etch mask having a lithographic pattern to define a lithographic width, and then trimming the etch mask to provide a trimmed mask to define the pattern used for defining the width of the side wall spacer.
- the etch mask comprises a photoresist, which is etched anisotropically to form the trimmed mask using an oxygen based plasma etch.
- the etch mask comprises a hard mask defined using a lithographic process, which is etched to reduce its width to form the trimmed mask.
- the three dimensions that define the size of the active region in the phase change pin for the cell described herein are preferably less than 50 nanometers, and can all be less than the minimum feature size of the lithographic process applied to make the cell.
- the dimensions are defined in technology described herein, by the thin film thickness of phase change material, the inter-electrode dielectric thin film thickness, and the trimmed mask.
- the cell size (the volume of the phase change material) is very small (smaller than F 3 , where F is the minimum lithographic feature size for the process used to manufacture the memory cell).
- the resulting cell of phase change material comprises a narrow pin on the side wall of an electrode stack.
- the contact area between at least one of the top and bottom electrodes and the phase change material pin is also defined sub-lithographically by electrode layer thicknesses for the heights, and the photo-resist pattern trimming process for the width of the contacts.
- the small cell and small contact region allow implementation of a memory with very small reset current and low power consumption.
- a memory device includes a stack including a first electrode, an inter-electrode insulating member over the first electrode, and a second electrode over the inter-electrode insulating member.
- the stack has a side wall over at least the insulating member.
- a spacer comprising programmable resistive material on the side wall is in electrical communication with the first and second electrodes.
- the spacer has a length extending from the first electrode to the second electrode along the side wall on the insulating layer, which is generally orthogonal to the length and a thickness.
- the width and thickness of the spacer are less than 40 nanometers in embodiments of the technology described herein.
- the programmable resistive material comprises a phase change material, which is reversibly programmable.
- phase change material pin can be used to make a very small pin for other nano-technology uses on an integrated circuit or other device, using materials other than phase change materials, like metals, dielectrics, organic materials, semiconductors, and so on.
- the small dimension side wall pin can be formed on structures other than that used for the phase change memory cell described herein, such as structures comprising other types of stacks of thin films, such as stacks of thin film dielectrics, with and without an electrode layer for contact to the pin.
- FIG. 1 illustrates an embodiment of a side wall active pin phase change memory element.
- FIG. 2 is a schematic diagram for a memory array comprising phase change memory elements.
- FIG. 3 is a block diagram of an integrated circuit device including a thin film fuse phase change memory array and other circuitry.
- FIG. 4 is a cross-section of the final array structure for an embodiment of the invention.
- FIG. 5 is a cross-section of the structure after front-end-of-line processing and formation of electrode stack thin film layers.
- FIG. 6A and FIG. 6B show top and cross-sectional views respectively after electrode stack etching the structure from FIG. 5 .
- FIG. 7 shows phase change material thin film deposition on the structure of FIG. 6B .
- FIG. 8A and FIG. 8B show top and cross-sectional views respectively after GST thin film spacer etching.
- FIG. 9 shows a cross-sectional view after dielectric fill layer formation.
- FIG. 10 shows a cross-sectional view after chemical mechanical polishing for planarization and exposure of the phase change material side wall.
- FIG. 11 shows a top view after formation of a photoresist pattern, and trimming for definition of phase change side wall pin width.
- FIG. 12A and FIG. 12B show top and cross-sectional views respectively after selective etching of the phase change material side wall to define a phase change side wall pin width dimension.
- FIG. 13 shows a top view after removal of the photoresist, with the resulting phase change material side wall pin.
- FIG. 14 shows a cross-sectional view after filling in the small seam left by removal of the phase change material side wall, and subsequent oxide deposition.
- FIG. 15 shows top and cross-sectional views after via formation and metallization for definition of the bit lines.
- FIG. 16 illustrates an embodiment in which the thin film phase change material side wall is partially etched.
- FIG. 17 illustrates a first stage in a representative process for manufacturing a small pin on an integrated circuit.
- FIG. 18 illustrates a second stage in a representative process for manufacturing a small pin on an integrated circuit.
- FIG. 19 illustrates a third stage in a representative process for manufacturing a small pin on an integrated circuit.
- FIG. 20 illustrates a fourth stage in a representative process for manufacturing a small pin on an integrated circuit.
- FIGS. 21 and 22 illustrate cross-section and perspective views, respectively, of a fifth stage in a representative process for manufacturing a small pin on an integrated circuit.
- FIG. 23 illustrates a sixth stage in a representative process for manufacturing a small pin on an integrated circuit.
- FIG. 24 illustrates a seventh stage in a representative process for manufacturing a small pin on an integrated circuit.
- FIG. 25 illustrates an eighth stage in a representative process for manufacturing a small pin on an integrated circuit.
- FIG. 26 illustrates a small pin on made as described herein.
- FIG. 1 is a perspective view of a side wall active pin memory cell 10 .
- the cell includes a narrow side wall spacer, referred to as a pin 5 on a side wall of an electrode stack that includes a thin film electrode 6 , and a thin film electrode 7 separated by an inter-electrode dielectric layer 8 .
- a dielectric 9 overlies the electrode stack in the illustrated embodiment.
- the pin 5 consists of a programmable resistive material, such as a phase change material.
- the pin 5 has an active region, within which the phase change is confined, with a length L between a first electrode 6 and a second electrode 7 which is determined by the thickness of the inter-electrode dielectric layer 8 .
- the active region of the pin 5 has a thickness T determined by the thickness of a thin film formed on the side wall of the electrode stack.
- the electrode stack is made using a photolithographic process or other type of lithographic process so that its width is about equal to the minimum feature size specified for the lithographic process.
- the width W of the electrode stack may be on the order of 90 nanometers.
- the active region of the pin 5 has a width which is less than the minimum feature size for the lithographic process used to define the electrode stack. In embodiments described herein, the width of the active region of the pin 5 is about 40 nanometers or less.
- the active region of the pin 5 has a length L defined by a thin film thickness of the inter-electrode dielectric 8 , which in embodiments of the invention can range between about 20 and 50 nanometers.
- the active region of the pin 5 has a thickness T which is defined by the thin film thickness of the material used to form the side wall pin, which in embodiments of the invention can range between about 10 and 50 nanometers. Accordingly, all three dimensions of the pin 5 are less than 50 nanometers in embodiments of the present invention, and more preferably about 40 or less nanometers.
- the programmable resistive material comprises a phase change material, such as Ge 2 Sb 2 Te 5 or other materials described below.
- the volume of material within the pin 5 in which the phase change is induced in the structure illustrated in FIG. 1 , is therefore very small.
- the volume of the active region is less than 64 ⁇ 10 ⁇ 24 m 3 . Accordingly, the magnitude of the reset current required for changing the phase is very small.
- Embodiments of the memory cell include phase change based memory materials, including chalcogenide based materials and other materials, for the side wall pin 5 .
- Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VI of the periodic table.
- Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical.
- Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals.
- a chalcogenide alloy usually contains one or more elements from column six of the periodic table of elements, such as germanium (Ge) and tin (Sn).
- chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag).
- Sb antimony
- Ga gallium
- In indium
- silver silver
- phase change based memory materials include alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S.
- compositions can be workable.
- the compositions can be characterized as Te a Ge b Sb 100 ⁇ (a+b) , where a and b represent atomic percentages that total 100% of the atoms of the constituent elements.
- One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te.
- Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%.
- a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties.
- chromium (Cr) iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof
- Ge/Sb/Te chromium
- Specific examples of memory materials that may be useful are given in Ovshinsky '112 at columns 11-13, which examples are hereby incorporated by reference.
- Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These phase change materials are at least bistable.
- amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase.
- crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase.
- phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states.
- Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy.
- the material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states.
- the electrical properties in the material may vary accordingly.
- Phase change materials can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined empirically, without undue experimentation, specifically adapted to a particular phase change alloy.
- phase change material is referred to as GST, and it will be understood that other types of phase change materials can be used.
- a material useful for implementation of a memory cell as described herein is Ge 2 Sb 2 Te 5 .
- programmable resistive material like a phase change material
- the material having a resistance which is programmable, and preferably in a reversible manner such as by having at least two solid phases that can be reversibly induced by electrical current. These at least two phases include an amorphous phase and a crystalline phase. However, in operation, the programmable resistive material may not be fully converted to either an amorphous or crystalline phase. Intermediate phases or mixtures of phases may have a detectable difference in material characteristics. The two solid phases should generally be bistable and have different electrical properties.
- the programmable resistive material may be a chalcogenide material.
- a chalcogenide material may include GST. Alternatively, it may be one of the other phase change materials identified above.
- FIG. 2 is a schematic illustration of a memory array, which can be implemented as described herein.
- a common source line 28 , a word line 23 and a word line 24 are arranged generally parallel in the Y-direction.
- Bit lines 41 and 42 are arranged generally parallel in the X-direction.
- a Y-decoder and a word line driver in block 45 are coupled to the word lines 23 , 24 .
- An X-decoder and a set of sense amplifiers in block 46 are coupled to the bit lines 41 and 42 .
- the common source line 28 is coupled to the source terminals of access transistors 50 , 51 , 52 and 53 .
- the gate of access transistor 50 is coupled to the word line 23 .
- the gate of access transistor 51 is coupled to the word line 24 .
- the gate of access transistor 52 is coupled to the word line 23 .
- the gate of access transistor 53 is coupled to the word line 24 .
- the drain of access transistor 50 is coupled to the bottom electrode member 32 for side wall pin memory cell 35 , which has top electrode member 34 .
- the top electrode member 34 is coupled to the bit line 41 .
- the drain of access transistor 51 is coupled to the bottom electrode member 33 for side wall pin memory cell 36 , which has top electrode member 37 .
- the top electrode member 37 is coupled to the bit line 41 .
- Access transistors 52 and 53 are coupled to corresponding side wall pin memory cells as well on bit line 42 .
- the common source line 28 is shared by two rows of memory cells, where a row is arranged in the Y-direction in the illustrated schematic.
- the access transistors can be replaced by diodes, or other structures for controlling current flow to selected devices in the array for reading and writing data.
- FIG. 3 is a simplified block diagram of an integrated circuit according to an embodiment of the present invention.
- the integrated circuit 74 includes a memory array 55 implemented using side wall active pin phase change memory cells, on a semiconductor substrate.
- a row decoder 56 is coupled to a plurality of word lines 62 , and arranged along rows in the memory array 55 .
- a column decoder 63 is coupled to a plurality of bit lines 64 arranged along columns in the memory array 55 for reading and programming data from the side wall pin memory cells in the array 55 . Addresses are supplied on bus 58 to column decoder 63 and row decoder 56 .
- Sense amplifiers and data-in structures in block 59 are coupled to the column decoder 63 via data bus 67 .
- Data is supplied via the data-in line 71 from input/output ports on the integrated circuit 75 or from other data sources internal or external to the integrated circuit 75 , to the data-in structures in block 59 .
- other circuitry is included on the integrated circuit, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the thin film fuse phase change memory cell array.
- Data is supplied via the data-out line 72 from the sense amplifiers in block 59 to input/output ports on the integrated circuit 75 , or to other data destinations internal or external to the integrated circuit 75 .
- a controller implemented in this example using bias arrangement state machine 69 controls the application of bias arrangement supply voltages 68 , such as read, program, erase, erase verify and program verify voltages.
- the controller can be implemented using special-purpose logic circuitry as known in the art.
- the controller comprises a general-purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device.
- a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller.
- FIG. 4 depicts a cross-section of a plurality of side wall active pin phase change random access memory cells 100 - 103 .
- the cells 100 - 103 are formed on a semiconductor substrate 110 .
- Isolation structures such as shallow trench isolation STI dielectric trenches 111 and 112 isolate pairs of rows of memory cell access transistors.
- the access transistors are formed by common source region 116 in the substrate 110 , and drain regions 115 and 117 in the substrate 110 .
- Polysilicon word lines 113 and 114 forms the gates of the access transistors.
- the dielectric fill layer 118 is formed over the polysilicon word lines 113 , 114 .
- Contact plug structures 141 and 120 contact individual access transistor drains, and common source line 119 contacts source regions along a row in the array.
- the common source line 119 contacts the common source region 116 .
- the plug structure 120 contacts a bottom electrode 121 of cell 101 .
- the cell 101 like cells 100 , 102 and 103 , includes a thin film bottom electrode 121 , a thin film inter-electrode dielectric layer 122 , a thin film top electrode 123 , and a side wall pin 124 comprising GST or another phase change material.
- a dielectric fill layer 127 overlies the cells 100 - 103 .
- Tungsten plug 126 contacts the top electrode 123 .
- a patterned metal layer providing contacts 129 , 130 , 131 , 132 overlies the dielectric fill layer 127 .
- contacts 129 - 132 are part of a single bit line extending to decoding circuits as can be seen with reference to FIG. 2 .
- a thin oxide layer 125 is shown overlying the top electrode 123 .
- the layer 125 is used for process margin as described below.
- the patterned metal layer comprises copper metallization.
- Other types of metallization including aluminum and aluminum alloys, could be utilized as well.
- the top and bottom electrodes (e.g. 121 , 123 ) comprise TiN or TaN with a thickness of 10 to 30 nm.
- the electrodes may be TiAlN or TaAlN, or may comprise one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, Ru and O.
- the inter-electrode insulating layer may be silicon oxide, silicon oxynitride, silicon nitride, Al 2 O 3 , other low K dielectrics, or an ONO or SONO multi-layer structure.
- the inter-electrode insulating layer may comprise one or more elements selected from the group consisting of Si, Ti, Al, Ta, N, O, and C.
- the inter-electrode thickness may be 10 to 200 nm, and more preferably 50 nanometers or less.
- the second electrode may be TiN or TaN.
- FIG. 5 illustrates a structure 99 after front-end-of-line processing, forming the standard CMOS components in the illustrated embodiment corresponding to the word lines, the source line, and the access transistors in the array shown in FIG. 2 .
- source line 119 overlies doped region 116 in the semiconductor substrate, where the doped region 116 corresponds with the source terminal of a first access transistor on the left in the figure, and of a second access transistor on the right in the figure.
- the source line 119 extends to the top surface of the structure 99 .
- the source line does not extend all the way to the surface.
- Doped region 115 corresponds with the drain terminal of the first access transistor.
- Dielectric layer 118 overlies the polysilicon word line 113 .
- Plug 120 contacts doped region 115 , and provides a conductive path to the surface of the structure 99 for contact to a memory cell electrode as described below.
- the drain terminal of the second access transistor is provided by doped region 117 .
- a word line including polysilicon line 114 , and the silicide cap (not shown) acts as the gate for the second access transistor.
- Plug 141 contacts doped region 117 and provides a conductive path to the top surface of the structure 99 for contact to a memory cell electrode as described below.
- Isolation trenches 111 and 112 separate the two-transistor structure coupled to the plugs 120 and 141 , from adjacent two-transistor structures.
- the structure 99 illustrated in FIG. 5 provides a substrate for formation of memory cell components, as described in more detail below.
- a multilayer, thin film structure is formed including bottom electrode thin film 150 , top electrode thin film 152 , inter-electrode dielectric 151 , and protective top dielectric 153 .
- the bottom electrode film 150 has a thickness less than 50 nanometers, and preferably in the range of 10 to 30 nanometers.
- the top electrode film 152 has a thickness less than 50 nanometers, and preferably in the range of 10 to 30 nanometers, and can be different than that of the bottom electrode film.
- the thickness of the top electrode film 152 can be slightly greater than that of the bottom electrode, in order to improve process margin for reliable contacts using tungsten plug technology and the like.
- the top dielectric 153 provides process margin for use of chemical mechanical polishing for planarization, variations in side wall spacer etching, and the like. Alternative embodiments without the top dielectric 153 might be implemented.
- FIG. 6A shows a mask pattern in top view including a first rectangle 155 and a second rectangle 156 for etching the multilayer thin film structure of FIG. 5 , to form the electrode stacks 60 , 65 , as shown in cross-section in FIG. 6B .
- the electrode stack 60 includes the bottom electrode 121 , inter-electrode dielectric 122 , and the top electrode 123 .
- the electrode stack 60 has side wall 61 .
- the electrode stack 65 has side wall 66 .
- Reactive ion etching REI is utilized in order to establish side walls 61 , 66 as vertical as possible.
- the reactive ion etching RIE may over-cut into the dielectric fill layer 118 . In a representative process the over-cut is about 20 nanometers. BCl 3 and/or Cl 2 based recipes for the processes can be used.
- FIG. 7 illustrates a structure after depositing, by sputtering for example, a conformal layer 170 of GST, or other programmable resistive material, over the stacks 60 , 65 .
- GST can be deposited using sputtering without collimation at about 250 degrees C. This results in a thin film having a thickness on the top of the electrode stacks of about 60 to 80 nanometers, a thickness on the side walls of about 20 to 30 nanometers, and a thickness between the stacks of about 60 to 80 nanometers, when using Ge 2 Sb 2 Te 5 as the phase change material.
- Various embodiments of the process can sputter the entire wafer to thickness of 40 to 100 nanometers on the flat surfaces.
- FIG. 8A illustrates the results of side wall etching in plan view, by an etching processes which remove the GST layer from the flat surfaces, and leave side walls 171 on stack 60 and side walls 172 on stack 65 , completely surrounding the stacks 60 , 65 .
- Anisotropic Cl 2 and/or BCl 3 recipe RIE processes can be used.
- FIG. 8B shows the side walls 171 and 172 in cross-section. The side walls have tops slightly below the surface of the top dielectric layer 160 , due to slight over-etching to ensure total removal from the surface 173 of the structure 99 .
- FIG. 9 illustrates a dielectric fill-in process.
- the process involves formation of a low-temperature liner oxide, a silicon nitride layer or silicon oxide layer (not shown), using a process temperature less than about 200 degrees C., over the phase change material side walls.
- One suitable process is to apply silicon dioxide using plasma enhanced chemical vapor deposition PECVD.
- the dielectric fill 180 is implemented using a higher temperature process such as high-density plasma HDP CVD of silicon dioxide or other similar material.
- an oxide chemical mechanical polishing CMP process is applied to planarize the structure, and to expose the tops 181 , 182 of the GST side walls 171 , 172 .
- the top dielectric layer on the electrode stack ensures that the CMP does not touch the top electrode material, such as TiN, and protects it from following RIE processes or other etching steps.
- FIG. 11 illustrates photoresist pattern trimming for the purpose of forming a sub-lithographic mask to trim the side walls 171 , 172 .
- a photo resist pattern is formed using lithographic techniques involving transferring a pattern from a mask or set of masks to the photoresist layer, including a rectangular extension 185 over the stack 60 and a rectangular extension 186 over the stack 65 as shown in dotted line outline.
- the width W 1 of the extensions 185 , 186 after development of the photoresist, is close to the minimum feature size for the lithographic process utilized to form the pattern extension 185 , 186 .
- the width W 1 of the extensions 185 , 186 is reduced to sub-lithographic width W 2 by photoresist trimming to leave a narrow trimmed mask 187 , 188 .
- the photoresist is etched anisotropically using an oxide plasma to trim the width and thickness of the patterned photoresist, down to a width W 2 less than 50 nanometers in exemplary embodiments, and to width W 2 of for example about 40 nanometers in a 0.2 micron (200 nanometer) minimum feature size lithographic process environment.
- a hard mask layer (not shown), such as a low temperature deposited layer of SiN or SiO 2 , can be put between the photoresist pattern and the surface of the stacks 60 , 65 , to prevent etching damage of the cell, if the photoresist is not thick enough after the trimming process, or selective etching of the GST and the hard mask is improved by the hard mask.
- FIG. 12A illustrates side wall cell width etching in plan view according to the trimmed mask 187 , 188 , using for example a chlorine based reactive ion etch so that the dielectric fill 180 is not etched.
- the etch removes the exposed GST, leaving a narrow side wall pin 124 shown in cross-section in FIG. 12B , on the electrode stack.
- a seam 190 around the stack 60 and the stack 65 is left in the dielectric layer 180 , which preferably extends to the top surface 173 of the structure 99 with complete removal of the GST.
- all the GST in the seam 190 need not be removed. Rather it is sufficient that a significant portion of the GST in the seam 190 is removed, so that current between the bottom and top electrodes is concentrated in a narrow pin on the inter-electrode dielectric layer of the stack.
- FIG. 13 illustrates the next step in the process in plan view, which involves removal of the trimmed photoresist mask ( 187 , 188 ) and hard mask layer (if any).
- the side wall pin 124 on stack 60 and side wall pin 124 A on stack 65 have a sub-lithographic width W on the order of 40 nanometers or less in embodiments of the process.
- FIG. 14 illustrates the small seam fill-in and oxide deposition step.
- the small seams 190 ( FIG. 13B ) left by the removal of the side walls can be filled with electrical and/or thermally insulating fills 193 , 194 , using atomic layer deposition.
- atomic layer deposition is used to deposit dielectric material such as AlO 2 , HfO 2 and the like.
- the seams can be filled by spin coating silicon oxide using inorganic spin on glass or “low K” material.
- the seams are sealed to form a void that is substantially evacuated, to provide good thermal isolation for the cells.
- a top oxide deposition covers the electrode stacks with a layer 195 of dielectric, which is planarized in preparation for subsequent metallization.
- the top oxide layer is preferably formed by PECVD, or other lower temperature process.
- FIG. 15 shows via formation and metallization for bit lines and contacts to the memory cells.
- Vias are etched in the layer 195 and filled with tungsten or other conductor material to form plugs 196 and 197 making contact to the top electrode layer 123 in stack 60 and top electrode layer 123 A in stack 65 .
- a patterned metal layer 198 provides bit lines extending in the plane of the drawing to decoding circuits.
- the plugs 120 and 141 provide contacts between the respective bottom electrodes of the stacks 60 and 65 , to the drains 115 and 117 of the access transistors.
- the word lines 113 , 114 are formed by the polysilicon gates on the access transistors.
- the common source doped region 116 , and source line 119 provides for sensing current flow from the bit lines through the memory cells, to the access transistor and down the common source line.
- FIG. 16 shows a cross-section of an electrode stack, such as stack 60 , after deposition of the GST layer side wall etching, in an alternative embodiment, in which the GST layer is only partially etched around the periphery of the electrode stack, leaving a residual layer 203 in the bottom of the seam ( 190 , see FIG. 12B ) around the stack.
- the pin 201 has a sub-lithographic width where it contacts the top electrode layer 202 , extending into the inter-electrode dielectric layer, so that current flow is concentrated in the narrow region 210 of the phase change material pin.
- FIGS. 17-25 illustrate a sequence of stages in another representative process for making a small pin.
- FIG. 17 illustrates a substrate that comprises a silicon wafer 300 having a first layer 301 of material and a second layer 302 of material formed thereon.
- the first layer 301 of material comprises “material B”
- the second layer 302 of material comprises “material A,” wherein the two materials are selected so that they can be selectively etched.
- Representative materials include silicon nitride and silicon dioxide in integrated circuit, flat panel display and related manufacturing processes.
- Representative thicknesses for the first layer 301 of material range from about 50 to about 500 nanometers, and more specifically can be around 200 nanometers of the silicon nitride for the example shown.
- Representative thicknesses for the second layer 302 of material likewise range from about 50 to about 500 nanometers in some practical examples, and more specifically can be about 220 nanometers of silicon dioxide for the example shown.
- FIG. 18 illustrates a second stage in the representative process.
- the second layer 302 of material is etched according to a pattern, down to the surface 307 of the first layer 301 of material, leaving a structure 303 with a side wall 305 in the second layer 302 of material and a structure 304 with a side wall 306 in the second layer 302 of material.
- FIG. 19 illustrates a third stage in the representative process.
- a layer 308 of sidewall material is formed over the structures 303 , 304 and the surface 307 of the first layer 301 of material, and conformal with the side walls 305 , 306 in the second layer 302 of material.
- the sidewall material comprises a phase change material as described above in one embodiment.
- the sidewall material comprises a metal, such as aluminum, tungsten, copper, titanium, titanium nitride, tantalum, tantalum nitride, gold, and platinum and other metals, metal compounds and metal alloys.
- the sidewall material comprises a semiconductor, such as silicon, germanium, gallium nitride, and other compounds.
- the sidewall material comprises a non-metal, such as aluminum oxide, titanium oxide, hafnium oxide, or other high-K, and thermally and electrically insulating materials.
- Materials which can be used for the sidewall material include conductors, semiconductors, and insulators.
- Materials used for the side wall material can be crystalline, polycrystalline and amorphous materials.
- Materials used for the sidewall may be active materials such as used for memory elements, transistor gates, laser diodes, quantum well devices and the like.
- the thickness of the layer 308 of sidewall material depends on the particular application. In representative structures, the sidewall material on the side walls 305 , 306 ranges from about 10 nanometers to about 50 nanometers. In other structures, greater or lesser thicknesses of the sidewall material may be applied.
- FIG. 20 illustrates a fourth stage in the representative process.
- a fill layer 309 is formed over the layer 308 of the sidewall material.
- the material used for the fill layer 309 may comprise “material A,” or silicon dioxide in this example.
- the material used for the fill layer 309 is different than “material A,” including for example a material that is the same as “material B.”
- the material used for the fill layer 309 is preferably suitable for an etch back and planarization process used in subsequent processing as described below.
- FIGS. 21 and 22 illustrate a fifth stage in the representative process.
- the structure of FIG. 20 is etched back and planarized, using a procedure such as chemical mechanical polishing.
- the resulting structure has a planar surface including a surface 310 of structure 303 , the surface 312 of the sidewall material, the surface 314 of the fill material, the surface 313 of the sidewall material, and the surface 311 of the structure 304 .
- side walls on the ends of the trench filled by layer 309 have surfaces 315 , 316 which are flush with the surface 314 of the fill material, and with the surfaces 312 , 313 of the sidewall material, after the chemical mechanical polishing or other etch back and planarization steps.
- FIG. 23 shows a next stage in the representative procedure, in which a layer of photoresist is deposited, patterned and developed to form a lithographic mask 320 over at least one of the side wall spacers, such as the side wall spacer having exposed surface 313 .
- the mask 320 extends from over the surface 314 of the fill layer 309 , across the surface 313 of the sidewall spacer, over the structure 304 .
- the width of the lithographic mask 320 is defined using a lithographic process, such as a photolithographic process and preferably has the minimum feature size specified for the lithographic process utilized. For example, modern lithographic processes may have a minimum feature size ranging from about 90 to about 200 nanometers. Advanced lithographic processes may be applied to achieve small minimum feature sizes.
- FIG. 24 shows a seventh stage in the representative procedure.
- the lithographic mask 320 is trimmed, using an anisotropic etching procedure such as oxygen based plasma etching applied to photoresist materials.
- an anisotropic etching procedure such as oxygen based plasma etching applied to photoresist materials.
- a sub-lithographic, trimmed mask 321 is formed having a width which is less than the minimum feature size specified for the lithographic process.
- the width of the trimmed mask 321 for a representative embodiment is about 40 nanometers or less, where the minimum feature size is about 200 nanometers or less.
- both the width and thickness of the lithographic mask 320 are trimmed, so that the trimmed mask 321 is both more narrow, and thinner than the lithographic mask.
- a hard mask material may be utilized along with or in place of the photoresist.
- a layer of silicon nitride may be formed and patterned using the lithographic process to provide a lithographic mask 320 comprising silicon nitride.
- the silicon nitride lithographic mask 320 may then be etched to form the trimmed mask 321 .
- the resulting structure is selectively etched to remove the sidewall material in regions not covered by the trimmed mask 321 .
- the selective etching removes all of the fill material down to the surface (not shown) of the first layer 301 of material, and results in a patch 323 of sidewall material below the fill layer 309 and continuous with the pin 325 of sidewall material left on the sidewall between the structure 304 and the fill layer 309 .
- FIG. 25 shows an eighth stage in the procedure.
- the trimmed mask 321 is removed leaving small pin 325 and the seam between the fill layer 309 and the structure 304 .
- the length of the pin is determined by the thin film thickness after etch back of the second layer 302 of material.
- the thickness of the pin is determined by the thin film thickness of the sidewall material on the sidewall of the structure 304 .
- the width of the pin is determined by the sub-lithographic, trimmed mask 321 and the etching process utilized to selectively etch according to the pattern defined by the trimmed mask 321 .
- FIG. 26 illustrates a pin 325 manufactured as described herein.
- the pin 325 consists of a narrow sidewall spacer on a structure 330 that includes a patch 323 of sidewall material, and a layer of fill material 309 .
- the top 326 of the pin 325 is flush with the surface 314 of the fill layer 309 .
- the pin 325 is shown on the side of the structure 330 that comprises the fill layer 309 .
- the fill layer 309 may be removed, leaving the pin 325 on the side of the structure 304 of the second layer 302 of material.
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Abstract
A method of forming a device comprises forming a structure with a side wall. A side wall spacer is formed on the side wall. The side wall spacer is etched according to a pattern to define the width of the side wall spacer. The width is sub-lithographic, including for example about 40 nanometers or less.
Description
- The benefit of U.S. Provisional Application No. 60/630,123; filed 22 Nov. 2004, entitled SIDE WALL ACTIVE PHASE CHANGE RAM AND MANUFACTURING METHOD, is hereby claimed.
- International Business Machines Corporation, a New York corporation; Macronix International Corporation, Ltd., a Taiwan corporation, and Infineon Technologies A.G., a German corporation, are parties to a Joint Research Agreement.
- 1. Field of the Invention
- The present invention relates to methods for manufacturing integrated circuits and other devices, and more particularly to methods for making very small pin-shaped structures.
- 2. Description of Related Art
- A need arises in integrated circuit manufacturing processes for making very small structures. For example, small elements comprising chalcogenide materials or other phase change materials can be caused to change phase by application of electrical current. This property has generated interest in using phase change materials to form nonvolatile memory circuits.
- One direction of development has been toward using small quantities of programmable resistive material, particularly in small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et al., “Method of Making Chalogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov. 21, 2000.
- My U.S. Patent application Publication No. US-2004-0026686-A1 describes a phase change memory cell in which the phase change element comprises a side wall on an electrode/dielectric/electrode stack. Data is stored by causing transitions in the phase change material between amorphous and crystalline states using current. Current heats the material and causes transitions between the states. The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from crystalline state to amorphous state. The magnitude of the reset current needed for reset can be reduced by reducing the size of the phase change material element in the cell and of the contact area between electrodes and the phase change material.
- Other applications for small structures arise in integrated circuit manufacturing, and it is desirable to provide new manufacturing techniques and structures satisfying this need.
- The present invention includes methods to form a narrow side wall spacer or pin. A method of forming a memory cell based on such a narrow side wall spacer or pin is described which comprises forming a stack comprising a first electrode, an insulating layer over the first electrode, and a second electrode over the insulating layer, with a side wall on at least the insulating layer of the stack. A side wall spacer comprising a programmable resistive material in electrical communication with the first and second electrodes is formed. The side wall spacer has a length extending from the first electrode to the second electrode along the side wall, a width generally orthogonal to the length, and a thickness determined by the thickness of a layer of programmable resistive material used to form the side wall spacer. The side wall spacer is formed by depositing a layer of programmable resistive material over the side wall of the stack, anisotropically etching the layer of programmable resistive material to remove it in areas away from the side wall, and selectively etching the programmable resistive material according to a pattern to define the width of the side wall spacer. In embodiments described herein, the width is less than 50 nanometers, and more preferably about 40 nanometers or less.
- In order to selectively etch the programmable resistive material according to a pattern to define a side wall spacer with such a narrow width, one technique includes forming an etch mask having a lithographic pattern to define a lithographic width, and then trimming the etch mask to provide a trimmed mask to define the pattern used for defining the width of the side wall spacer. In one example, the etch mask comprises a photoresist, which is etched anisotropically to form the trimmed mask using an oxygen based plasma etch. In another example, the etch mask comprises a hard mask defined using a lithographic process, which is etched to reduce its width to form the trimmed mask.
- The three dimensions that define the size of the active region in the phase change pin for the cell described herein are preferably less than 50 nanometers, and can all be less than the minimum feature size of the lithographic process applied to make the cell. The dimensions are defined in technology described herein, by the thin film thickness of phase change material, the inter-electrode dielectric thin film thickness, and the trimmed mask. As a result, the cell size (the volume of the phase change material) is very small (smaller than F3, where F is the minimum lithographic feature size for the process used to manufacture the memory cell). The resulting cell of phase change material comprises a narrow pin on the side wall of an electrode stack. The contact area between at least one of the top and bottom electrodes and the phase change material pin is also defined sub-lithographically by electrode layer thicknesses for the heights, and the photo-resist pattern trimming process for the width of the contacts. The small cell and small contact region allow implementation of a memory with very small reset current and low power consumption.
- A memory device is also described that includes a stack including a first electrode, an inter-electrode insulating member over the first electrode, and a second electrode over the inter-electrode insulating member. The stack has a side wall over at least the insulating member. A spacer comprising programmable resistive material on the side wall is in electrical communication with the first and second electrodes. The spacer has a length extending from the first electrode to the second electrode along the side wall on the insulating layer, which is generally orthogonal to the length and a thickness. The width and thickness of the spacer are less than 40 nanometers in embodiments of the technology described herein. The programmable resistive material comprises a phase change material, which is reversibly programmable.
- The method described herein for formation of the phase change material pin can be used to make a very small pin for other nano-technology uses on an integrated circuit or other device, using materials other than phase change materials, like metals, dielectrics, organic materials, semiconductors, and so on. The small dimension side wall pin can be formed on structures other than that used for the phase change memory cell described herein, such as structures comprising other types of stacks of thin films, such as stacks of thin film dielectrics, with and without an electrode layer for contact to the pin.
- Other aspects and advantages of the technology described herein can be understood with reference to the figures and the detailed description which follow.
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FIG. 1 illustrates an embodiment of a side wall active pin phase change memory element. -
FIG. 2 is a schematic diagram for a memory array comprising phase change memory elements. -
FIG. 3 is a block diagram of an integrated circuit device including a thin film fuse phase change memory array and other circuitry. -
FIG. 4 is a cross-section of the final array structure for an embodiment of the invention. -
FIG. 5 is a cross-section of the structure after front-end-of-line processing and formation of electrode stack thin film layers. -
FIG. 6A andFIG. 6B show top and cross-sectional views respectively after electrode stack etching the structure fromFIG. 5 . -
FIG. 7 shows phase change material thin film deposition on the structure ofFIG. 6B . -
FIG. 8A andFIG. 8B show top and cross-sectional views respectively after GST thin film spacer etching. -
FIG. 9 shows a cross-sectional view after dielectric fill layer formation. -
FIG. 10 shows a cross-sectional view after chemical mechanical polishing for planarization and exposure of the phase change material side wall. -
FIG. 11 shows a top view after formation of a photoresist pattern, and trimming for definition of phase change side wall pin width. -
FIG. 12A andFIG. 12B show top and cross-sectional views respectively after selective etching of the phase change material side wall to define a phase change side wall pin width dimension. -
FIG. 13 shows a top view after removal of the photoresist, with the resulting phase change material side wall pin. -
FIG. 14 shows a cross-sectional view after filling in the small seam left by removal of the phase change material side wall, and subsequent oxide deposition. -
FIG. 15 shows top and cross-sectional views after via formation and metallization for definition of the bit lines. -
FIG. 16 illustrates an embodiment in which the thin film phase change material side wall is partially etched. -
FIG. 17 illustrates a first stage in a representative process for manufacturing a small pin on an integrated circuit. -
FIG. 18 illustrates a second stage in a representative process for manufacturing a small pin on an integrated circuit. -
FIG. 19 illustrates a third stage in a representative process for manufacturing a small pin on an integrated circuit. -
FIG. 20 illustrates a fourth stage in a representative process for manufacturing a small pin on an integrated circuit. -
FIGS. 21 and 22 illustrate cross-section and perspective views, respectively, of a fifth stage in a representative process for manufacturing a small pin on an integrated circuit. -
FIG. 23 illustrates a sixth stage in a representative process for manufacturing a small pin on an integrated circuit. -
FIG. 24 illustrates a seventh stage in a representative process for manufacturing a small pin on an integrated circuit. -
FIG. 25 illustrates an eighth stage in a representative process for manufacturing a small pin on an integrated circuit. -
FIG. 26 illustrates a small pin on made as described herein. - The following detailed description is made with reference to the figures. Preferred embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows.
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FIG. 1 is a perspective view of a side wall activepin memory cell 10. The cell includes a narrow side wall spacer, referred to as apin 5 on a side wall of an electrode stack that includes athin film electrode 6, and athin film electrode 7 separated by an inter-electrodedielectric layer 8. A dielectric 9 overlies the electrode stack in the illustrated embodiment. Thepin 5 consists of a programmable resistive material, such as a phase change material. Thepin 5 has an active region, within which the phase change is confined, with a length L between afirst electrode 6 and asecond electrode 7 which is determined by the thickness of the inter-electrodedielectric layer 8. The active region of thepin 5 has a thickness T determined by the thickness of a thin film formed on the side wall of the electrode stack. The electrode stack is made using a photolithographic process or other type of lithographic process so that its width is about equal to the minimum feature size specified for the lithographic process. For advanced lithographic processes the width W of the electrode stack may be on the order of 90 nanometers. The active region of thepin 5 has a width which is less than the minimum feature size for the lithographic process used to define the electrode stack. In embodiments described herein, the width of the active region of thepin 5 is about 40 nanometers or less. - As illustrated, the active region of the
pin 5 has a length L defined by a thin film thickness of theinter-electrode dielectric 8, which in embodiments of the invention can range between about 20 and 50 nanometers. Likewise, the active region of thepin 5 has a thickness T which is defined by the thin film thickness of the material used to form the side wall pin, which in embodiments of the invention can range between about 10 and 50 nanometers. Accordingly, all three dimensions of thepin 5 are less than 50 nanometers in embodiments of the present invention, and more preferably about 40 or less nanometers. - In embodiments of the invention, the programmable resistive material comprises a phase change material, such as Ge2Sb2Te5 or other materials described below. The volume of material within the
pin 5, in which the phase change is induced in the structure illustrated inFIG. 1 , is therefore very small. For embodiments in which the length L, the width W and the thickness T of the active region of thepin 5 are less than 40 nanometers, the volume of the active region is less than 64×10−24 m3. Accordingly, the magnitude of the reset current required for changing the phase is very small. - Embodiments of the memory cell include phase change based memory materials, including chalcogenide based materials and other materials, for the
side wall pin 5. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VI of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from column six of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as TeaGebSb100−(a+b), where a and b represent atomic percentages that total 100% of the atoms of the constituent elements. One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb (Ovshinsky '112 patent, cols 10-11). Particular alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4 and GeSb4Te7 (Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v.3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky '112 at columns 11-13, which examples are hereby incorporated by reference. - Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These phase change materials are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly.
- Phase change materials can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined empirically, without undue experimentation, specifically adapted to a particular phase change alloy.
- In following sections of the disclosure, the phase change material is referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a memory cell as described herein is Ge2Sb2Te5.
- Useful characteristics of the programmable resistive material, like a phase change material include the material having a resistance which is programmable, and preferably in a reversible manner, such as by having at least two solid phases that can be reversibly induced by electrical current. These at least two phases include an amorphous phase and a crystalline phase. However, in operation, the programmable resistive material may not be fully converted to either an amorphous or crystalline phase. Intermediate phases or mixtures of phases may have a detectable difference in material characteristics. The two solid phases should generally be bistable and have different electrical properties. The programmable resistive material may be a chalcogenide material. A chalcogenide material may include GST. Alternatively, it may be one of the other phase change materials identified above.
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FIG. 2 is a schematic illustration of a memory array, which can be implemented as described herein. In the schematic illustration ofFIG. 2 , acommon source line 28, aword line 23 and aword line 24 are arranged generally parallel in the Y-direction.Bit lines block 45 are coupled to the word lines 23, 24. An X-decoder and a set of sense amplifiers inblock 46 are coupled to the bit lines 41 and 42. Thecommon source line 28 is coupled to the source terminals ofaccess transistors access transistor 50 is coupled to theword line 23. The gate ofaccess transistor 51 is coupled to theword line 24. The gate ofaccess transistor 52 is coupled to theword line 23. The gate ofaccess transistor 53 is coupled to theword line 24. The drain ofaccess transistor 50 is coupled to thebottom electrode member 32 for side wallpin memory cell 35, which hastop electrode member 34. Thetop electrode member 34 is coupled to thebit line 41. Likewise, the drain ofaccess transistor 51 is coupled to thebottom electrode member 33 for side wallpin memory cell 36, which hastop electrode member 37. Thetop electrode member 37 is coupled to thebit line 41.Access transistors bit line 42. It can be seen that thecommon source line 28 is shared by two rows of memory cells, where a row is arranged in the Y-direction in the illustrated schematic. In other embodiments, the access transistors can be replaced by diodes, or other structures for controlling current flow to selected devices in the array for reading and writing data. -
FIG. 3 is a simplified block diagram of an integrated circuit according to an embodiment of the present invention. Theintegrated circuit 74 includes a memory array 55 implemented using side wall active pin phase change memory cells, on a semiconductor substrate. Arow decoder 56 is coupled to a plurality ofword lines 62, and arranged along rows in the memory array 55. A column decoder 63 is coupled to a plurality ofbit lines 64 arranged along columns in the memory array 55 for reading and programming data from the side wall pin memory cells in the array 55. Addresses are supplied onbus 58 to column decoder 63 androw decoder 56. Sense amplifiers and data-in structures in block 59 are coupled to the column decoder 63 viadata bus 67. Data is supplied via the data-inline 71 from input/output ports on theintegrated circuit 75 or from other data sources internal or external to theintegrated circuit 75, to the data-in structures in block 59. In the illustrated embodiment, other circuitry is included on the integrated circuit, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the thin film fuse phase change memory cell array. Data is supplied via the data-outline 72 from the sense amplifiers in block 59 to input/output ports on theintegrated circuit 75, or to other data destinations internal or external to theintegrated circuit 75. - A controller implemented in this example using bias
arrangement state machine 69 controls the application of biasarrangement supply voltages 68, such as read, program, erase, erase verify and program verify voltages. The controller can be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the controller comprises a general-purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller. -
FIG. 4 depicts a cross-section of a plurality of side wall active pin phase change random access memory cells 100-103. The cells 100-103 are formed on asemiconductor substrate 110. Isolation structures such as shallow trench isolation STIdielectric trenches common source region 116 in thesubstrate 110, and drainregions substrate 110. Polysilicon word lines 113 and 114 forms the gates of the access transistors. Thedielectric fill layer 118 is formed over the polysilicon word lines 113, 114.Contact plug structures common source line 119 contacts source regions along a row in the array. Thecommon source line 119 contacts thecommon source region 116. Theplug structure 120 contacts abottom electrode 121 ofcell 101. Thecell 101, likecells film bottom electrode 121, a thin filminter-electrode dielectric layer 122, a thinfilm top electrode 123, and aside wall pin 124 comprising GST or another phase change material. Adielectric fill layer 127 overlies the cells 100-103. Tungsten plug 126 contacts thetop electrode 123. A patterned metallayer providing contacts dielectric fill layer 127. Typically the contacts 129-132 are part of a single bit line extending to decoding circuits as can be seen with reference toFIG. 2 . Athin oxide layer 125 is shown overlying thetop electrode 123. Thelayer 125 is used for process margin as described below. - In representative embodiments, the patterned metal layer (contacts 129-132) comprises copper metallization. Other types of metallization, including aluminum and aluminum alloys, could be utilized as well. The top and bottom electrodes (e.g. 121, 123) comprise TiN or TaN with a thickness of 10 to 30 nm. Alternatively, the electrodes may be TiAlN or TaAlN, or may comprise one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, Ru and O. The inter-electrode insulating layer may be silicon oxide, silicon oxynitride, silicon nitride, Al2O3, other low K dielectrics, or an ONO or SONO multi-layer structure. Alternatively, the inter-electrode insulating layer may comprise one or more elements selected from the group consisting of Si, Ti, Al, Ta, N, O, and C. The inter-electrode thickness may be 10 to 200 nm, and more preferably 50 nanometers or less. The second electrode may be TiN or TaN.
-
FIG. 5 illustrates astructure 99 after front-end-of-line processing, forming the standard CMOS components in the illustrated embodiment corresponding to the word lines, the source line, and the access transistors in the array shown inFIG. 2 . InFIG. 5 ,source line 119 overlies dopedregion 116 in the semiconductor substrate, where the dopedregion 116 corresponds with the source terminal of a first access transistor on the left in the figure, and of a second access transistor on the right in the figure. In this embodiment, thesource line 119 extends to the top surface of thestructure 99. In other embodiments the source line does not extend all the way to the surface.Doped region 115 corresponds with the drain terminal of the first access transistor. A wordline including polysilicon 113, and silicide cap (not shown), acts as the gate of the first access transistor.Dielectric layer 118 overlies thepolysilicon word line 113. Plug 120 contacts dopedregion 115, and provides a conductive path to the surface of thestructure 99 for contact to a memory cell electrode as described below. The drain terminal of the second access transistor is provided by dopedregion 117. A word line includingpolysilicon line 114, and the silicide cap (not shown) acts as the gate for the second access transistor. Plug 141 contacts dopedregion 117 and provides a conductive path to the top surface of thestructure 99 for contact to a memory cell electrode as described below.Isolation trenches plugs structure 99 illustrated inFIG. 5 provides a substrate for formation of memory cell components, as described in more detail below. - After formation of the
plugs source line 119 for thestructure 99, a multilayer, thin film structure is formed including bottom electrodethin film 150, top electrodethin film 152,inter-electrode dielectric 151, and protective top dielectric 153. Thebottom electrode film 150 has a thickness less than 50 nanometers, and preferably in the range of 10 to 30 nanometers. Thetop electrode film 152 has a thickness less than 50 nanometers, and preferably in the range of 10 to 30 nanometers, and can be different than that of the bottom electrode film. For example, the thickness of thetop electrode film 152 can be slightly greater than that of the bottom electrode, in order to improve process margin for reliable contacts using tungsten plug technology and the like. The top dielectric 153 provides process margin for use of chemical mechanical polishing for planarization, variations in side wall spacer etching, and the like. Alternative embodiments without the top dielectric 153 might be implemented. -
FIG. 6A shows a mask pattern in top view including afirst rectangle 155 and asecond rectangle 156 for etching the multilayer thin film structure ofFIG. 5 , to form the electrode stacks 60, 65, as shown in cross-section inFIG. 6B . Theelectrode stack 60 includes thebottom electrode 121,inter-electrode dielectric 122, and thetop electrode 123. Theelectrode stack 60 hasside wall 61. Likewise, theelectrode stack 65 hasside wall 66. Reactive ion etching REI is utilized in order to establishside walls dielectric fill layer 118. In a representative process the over-cut is about 20 nanometers. BCl3 and/or Cl2 based recipes for the processes can be used. -
FIG. 7 illustrates a structure after depositing, by sputtering for example, aconformal layer 170 of GST, or other programmable resistive material, over thestacks -
FIG. 8A illustrates the results of side wall etching in plan view, by an etching processes which remove the GST layer from the flat surfaces, and leaveside walls 171 onstack 60 andside walls 172 onstack 65, completely surrounding thestacks FIG. 8B shows theside walls top dielectric layer 160, due to slight over-etching to ensure total removal from thesurface 173 of thestructure 99. -
FIG. 9 illustrates a dielectric fill-in process. The process involves formation of a low-temperature liner oxide, a silicon nitride layer or silicon oxide layer (not shown), using a process temperature less than about 200 degrees C., over the phase change material side walls. One suitable process is to apply silicon dioxide using plasma enhanced chemical vapor deposition PECVD. After formation of the liner, thedielectric fill 180 is implemented using a higher temperature process such as high-density plasma HDP CVD of silicon dioxide or other similar material. - As illustrated in
FIG. 10 , an oxide chemical mechanical polishing CMP process is applied to planarize the structure, and to expose the tops 181, 182 of theGST side walls -
FIG. 11 illustrates photoresist pattern trimming for the purpose of forming a sub-lithographic mask to trim theside walls rectangular extension 185 over thestack 60 and arectangular extension 186 over thestack 65 as shown in dotted line outline. The width W1 of theextensions pattern extension extensions mask - In an alternative embodiment, a hard mask layer (not shown), such as a low temperature deposited layer of SiN or SiO2, can be put between the photoresist pattern and the surface of the
stacks -
FIG. 12A illustrates side wall cell width etching in plan view according to the trimmedmask dielectric fill 180 is not etched. The etch removes the exposed GST, leaving a narrowside wall pin 124 shown in cross-section inFIG. 12B , on the electrode stack. Aseam 190 around thestack 60 and thestack 65 is left in thedielectric layer 180, which preferably extends to thetop surface 173 of thestructure 99 with complete removal of the GST. In embodiments of the process, all the GST in theseam 190 need not be removed. Rather it is sufficient that a significant portion of the GST in theseam 190 is removed, so that current between the bottom and top electrodes is concentrated in a narrow pin on the inter-electrode dielectric layer of the stack. -
FIG. 13 illustrates the next step in the process in plan view, which involves removal of the trimmed photoresist mask (187, 188) and hard mask layer (if any). Theside wall pin 124 onstack 60 andside wall pin 124A onstack 65 have a sub-lithographic width W on the order of 40 nanometers or less in embodiments of the process. -
FIG. 14 illustrates the small seam fill-in and oxide deposition step. The small seams 190 (FIG. 13B ) left by the removal of the side walls can be filled with electrical and/or thermally insulatingfills layer 195 of dielectric, which is planarized in preparation for subsequent metallization. The top oxide layer is preferably formed by PECVD, or other lower temperature process. -
FIG. 15 shows via formation and metallization for bit lines and contacts to the memory cells. Vias are etched in thelayer 195 and filled with tungsten or other conductor material to formplugs top electrode layer 123 instack 60 andtop electrode layer 123A instack 65. A patternedmetal layer 198 provides bit lines extending in the plane of the drawing to decoding circuits. As described above, theplugs stacks drains region 116, andsource line 119, provides for sensing current flow from the bit lines through the memory cells, to the access transistor and down the common source line. -
FIG. 16 shows a cross-section of an electrode stack, such asstack 60, after deposition of the GST layer side wall etching, in an alternative embodiment, in which the GST layer is only partially etched around the periphery of the electrode stack, leaving aresidual layer 203 in the bottom of the seam (190, seeFIG. 12B ) around the stack. In the embodiment ofFIG. 16 , thepin 201 has a sub-lithographic width where it contacts thetop electrode layer 202, extending into the inter-electrode dielectric layer, so that current flow is concentrated in thenarrow region 210 of the phase change material pin. - The phase change material pin described above, and the process for making it, are representative of technologies using nano-scale structures as described herein.
FIGS. 17-25 illustrate a sequence of stages in another representative process for making a small pin.FIG. 17 illustrates a substrate that comprises asilicon wafer 300 having afirst layer 301 of material and a second layer 302 of material formed thereon. In the illustrated example, thefirst layer 301 of material comprises “material B” and the second layer 302 of material comprises “material A,” wherein the two materials are selected so that they can be selectively etched. Representative materials include silicon nitride and silicon dioxide in integrated circuit, flat panel display and related manufacturing processes. Representative thicknesses for thefirst layer 301 of material range from about 50 to about 500 nanometers, and more specifically can be around 200 nanometers of the silicon nitride for the example shown. Representative thicknesses for the second layer 302 of material likewise range from about 50 to about 500 nanometers in some practical examples, and more specifically can be about 220 nanometers of silicon dioxide for the example shown. -
FIG. 18 illustrates a second stage in the representative process. In this stage, the second layer 302 of material is etched according to a pattern, down to thesurface 307 of thefirst layer 301 of material, leaving astructure 303 with aside wall 305 in the second layer 302 of material and astructure 304 with aside wall 306 in the second layer 302 of material. -
FIG. 19 illustrates a third stage in the representative process. In this stage, alayer 308 of sidewall material is formed over thestructures surface 307 of thefirst layer 301 of material, and conformal with theside walls layer 308 of sidewall material depends on the particular application. In representative structures, the sidewall material on theside walls -
FIG. 20 illustrates a fourth stage in the representative process. In this stage, afill layer 309 is formed over thelayer 308 of the sidewall material. The material used for thefill layer 309 may comprise “material A,” or silicon dioxide in this example. In alternative systems, the material used for thefill layer 309 is different than “material A,” including for example a material that is the same as “material B.” The material used for thefill layer 309 is preferably suitable for an etch back and planarization process used in subsequent processing as described below. -
FIGS. 21 and 22 illustrate a fifth stage in the representative process. In the fifth stage, the structure ofFIG. 20 is etched back and planarized, using a procedure such as chemical mechanical polishing. The resulting structure has a planar surface including asurface 310 ofstructure 303, thesurface 312 of the sidewall material, thesurface 314 of the fill material, thesurface 313 of the sidewall material, and thesurface 311 of thestructure 304. As can be seen inFIG. 22 , side walls on the ends of the trench filled bylayer 309 havesurfaces surface 314 of the fill material, and with thesurfaces -
FIG. 23 shows a next stage in the representative procedure, in which a layer of photoresist is deposited, patterned and developed to form alithographic mask 320 over at least one of the side wall spacers, such as the side wall spacer having exposedsurface 313. Themask 320 extends from over thesurface 314 of thefill layer 309, across thesurface 313 of the sidewall spacer, over thestructure 304. The width of thelithographic mask 320 is defined using a lithographic process, such as a photolithographic process and preferably has the minimum feature size specified for the lithographic process utilized. For example, modern lithographic processes may have a minimum feature size ranging from about 90 to about 200 nanometers. Advanced lithographic processes may be applied to achieve small minimum feature sizes. -
FIG. 24 shows a seventh stage in the representative procedure. In the seventh stage, thelithographic mask 320 is trimmed, using an anisotropic etching procedure such as oxygen based plasma etching applied to photoresist materials. As a result of the etching of thelithographic mask 320, a sub-lithographic, trimmedmask 321 is formed having a width which is less than the minimum feature size specified for the lithographic process. The width of the trimmedmask 321 for a representative embodiment is about 40 nanometers or less, where the minimum feature size is about 200 nanometers or less. As illustrated inFIG. 24 , both the width and thickness of thelithographic mask 320 are trimmed, so that the trimmedmask 321 is both more narrow, and thinner than the lithographic mask. In alternative systems, a hard mask material may be utilized along with or in place of the photoresist. For example, a layer of silicon nitride may be formed and patterned using the lithographic process to provide alithographic mask 320 comprising silicon nitride. The silicon nitridelithographic mask 320 may then be etched to form the trimmedmask 321. After forming a trimmedmask 321, the resulting structure is selectively etched to remove the sidewall material in regions not covered by the trimmedmask 321. As a result of the selective etching, seams 322 are left surrounding thefill layer 309 having asurface 314. In a preferred embodiment, the selective etching removes all of the fill material down to the surface (not shown) of thefirst layer 301 of material, and results in apatch 323 of sidewall material below thefill layer 309 and continuous with thepin 325 of sidewall material left on the sidewall between thestructure 304 and thefill layer 309. -
FIG. 25 shows an eighth stage in the procedure. In the eighth stage, the trimmedmask 321 is removed leavingsmall pin 325 and the seam between thefill layer 309 and thestructure 304. The length of the pin is determined by the thin film thickness after etch back of the second layer 302 of material. The thickness of the pin is determined by the thin film thickness of the sidewall material on the sidewall of thestructure 304. The width of the pin is determined by the sub-lithographic, trimmedmask 321 and the etching process utilized to selectively etch according to the pattern defined by the trimmedmask 321. -
FIG. 26 illustrates apin 325 manufactured as described herein. Thepin 325 consists of a narrow sidewall spacer on astructure 330 that includes apatch 323 of sidewall material, and a layer offill material 309. The top 326 of thepin 325 is flush with thesurface 314 of thefill layer 309. In the illustrated structure, thepin 325 is shown on the side of thestructure 330 that comprises thefill layer 309. In alternative systems, thefill layer 309 may be removed, leaving thepin 325 on the side of thestructure 304 of the second layer 302 of material. - While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.
Claims (26)
1. A method of forming a small structure, comprising:
forming a structure having a side wall on a surface of a substrate;
forming a side wall spacer on the side wall, wherein forming the side wall spacer comprises depositing a layer of the side wall material on the side wall, and selectively etching the side wall material according to a pattern to define the width of the side wall spacer, the width being less than 40 nm.
2. The method of claim 1 , wherein said selectively etching includes forming an etch mask having a lithographic pattern to define a lithographic width; and trimming the etch mask to provide a trimmed mask to define the pattern to define the width.
3. The method of claim 1 , wherein said selectively etching includes forming an etch mask having a lithographic pattern to define a lithographic width; and anisotropically etching the etch mask to provide a trimmed mask to define the pattern to define the width.
4. The method of claim 1 , including after said depositing, anisotropically etching the layer of side wall material to remove side wall material from regions other than the side wall of the structure.
5. The method of claim 1 , including after said depositing,
applying a layer of fill material over the structure and layer of side wall material;
etching back the layer of fill material and layer of side wall material on top of the structure to leave a substantially planar surface and expose the side wall material on the side wall at the substantially planar surface.
6. The method of claim 5 , wherein the etching back comprises chemical mechanical polishing.
7. The method of claim 1 , wherein the structure has a thickness less than 1 micron and the side wall spacer has a length along the side wall less than 1 micron.
8. The method of claim 1 , wherein the structure has a thickness less than 0.5 microns and the side wall spacer has a length along the side wall less than 0.5 microns.
9. The method of claim 1 , wherein the structure comprises a plurality of layers, including at least one insulating layer and at least one conductive layer, and the side wall material comprises a conductive material in electrical communication with said at least one conductive layer.
10. The method of claim 1 , wherein the structure comprises a plurality of layers, including at least one insulating layer and at least one conductive layer, and the side wall material comprises a semiconductive material in electrical communication with said at least one conductive layer.
11. A method of forming a small structure, comprising:
forming a structure having a side wall on a surface of a substrate using a lithographic process having a minimum lithographic feature size;
forming a side wall spacer on the side wall, wherein forming the side wall spacer comprises depositing a layer of the side wall material on the side wall, and selectively etching the side wall material according to a pattern to define the width of the side wall spacer, the width being less than the minimum lithographic feature size.
12. The method of claim 11 , wherein said selectively etching includes forming an etch mask having a lithographic pattern to define a lithographic width; and trimming the etch mask to provide a trimmed mask to define the pattern to define the width.
13. The method of claim 11 , wherein said selectively etching includes forming an etch mask having a lithographic pattern to define a lithographic width; and
anisotropically etching the etch mask to provide a trimmed mask to define the pattern to define the width.
14. The method of claim 11 , including after said depositing, anisotropically etching the layer of side wall material to remove side wall material from regions other than the side wall of the structure.
15. The method of claim 11 , including after said depositing,
applying a layer of fill material over the structure and layer of side wall material;
etching back the layer of fill material and layer of side wall material on top of the structure to leave a substantially planar surface and expose the side wall material on the side wall at the substantially planar surface.
16. The method of claim 15 , wherein the etching back comprises chemical mechanical polishing.
17. The method of claim 11 , wherein the structure has a thickness less than 1 micron and the side wall spacer has a length along the side wall less than 1 micron.
18. The method of claim 11 , wherein the structure has a thickness less than 0.5 microns and the side wall spacer has a length along the side wall less than 0.5 microns.
19. The method of claim 11 , wherein the structure comprises a plurality of layers, including at least one insulating layer and at least one conductive layer, and the side wall material comprises a conductive material in electrical communication with said at least one conductive layer.
20. The method of claim 11 , wherein the structure comprises a plurality of layers, including at least one insulating layer and at least one conductive layer, and the side wall material comprises a semiconductive material in electrical communication with said at least one conductive layer.
21. A device, including:
a member having a side wall; and
a spacer along the side wall of the member the spacer having a length along the side wall, a width generally orthogonal to the length, and a thickness, and wherein the width and the thickness are less than 40 nm.
22. The device of claim 21 , wherein the spacer has a thickness of 10 to 20 nm.
23. The device of claim 21 , wherein the structure has a thickness less than 1 micron and the side wall spacer has a length along the side wall less than 1 micron.
24. The device of claim 21 , wherein the structure has a thickness less than 0.5 microns and the side wall spacer has a length along the side wall less than 0.5 microns.
25. The device of claim 21 , wherein the structure comprises a plurality of layers, including at least one insulating layer and at least one conductive layer, and the side wall material comprises a conductive material in electrical communication with said at least one conductive layer.
26. The device of claim 21 , wherein the structure comprises a plurality of layers, including at least one insulating layer and at least one conductive layer, and the side wall material comprises a semiconductive material in electrical communication with said at least one conductive layer.
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US11/285,525 US20060108667A1 (en) | 2004-11-22 | 2005-11-21 | Method for manufacturing a small pin on integrated circuits or other devices |
TW094141001A TW200623474A (en) | 2004-11-22 | 2005-11-22 | Method for manufacturing a small pin on integrated circuits or other devices |
CN2010105838799A CN102088059A (en) | 2004-11-22 | 2005-11-22 | Method for manufacturing a small pin on integrated circuits or other devices |
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US11/285,525 US20060108667A1 (en) | 2004-11-22 | 2005-11-21 | Method for manufacturing a small pin on integrated circuits or other devices |
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US11/285,473 Expired - Fee Related US7608503B2 (en) | 2004-11-22 | 2005-11-21 | Side wall active pin memory and manufacturing method |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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US20070108431A1 (en) * | 2005-11-15 | 2007-05-17 | Chen Shih H | I-shaped phase change memory cell |
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US20070285960A1 (en) * | 2006-05-24 | 2007-12-13 | Macronix International Co., Ltd. | Single-Mask Phase Change Memory Element |
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US20080142984A1 (en) * | 2006-12-15 | 2008-06-19 | Macronix International Co., Ltd. | Multi-Layer Electrode Structure |
US20080144353A1 (en) * | 2006-12-13 | 2008-06-19 | Macronix International Co., Ltd. | Method, Apparatus and Computer Program Product for Read Before Programming Process on Programmable Resistive Memory Cell |
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US20080166875A1 (en) * | 2005-11-15 | 2008-07-10 | Macronix International Co., Ltd. | Thermally contained/insulated phase change memory device and method (combined) |
US20080186755A1 (en) * | 2007-02-05 | 2008-08-07 | Macronix International Co., Ltd. | Memory cell device and programming methods |
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US20080192534A1 (en) * | 2007-02-08 | 2008-08-14 | Macronix International Co., Ltd. | Memory element with reduced-current phase change element |
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US20080247224A1 (en) * | 2007-04-06 | 2008-10-09 | Macronix International Co., Ltd. | Phase Change Memory Bridge Cell with Diode Isolation Device |
US20080259672A1 (en) * | 2007-04-17 | 2008-10-23 | Macronix International Co., Ltd. | 4f2 self align side wall active phase change memory |
US20080266940A1 (en) * | 2005-11-21 | 2008-10-30 | Erh-Kun Lai | Air Cell Thermal Isolation for a Memory Array Formed of a Programmable Resistive Material |
US20090014706A1 (en) * | 2007-07-13 | 2009-01-15 | Macronix International Co., Ltd. | 4f2 self align fin bottom electrodes fet drive phase change memory |
US20090020740A1 (en) * | 2007-07-20 | 2009-01-22 | Macronix International Co., Ltd. | Resistive memory structure with buffer layer |
US20090032793A1 (en) * | 2007-08-03 | 2009-02-05 | Macronix International Co., Ltd. | Resistor Random Access Memory Structure Having a Defined Small Area of Electrical Contact |
US20090032796A1 (en) * | 2007-07-31 | 2009-02-05 | Macronix International Co., Ltd. | Phase change memory bridge cell |
US20090072215A1 (en) * | 2007-09-14 | 2009-03-19 | Macronix International Co., Ltd. | Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing |
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US20090189138A1 (en) * | 2008-01-28 | 2009-07-30 | Macronix International Co., Ltd. | Fill-in etching free pore device |
US20090236743A1 (en) * | 2006-01-09 | 2009-09-24 | Macronix International Co., Ltd. | Programmable Resistive RAM and Manufacturing Method |
US20090242880A1 (en) * | 2008-03-25 | 2009-10-01 | Macronix International Co., Ltd. | Thermally stabilized electrode structure |
US20090242865A1 (en) * | 2008-03-31 | 2009-10-01 | Macronix International Co., Ltd | Memory array with diode driver and method for fabricating the same |
US20090258135A1 (en) * | 2008-04-11 | 2009-10-15 | Sandisk 3D Llc | Method of making nonvolatile memory cell containing carbon resistivity switching as a storage element by low temperature processing |
US20090256129A1 (en) * | 2008-04-11 | 2009-10-15 | Sandisk 3D Llc | Sidewall structured switchable resistor cell |
US20090257265A1 (en) * | 2008-04-11 | 2009-10-15 | Sandisk 3D Llc | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same |
US20090258489A1 (en) * | 2008-04-11 | 2009-10-15 | Sandisk 3D Llc | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same |
US20090257266A1 (en) * | 2008-04-11 | 2009-10-15 | Sandisk 3D Llc | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same |
US20090261313A1 (en) * | 2008-04-22 | 2009-10-22 | Macronix International Co., Ltd. | Memory cell having a buried phase change region and method for fabricating the same |
US20090279349A1 (en) * | 2008-05-08 | 2009-11-12 | Macronix International Co., Ltd. | Phase change device having two or more substantial amorphous regions in high resistance state |
WO2009122349A3 (en) * | 2008-04-01 | 2009-11-26 | Nxp B.V. | Vertical phase change memory cell |
US20090309087A1 (en) * | 2008-06-12 | 2009-12-17 | Macronix International Co., Ltd. | Phase change memory cell having top and bottom sidewall contacts |
US20100006814A1 (en) * | 2008-07-11 | 2010-01-14 | Industrial Technology Research Institute | Phase-change memory element |
US7663135B2 (en) | 2007-01-31 | 2010-02-16 | Macronix International Co., Ltd. | Memory cell having a side electrode contact |
US20100117048A1 (en) * | 2008-11-07 | 2010-05-13 | Macronix International Co., Ltd. | Memory cell access device having a pn-junction with polycrystalline and single-crystal semiconductor regions |
US20100117050A1 (en) * | 2008-11-12 | 2010-05-13 | Industrial Technology Research Institute | Phase-change memory element |
US20100117049A1 (en) * | 2008-11-07 | 2010-05-13 | Macronix International Co., Ltd. | Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions |
US7719913B2 (en) | 2008-09-12 | 2010-05-18 | Macronix International Co., Ltd. | Sensing circuit for PCRAM applications |
US7718989B2 (en) | 2006-12-28 | 2010-05-18 | Macronix International Co., Ltd. | Resistor random access memory cell device |
US7729161B2 (en) | 2007-08-02 | 2010-06-01 | Macronix International Co., Ltd. | Phase change memory with dual word lines and source lines and method of operating same |
US7741636B2 (en) | 2006-01-09 | 2010-06-22 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US7749854B2 (en) | 2006-12-06 | 2010-07-06 | Macronix International Co., Ltd. | Method for making a self-converged memory material element for memory cell |
US7772581B2 (en) | 2006-09-11 | 2010-08-10 | Macronix International Co., Ltd. | Memory device having wide area phase change element and small electrode contact area |
US7786461B2 (en) | 2007-04-03 | 2010-08-31 | Macronix International Co., Ltd. | Memory structure with reduced-size memory element between memory material portions |
US7786460B2 (en) | 2005-11-15 | 2010-08-31 | Macronix International Co., Ltd. | Phase change memory device and manufacturing method |
US20100264396A1 (en) * | 2009-04-20 | 2010-10-21 | Macronix International Co., Ltd. | Ring-shaped electrode and manufacturing method for same |
US7825398B2 (en) | 2008-04-07 | 2010-11-02 | Macronix International Co., Ltd. | Memory cell having improved mechanical stability |
US20100295009A1 (en) * | 2009-05-22 | 2010-11-25 | Macronix International Co., Ltd. | Phase Change Memory Cells Having Vertical Channel Access Transistor and Memory Plane |
US7842536B2 (en) | 2005-11-21 | 2010-11-30 | Macronix International Co., Ltd. | Vacuum jacket for phase change memory element |
US7863655B2 (en) | 2006-10-24 | 2011-01-04 | Macronix International Co., Ltd. | Phase change memory cells with dual access devices |
US7867815B2 (en) | 2005-11-16 | 2011-01-11 | Macronix International Co., Ltd. | Spacer electrode small pin phase change RAM and manufacturing method |
US7869270B2 (en) | 2008-12-29 | 2011-01-11 | Macronix International Co., Ltd. | Set algorithm for phase change memory cell |
US7894254B2 (en) | 2009-07-15 | 2011-02-22 | Macronix International Co., Ltd. | Refresh circuitry for phase change memory |
US7897954B2 (en) | 2008-10-10 | 2011-03-01 | Macronix International Co., Ltd. | Dielectric-sandwiched pillar memory device |
US7903457B2 (en) | 2008-08-19 | 2011-03-08 | Macronix International Co., Ltd. | Multiple phase change materials in an integrated circuit for system on a chip application |
US7902538B2 (en) | 2005-11-28 | 2011-03-08 | Macronix International Co., Ltd. | Phase change memory cell with first and second transition temperature portions |
US7910906B2 (en) | 2006-10-04 | 2011-03-22 | Macronix International Co., Ltd. | Memory cell device with circumferentially-extending memory element |
US7919766B2 (en) | 2007-10-22 | 2011-04-05 | Macronix International Co., Ltd. | Method for making self aligning pillar memory cell device |
US7932506B2 (en) | 2008-07-22 | 2011-04-26 | Macronix International Co., Ltd. | Fully self-aligned pore-type memory cell having diode access device |
US7933139B2 (en) | 2009-05-15 | 2011-04-26 | Macronix International Co., Ltd. | One-transistor, one-resistor, one-capacitor phase change memory |
US7956358B2 (en) | 2006-02-07 | 2011-06-07 | Macronix International Co., Ltd. | I-shaped phase change memory cell with thermal isolation |
US7956344B2 (en) | 2007-02-27 | 2011-06-07 | Macronix International Co., Ltd. | Memory cell with memory element contacting ring-shaped upper end of bottom electrode |
US7968876B2 (en) | 2009-05-22 | 2011-06-28 | Macronix International Co., Ltd. | Phase change memory cell having vertical channel access transistor |
US7972893B2 (en) | 2006-04-17 | 2011-07-05 | Macronix International Co., Ltd. | Memory device manufacturing method |
US8030635B2 (en) | 2009-01-13 | 2011-10-04 | Macronix International Co., Ltd. | Polysilicon plug bipolar transistor for phase change memory |
US8036014B2 (en) | 2008-11-06 | 2011-10-11 | Macronix International Co., Ltd. | Phase change memory program method without over-reset |
US8064248B2 (en) | 2009-09-17 | 2011-11-22 | Macronix International Co., Ltd. | 2T2R-1T1R mix mode phase change memory array |
US8064247B2 (en) | 2009-01-14 | 2011-11-22 | Macronix International Co., Ltd. | Rewritable memory device based on segregation/re-absorption |
US8062833B2 (en) | 2005-12-30 | 2011-11-22 | Macronix International Co., Ltd. | Chalcogenide layer etching method |
US8077505B2 (en) | 2008-05-07 | 2011-12-13 | Macronix International Co., Ltd. | Bipolar switching of phase change device |
US8089137B2 (en) | 2009-01-07 | 2012-01-03 | Macronix International Co., Ltd. | Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method |
US8097871B2 (en) | 2009-04-30 | 2012-01-17 | Macronix International Co., Ltd. | Low operational current phase change memory structures |
US8107283B2 (en) | 2009-01-12 | 2012-01-31 | Macronix International Co., Ltd. | Method for setting PCRAM devices |
US8110822B2 (en) | 2009-07-15 | 2012-02-07 | Macronix International Co., Ltd. | Thermal protect PCRAM structure and methods for making |
US8134857B2 (en) | 2008-06-27 | 2012-03-13 | Macronix International Co., Ltd. | Methods for high speed reading operation of phase change memory and device employing same |
US8158965B2 (en) | 2008-02-05 | 2012-04-17 | Macronix International Co., Ltd. | Heating center PCRAM structure and methods for making |
US8173987B2 (en) | 2009-04-27 | 2012-05-08 | Macronix International Co., Ltd. | Integrated circuit 3D phase change memory array and manufacturing method |
US8178387B2 (en) | 2009-10-23 | 2012-05-15 | Macronix International Co., Ltd. | Methods for reducing recrystallization time for a phase change material |
US8198619B2 (en) | 2009-07-15 | 2012-06-12 | Macronix International Co., Ltd. | Phase change memory cell structure |
US8238149B2 (en) | 2009-06-25 | 2012-08-07 | Macronix International Co., Ltd. | Methods and apparatus for reducing defect bits in phase change memory |
US8310864B2 (en) | 2010-06-15 | 2012-11-13 | Macronix International Co., Ltd. | Self-aligned bit line under word line memory array |
US8324605B2 (en) | 2008-10-02 | 2012-12-04 | Macronix International Co., Ltd. | Dielectric mesh isolated phase change structure for phase change memory |
US8363463B2 (en) | 2009-06-25 | 2013-01-29 | Macronix International Co., Ltd. | Phase change memory having one or more non-constant doping profiles |
US8395935B2 (en) | 2010-10-06 | 2013-03-12 | Macronix International Co., Ltd. | Cross-point self-aligned reduced cell size phase change memory |
US8406033B2 (en) | 2009-06-22 | 2013-03-26 | Macronix International Co., Ltd. | Memory device and method for sensing and fixing margin cells |
US8426838B2 (en) | 2008-01-25 | 2013-04-23 | Higgs Opl. Capital Llc | Phase-change memory |
US8467238B2 (en) | 2010-11-15 | 2013-06-18 | Macronix International Co., Ltd. | Dynamic pulse operation for phase change memory |
US8497182B2 (en) | 2011-04-19 | 2013-07-30 | Macronix International Co., Ltd. | Sidewall thin film electrode with self-aligned top electrode and programmable resistance memory |
US8497705B2 (en) | 2010-11-09 | 2013-07-30 | Macronix International Co., Ltd. | Phase change device for interconnection of programmable logic device |
US8729521B2 (en) | 2010-05-12 | 2014-05-20 | Macronix International Co., Ltd. | Self aligned fin-type programmable memory cell |
US8809829B2 (en) | 2009-06-15 | 2014-08-19 | Macronix International Co., Ltd. | Phase change memory having stabilized microstructure and manufacturing method |
US8916414B2 (en) | 2013-03-13 | 2014-12-23 | Macronix International Co., Ltd. | Method for making memory cell by melting phase change material in confined space |
US8933536B2 (en) | 2009-01-22 | 2015-01-13 | Macronix International Co., Ltd. | Polysilicon pillar bipolar transistor with self-aligned memory element |
US8987700B2 (en) | 2011-12-02 | 2015-03-24 | Macronix International Co., Ltd. | Thermally confined electrode for programmable resistance memory |
US9159412B1 (en) | 2014-07-15 | 2015-10-13 | Macronix International Co., Ltd. | Staggered write and verify for phase change memory |
US9336879B2 (en) | 2014-01-24 | 2016-05-10 | Macronix International Co., Ltd. | Multiple phase change materials in an integrated circuit for system on a chip application |
US9559113B2 (en) | 2014-05-01 | 2017-01-31 | Macronix International Co., Ltd. | SSL/GSL gate oxide in 3D vertical channel NAND |
US9672906B2 (en) | 2015-06-19 | 2017-06-06 | Macronix International Co., Ltd. | Phase change memory with inter-granular switching |
FR3124891A1 (en) * | 2021-06-30 | 2023-01-06 | Stmicroelectronics (Crolles 2) Sas | Phase change memory |
Families Citing this family (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7547945B2 (en) | 2004-09-01 | 2009-06-16 | Micron Technology, Inc. | Transistor devices, transistor structures and semiconductor constructions |
US7427770B2 (en) | 2005-04-22 | 2008-09-23 | Micron Technology, Inc. | Memory array for increased bit density |
US8237140B2 (en) | 2005-06-17 | 2012-08-07 | Macronix International Co., Ltd. | Self-aligned, embedded phase change RAM |
US7282401B2 (en) | 2005-07-08 | 2007-10-16 | Micron Technology, Inc. | Method and apparatus for a self-aligned recessed access device (RAD) transistor gate |
US7867851B2 (en) | 2005-08-30 | 2011-01-11 | Micron Technology, Inc. | Methods of forming field effect transistors on substrates |
US7397060B2 (en) * | 2005-11-14 | 2008-07-08 | Macronix International Co., Ltd. | Pipe shaped phase change memory |
US7456421B2 (en) * | 2006-01-30 | 2008-11-25 | Macronix International Co., Ltd. | Vertical side wall active pin structures in a phase change memory and manufacturing methods |
US7700441B2 (en) | 2006-02-02 | 2010-04-20 | Micron Technology, Inc. | Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates |
US9178141B2 (en) | 2006-04-04 | 2015-11-03 | Micron Technology, Inc. | Memory elements using self-aligned phase change material layers and methods of manufacturing same |
US7812334B2 (en) | 2006-04-04 | 2010-10-12 | Micron Technology, Inc. | Phase change memory elements using self-aligned phase change material layers and methods of making and using same |
US7324366B2 (en) * | 2006-04-21 | 2008-01-29 | International Business Machines Corporation | Non-volatile memory architecture employing bipolar programmable resistance storage elements |
US7608848B2 (en) | 2006-05-09 | 2009-10-27 | Macronix International Co., Ltd. | Bridge resistance random access memory device with a singular contact structure |
US7732800B2 (en) | 2006-05-30 | 2010-06-08 | Macronix International Co., Ltd. | Resistor random access memory cell with L-shaped electrode |
US7602001B2 (en) * | 2006-07-17 | 2009-10-13 | Micron Technology, Inc. | Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells |
US7772632B2 (en) | 2006-08-21 | 2010-08-10 | Micron Technology, Inc. | Memory arrays and methods of fabricating memory arrays |
US7638357B2 (en) * | 2006-08-25 | 2009-12-29 | Micron Technology, Inc. | Programmable resistance memory devices and systems using the same and methods of forming the same |
US7560723B2 (en) * | 2006-08-29 | 2009-07-14 | Micron Technology, Inc. | Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication |
US7589995B2 (en) | 2006-09-07 | 2009-09-15 | Micron Technology, Inc. | One-transistor memory cell with bias gate |
KR100801084B1 (en) * | 2007-01-08 | 2008-02-05 | 삼성전자주식회사 | Nonvolatile memory device using variable resistive element and fabricating method thereof |
US7525176B2 (en) | 2007-01-30 | 2009-04-28 | International Business Machines Corporation | Phase change memory cell design with adjusted seam location |
CN101743649B (en) * | 2007-05-01 | 2013-04-24 | 校际微电子中心 | Non-volatile memory device |
CN101312230B (en) * | 2007-05-25 | 2010-10-13 | 财团法人工业技术研究院 | Phase change storage apparatus and method of manufacture |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US7745807B2 (en) * | 2007-07-11 | 2010-06-29 | International Business Machines Corporation | Current constricting phase change memory element structure |
TW200926356A (en) * | 2007-12-11 | 2009-06-16 | Ind Tech Res Inst | Method for fabricating phase-change memory |
US7768812B2 (en) | 2008-01-15 | 2010-08-03 | Micron Technology, Inc. | Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices |
US8338812B2 (en) * | 2008-01-16 | 2012-12-25 | Micron Technology, Inc. | Vertical spacer electrodes for variable-resistance material memories and vertical spacer variable-resistance material memory cells |
US8034655B2 (en) | 2008-04-08 | 2011-10-11 | Micron Technology, Inc. | Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays |
US8211743B2 (en) | 2008-05-02 | 2012-07-03 | Micron Technology, Inc. | Methods of forming non-volatile memory cells having multi-resistive state material between conductive electrodes |
US8134137B2 (en) | 2008-06-18 | 2012-03-13 | Micron Technology, Inc. | Memory device constructions, memory cell forming methods, and semiconductor construction forming methods |
US9343665B2 (en) | 2008-07-02 | 2016-05-17 | Micron Technology, Inc. | Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array |
KR20100076274A (en) * | 2008-12-26 | 2010-07-06 | 주식회사 하이닉스반도체 | Phase changeable memory device and method of manufacturing the same |
US8829646B2 (en) * | 2009-04-27 | 2014-09-09 | Macronix International Co., Ltd. | Integrated circuit 3D memory array and manufacturing method |
US8198160B2 (en) * | 2010-04-19 | 2012-06-12 | Jun Liu | Vertical transistor phase change memory |
US8427859B2 (en) | 2010-04-22 | 2013-04-23 | Micron Technology, Inc. | Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells |
US8411477B2 (en) | 2010-04-22 | 2013-04-02 | Micron Technology, Inc. | Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells |
US8289763B2 (en) | 2010-06-07 | 2012-10-16 | Micron Technology, Inc. | Memory arrays |
US9082954B2 (en) | 2010-09-24 | 2015-07-14 | Macronix International Co., Ltd. | PCRAM with current flowing laterally relative to axis defined by electrodes |
US8351242B2 (en) | 2010-09-29 | 2013-01-08 | Micron Technology, Inc. | Electronic devices, memory devices and memory arrays |
US8759809B2 (en) | 2010-10-21 | 2014-06-24 | Micron Technology, Inc. | Integrated circuitry comprising nonvolatile memory cells having platelike electrode and ion conductive material layer |
US8796661B2 (en) * | 2010-11-01 | 2014-08-05 | Micron Technology, Inc. | Nonvolatile memory cells and methods of forming nonvolatile memory cell |
US8526213B2 (en) | 2010-11-01 | 2013-09-03 | Micron Technology, Inc. | Memory cells, methods of programming memory cells, and methods of forming memory cells |
US9454997B2 (en) | 2010-12-02 | 2016-09-27 | Micron Technology, Inc. | Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells |
US8431458B2 (en) | 2010-12-27 | 2013-04-30 | Micron Technology, Inc. | Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells |
US8791447B2 (en) | 2011-01-20 | 2014-07-29 | Micron Technology, Inc. | Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells |
US8488365B2 (en) | 2011-02-24 | 2013-07-16 | Micron Technology, Inc. | Memory cells |
US8537592B2 (en) | 2011-04-15 | 2013-09-17 | Micron Technology, Inc. | Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells |
US8779592B2 (en) * | 2012-05-01 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Via-free interconnect structure with self-aligned metal line interconnections |
US8981330B2 (en) | 2012-07-16 | 2015-03-17 | Macronix International Co., Ltd. | Thermally-confined spacer PCM cells |
US8729523B2 (en) | 2012-08-31 | 2014-05-20 | Micron Technology, Inc. | Three dimensional memory array architecture |
US8841649B2 (en) * | 2012-08-31 | 2014-09-23 | Micron Technology, Inc. | Three dimensional memory array architecture |
CN103972385B (en) * | 2013-02-01 | 2017-06-20 | 厦门博佳琴电子科技有限公司 | A kind of embedded phase change memory and its manufacture method |
US9214351B2 (en) | 2013-03-12 | 2015-12-15 | Macronix International Co., Ltd. | Memory architecture of thin film 3D array |
JP6162031B2 (en) * | 2013-11-26 | 2017-07-12 | 株式会社日立製作所 | Phase change memory and semiconductor recording / reproducing apparatus |
US9537092B2 (en) * | 2015-03-23 | 2017-01-03 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits with memory cells and methods of manufacturing the same |
US9793323B1 (en) | 2016-07-11 | 2017-10-17 | Macronix International Co., Ltd. | Phase change memory with high endurance |
JP6316371B2 (en) * | 2016-10-13 | 2018-04-25 | Nissha株式会社 | Pressure sensor |
US10121826B1 (en) | 2017-04-28 | 2018-11-06 | Winbond Electronics Corp. | Semiconductor device and method of fabricating the same |
US10461125B2 (en) | 2017-08-29 | 2019-10-29 | Micron Technology, Inc. | Three dimensional memory arrays |
US11088323B2 (en) | 2018-08-30 | 2021-08-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Top electrode last scheme for memory cell to prevent metal redeposit |
CN112420919A (en) * | 2019-08-23 | 2021-02-26 | 联华电子股份有限公司 | Structure of variable resistance type memory and manufacturing method thereof |
US20220407000A1 (en) * | 2021-06-16 | 2022-12-22 | Macronix International Co., Ltd. | Memory with laminated cell |
Citations (87)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3271591A (en) * | 1963-09-20 | 1966-09-06 | Energy Conversion Devices Inc | Symmetrical current controlling device |
US3530441A (en) * | 1969-01-15 | 1970-09-22 | Energy Conversion Devices Inc | Method and apparatus for storing and retrieving information |
US4599705A (en) * | 1979-12-13 | 1986-07-08 | Energy Conversion Devices, Inc. | Programmable cell for use in programmable electronic arrays |
US4719594A (en) * | 1984-11-01 | 1988-01-12 | Energy Conversion Devices, Inc. | Grooved optical data storage device including a chalcogenide memory layer |
US5177567A (en) * | 1991-07-19 | 1993-01-05 | Energy Conversion Devices, Inc. | Thin-film structure for chalcogenide electrical switching devices and process therefor |
US5534712A (en) * | 1991-01-18 | 1996-07-09 | Energy Conversion Devices, Inc. | Electrically erasable memory elements characterized by reduced current and improved thermal stability |
US5789277A (en) * | 1996-07-22 | 1998-08-04 | Micron Technology, Inc. | Method of making chalogenide memory device |
US5789758A (en) * | 1995-06-07 | 1998-08-04 | Micron Technology, Inc. | Chalcogenide memory cell with a plurality of chalcogenide electrodes |
US5814527A (en) * | 1996-07-22 | 1998-09-29 | Micron Technology, Inc. | Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories |
US5869843A (en) * | 1995-06-07 | 1999-02-09 | Micron Technology, Inc. | Memory array having a multi-state element and method for forming such array or cells thereof |
US5879955A (en) * | 1995-06-07 | 1999-03-09 | Micron Technology, Inc. | Method for fabricating an array of ultra-small pores for chalcogenide memory cells |
US5952671A (en) * | 1997-05-09 | 1999-09-14 | Micron Technology, Inc. | Small electrode for a chalcogenide switching device and method for fabricating same |
US5958358A (en) * | 1992-07-08 | 1999-09-28 | Yeda Research And Development Co., Ltd. | Oriented polycrystalline thin films of transition metal chalcogenides |
US6011725A (en) * | 1997-08-01 | 2000-01-04 | Saifun Semiconductors, Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US6025220A (en) * | 1996-06-18 | 2000-02-15 | Micron Technology, Inc. | Method of forming a polysilicon diode and devices incorporating such diode |
US6031287A (en) * | 1997-06-18 | 2000-02-29 | Micron Technology, Inc. | Contact structure and memory element incorporating the same |
US6034882A (en) * | 1998-11-16 | 2000-03-07 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US6087674A (en) * | 1996-10-28 | 2000-07-11 | Energy Conversion Devices, Inc. | Memory element with memory material comprising phase-change material and dielectric material |
US6177317B1 (en) * | 1999-04-14 | 2001-01-23 | Macronix International Co., Ltd. | Method of making nonvolatile memory devices having reduced resistance diffusion regions |
US6236059B1 (en) * | 1996-08-22 | 2001-05-22 | Micron Technology, Inc. | Memory cell incorporating a chalcogenide element and method of making same |
USRE37259E1 (en) * | 1996-04-19 | 2001-07-03 | Energy Conversion Devices, Inc. | Multibit single cell memory element having tapered contact |
US6271090B1 (en) * | 2000-12-22 | 2001-08-07 | Macronix International Co., Ltd. | Method for manufacturing flash memory device with dual floating gates and two bits per cell |
US6280684B1 (en) * | 1994-12-13 | 2001-08-28 | Ricoh Company, Ltd. | Sputtering target, method of producing the target, optical recording medium fabricated by using the sputtering target, and method of fabricating the optical recording medium |
US6339544B1 (en) * | 2000-09-29 | 2002-01-15 | Intel Corporation | Method to enhance performance of thermal resistor device |
USRE37529E1 (en) * | 1994-12-13 | 2002-01-29 | Milwaukee Tool Corporation | Clutch mechanism for reciprocating saws |
US6351406B1 (en) * | 1998-11-16 | 2002-02-26 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US20020081833A1 (en) * | 2000-12-22 | 2002-06-27 | Li Calvin K. | Patterning three dimensional structures |
US6420216B1 (en) * | 2000-03-14 | 2002-07-16 | International Business Machines Corporation | Fuse processing using dielectric planarization pillars |
US6420215B1 (en) * | 2000-04-28 | 2002-07-16 | Matrix Semiconductor, Inc. | Three-dimensional memory array and method of fabrication |
US6420725B1 (en) * | 1995-06-07 | 2002-07-16 | Micron Technology, Inc. | Method and apparatus for forming an integrated circuit electrode having a reduced contact area |
US6423621B2 (en) * | 1996-10-02 | 2002-07-23 | Micron Technology, Inc. | Controllable ovonic phase-change semiconductor memory device and methods of fabricating the same |
US6429064B1 (en) * | 2000-09-29 | 2002-08-06 | Intel Corporation | Reduced contact area of sidewall conductor |
US6511867B2 (en) * | 2001-06-30 | 2003-01-28 | Ovonyx, Inc. | Utilizing atomic layer deposition for programmable device |
US6512241B1 (en) * | 2001-12-31 | 2003-01-28 | Intel Corporation | Phase change material memory device |
US6514788B2 (en) * | 2001-05-29 | 2003-02-04 | Bae Systems Information And Electronic Systems Integration Inc. | Method for manufacturing contacts for a Chalcogenide memory device |
US6534781B2 (en) * | 2000-12-26 | 2003-03-18 | Ovonyx, Inc. | Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact |
US6545903B1 (en) * | 2001-12-17 | 2003-04-08 | Texas Instruments Incorporated | Self-aligned resistive plugs for forming memory cell with phase change material |
US6555860B2 (en) * | 2000-09-29 | 2003-04-29 | Intel Corporation | Compositionally modified resistive electrode |
US6563156B2 (en) * | 2001-03-15 | 2003-05-13 | Micron Technology, Inc. | Memory elements and methods for making same |
US6566700B2 (en) * | 2001-10-11 | 2003-05-20 | Ovonyx, Inc. | Carbon-containing interfacial layer for phase-change memory |
US6567293B1 (en) * | 2000-09-29 | 2003-05-20 | Ovonyx, Inc. | Single level metal memory cell using chalcogenide cladding |
US6579760B1 (en) * | 2002-03-28 | 2003-06-17 | Macronix International Co., Ltd. | Self-aligned, programmable phase change memory |
US6586761B2 (en) * | 2001-09-07 | 2003-07-01 | Intel Corporation | Phase change material memory device |
US6589714B2 (en) * | 2001-06-26 | 2003-07-08 | Ovonyx, Inc. | Method for making programmable resistance memory element using silylated photoresist |
US6605527B2 (en) * | 2001-06-30 | 2003-08-12 | Intel Corporation | Reduced area intersection between electrode and programming element |
US6605821B1 (en) * | 2002-05-10 | 2003-08-12 | Hewlett-Packard Development Company, L.P. | Phase change material electronic memory structure and method for forming |
US6607974B2 (en) * | 2000-07-14 | 2003-08-19 | Micron Technology, Inc. | Method of forming a contact structure in a semiconductor device |
US6673700B2 (en) * | 2001-06-30 | 2004-01-06 | Ovonyx, Inc. | Reduced area intersection between electrode and programming element |
US6744088B1 (en) * | 2002-12-13 | 2004-06-01 | Intel Corporation | Phase change memory device on a planar composite layer |
US20050029502A1 (en) * | 2003-08-04 | 2005-02-10 | Hudgens Stephen J. | Processing phase change material to improve programming speed |
US6859389B2 (en) * | 2002-10-31 | 2005-02-22 | Dai Nippon Printing Co., Ltd. | Phase change-type memory element and process for producing the same |
US6861267B2 (en) * | 2001-09-17 | 2005-03-01 | Intel Corporation | Reducing shunts in memories with phase-change material |
US6864500B2 (en) * | 2002-04-10 | 2005-03-08 | Micron Technology, Inc. | Programmable conductor memory cell structure |
US6864503B2 (en) * | 2002-08-09 | 2005-03-08 | Macronix International Co., Ltd. | Spacer chalcogenide memory method and device |
US6867638B2 (en) * | 2002-01-10 | 2005-03-15 | Silicon Storage Technology, Inc. | High voltage generation and regulation system for digital multilevel nonvolatile memory |
US6888750B2 (en) * | 2000-04-28 | 2005-05-03 | Matrix Semiconductor, Inc. | Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication |
US6894305B2 (en) * | 2003-02-24 | 2005-05-17 | Samsung Electronics Co., Ltd. | Phase-change memory devices with a self-heater structure |
US6903362B2 (en) * | 2001-05-09 | 2005-06-07 | Science Applications International Corporation | Phase change switches and circuits coupling to electromagnetic waves containing phase change switches |
US6909107B2 (en) * | 2002-12-30 | 2005-06-21 | Bae Systems, Information And Electronic Systems Integration, Inc. | Method for manufacturing sidewall contacts for a chalcogenide memory device |
US6927410B2 (en) * | 2003-09-04 | 2005-08-09 | Silicon Storage Technology, Inc. | Memory device with discrete layers of phase change memory material |
US6933516B2 (en) * | 2001-10-11 | 2005-08-23 | Ovonyx, Inc. | Forming tapered lower electrode phase-change memories |
US6937507B2 (en) * | 2003-12-05 | 2005-08-30 | Silicon Storage Technology, Inc. | Memory device and method of operating same |
US6936840B2 (en) * | 2004-01-30 | 2005-08-30 | International Business Machines Corporation | Phase-change memory cell and method of fabricating the phase-change memory cell |
US6992932B2 (en) * | 2002-10-29 | 2006-01-31 | Saifun Semiconductors Ltd | Method circuit and system for read error detection in a non-volatile memory array |
US7023009B2 (en) * | 1997-10-01 | 2006-04-04 | Ovonyx, Inc. | Electrically programmable memory element with improved contacts |
US7042001B2 (en) * | 2004-01-29 | 2006-05-09 | Samsung Electronics Co., Ltd. | Phase change memory devices including memory elements having variable cross-sectional areas |
US20060110878A1 (en) * | 2004-11-22 | 2006-05-25 | Macronix International Co., Ltd. | Side wall active pin memory and manufacturing method |
US7067865B2 (en) * | 2003-06-06 | 2006-06-27 | Macronix International Co., Ltd. | High density chalcogenide memory cells |
US7166533B2 (en) * | 2005-04-08 | 2007-01-23 | Infineon Technologies, Ag | Phase change memory cell defined by a pattern shrink material process |
US20070030721A1 (en) * | 2001-07-25 | 2007-02-08 | Nantero, Inc. | Device selection circuitry constructed with nanotube technology |
US20070109843A1 (en) * | 2005-11-15 | 2007-05-17 | Macronix International Co., Ltd. | Phase Change Memory Device and Manufacturing Method |
US20070109836A1 (en) * | 2005-11-15 | 2007-05-17 | Macronix International Co., Ltd. | Thermally insulated phase change memory device and manufacturing method |
US20070111429A1 (en) * | 2005-11-14 | 2007-05-17 | Macronix International Co., Ltd. | Method of manufacturing a pipe shaped phase change memory |
US20070108431A1 (en) * | 2005-11-15 | 2007-05-17 | Chen Shih H | I-shaped phase change memory cell |
US20070108429A1 (en) * | 2005-11-14 | 2007-05-17 | Macronix International Co., Ltd. | Pipe shaped phase change memory |
US7220983B2 (en) * | 2004-12-09 | 2007-05-22 | Macronix International Co., Ltd. | Self-aligned small contact phase-change memory method and device |
US20070117315A1 (en) * | 2005-11-22 | 2007-05-24 | Macronix International Co., Ltd. | Memory cell device and manufacturing method |
US20070115794A1 (en) * | 2005-11-21 | 2007-05-24 | Macronix International Co., Ltd. | Thermal isolation for an active-sidewall phase change memory cell |
US20070121374A1 (en) * | 2005-11-15 | 2007-05-31 | Macronix International Co., Ltd. | Phase Change Memory Device and Manufacturing Method |
US20070121363A1 (en) * | 2005-11-28 | 2007-05-31 | Macronix International Co., Ltd. | Phase Change Memory Cell and Manufacturing Method |
US20070126040A1 (en) * | 2005-11-21 | 2007-06-07 | Hsiang-Lan Lung | Vacuum cell thermal isolation for a phase change memory device |
US20070131980A1 (en) * | 2005-11-21 | 2007-06-14 | Lung Hsiang L | Vacuum jacket for phase change memory element |
US20070131922A1 (en) * | 2005-12-13 | 2007-06-14 | Macronix International Co., Ltd. | Thin Film Fuse Phase Change Cell with Thermal Isolation Pad and Manufacturing Method |
US20070138458A1 (en) * | 2005-06-17 | 2007-06-21 | Macronix International Co., Ltd. | Damascene Phase Change RAM and Manufacturing Method |
US20070147105A1 (en) * | 2005-11-28 | 2007-06-28 | Macronix International Co., Ltd. | Phase Change Memory Cell and Manufacturing Method |
US20070154847A1 (en) * | 2005-12-30 | 2007-07-05 | Macronix International Co., Ltd. | Chalcogenide layer etching method |
US20070155172A1 (en) * | 2005-12-05 | 2007-07-05 | Macronix International Co., Ltd. | Manufacturing Method for Phase Change RAM with Electrode Layer Process |
Family Cites Families (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4876220A (en) | 1986-05-16 | 1989-10-24 | Actel Corporation | Method of making programmable low impedance interconnect diode element |
JP2685770B2 (en) | 1987-12-28 | 1997-12-03 | 株式会社東芝 | Nonvolatile semiconductor memory device |
US5166758A (en) | 1991-01-18 | 1992-11-24 | Energy Conversion Devices, Inc. | Electrically erasable phase change memory |
JP2825031B2 (en) * | 1991-08-06 | 1998-11-18 | 日本電気株式会社 | Semiconductor memory device |
US5166096A (en) | 1991-10-29 | 1992-11-24 | International Business Machines Corporation | Process for fabricating self-aligned contact studs for semiconductor structures |
JP2884962B2 (en) * | 1992-10-30 | 1999-04-19 | 日本電気株式会社 | Semiconductor memory |
US5515488A (en) * | 1994-08-30 | 1996-05-07 | Xerox Corporation | Method and apparatus for concurrent graphical visualization of a database search and its search history |
US5831276A (en) | 1995-06-07 | 1998-11-03 | Micron Technology, Inc. | Three-dimensional container diode for use with multi-state material in a non-volatile memory cell |
US5837564A (en) | 1995-11-01 | 1998-11-17 | Micron Technology, Inc. | Method for optimal crystallization to obtain high electrical performance from chalcogenides |
US5866928A (en) * | 1996-07-16 | 1999-02-02 | Micron Technology, Inc. | Single digit line with cell contact interconnect |
US5985698A (en) | 1996-07-22 | 1999-11-16 | Micron Technology, Inc. | Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell |
US6015977A (en) | 1997-01-28 | 2000-01-18 | Micron Technology, Inc. | Integrated circuit memory cell having a small active area and method of forming same |
US5902704A (en) * | 1997-07-02 | 1999-05-11 | Lsi Logic Corporation | Process for forming photoresist mask over integrated circuit structures with critical dimension control |
US6617192B1 (en) | 1997-10-01 | 2003-09-09 | Ovonyx, Inc. | Electrically programmable memory element with multi-regioned contact |
US6087269A (en) * | 1998-04-20 | 2000-07-11 | Advanced Micro Devices, Inc. | Method of making an interconnect using a tungsten hard mask |
US6372651B1 (en) | 1998-07-17 | 2002-04-16 | Advanced Micro Devices, Inc. | Method for trimming a photoresist pattern line for memory gate etching |
US6483736B2 (en) | 1998-11-16 | 2002-11-19 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US6759315B1 (en) * | 1999-01-04 | 2004-07-06 | International Business Machines Corporation | Method for selective trimming of gate structures and apparatus formed thereby |
US6077674A (en) * | 1999-10-27 | 2000-06-20 | Agilent Technologies Inc. | Method of producing oligonucleotide arrays with features of high purity |
US6314014B1 (en) | 1999-12-16 | 2001-11-06 | Ovonyx, Inc. | Programmable resistance memory arrays with reference cells |
US6501111B1 (en) | 2000-06-30 | 2002-12-31 | Intel Corporation | Three-dimensional (3D) programmable device |
US6569705B2 (en) | 2000-12-21 | 2003-05-27 | Intel Corporation | Metal structure for a phase-change memory device |
TW490675B (en) | 2000-12-22 | 2002-06-11 | Macronix Int Co Ltd | Control method of multi-stated NROM |
KR100625129B1 (en) * | 2001-01-30 | 2006-09-18 | 가부시키가이샤 히타치세이사쿠쇼 | Method for producing semiconductor integrated circuit device |
US6487114B2 (en) | 2001-02-28 | 2002-11-26 | Macronix International Co., Ltd. | Method of reading two-bit memories of NROM cell |
US6613604B2 (en) | 2001-08-02 | 2003-09-02 | Ovonyx, Inc. | Method for making small pore for use in programmable resistance memory element |
US6709958B2 (en) | 2001-08-30 | 2004-03-23 | Micron Technology, Inc. | Integrated circuit device and fabrication using metal-doped chalcogenide materials |
US6749971B2 (en) * | 2001-12-11 | 2004-06-15 | Advanced Micro Devices, Inc. | Method of enhancing clear field phase shift masks with chrome border around phase 180 regions |
JP3796457B2 (en) | 2002-02-28 | 2006-07-12 | 富士通株式会社 | Nonvolatile semiconductor memory device |
US6732651B2 (en) * | 2002-03-22 | 2004-05-11 | Oxy-Dry Corporation | Printing press with infrared dryer safety system |
US6620715B1 (en) | 2002-03-29 | 2003-09-16 | Cypress Semiconductor Corp. | Method for forming sub-critical dimension structures in an integrated circuit |
US6670628B2 (en) * | 2002-04-04 | 2003-12-30 | Hewlett-Packard Company, L.P. | Low heat loss and small contact area composite electrode for a phase change media memory device |
CN1639868A (en) * | 2002-04-09 | 2005-07-13 | 松下电器产业株式会社 | Non-volatile memory and the fabrication method thereof |
JP4408012B2 (en) * | 2002-07-01 | 2010-02-03 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
US6850432B2 (en) * | 2002-08-20 | 2005-02-01 | Macronix International Co., Ltd. | Laser programmable electrically readable phase-change memory method and device |
JP4133141B2 (en) | 2002-09-10 | 2008-08-13 | 株式会社エンプラス | Socket for electrical parts |
JP4190238B2 (en) * | 2002-09-13 | 2008-12-03 | 株式会社ルネサステクノロジ | Nonvolatile semiconductor memory device |
US6791102B2 (en) | 2002-12-13 | 2004-09-14 | Intel Corporation | Phase change memory |
TW200504423A (en) * | 2003-07-17 | 2005-02-01 | Ind Tech Res Inst | Apparatus for improving uniformity used in backlight module |
US6815704B1 (en) | 2003-09-04 | 2004-11-09 | Silicon Storage Technology, Inc. | Phase change memory device employing thermally insulating voids |
US6808991B1 (en) | 2003-11-19 | 2004-10-26 | Macronix International Co., Ltd. | Method for forming twin bit cell flash memory |
US6924178B2 (en) * | 2003-12-08 | 2005-08-02 | International Business Machines Corporation | Oxide/nitride stacked in FinFET spacer process |
US7354847B2 (en) * | 2004-01-26 | 2008-04-08 | Taiwan Semiconductor Manufacturing Company | Method of trimming technology |
US7858980B2 (en) * | 2004-03-01 | 2010-12-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Reduced active area in a phase change memory structure |
US7087471B2 (en) * | 2004-03-15 | 2006-08-08 | International Business Machines Corporation | Locally thinned fins |
US7365385B2 (en) * | 2004-08-30 | 2008-04-29 | Micron Technology, Inc. | DRAM layout with vertical FETs and method of formation |
KR100827653B1 (en) * | 2004-12-06 | 2008-05-07 | 삼성전자주식회사 | Phase changeable memory cells and methods of forming the same |
US7214958B2 (en) * | 2005-02-10 | 2007-05-08 | Infineon Technologies Ag | Phase change memory cell with high read margin at low power operation |
US20070037101A1 (en) * | 2005-08-15 | 2007-02-15 | Fujitsu Limited | Manufacture method for micro structure |
US7414258B2 (en) * | 2005-11-16 | 2008-08-19 | Macronix International Co., Ltd. | Spacer electrode small pin phase change memory RAM and manufacturing method |
-
2005
- 2005-11-21 US US11/285,525 patent/US20060108667A1/en not_active Abandoned
- 2005-11-21 US US11/285,473 patent/US7608503B2/en not_active Expired - Fee Related
- 2005-11-22 CN CN2010105838799A patent/CN102088059A/en active Pending
- 2005-11-22 TW TW094141002A patent/TWI355045B/en active
- 2005-11-22 CN CNA2005101248255A patent/CN1917248A/en active Pending
- 2005-11-22 CN CN2005101248240A patent/CN1819297B/en not_active Expired - Fee Related
- 2005-11-22 TW TW094141001A patent/TW200623474A/en unknown
Patent Citations (98)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3271591A (en) * | 1963-09-20 | 1966-09-06 | Energy Conversion Devices Inc | Symmetrical current controlling device |
US3530441A (en) * | 1969-01-15 | 1970-09-22 | Energy Conversion Devices Inc | Method and apparatus for storing and retrieving information |
US4599705A (en) * | 1979-12-13 | 1986-07-08 | Energy Conversion Devices, Inc. | Programmable cell for use in programmable electronic arrays |
US4719594A (en) * | 1984-11-01 | 1988-01-12 | Energy Conversion Devices, Inc. | Grooved optical data storage device including a chalcogenide memory layer |
US5534712A (en) * | 1991-01-18 | 1996-07-09 | Energy Conversion Devices, Inc. | Electrically erasable memory elements characterized by reduced current and improved thermal stability |
US5177567A (en) * | 1991-07-19 | 1993-01-05 | Energy Conversion Devices, Inc. | Thin-film structure for chalcogenide electrical switching devices and process therefor |
US5958358A (en) * | 1992-07-08 | 1999-09-28 | Yeda Research And Development Co., Ltd. | Oriented polycrystalline thin films of transition metal chalcogenides |
US6280684B1 (en) * | 1994-12-13 | 2001-08-28 | Ricoh Company, Ltd. | Sputtering target, method of producing the target, optical recording medium fabricated by using the sputtering target, and method of fabricating the optical recording medium |
USRE37529E1 (en) * | 1994-12-13 | 2002-01-29 | Milwaukee Tool Corporation | Clutch mechanism for reciprocating saws |
US6077729A (en) * | 1995-06-07 | 2000-06-20 | Micron Technology, Inc. | Memory array having a multi-state element and method for forming such array or cellis thereof |
US6104038A (en) * | 1995-06-07 | 2000-08-15 | Micron Technology, Inc. | Method for fabricating an array of ultra-small pores for chalcogenide memory cells |
US5920788A (en) * | 1995-06-07 | 1999-07-06 | Micron Technology, Inc. | Chalcogenide memory cell with a plurality of chalcogenide electrodes |
US5869843A (en) * | 1995-06-07 | 1999-02-09 | Micron Technology, Inc. | Memory array having a multi-state element and method for forming such array or cells thereof |
US5879955A (en) * | 1995-06-07 | 1999-03-09 | Micron Technology, Inc. | Method for fabricating an array of ultra-small pores for chalcogenide memory cells |
US6420725B1 (en) * | 1995-06-07 | 2002-07-16 | Micron Technology, Inc. | Method and apparatus for forming an integrated circuit electrode having a reduced contact area |
US5789758A (en) * | 1995-06-07 | 1998-08-04 | Micron Technology, Inc. | Chalcogenide memory cell with a plurality of chalcogenide electrodes |
USRE37259E1 (en) * | 1996-04-19 | 2001-07-03 | Energy Conversion Devices, Inc. | Multibit single cell memory element having tapered contact |
US6025220A (en) * | 1996-06-18 | 2000-02-15 | Micron Technology, Inc. | Method of forming a polysilicon diode and devices incorporating such diode |
US5814527A (en) * | 1996-07-22 | 1998-09-29 | Micron Technology, Inc. | Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories |
US6111264A (en) * | 1996-07-22 | 2000-08-29 | Micron Technology, Inc. | Small pores defined by a disposable internal spacer for use in chalcogenide memories |
US5789277A (en) * | 1996-07-22 | 1998-08-04 | Micron Technology, Inc. | Method of making chalogenide memory device |
US6236059B1 (en) * | 1996-08-22 | 2001-05-22 | Micron Technology, Inc. | Memory cell incorporating a chalcogenide element and method of making same |
US6423621B2 (en) * | 1996-10-02 | 2002-07-23 | Micron Technology, Inc. | Controllable ovonic phase-change semiconductor memory device and methods of fabricating the same |
US6087674A (en) * | 1996-10-28 | 2000-07-11 | Energy Conversion Devices, Inc. | Memory element with memory material comprising phase-change material and dielectric material |
US5952671A (en) * | 1997-05-09 | 1999-09-14 | Micron Technology, Inc. | Small electrode for a chalcogenide switching device and method for fabricating same |
US6189582B1 (en) * | 1997-05-09 | 2001-02-20 | Micron Technology, Inc. | Small electrode for a chalcogenide switching device and method for fabricating same |
US6031287A (en) * | 1997-06-18 | 2000-02-29 | Micron Technology, Inc. | Contact structure and memory element incorporating the same |
US6011725A (en) * | 1997-08-01 | 2000-01-04 | Saifun Semiconductors, Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US7023009B2 (en) * | 1997-10-01 | 2006-04-04 | Ovonyx, Inc. | Electrically programmable memory element with improved contacts |
US6185122B1 (en) * | 1998-11-16 | 2001-02-06 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US6034882A (en) * | 1998-11-16 | 2000-03-07 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US6351406B1 (en) * | 1998-11-16 | 2002-02-26 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US6177317B1 (en) * | 1999-04-14 | 2001-01-23 | Macronix International Co., Ltd. | Method of making nonvolatile memory devices having reduced resistance diffusion regions |
US6420216B1 (en) * | 2000-03-14 | 2002-07-16 | International Business Machines Corporation | Fuse processing using dielectric planarization pillars |
US6888750B2 (en) * | 2000-04-28 | 2005-05-03 | Matrix Semiconductor, Inc. | Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication |
US6420215B1 (en) * | 2000-04-28 | 2002-07-16 | Matrix Semiconductor, Inc. | Three-dimensional memory array and method of fabrication |
US6607974B2 (en) * | 2000-07-14 | 2003-08-19 | Micron Technology, Inc. | Method of forming a contact structure in a semiconductor device |
US6339544B1 (en) * | 2000-09-29 | 2002-01-15 | Intel Corporation | Method to enhance performance of thermal resistor device |
US6429064B1 (en) * | 2000-09-29 | 2002-08-06 | Intel Corporation | Reduced contact area of sidewall conductor |
US6597009B2 (en) * | 2000-09-29 | 2003-07-22 | Intel Corporation | Reduced contact area of sidewall conductor |
US6567293B1 (en) * | 2000-09-29 | 2003-05-20 | Ovonyx, Inc. | Single level metal memory cell using chalcogenide cladding |
US6555860B2 (en) * | 2000-09-29 | 2003-04-29 | Intel Corporation | Compositionally modified resistive electrode |
US20020081833A1 (en) * | 2000-12-22 | 2002-06-27 | Li Calvin K. | Patterning three dimensional structures |
US6271090B1 (en) * | 2000-12-22 | 2001-08-07 | Macronix International Co., Ltd. | Method for manufacturing flash memory device with dual floating gates and two bits per cell |
US6534781B2 (en) * | 2000-12-26 | 2003-03-18 | Ovonyx, Inc. | Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact |
US6593176B2 (en) * | 2000-12-26 | 2003-07-15 | Ovonyx, Inc. | Method for forming phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact |
US6563156B2 (en) * | 2001-03-15 | 2003-05-13 | Micron Technology, Inc. | Memory elements and methods for making same |
US6903362B2 (en) * | 2001-05-09 | 2005-06-07 | Science Applications International Corporation | Phase change switches and circuits coupling to electromagnetic waves containing phase change switches |
US6514788B2 (en) * | 2001-05-29 | 2003-02-04 | Bae Systems Information And Electronic Systems Integration Inc. | Method for manufacturing contacts for a Chalcogenide memory device |
US6589714B2 (en) * | 2001-06-26 | 2003-07-08 | Ovonyx, Inc. | Method for making programmable resistance memory element using silylated photoresist |
US6511867B2 (en) * | 2001-06-30 | 2003-01-28 | Ovonyx, Inc. | Utilizing atomic layer deposition for programmable device |
US6605527B2 (en) * | 2001-06-30 | 2003-08-12 | Intel Corporation | Reduced area intersection between electrode and programming element |
US6673700B2 (en) * | 2001-06-30 | 2004-01-06 | Ovonyx, Inc. | Reduced area intersection between electrode and programming element |
US20070030721A1 (en) * | 2001-07-25 | 2007-02-08 | Nantero, Inc. | Device selection circuitry constructed with nanotube technology |
US6586761B2 (en) * | 2001-09-07 | 2003-07-01 | Intel Corporation | Phase change material memory device |
US6861267B2 (en) * | 2001-09-17 | 2005-03-01 | Intel Corporation | Reducing shunts in memories with phase-change material |
US6933516B2 (en) * | 2001-10-11 | 2005-08-23 | Ovonyx, Inc. | Forming tapered lower electrode phase-change memories |
US6566700B2 (en) * | 2001-10-11 | 2003-05-20 | Ovonyx, Inc. | Carbon-containing interfacial layer for phase-change memory |
US6545903B1 (en) * | 2001-12-17 | 2003-04-08 | Texas Instruments Incorporated | Self-aligned resistive plugs for forming memory cell with phase change material |
US6512241B1 (en) * | 2001-12-31 | 2003-01-28 | Intel Corporation | Phase change material memory device |
US6867638B2 (en) * | 2002-01-10 | 2005-03-15 | Silicon Storage Technology, Inc. | High voltage generation and regulation system for digital multilevel nonvolatile memory |
US6579760B1 (en) * | 2002-03-28 | 2003-06-17 | Macronix International Co., Ltd. | Self-aligned, programmable phase change memory |
US6864500B2 (en) * | 2002-04-10 | 2005-03-08 | Micron Technology, Inc. | Programmable conductor memory cell structure |
US6605821B1 (en) * | 2002-05-10 | 2003-08-12 | Hewlett-Packard Development Company, L.P. | Phase change material electronic memory structure and method for forming |
US6864503B2 (en) * | 2002-08-09 | 2005-03-08 | Macronix International Co., Ltd. | Spacer chalcogenide memory method and device |
US20050093022A1 (en) * | 2002-08-09 | 2005-05-05 | Macronix International Co., Ltd. | Spacer chalcogenide memory device |
US7033856B2 (en) * | 2002-08-09 | 2006-04-25 | Macronix International Co. Ltd | Spacer chalcogenide memory method |
US6992932B2 (en) * | 2002-10-29 | 2006-01-31 | Saifun Semiconductors Ltd | Method circuit and system for read error detection in a non-volatile memory array |
US6859389B2 (en) * | 2002-10-31 | 2005-02-22 | Dai Nippon Printing Co., Ltd. | Phase change-type memory element and process for producing the same |
US6744088B1 (en) * | 2002-12-13 | 2004-06-01 | Intel Corporation | Phase change memory device on a planar composite layer |
US6909107B2 (en) * | 2002-12-30 | 2005-06-21 | Bae Systems, Information And Electronic Systems Integration, Inc. | Method for manufacturing sidewall contacts for a chalcogenide memory device |
US6894305B2 (en) * | 2003-02-24 | 2005-05-17 | Samsung Electronics Co., Ltd. | Phase-change memory devices with a self-heater structure |
US7067865B2 (en) * | 2003-06-06 | 2006-06-27 | Macronix International Co., Ltd. | High density chalcogenide memory cells |
US20050029502A1 (en) * | 2003-08-04 | 2005-02-10 | Hudgens Stephen J. | Processing phase change material to improve programming speed |
US6927410B2 (en) * | 2003-09-04 | 2005-08-09 | Silicon Storage Technology, Inc. | Memory device with discrete layers of phase change memory material |
US6937507B2 (en) * | 2003-12-05 | 2005-08-30 | Silicon Storage Technology, Inc. | Memory device and method of operating same |
US7042001B2 (en) * | 2004-01-29 | 2006-05-09 | Samsung Electronics Co., Ltd. | Phase change memory devices including memory elements having variable cross-sectional areas |
US6936840B2 (en) * | 2004-01-30 | 2005-08-30 | International Business Machines Corporation | Phase-change memory cell and method of fabricating the phase-change memory cell |
US20060110878A1 (en) * | 2004-11-22 | 2006-05-25 | Macronix International Co., Ltd. | Side wall active pin memory and manufacturing method |
US7220983B2 (en) * | 2004-12-09 | 2007-05-22 | Macronix International Co., Ltd. | Self-aligned small contact phase-change memory method and device |
US7166533B2 (en) * | 2005-04-08 | 2007-01-23 | Infineon Technologies, Ag | Phase change memory cell defined by a pattern shrink material process |
US20070138458A1 (en) * | 2005-06-17 | 2007-06-21 | Macronix International Co., Ltd. | Damascene Phase Change RAM and Manufacturing Method |
US20070111429A1 (en) * | 2005-11-14 | 2007-05-17 | Macronix International Co., Ltd. | Method of manufacturing a pipe shaped phase change memory |
US20070108429A1 (en) * | 2005-11-14 | 2007-05-17 | Macronix International Co., Ltd. | Pipe shaped phase change memory |
US20070121374A1 (en) * | 2005-11-15 | 2007-05-31 | Macronix International Co., Ltd. | Phase Change Memory Device and Manufacturing Method |
US20070109843A1 (en) * | 2005-11-15 | 2007-05-17 | Macronix International Co., Ltd. | Phase Change Memory Device and Manufacturing Method |
US20070109836A1 (en) * | 2005-11-15 | 2007-05-17 | Macronix International Co., Ltd. | Thermally insulated phase change memory device and manufacturing method |
US20070108430A1 (en) * | 2005-11-15 | 2007-05-17 | Macronix International Co., Ltd. | Thermally contained/insulated phase change memory device and method (combined) |
US20070108431A1 (en) * | 2005-11-15 | 2007-05-17 | Chen Shih H | I-shaped phase change memory cell |
US20070131980A1 (en) * | 2005-11-21 | 2007-06-14 | Lung Hsiang L | Vacuum jacket for phase change memory element |
US20070126040A1 (en) * | 2005-11-21 | 2007-06-07 | Hsiang-Lan Lung | Vacuum cell thermal isolation for a phase change memory device |
US20070115794A1 (en) * | 2005-11-21 | 2007-05-24 | Macronix International Co., Ltd. | Thermal isolation for an active-sidewall phase change memory cell |
US20070117315A1 (en) * | 2005-11-22 | 2007-05-24 | Macronix International Co., Ltd. | Memory cell device and manufacturing method |
US20070121363A1 (en) * | 2005-11-28 | 2007-05-31 | Macronix International Co., Ltd. | Phase Change Memory Cell and Manufacturing Method |
US20070147105A1 (en) * | 2005-11-28 | 2007-06-28 | Macronix International Co., Ltd. | Phase Change Memory Cell and Manufacturing Method |
US20070155172A1 (en) * | 2005-12-05 | 2007-07-05 | Macronix International Co., Ltd. | Manufacturing Method for Phase Change RAM with Electrode Layer Process |
US20070131922A1 (en) * | 2005-12-13 | 2007-06-14 | Macronix International Co., Ltd. | Thin Film Fuse Phase Change Cell with Thermal Isolation Pad and Manufacturing Method |
US20070154847A1 (en) * | 2005-12-30 | 2007-07-05 | Macronix International Co., Ltd. | Chalcogenide layer etching method |
Cited By (221)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070153500A1 (en) * | 2001-11-07 | 2007-07-05 | Michael Waters | Lighting device |
US20060110878A1 (en) * | 2004-11-22 | 2006-05-25 | Macronix International Co., Ltd. | Side wall active pin memory and manufacturing method |
US20070274121A1 (en) * | 2005-06-17 | 2007-11-29 | Macronix International Co., Ltd. | Multi-level memory cell having phase change element and asymmetrical thermal boundary |
US7964468B2 (en) | 2005-06-17 | 2011-06-21 | Macronix International Co., Ltd. | Multi-level memory cell having phase change element and asymmetrical thermal boundary |
US7696503B2 (en) | 2005-06-17 | 2010-04-13 | Macronix International Co., Ltd. | Multi-level memory cell having phase change element and asymmetrical thermal boundary |
US20070108431A1 (en) * | 2005-11-15 | 2007-05-17 | Chen Shih H | I-shaped phase change memory cell |
US20070121374A1 (en) * | 2005-11-15 | 2007-05-31 | Macronix International Co., Ltd. | Phase Change Memory Device and Manufacturing Method |
US7932101B2 (en) | 2005-11-15 | 2011-04-26 | Macronix International Co., Ltd. | Thermally contained/insulated phase change memory device and method |
US7786460B2 (en) | 2005-11-15 | 2010-08-31 | Macronix International Co., Ltd. | Phase change memory device and manufacturing method |
US20080166875A1 (en) * | 2005-11-15 | 2008-07-10 | Macronix International Co., Ltd. | Thermally contained/insulated phase change memory device and method (combined) |
US7993962B2 (en) | 2005-11-15 | 2011-08-09 | Macronix International Co., Ltd. | I-shaped phase change memory cell |
US8008114B2 (en) | 2005-11-15 | 2011-08-30 | Macronix International Co., Ltd. | Phase change memory device and manufacturing method |
US7867815B2 (en) | 2005-11-16 | 2011-01-11 | Macronix International Co., Ltd. | Spacer electrode small pin phase change RAM and manufacturing method |
US20080266940A1 (en) * | 2005-11-21 | 2008-10-30 | Erh-Kun Lai | Air Cell Thermal Isolation for a Memory Array Formed of a Programmable Resistive Material |
US7687307B2 (en) | 2005-11-21 | 2010-03-30 | Macronix International Co., Ltd. | Vacuum jacketed electrode for phase change memory element |
US7816661B2 (en) | 2005-11-21 | 2010-10-19 | Macronix International Co., Ltd. | Air cell thermal isolation for a memory array formed of a programmable resistive material |
US8097487B2 (en) | 2005-11-21 | 2012-01-17 | Macronix International Co., Ltd. | Method for making a phase change memory device with vacuum cell thermal isolation |
US20070158862A1 (en) * | 2005-11-21 | 2007-07-12 | Hsiang-Lan Lung | Vacuum jacketed electrode for phase change memory element |
US7829876B2 (en) | 2005-11-21 | 2010-11-09 | Macronix International Co., Ltd. | Vacuum cell thermal isolation for a phase change memory device |
US20090098678A1 (en) * | 2005-11-21 | 2009-04-16 | Macronix International Co., Ltd. | Vacuum jacketed electrode for phase change memory element |
US8110430B2 (en) | 2005-11-21 | 2012-02-07 | Macronix International Co., Ltd. | Vacuum jacket for phase change memory element |
US7842536B2 (en) | 2005-11-21 | 2010-11-30 | Macronix International Co., Ltd. | Vacuum jacket for phase change memory element |
US20070126040A1 (en) * | 2005-11-21 | 2007-06-07 | Hsiang-Lan Lung | Vacuum cell thermal isolation for a phase change memory device |
US20070117315A1 (en) * | 2005-11-22 | 2007-05-24 | Macronix International Co., Ltd. | Memory cell device and manufacturing method |
US7929340B2 (en) | 2005-11-28 | 2011-04-19 | Macronix International Co., Ltd. | Phase change memory cell and manufacturing method |
US20070147105A1 (en) * | 2005-11-28 | 2007-06-28 | Macronix International Co., Ltd. | Phase Change Memory Cell and Manufacturing Method |
US7902538B2 (en) | 2005-11-28 | 2011-03-08 | Macronix International Co., Ltd. | Phase change memory cell with first and second transition temperature portions |
US7688619B2 (en) | 2005-11-28 | 2010-03-30 | Macronix International Co., Ltd. | Phase change memory cell and manufacturing method |
US20070128870A1 (en) * | 2005-12-02 | 2007-06-07 | Macronix International Co., Ltd. | Surface Topology Improvement Method for Plug Surface Areas |
US7923285B2 (en) | 2005-12-27 | 2011-04-12 | Macronix International, Co. Ltd. | Method for forming self-aligned thermal isolation cell for a variable resistance memory array |
US20090148981A1 (en) * | 2005-12-27 | 2009-06-11 | Macronix International Co., Ltd. | Method for forming self-aligned thermal isolation cell for a variable resistance memory array |
US20070158633A1 (en) * | 2005-12-27 | 2007-07-12 | Macronix International Co., Ltd. | Method for Forming Self-Aligned Thermal Isolation Cell for a Variable Resistance Memory Array |
US8062833B2 (en) | 2005-12-30 | 2011-11-22 | Macronix International Co., Ltd. | Chalcogenide layer etching method |
US7741636B2 (en) | 2006-01-09 | 2010-06-22 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US8178388B2 (en) | 2006-01-09 | 2012-05-15 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US20090236743A1 (en) * | 2006-01-09 | 2009-09-24 | Macronix International Co., Ltd. | Programmable Resistive RAM and Manufacturing Method |
US8158963B2 (en) | 2006-01-09 | 2012-04-17 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US20070158632A1 (en) * | 2006-01-09 | 2007-07-12 | Macronix International Co., Ltd. | Method for Fabricating a Pillar-Shaped Phase Change Memory Element |
US20070173063A1 (en) * | 2006-01-24 | 2007-07-26 | Macronix International Co., Ltd. | Self-aligned manufacturing method, and manufacturing method for thin film fuse phase change ram |
US7956358B2 (en) | 2006-02-07 | 2011-06-07 | Macronix International Co., Ltd. | I-shaped phase change memory cell with thermal isolation |
US7972893B2 (en) | 2006-04-17 | 2011-07-05 | Macronix International Co., Ltd. | Memory device manufacturing method |
US7928421B2 (en) | 2006-04-21 | 2011-04-19 | Macronix International Co., Ltd. | Phase change memory cell with vacuum spacer |
US20070246699A1 (en) * | 2006-04-21 | 2007-10-25 | Hsiang-Lan Lung | Phase change memory cell with vacuum spacer |
US20070285960A1 (en) * | 2006-05-24 | 2007-12-13 | Macronix International Co., Ltd. | Single-Mask Phase Change Memory Element |
US20070298535A1 (en) * | 2006-06-27 | 2007-12-27 | Macronix International Co., Ltd. | Memory Cell With Memory Material Insulation and Manufacturing Method |
US7696506B2 (en) | 2006-06-27 | 2010-04-13 | Macronix International Co., Ltd. | Memory cell with memory material insulation and manufacturing method |
US7785920B2 (en) | 2006-07-12 | 2010-08-31 | Macronix International Co., Ltd. | Method for making a pillar-type phase change memory element |
US20080014676A1 (en) * | 2006-07-12 | 2008-01-17 | Macronix International Co., Ltd. | Method for Making a Pillar-Type Phase Change Memory Element |
US7745811B2 (en) * | 2006-08-16 | 2010-06-29 | Industrial Technology Research Institute | Phase change memory devices and methods for fabricating the same |
US20080042243A1 (en) * | 2006-08-16 | 2008-02-21 | Industrial Technology Research Institute | Phase change memory devices and methods for fabricating the same |
US20100261329A1 (en) * | 2006-09-11 | 2010-10-14 | Macronix International Co., Ltd. | Memory device having wide area phase change element and small electrode contact area |
US7772581B2 (en) | 2006-09-11 | 2010-08-10 | Macronix International Co., Ltd. | Memory device having wide area phase change element and small electrode contact area |
US7964437B2 (en) | 2006-09-11 | 2011-06-21 | Macronix International Co., Ltd. | Memory device having wide area phase change element and small electrode contact area |
US20080078983A1 (en) * | 2006-09-28 | 2008-04-03 | Wolfgang Raberg | Layer structures comprising chalcogenide materials |
US7910906B2 (en) | 2006-10-04 | 2011-03-22 | Macronix International Co., Ltd. | Memory cell device with circumferentially-extending memory element |
US8110456B2 (en) | 2006-10-24 | 2012-02-07 | Macronix International Co., Ltd. | Method for making a self aligning memory device |
US20110076825A1 (en) * | 2006-10-24 | 2011-03-31 | Macronix International Co., Ltd. | Method for Making a Self Aligning Memory Device |
US7863655B2 (en) | 2006-10-24 | 2011-01-04 | Macronix International Co., Ltd. | Phase change memory cells with dual access devices |
US7749854B2 (en) | 2006-12-06 | 2010-07-06 | Macronix International Co., Ltd. | Method for making a self-converged memory material element for memory cell |
US20080137400A1 (en) * | 2006-12-06 | 2008-06-12 | Macronix International Co., Ltd. | Phase Change Memory Cell with Thermal Barrier and Method for Fabricating the Same |
US20080138930A1 (en) * | 2006-12-06 | 2008-06-12 | Macronix International Co., Ltd. | Method for Making a Keyhole Opening during the Manufacture of a Memory Cell |
US7682868B2 (en) | 2006-12-06 | 2010-03-23 | Macronix International Co., Ltd. | Method for making a keyhole opening during the manufacture of a memory cell |
US7903447B2 (en) | 2006-12-13 | 2011-03-08 | Macronix International Co., Ltd. | Method, apparatus and computer program product for read before programming process on programmable resistive memory cell |
US20080144353A1 (en) * | 2006-12-13 | 2008-06-19 | Macronix International Co., Ltd. | Method, Apparatus and Computer Program Product for Read Before Programming Process on Programmable Resistive Memory Cell |
US8344347B2 (en) | 2006-12-15 | 2013-01-01 | Macronix International Co., Ltd. | Multi-layer electrode structure |
US20080142984A1 (en) * | 2006-12-15 | 2008-06-19 | Macronix International Co., Ltd. | Multi-Layer Electrode Structure |
US7718989B2 (en) | 2006-12-28 | 2010-05-18 | Macronix International Co., Ltd. | Resistor random access memory cell device |
US8178405B2 (en) | 2006-12-28 | 2012-05-15 | Macronix International Co., Ltd. | Resistor random access memory cell device |
US20080165571A1 (en) * | 2007-01-09 | 2008-07-10 | Macronix International Co., Ltd. | Method, Apparatus and Computer Program Product for Read Before Programming Process on Multiple Programmable Resistive Memory Cell |
US20080165572A1 (en) * | 2007-01-09 | 2008-07-10 | Macronix International Co., Ltd. | Method, Apparatus and Computer Program Product for Stepped Reset Programming Process on Programmable Resistive Memory Cell |
US20100133500A1 (en) * | 2007-01-31 | 2010-06-03 | Macronix International Co., Ltd. | Memory Cell Having a Side Electrode Contact |
US7663135B2 (en) | 2007-01-31 | 2010-02-16 | Macronix International Co., Ltd. | Memory cell having a side electrode contact |
US7964863B2 (en) | 2007-01-31 | 2011-06-21 | Macronix International Co., Ltd. | Memory cell having a side electrode contact |
US20080185730A1 (en) * | 2007-02-02 | 2008-08-07 | Macronix International Co., Ltd. | Memory cell device with coplanar electrode surface and method |
US7972895B2 (en) | 2007-02-02 | 2011-07-05 | Macronix International Co., Ltd. | Memory cell device with coplanar electrode surface and method |
US20100029042A1 (en) * | 2007-02-02 | 2010-02-04 | Macronix International Co., Ltd. | Memory cell device with coplanar electrode surface and method |
US20080186755A1 (en) * | 2007-02-05 | 2008-08-07 | Macronix International Co., Ltd. | Memory cell device and programming methods |
US7701759B2 (en) | 2007-02-05 | 2010-04-20 | Macronix International Co., Ltd. | Memory cell device and programming methods |
US7920415B2 (en) | 2007-02-05 | 2011-04-05 | Macronix International Co., Ltd. | Memory cell device and programming methods |
US20080192534A1 (en) * | 2007-02-08 | 2008-08-14 | Macronix International Co., Ltd. | Memory element with reduced-current phase change element |
US20080191187A1 (en) * | 2007-02-12 | 2008-08-14 | Macronix International Co., Ltd. | Method for manufacturing a phase change memory device with pillar bottom electrode |
US8138028B2 (en) | 2007-02-12 | 2012-03-20 | Macronix International Co., Ltd | Method for manufacturing a phase change memory device with pillar bottom electrode |
US8263960B2 (en) | 2007-02-14 | 2012-09-11 | Macronix International Co., Ltd. | Phase change memory cell with filled sidewall memory element and method for fabricating the same |
US7884343B2 (en) | 2007-02-14 | 2011-02-08 | Macronix International Co., Ltd. | Phase change memory cell with filled sidewall memory element and method for fabricating the same |
US20080191186A1 (en) * | 2007-02-14 | 2008-08-14 | Macronix International Co., Ltd. | Phase change memory cell with filled sidewall memory element and method for fabricating the same |
US7956344B2 (en) | 2007-02-27 | 2011-06-07 | Macronix International Co., Ltd. | Memory cell with memory element contacting ring-shaped upper end of bottom electrode |
US7875493B2 (en) | 2007-04-03 | 2011-01-25 | Macronix International Co., Ltd. | Memory structure with reduced-size memory element between memory material portions |
US7786461B2 (en) | 2007-04-03 | 2010-08-31 | Macronix International Co., Ltd. | Memory structure with reduced-size memory element between memory material portions |
US8610098B2 (en) | 2007-04-06 | 2013-12-17 | Macronix International Co., Ltd. | Phase change memory bridge cell with diode isolation device |
US20080247224A1 (en) * | 2007-04-06 | 2008-10-09 | Macronix International Co., Ltd. | Phase Change Memory Bridge Cell with Diode Isolation Device |
US7755076B2 (en) | 2007-04-17 | 2010-07-13 | Macronix International Co., Ltd. | 4F2 self align side wall active phase change memory |
US20080259672A1 (en) * | 2007-04-17 | 2008-10-23 | Macronix International Co., Ltd. | 4f2 self align side wall active phase change memory |
US8237148B2 (en) | 2007-04-17 | 2012-08-07 | Macronix International Co., Ltd. | 4F2 self align side wall active phase change memory |
US8513637B2 (en) * | 2007-07-13 | 2013-08-20 | Macronix International Co., Ltd. | 4F2 self align fin bottom electrodes FET drive phase change memory |
US20090014706A1 (en) * | 2007-07-13 | 2009-01-15 | Macronix International Co., Ltd. | 4f2 self align fin bottom electrodes fet drive phase change memory |
US7943920B2 (en) | 2007-07-20 | 2011-05-17 | Macronix International Co., Ltd. | Resistive memory structure with buffer layer |
US20090020740A1 (en) * | 2007-07-20 | 2009-01-22 | Macronix International Co., Ltd. | Resistive memory structure with buffer layer |
US7777215B2 (en) | 2007-07-20 | 2010-08-17 | Macronix International Co., Ltd. | Resistive memory structure with buffer layer |
US7884342B2 (en) | 2007-07-31 | 2011-02-08 | Macronix International Co., Ltd. | Phase change memory bridge cell |
US20090032796A1 (en) * | 2007-07-31 | 2009-02-05 | Macronix International Co., Ltd. | Phase change memory bridge cell |
US7729161B2 (en) | 2007-08-02 | 2010-06-01 | Macronix International Co., Ltd. | Phase change memory with dual word lines and source lines and method of operating same |
US7978509B2 (en) | 2007-08-02 | 2011-07-12 | Macronix International Co., Ltd. | Phase change memory with dual word lines and source lines and method of operating same |
US20090032793A1 (en) * | 2007-08-03 | 2009-02-05 | Macronix International Co., Ltd. | Resistor Random Access Memory Structure Having a Defined Small Area of Electrical Contact |
US9018615B2 (en) | 2007-08-03 | 2015-04-28 | Macronix International Co., Ltd. | Resistor random access memory structure having a defined small area of electrical contact |
US20100065808A1 (en) * | 2007-09-14 | 2010-03-18 | Macronix International Co., Ltd. | Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing |
US20090072215A1 (en) * | 2007-09-14 | 2009-03-19 | Macronix International Co., Ltd. | Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing |
US20090072216A1 (en) * | 2007-09-14 | 2009-03-19 | Macronix International Co., Ltd. | Phase change memory cell array with self-converged bottom electrode and method for manufacturing |
US8143612B2 (en) | 2007-09-14 | 2012-03-27 | Marconix International Co., Ltd. | Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing |
US8860111B2 (en) | 2007-09-14 | 2014-10-14 | Macronix International Co., Ltd. | Phase change memory cell array with self-converged bottom electrode and method for manufacturing |
US8178386B2 (en) | 2007-09-14 | 2012-05-15 | Macronix International Co., Ltd. | Phase change memory cell array with self-converged bottom electrode and method for manufacturing |
US20090095948A1 (en) * | 2007-10-12 | 2009-04-16 | Macronix International Co., Ltd. | Programmable Resistive Memory with Diode Structure |
US7919766B2 (en) | 2007-10-22 | 2011-04-05 | Macronix International Co., Ltd. | Method for making self aligning pillar memory cell device |
US8222071B2 (en) | 2007-10-22 | 2012-07-17 | Macronix International Co., Ltd. | Method for making self aligning pillar memory cell device |
US7804083B2 (en) | 2007-11-14 | 2010-09-28 | Macronix International Co., Ltd. | Phase change memory cell including a thermal protect bottom electrode and manufacturing methods |
US20090122588A1 (en) * | 2007-11-14 | 2009-05-14 | Macronix International Co., Ltd. | Phase change memory cell including a thermal protect bottom electrode and manufacturing methods |
US7893418B2 (en) | 2007-12-07 | 2011-02-22 | Macronix International Co., Ltd. | Phase change memory cell having interface structures with essentially equal thermal impedances and manufacturing methods |
US20090147564A1 (en) * | 2007-12-07 | 2009-06-11 | Macronix International Co., Ltd. | Phase change memory cell having interface structures with essentially equal thermal impedances and manufacturing methods |
US7646631B2 (en) | 2007-12-07 | 2010-01-12 | Macronix International Co., Ltd. | Phase change memory cell having interface structures with essentially equal thermal impedances and manufacturing methods |
US20100072447A1 (en) * | 2007-12-07 | 2010-03-25 | Macronix International Co., Ltd. | Phase change memory cell having interface structures with essentially equal thermal impedances and manufacturing methods |
US20090184310A1 (en) * | 2008-01-18 | 2009-07-23 | Macronix International Co., Ltd. | Memory cell with memory element contacting an inverted t-shaped bottom electrode |
US7879643B2 (en) | 2008-01-18 | 2011-02-01 | Macronix International Co., Ltd. | Memory cell with memory element contacting an inverted T-shaped bottom electrode |
US8426838B2 (en) | 2008-01-25 | 2013-04-23 | Higgs Opl. Capital Llc | Phase-change memory |
US9087985B2 (en) | 2008-01-25 | 2015-07-21 | Higgs Opl.Capital Llc | Phase-change memory |
US8716099B2 (en) | 2008-01-25 | 2014-05-06 | Higgs Opl. Capital Llc | Phase-change memory |
US20090189138A1 (en) * | 2008-01-28 | 2009-07-30 | Macronix International Co., Ltd. | Fill-in etching free pore device |
US7879645B2 (en) | 2008-01-28 | 2011-02-01 | Macronix International Co., Ltd. | Fill-in etching free pore device |
US8158965B2 (en) | 2008-02-05 | 2012-04-17 | Macronix International Co., Ltd. | Heating center PCRAM structure and methods for making |
US20090242880A1 (en) * | 2008-03-25 | 2009-10-01 | Macronix International Co., Ltd. | Thermally stabilized electrode structure |
US8293600B2 (en) | 2008-03-25 | 2012-10-23 | Macronix International Co., Ltd. | Thermally stabilized electrode structure |
US8084842B2 (en) | 2008-03-25 | 2011-12-27 | Macronix International Co., Ltd. | Thermally stabilized electrode structure |
US8030634B2 (en) | 2008-03-31 | 2011-10-04 | Macronix International Co., Ltd. | Memory array with diode driver and method for fabricating the same |
US20090242865A1 (en) * | 2008-03-31 | 2009-10-01 | Macronix International Co., Ltd | Memory array with diode driver and method for fabricating the same |
US8558213B2 (en) | 2008-04-01 | 2013-10-15 | Nxp B.V. | Vertical phase change memory cell |
WO2009122349A3 (en) * | 2008-04-01 | 2009-11-26 | Nxp B.V. | Vertical phase change memory cell |
US7825398B2 (en) | 2008-04-07 | 2010-11-02 | Macronix International Co., Ltd. | Memory cell having improved mechanical stability |
US7723180B2 (en) | 2008-04-11 | 2010-05-25 | Sandisk 3D Llc | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same |
US8048474B2 (en) | 2008-04-11 | 2011-11-01 | Sandisk 3D Llc | Method of making nonvolatile memory cell containing carbon resistivity switching as a storage element by low temperature processing |
US20090256129A1 (en) * | 2008-04-11 | 2009-10-15 | Sandisk 3D Llc | Sidewall structured switchable resistor cell |
US20090257265A1 (en) * | 2008-04-11 | 2009-10-15 | Sandisk 3D Llc | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same |
CN102983273A (en) * | 2008-04-11 | 2013-03-20 | 桑迪士克3D公司 | Sidewall structured switchable resistor cell |
WO2009126492A1 (en) * | 2008-04-11 | 2009-10-15 | Sandisk 3D Llc | Sidewall structured switchable resistor cell |
US20090258489A1 (en) * | 2008-04-11 | 2009-10-15 | Sandisk 3D Llc | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same |
US20090258135A1 (en) * | 2008-04-11 | 2009-10-15 | Sandisk 3D Llc | Method of making nonvolatile memory cell containing carbon resistivity switching as a storage element by low temperature processing |
US20090257266A1 (en) * | 2008-04-11 | 2009-10-15 | Sandisk 3D Llc | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same |
US7859887B2 (en) | 2008-04-11 | 2010-12-28 | Sandisk 3D Llc | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same |
US7830698B2 (en) | 2008-04-11 | 2010-11-09 | Sandisk 3D Llc | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same |
US7812335B2 (en) | 2008-04-11 | 2010-10-12 | Sandisk 3D Llc | Sidewall structured switchable resistor cell |
US20090261313A1 (en) * | 2008-04-22 | 2009-10-22 | Macronix International Co., Ltd. | Memory cell having a buried phase change region and method for fabricating the same |
US7791057B2 (en) | 2008-04-22 | 2010-09-07 | Macronix International Co., Ltd. | Memory cell having a buried phase change region and method for fabricating the same |
US8077505B2 (en) | 2008-05-07 | 2011-12-13 | Macronix International Co., Ltd. | Bipolar switching of phase change device |
US8059449B2 (en) | 2008-05-08 | 2011-11-15 | Macronix International Co., Ltd. | Phase change device having two or more substantial amorphous regions in high resistance state |
US7701750B2 (en) | 2008-05-08 | 2010-04-20 | Macronix International Co., Ltd. | Phase change device having two or more substantial amorphous regions in high resistance state |
US20090279349A1 (en) * | 2008-05-08 | 2009-11-12 | Macronix International Co., Ltd. | Phase change device having two or more substantial amorphous regions in high resistance state |
US8415651B2 (en) | 2008-06-12 | 2013-04-09 | Macronix International Co., Ltd. | Phase change memory cell having top and bottom sidewall contacts |
US20090309087A1 (en) * | 2008-06-12 | 2009-12-17 | Macronix International Co., Ltd. | Phase change memory cell having top and bottom sidewall contacts |
US8134857B2 (en) | 2008-06-27 | 2012-03-13 | Macronix International Co., Ltd. | Methods for high speed reading operation of phase change memory and device employing same |
US20100006814A1 (en) * | 2008-07-11 | 2010-01-14 | Industrial Technology Research Institute | Phase-change memory element |
TWI387056B (en) * | 2008-07-11 | 2013-02-21 | Higgs Opl Capital Llc | Phase change memory and method for fabricating the same |
US7919768B2 (en) | 2008-07-11 | 2011-04-05 | Industrial Technology Research Institute | Phase-change memory element |
US7932506B2 (en) | 2008-07-22 | 2011-04-26 | Macronix International Co., Ltd. | Fully self-aligned pore-type memory cell having diode access device |
US8315088B2 (en) | 2008-08-19 | 2012-11-20 | Macronix International Co., Ltd. | Multiple phase change materials in an integrated circuit for system on a chip application |
US7903457B2 (en) | 2008-08-19 | 2011-03-08 | Macronix International Co., Ltd. | Multiple phase change materials in an integrated circuit for system on a chip application |
US7719913B2 (en) | 2008-09-12 | 2010-05-18 | Macronix International Co., Ltd. | Sensing circuit for PCRAM applications |
US8324605B2 (en) | 2008-10-02 | 2012-12-04 | Macronix International Co., Ltd. | Dielectric mesh isolated phase change structure for phase change memory |
US7897954B2 (en) | 2008-10-10 | 2011-03-01 | Macronix International Co., Ltd. | Dielectric-sandwiched pillar memory device |
US8036014B2 (en) | 2008-11-06 | 2011-10-11 | Macronix International Co., Ltd. | Phase change memory program method without over-reset |
US20100117049A1 (en) * | 2008-11-07 | 2010-05-13 | Macronix International Co., Ltd. | Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions |
US8664689B2 (en) | 2008-11-07 | 2014-03-04 | Macronix International Co., Ltd. | Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions |
US20100117048A1 (en) * | 2008-11-07 | 2010-05-13 | Macronix International Co., Ltd. | Memory cell access device having a pn-junction with polycrystalline and single-crystal semiconductor regions |
US8907316B2 (en) | 2008-11-07 | 2014-12-09 | Macronix International Co., Ltd. | Memory cell access device having a pn-junction with polycrystalline and single crystal semiconductor regions |
US10573807B2 (en) | 2008-11-12 | 2020-02-25 | Gula Consulting Limited Liability Company | Phase change memory element |
US8604457B2 (en) | 2008-11-12 | 2013-12-10 | Higgs Opl. Capital Llc | Phase-change memory element |
US8884260B2 (en) | 2008-11-12 | 2014-11-11 | Higgs Opl. Capital Llc | Phase change memory element |
US20100117050A1 (en) * | 2008-11-12 | 2010-05-13 | Industrial Technology Research Institute | Phase-change memory element |
US9735352B2 (en) | 2008-11-12 | 2017-08-15 | Gula Consulting Limited Liability Company | Phase change memory element |
US9245924B2 (en) | 2008-11-12 | 2016-01-26 | Higgs Opl. Capital Llc | Phase change memory element |
US8094488B2 (en) | 2008-12-29 | 2012-01-10 | Macronix International Co., Ltd. | Set algorithm for phase change memory cell |
US7869270B2 (en) | 2008-12-29 | 2011-01-11 | Macronix International Co., Ltd. | Set algorithm for phase change memory cell |
US8089137B2 (en) | 2009-01-07 | 2012-01-03 | Macronix International Co., Ltd. | Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method |
US8107283B2 (en) | 2009-01-12 | 2012-01-31 | Macronix International Co., Ltd. | Method for setting PCRAM devices |
US8030635B2 (en) | 2009-01-13 | 2011-10-04 | Macronix International Co., Ltd. | Polysilicon plug bipolar transistor for phase change memory |
US8237144B2 (en) | 2009-01-13 | 2012-08-07 | Macronix International Co., Ltd. | Polysilicon plug bipolar transistor for phase change memory |
US8064247B2 (en) | 2009-01-14 | 2011-11-22 | Macronix International Co., Ltd. | Rewritable memory device based on segregation/re-absorption |
US8933536B2 (en) | 2009-01-22 | 2015-01-13 | Macronix International Co., Ltd. | Polysilicon pillar bipolar transistor with self-aligned memory element |
US8084760B2 (en) | 2009-04-20 | 2011-12-27 | Macronix International Co., Ltd. | Ring-shaped electrode and manufacturing method for same |
US20100264396A1 (en) * | 2009-04-20 | 2010-10-21 | Macronix International Co., Ltd. | Ring-shaped electrode and manufacturing method for same |
US8173987B2 (en) | 2009-04-27 | 2012-05-08 | Macronix International Co., Ltd. | Integrated circuit 3D phase change memory array and manufacturing method |
US8916845B2 (en) | 2009-04-30 | 2014-12-23 | Macronix International Co., Ltd. | Low operational current phase change memory structures |
US8097871B2 (en) | 2009-04-30 | 2012-01-17 | Macronix International Co., Ltd. | Low operational current phase change memory structures |
US7933139B2 (en) | 2009-05-15 | 2011-04-26 | Macronix International Co., Ltd. | One-transistor, one-resistor, one-capacitor phase change memory |
US7968876B2 (en) | 2009-05-22 | 2011-06-28 | Macronix International Co., Ltd. | Phase change memory cell having vertical channel access transistor |
US20100295009A1 (en) * | 2009-05-22 | 2010-11-25 | Macronix International Co., Ltd. | Phase Change Memory Cells Having Vertical Channel Access Transistor and Memory Plane |
US8624236B2 (en) | 2009-05-22 | 2014-01-07 | Macronix International Co., Ltd. | Phase change memory cell having vertical channel access transistor |
US8350316B2 (en) | 2009-05-22 | 2013-01-08 | Macronix International Co., Ltd. | Phase change memory cells having vertical channel access transistor and memory plane |
US8313979B2 (en) | 2009-05-22 | 2012-11-20 | Macronix International Co., Ltd. | Phase change memory cell having vertical channel access transistor |
US8809829B2 (en) | 2009-06-15 | 2014-08-19 | Macronix International Co., Ltd. | Phase change memory having stabilized microstructure and manufacturing method |
US8406033B2 (en) | 2009-06-22 | 2013-03-26 | Macronix International Co., Ltd. | Memory device and method for sensing and fixing margin cells |
US8363463B2 (en) | 2009-06-25 | 2013-01-29 | Macronix International Co., Ltd. | Phase change memory having one or more non-constant doping profiles |
US8238149B2 (en) | 2009-06-25 | 2012-08-07 | Macronix International Co., Ltd. | Methods and apparatus for reducing defect bits in phase change memory |
US8198619B2 (en) | 2009-07-15 | 2012-06-12 | Macronix International Co., Ltd. | Phase change memory cell structure |
US7894254B2 (en) | 2009-07-15 | 2011-02-22 | Macronix International Co., Ltd. | Refresh circuitry for phase change memory |
US8779408B2 (en) | 2009-07-15 | 2014-07-15 | Macronix International Co., Ltd. | Phase change memory cell structure |
US8110822B2 (en) | 2009-07-15 | 2012-02-07 | Macronix International Co., Ltd. | Thermal protect PCRAM structure and methods for making |
US8228721B2 (en) | 2009-07-15 | 2012-07-24 | Macronix International Co., Ltd. | Refresh circuitry for phase change memory |
US8064248B2 (en) | 2009-09-17 | 2011-11-22 | Macronix International Co., Ltd. | 2T2R-1T1R mix mode phase change memory array |
US8178387B2 (en) | 2009-10-23 | 2012-05-15 | Macronix International Co., Ltd. | Methods for reducing recrystallization time for a phase change material |
US8729521B2 (en) | 2010-05-12 | 2014-05-20 | Macronix International Co., Ltd. | Self aligned fin-type programmable memory cell |
US8853047B2 (en) | 2010-05-12 | 2014-10-07 | Macronix International Co., Ltd. | Self aligned fin-type programmable memory cell |
US8310864B2 (en) | 2010-06-15 | 2012-11-13 | Macronix International Co., Ltd. | Self-aligned bit line under word line memory array |
US8395935B2 (en) | 2010-10-06 | 2013-03-12 | Macronix International Co., Ltd. | Cross-point self-aligned reduced cell size phase change memory |
US8497705B2 (en) | 2010-11-09 | 2013-07-30 | Macronix International Co., Ltd. | Phase change device for interconnection of programmable logic device |
US8467238B2 (en) | 2010-11-15 | 2013-06-18 | Macronix International Co., Ltd. | Dynamic pulse operation for phase change memory |
US8497182B2 (en) | 2011-04-19 | 2013-07-30 | Macronix International Co., Ltd. | Sidewall thin film electrode with self-aligned top electrode and programmable resistance memory |
US9236568B2 (en) | 2011-04-19 | 2016-01-12 | Macronix International Co., Ltd. | Sidewall thin film electrode with self-aligned top electrode and programmable resistance memory |
US8987700B2 (en) | 2011-12-02 | 2015-03-24 | Macronix International Co., Ltd. | Thermally confined electrode for programmable resistance memory |
US8916414B2 (en) | 2013-03-13 | 2014-12-23 | Macronix International Co., Ltd. | Method for making memory cell by melting phase change material in confined space |
US9336879B2 (en) | 2014-01-24 | 2016-05-10 | Macronix International Co., Ltd. | Multiple phase change materials in an integrated circuit for system on a chip application |
US9559113B2 (en) | 2014-05-01 | 2017-01-31 | Macronix International Co., Ltd. | SSL/GSL gate oxide in 3D vertical channel NAND |
US9159412B1 (en) | 2014-07-15 | 2015-10-13 | Macronix International Co., Ltd. | Staggered write and verify for phase change memory |
US9672906B2 (en) | 2015-06-19 | 2017-06-06 | Macronix International Co., Ltd. | Phase change memory with inter-granular switching |
FR3124891A1 (en) * | 2021-06-30 | 2023-01-06 | Stmicroelectronics (Crolles 2) Sas | Phase change memory |
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TWI355045B (en) | 2011-12-21 |
CN102088059A (en) | 2011-06-08 |
TW200633145A (en) | 2006-09-16 |
CN1917248A (en) | 2007-02-21 |
CN1819297B (en) | 2013-08-21 |
US7608503B2 (en) | 2009-10-27 |
TWI354386B (en) | 2011-12-11 |
US20060110878A1 (en) | 2006-05-25 |
TW200623474A (en) | 2006-07-01 |
CN1819297A (en) | 2006-08-16 |
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