US20060113616A1 - Selective spacer layer deposition method for forming spacers with different widths - Google Patents
Selective spacer layer deposition method for forming spacers with different widths Download PDFInfo
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- US20060113616A1 US20060113616A1 US11/206,613 US20661305A US2006113616A1 US 20060113616 A1 US20060113616 A1 US 20060113616A1 US 20661305 A US20661305 A US 20661305A US 2006113616 A1 US2006113616 A1 US 2006113616A1
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- 125000006850 spacer group Chemical group 0.000 title claims abstract description 131
- 238000000151 deposition Methods 0.000 title description 13
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 18
- 229910052681 coesite Inorganic materials 0.000 claims description 11
- 229910052906 cristobalite Inorganic materials 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 229910052682 stishovite Inorganic materials 0.000 claims description 11
- 229910052905 tridymite Inorganic materials 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 239000003989 dielectric material Substances 0.000 claims 20
- 238000000034 method Methods 0.000 abstract description 15
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 239000002904 solvent Substances 0.000 description 5
- 229910018557 Si O Inorganic materials 0.000 description 3
- 229910007991 Si-N Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910006294 Si—N Inorganic materials 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
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- 150000004767 nitrides Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- 229920005591 polysilicon Polymers 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- -1 silicon nitride SiN Chemical class 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Definitions
- the present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of forming spacers with different widths on a semiconductor substrate.
- Fabricating integrated circuits with faster and/or an increasing number of semiconductor devices is a continuing trend in integrated circuit technology.
- a very influential factor in this trend is technology scaling, i.e., the reduction in transistor feature sizes.
- Technology scaling has enabled transistors to become smaller, thus allowing for more dense integrated circuits in terms of the number of transistors packed on a chip.
- Spacers are commonly used in the fabrication of semiconductor devices and integrated circuits.
- the spacers may be used, for example, to control transistor gate size, source and drain regions placement or other features. Because variously sized transistors and other features are often required in a particular integrated circuit design, spacers of different widths must be utilized during the fabrication thereof.
- Spacers of different widths are typically formed using conventional etching methods. These etching methods, unfortunately, may damage the thin, dielectric gate insulating layer and substrate. Accordingly, a new method is needed for forming spacers of varying width.
- a method for forming spacers with different widths on a semiconductor substrate. The method comprises the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.
- FIGS. 1-7 are cross sectional views illustrating a method for forming spacers with different widths on a semiconductor device according to the present invention.
- FIGS. 1-7 illustrate a method for forming two or more spacers with different widths on a semiconductor device according to the present invention.
- the semiconductor device 10 includes a substrate 20 that may be comprised of a semiconductor material, such as single crystal silicon or gallium arsenide.
- a plurality of features with different line widths are disposed over the substrate 20 and may include, for purposes of illustrating the method of the invention and not limitation, a first gate electrode 30 a of a first length, a second gate electrode 30 b of a second length, and a third gate electrode 30 c of a third length are disposed over the substrate 20 .
- the different gate lengths used in this embodiment of the invention may be provided, for example, to optimize the transistor performance of an embedded DRAM semiconductor device 10 .
- the gate electrodes 30 a - 30 c are electrically insulated from the substrate 20 by thin, dielectric gate insulating layers 32 a - 32 c.
- the gate electrodes 30 a - 30 c may be formed from a polysilicon, such as undoped poly, amorphous poly, doped poly, and the like, using conventional forming methods, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD).
- the thin, dielectric gate insulating layers 32 a - 32 c may be formed on the substrate 20 from an oxide layer using conventional forming methods, such as physical or chemical vapor deposition, prior to the formation of the gate electrodes 30 a - 30 c .
- the thin, dielectric gate insulating layers may be formed from a nitride layer.
- a first dielectric insulating spacer layer 40 is formed over the substrate 10 and gate electrodes 30 a - 30 c using conventional forming methods, such as PVD or CVD.
- the first spacer layer 40 may be formed from a nitride such as silicon nitride SiN, or an oxide such as silicon oxide SiO 2 .
- the first spacer layer 40 may be deposited to a thickness ranging from approximately 500 ⁇ to 1000 ⁇ .
- a first patterned photoresist layer or mask layer (not shown) is provided over the first spacer layer 40 , and the semiconductor device 10 is anisotropically etched to define the first spacer layer 40 into three spacers 50 a - 50 c each having the same width W 1 , adjacent the side walls of the gate electrodes 30 a - 30 c .
- the anisotropic etch may be performed using a conventional plasma reactive-ion etching method. After etching, the first mask layer is removed.
- spacers of other widths are formed in accordance with the present invention using selective deposition.
- spacers having a width W 2 which is greater than width W 1 , may be formed by providing a second mask layer 60 over the spacer 50 a of the first width and adjacent gate electrode 30 a , and then selectively depositing a second spacer layer 70 over the first spacer layer 40 of the two unmasked spacers 50 b and 50 c .
- the selective deposition may be accomplished by treating the substrate 20 with a plasma to generate dangling bonds on the surface of the first spacer layer 40 of the two unmasked spacers 50 b and 50 c .
- the dangling bonds alter the chemical properties of the surface, e.g.
- the second spacer layer 70 may be formed over the substrate using PVD or CVD. The portions 70 a of the second spacer layer 70 overlying the first spacer layers 40 of the unmasked spacers 50 b and 50 c firmly bond thereto via the dangling bonds at the interface of the first spacer layer 40 and the directly overlying portions 70 a of the second spacer layer 70 .
- the portions 70 b of the second spacer layer 70 directly overlying the untreated features are easily removed using for example, a wet bench, due to the lack of dangling bonds at the interface thereof. After enlarging the spacers 50 b and 50 c , the second mask layer 60 may then be removed.
- FIG. 5 illustrates the device 10 after removal of the weakly bonded portions of the second spacer layer 70 . As illustrated, the selective deposition process enlarges the spacers 50 b and 50 c to a width W 2 .
- a third mask layer 80 may be provided over the spacer 50 a of width W 1 and its adjacent gate electrode 30 a and spacer 50 b of width W 2 and its adjacent gate electrode 30 b as illustrated in FIG. 6 .
- a third spacer layer 90 is then selectively deposited over the second spacer layer portions 70 a of the unmasked spacer 50 c using the selective deposition process described above, i.e., treating the substrate with a plasma to generate dangling bonds on the surface of the second spacer layer portions 70 a of the unmasked spacer 50 c ; forming the third spacer layer 90 over the substrate using PVD or CVD; removing the weakly bonded portions 90 b of the third spacer layer 90 using a wet bench, and removing the third mask layer 80 , thereby leaving the spacer 50 c enlarged by the firmly bonded third spacer layer portions 90 a to a width of W 3 as illustrated in FIG. 7 .
- the plasma treatment may be performed using conventional CVD processing equipment.
- the plasma used in this process may comprise an NH 3 or N 2 O plasma, depending upon the composition of the spacer layer to be treated.
- an NH 3 plasma may be used to generate Si—N dangling bonds over the surface of the SiO 2 first spacer layer.
- the second spacer layer will then be formed by depositing SiO 2 over the plasma treated first spacer layer.
- the SiO 2 deposition produces an oxygen-rich, silicon oxynitride (SiON) film over the first spacer layer due to the Si—N dangling bonds, the oxygen-rich SiON film forming the second spacer layer.
- the unwanted portions of the second spacer layer formed over the other features of the device such as the gate electrodes (made of poly-silicon for example) and the substrate (made of silicon for example), will still be composed of SiO 2 because these features do not have dangling bonds. These unwanted SiO 2 portions of the second spacer layer are easily removed by solvent selectivity due to the different materials.
- the oxygen-rich SiON film forming the second spacer layer may be treated with an N 2 O plasma to generate Si—O dangling bonds over the surface of the second spacer layer.
- the third spacer layer will be formed by depositing SiN over the second spacer layer.
- the SiN deposition produces a nitrogen-rich, SiON film over the second spacer layer, the nitrogen-rich SiON film forming the third spacer layer.
- the unwanted portions of the third spacer layer formed over the other features of the device are still composed of SiN. These unwanted portions of the third spacer layer are easily removed by solvent selectivity due to the different materials.
- an N 2 O plasma may be used to generate Si—O dangling bonds over the surface of the SiN first spacer layer.
- the second spacer layer will then be formed by depositing SiN over the plasma treated first spacer layer.
- the SiN deposition produces an nitrogen-rich, silicon oxynitride (SiON) film over the first spacer layer due to the Si—O dangling bonds, the nitrogen-rich SiON film forming the second spacer layer.
- the unwanted portions of the second spacer layer formed over the other features of the device, such as the gate electrodes and the substrate, will still be composed of SiN because these features do not have dangling bonds. These unwanted SiN portions of the second spacer layer are easily removed by solvent selectivity due to the different materials.
- the nitrogen-rich SiON film forming the second spacer layer is treated with an NH 3 plasma to generate Si—N dangling bonds over the surface of the second spacer layer.
- the third spacer layer will be formed by depositing SiO 2 over the second spacer layer.
- the SiO 2 deposition produces an oxygen-rich, SiON film over the second spacer layer, the oxygen-rich SiON film forming the third spacer layer.
- the unwanted portions of the third spacer layer formed over the other features of the device are still composed of SiO 2 . These unwanted portions of the third spacer layer are easily removed by solvent selectivity due to the different materials.
- Spacers of increasing widths may be formed by repeating the selective deposition process as many times as desired.
- the width of a spacer formed in accordance with the present invention is determined by the number of spacer layers used to form the spacer.
- the present invention addresses and solves the problems associated with forming spacers of varying widths. Through selective deposition to form spacers of varying width, damage to the thin, dielectric gate insulating layer and substrate is avoided.
Abstract
A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.
Description
- This application is a divisional of U.S. patent application Ser. No. 10/408,689, filed Apr. 7, 2003. The entire disclosure of U.S. patent application Ser. No. 10/408,689 is incorporated herein by reference.
- The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of forming spacers with different widths on a semiconductor substrate.
- Fabricating integrated circuits with faster and/or an increasing number of semiconductor devices is a continuing trend in integrated circuit technology. A very influential factor in this trend is technology scaling, i.e., the reduction in transistor feature sizes. Technology scaling has enabled transistors to become smaller, thus allowing for more dense integrated circuits in terms of the number of transistors packed on a chip.
- At virtually the same time that transistors are becoming smaller, chip sizes have been increasing in size. The chip size increase has, in turn, resulted in transistor driving capability decreases and interconnect parasitics increases. Accordingly, integrated circuits, such as, embedded memory circuits, mixed-mode/RF signal circuits, and System on a Chip (SOC) circuits, must be very carefully designed to meet future speed demands. Design issues which are very critical in the development of such circuits include, for example, transistor architecture. Specifically, careful gate design, transistor sizing, and other such feature parameters are extremely important in order to optimize transistor performance.
- Spacers are commonly used in the fabrication of semiconductor devices and integrated circuits. The spacers may be used, for example, to control transistor gate size, source and drain regions placement or other features. Because variously sized transistors and other features are often required in a particular integrated circuit design, spacers of different widths must be utilized during the fabrication thereof.
- Spacers of different widths are typically formed using conventional etching methods. These etching methods, unfortunately, may damage the thin, dielectric gate insulating layer and substrate. Accordingly, a new method is needed for forming spacers of varying width.
- A method is disclosed herein for forming spacers with different widths on a semiconductor substrate. The method comprises the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.
-
FIGS. 1-7 are cross sectional views illustrating a method for forming spacers with different widths on a semiconductor device according to the present invention. -
FIGS. 1-7 illustrate a method for forming two or more spacers with different widths on a semiconductor device according to the present invention. - Referring to
FIG. 1 , there is illustrated a cross-section of a portion of asemiconductor device 10. Thesemiconductor device 10 includes asubstrate 20 that may be comprised of a semiconductor material, such as single crystal silicon or gallium arsenide. A plurality of features with different line widths are disposed over thesubstrate 20 and may include, for purposes of illustrating the method of the invention and not limitation, afirst gate electrode 30 a of a first length, asecond gate electrode 30 b of a second length, and athird gate electrode 30 c of a third length are disposed over thesubstrate 20. The different gate lengths used in this embodiment of the invention may be provided, for example, to optimize the transistor performance of an embeddedDRAM semiconductor device 10. The gate electrodes 30 a-30 c are electrically insulated from thesubstrate 20 by thin, dielectric gate insulating layers 32 a-32 c. - The gate electrodes 30 a-30 c may be formed from a polysilicon, such as undoped poly, amorphous poly, doped poly, and the like, using conventional forming methods, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). The thin, dielectric gate insulating layers 32 a-32 c, may be formed on the
substrate 20 from an oxide layer using conventional forming methods, such as physical or chemical vapor deposition, prior to the formation of the gate electrodes 30 a-30 c. In another embodiment, the thin, dielectric gate insulating layers may be formed from a nitride layer. - Referring to
FIG. 2 , a first dielectricinsulating spacer layer 40 is formed over thesubstrate 10 and gate electrodes 30 a-30 c using conventional forming methods, such as PVD or CVD. Thefirst spacer layer 40 may be formed from a nitride such as silicon nitride SiN, or an oxide such as silicon oxide SiO2. Thefirst spacer layer 40 may be deposited to a thickness ranging from approximately 500 Å to 1000 Å. - Referring to
FIG. 3 , a first patterned photoresist layer or mask layer (not shown) is provided over thefirst spacer layer 40, and thesemiconductor device 10 is anisotropically etched to define thefirst spacer layer 40 into three spacers 50 a-50 c each having the same width W1, adjacent the side walls of the gate electrodes 30 a-30 c. The anisotropic etch may be performed using a conventional plasma reactive-ion etching method. After etching, the first mask layer is removed. - Referring to
FIG. 4 , spacers of other widths are formed in accordance with the present invention using selective deposition. For example, spacers having a width W2, which is greater than width W1, may be formed by providing asecond mask layer 60 over thespacer 50 a of the first width andadjacent gate electrode 30 a, and then selectively depositing asecond spacer layer 70 over thefirst spacer layer 40 of the twounmasked spacers substrate 20 with a plasma to generate dangling bonds on the surface of thefirst spacer layer 40 of the twounmasked spacers unmasked gate electrodes substrate 20 because these features are made from different materials than thefirst spacer layer 40. After the plasma treatment, thesecond spacer layer 70 may be formed over the substrate using PVD or CVD. Theportions 70 a of thesecond spacer layer 70 overlying thefirst spacer layers 40 of theunmasked spacers first spacer layer 40 and the directly overlyingportions 70 a of thesecond spacer layer 70. However, theportions 70 b of thesecond spacer layer 70 directly overlying the untreated features are easily removed using for example, a wet bench, due to the lack of dangling bonds at the interface thereof. After enlarging thespacers second mask layer 60 may then be removed. -
FIG. 5 illustrates thedevice 10 after removal of the weakly bonded portions of thesecond spacer layer 70. As illustrated, the selective deposition process enlarges thespacers - If spacers having a width W3, which is greater than width W2, are desired, a
third mask layer 80 may be provided over thespacer 50 a of width W1 and itsadjacent gate electrode 30 a andspacer 50 b of width W2 and itsadjacent gate electrode 30 b as illustrated inFIG. 6 . Athird spacer layer 90 is then selectively deposited over the secondspacer layer portions 70 a of theunmasked spacer 50 c using the selective deposition process described above, i.e., treating the substrate with a plasma to generate dangling bonds on the surface of the secondspacer layer portions 70 a of theunmasked spacer 50 c; forming thethird spacer layer 90 over the substrate using PVD or CVD; removing the weakly bondedportions 90 b of thethird spacer layer 90 using a wet bench, and removing thethird mask layer 80, thereby leaving thespacer 50 c enlarged by the firmly bonded thirdspacer layer portions 90 a to a width of W3 as illustrated inFIG. 7 . - The plasma treatment may be performed using conventional CVD processing equipment. The plasma used in this process may comprise an NH3 or N2O plasma, depending upon the composition of the spacer layer to be treated. For example, in one embodiment of the invention where the first spacer layer is composed of SiO2, an NH3 plasma may be used to generate Si—N dangling bonds over the surface of the SiO2 first spacer layer. The second spacer layer will then be formed by depositing SiO2 over the plasma treated first spacer layer. The SiO2 deposition produces an oxygen-rich, silicon oxynitride (SiON) film over the first spacer layer due to the Si—N dangling bonds, the oxygen-rich SiON film forming the second spacer layer. The unwanted portions of the second spacer layer formed over the other features of the device, such as the gate electrodes (made of poly-silicon for example) and the substrate (made of silicon for example), will still be composed of SiO2 because these features do not have dangling bonds. These unwanted SiO2 portions of the second spacer layer are easily removed by solvent selectivity due to the different materials.
- If a third spacer layer is desired, the oxygen-rich SiON film forming the second spacer layer may be treated with an N2O plasma to generate Si—O dangling bonds over the surface of the second spacer layer. Next, the third spacer layer will be formed by depositing SiN over the second spacer layer. The SiN deposition produces a nitrogen-rich, SiON film over the second spacer layer, the nitrogen-rich SiON film forming the third spacer layer. The unwanted portions of the third spacer layer formed over the other features of the device are still composed of SiN. These unwanted portions of the third spacer layer are easily removed by solvent selectivity due to the different materials.
- In a second embodiment of the invention where the first spacer layer is composed of SiN, an N2O plasma may be used to generate Si—O dangling bonds over the surface of the SiN first spacer layer. The second spacer layer will then be formed by depositing SiN over the plasma treated first spacer layer. The SiN deposition produces an nitrogen-rich, silicon oxynitride (SiON) film over the first spacer layer due to the Si—O dangling bonds, the nitrogen-rich SiON film forming the second spacer layer. The unwanted portions of the second spacer layer formed over the other features of the device, such as the gate electrodes and the substrate, will still be composed of SiN because these features do not have dangling bonds. These unwanted SiN portions of the second spacer layer are easily removed by solvent selectivity due to the different materials.
- If a third spacer layer is desired, the nitrogen-rich SiON film forming the second spacer layer is treated with an NH3 plasma to generate Si—N dangling bonds over the surface of the second spacer layer. Next, the third spacer layer will be formed by depositing SiO2 over the second spacer layer. The SiO2 deposition produces an oxygen-rich, SiON film over the second spacer layer, the oxygen-rich SiON film forming the third spacer layer. The unwanted portions of the third spacer layer formed over the other features of the device are still composed of SiO2. These unwanted portions of the third spacer layer are easily removed by solvent selectivity due to the different materials.
- Spacers of increasing widths may be formed by repeating the selective deposition process as many times as desired. The width of a spacer formed in accordance with the present invention is determined by the number of spacer layers used to form the spacer.
- The present invention addresses and solves the problems associated with forming spacers of varying widths. Through selective deposition to form spacers of varying width, damage to the thin, dielectric gate insulating layer and substrate is avoided.
- While the foregoing invention has been described with reference to the above embodiments, various modifications and changes can be made without departing from the spirit of the invention. Accordingly, all such modifications and changes are considered to be within the scope of the appended claims.
Claims (7)
1-24. (canceled)
25. A semiconductor device comprising:
a substrate;
a plurality of spacers disposed on the substrate;
a first number of the spacers formed by a first spacer layer of a first dielectric material, the first spacer having a first width; and
a second number of the spacers defined by the first spacer layer of the first dielectric material and at least a second spacer layer of a second dielectric material, the second spacer having a second width which is different than the first width, the at least second dielectric material comprising one of an oxygen-rich SiON and a nitrogen-rich SiON.
26. The semiconductor device according to claim 25 , wherein the first dielectric material comprises SiO2 and the second dielectric material comprises the oxygen-rich SiON.
27. The semiconductor device according to claim 26 , further comprising a third number of the spacers defined by the first spacer layer of the first dielectric material, the second spacer layer of the second dielectric material, and a third spacer layer of a third dielectric material, the third spacer having a third width which is different than the first and second widths, the third dielectric material comprising the nitrogen-rich SiON.
28. The semiconductor device according to claim 25 , further comprising a third number of the spacers defined by the first spacer layer of the first dielectric material, the second spacer layer of the second dielectric material, and a third spacer layer of a third dielectric material, the third spacer having a third width which is different than the first and second widths, the third dielectric material comprising one of the oxygen-rich SiON and the nitrogen-rich SiON.
29. The semiconductor device according to claim 25 , wherein the first dielectric material comprises SiN and the second dielectric material comprises the nitrogen-rich SiON.
30. The semiconductor device according to claim 29 , further comprising a third number of the spacers defined by the first spacer layer of the first dielectric material, the second spacer layer of the second dielectric material, and a third spacer layer of a third dielectric material, the third spacer having a third width which is different than the first and second widths, the third dielectric material comprising the oxygen-rich SiON.
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US11/206,613 US20060113616A1 (en) | 2003-04-07 | 2005-08-18 | Selective spacer layer deposition method for forming spacers with different widths |
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US10/408,689 US6943077B2 (en) | 2003-04-07 | 2003-04-07 | Selective spacer layer deposition method for forming spacers with different widths |
US11/206,613 US20060113616A1 (en) | 2003-04-07 | 2005-08-18 | Selective spacer layer deposition method for forming spacers with different widths |
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JP5442235B2 (en) * | 2008-11-06 | 2014-03-12 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and semiconductor device |
US8492236B1 (en) * | 2012-01-12 | 2013-07-23 | Globalfoundries Singapore Pte. Ltd. | Step-like spacer profile |
US20150372107A1 (en) * | 2014-06-18 | 2015-12-24 | Stmicroelectronics, Inc. | Semiconductor devices having fins, and methods of forming semiconductor devices having fins |
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US20090189193A1 (en) * | 2006-06-30 | 2009-07-30 | Intel Corporation | Selective spacer formation on transistors of different classes on the same device |
US20110157854A1 (en) * | 2006-06-30 | 2011-06-30 | Giuseppe Curello | Selective spacer formation on transistors of different classes on the same device |
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KR20140069326A (en) * | 2011-09-30 | 2014-06-09 | 도쿄엘렉트론가부시키가이샤 | Multi-layer pattern from alternate ald processes |
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Also Published As
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US20040198060A1 (en) | 2004-10-07 |
CN1328759C (en) | 2007-07-25 |
TWI247361B (en) | 2006-01-11 |
US6943077B2 (en) | 2005-09-13 |
TW200421486A (en) | 2004-10-16 |
CN1542912A (en) | 2004-11-03 |
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