US20060120019A1 - Method of forming a capacitor - Google Patents
Method of forming a capacitor Download PDFInfo
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- US20060120019A1 US20060120019A1 US11/326,018 US32601806A US2006120019A1 US 20060120019 A1 US20060120019 A1 US 20060120019A1 US 32601806 A US32601806 A US 32601806A US 2006120019 A1 US2006120019 A1 US 2006120019A1
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention is directed generally to a capacitor and method for forming a capacitor and, more particularly, to a capacitor and method for forming a capacitor having an electrode formed from a transition metal, a conductive metal-oxide, alloys thereof, or combinations thereof.
- Minimum feature sizes in integrated circuits are sufficiently small that some fabrication processes are no longer effective. For example, in many applications sputter deposition is not effective for filling openings. Furthermore, the smaller dimensions are requiring higher performance from components and devices. For example, greater capacitance is required from small capacitors.
- One way to obtain higher capacitance is to use dielectrics having greater dielectric constants. Often, however, it is necessary to heat the dielectric to high temperatures in order to obtain the higher dielectric constant, and such heating can have adverse effects on the electrodes used to form the capacitor. For example, the electrodes will often oxidize, and the oxide will act as a lower permittivity dielectric in series with a higher permittivity dielectric. As a result, the oxide formed from the electrode will increase the effective distance between the electrodes, thereby decreasing the capacitance.
- the present invention is directed to a capacitor including a first electrode selected from a group consisting of transition metals, conductive metal-oxides, alloys thereof, and combinations thereof.
- the capacitor also includes a second electrode and a dielectric between the first and second electrodes.
- the present invention may be used to form capacitors in integrated circuits, such as those in memory devices and processors.
- the present invention also includes a method of forming a capacitor.
- the method includes forming a first electrode selected from a group consisting of transition metals, conductive metal-oxides, alloys thereof, and combinations thereof.
- the method also includes forming a second electrode and forming a dielectric between the first and second electrodes.
- the present invention solves problems experienced with the prior art because it provides for capacitors having improved physical structures, such as higher capacitance, smaller physical size, and smaller footprint, by utilizing improved dielectric properties, including electrodes that do not form dielectrics during subsequent processing steps.
- FIG. 1 is a cross-sectional view of a capacitor constructed according to the teachings of the present invention
- FIG. 2 is a cross-sectional view of a capacitor in an early stage of fabrication
- FIG. 3 is a cross-sectional view of the capacitor of FIG. 2 after the material forming the first electrode is removed from the top surface of the substrate assembly;
- FIG. 4 is a cross-sectional view of the capacitor of FIG. 3 after a portion of the substrate assembly is removed from around the first electrode;
- FIG. 5 is a cross-sectional view of the capacitor of FIG. 4 after a dielectric and second conductor, including a strap, are formed;
- FIG. 6 is a cross-sectional view of the capacitor of FIG. 5 after an additional layer is formed over the capacitor;
- FIG. 7 is a cross-sectional view of an alternative embodiment of a capacitor wherein the dielectric and second electrode are formed only on the inside of the first electrode;
- FIG. 8 is a cross-sectional view of the capacitor of FIG. 7 after an additional layer and interconnect are formed;
- FIG. 9 is a cross-sectional view of a post capacitor according to the teachings of the present invention.
- FIG. 10 is a cross-sectional view of the capacitor including the first electrode, second electrode, and dielectric are formed from a non-smooth material;
- FIG. 11 is a cross-sectional view of the capacitor of FIG. 10 in an early stage of fabrication after a layer of hemispherical grain polysilicon is formed in the opening;
- FIG. 12 is a cross-sectional view of the capacitor of FIG. 11 after the material forming the first electrode is formed;
- FIG. 13 is a cross-sectional view of the capacitor of FIG. 12 after the substrate is partially removed and after the hemispherical grain polysilicon is removed;
- FIG. 14 is a block diagram of a system including devices constructed according to the teachings of the present invention.
- substrate refers to a structure that is often the lowest layer of semiconductor material in a wafer or die, although in some technologies the substrate is not a semiconductor material.
- substrate assembly shall mean a substrate having one or more layers or structures formed thereon or therein. The substrate assembly may include one or more active or operable portions of a semiconductor device.
- FIG. 1 is a cross-sectional view of a capacitor 10 formed according to the present invention.
- the capacitor 10 includes a first electrode 12 , a second electrode 14 , and a dielectric 16 formed between the first and second electrodes 12 , 14 .
- the capacitor 10 is illustrated as a crown-shaped capacitor, although benefits of the present invention may be realized with capacitors 10 having many forms, including flat capacitors and post capacitors.
- the capacitor 10 may be formed on a substrate assembly 18 , and may include an interconnect 20 to, for example, a doped region 22 .
- the first electrode 12 may be formed from a transition metal, such as Pt, Rh, Ir, Ru, and Pd; from metals that form conductive metal oxides, such as IrO x , RuO x and RhO x (where x ⁇ 4); from conductive oxides; and from alloys of any of those materials.
- the first electrode 12 may also be formed from any combination of the foregoing materials.
- the first electrode 12 may also be formed from other materials that either do not oxidize during the formation of the capacitor 10 , or whose oxidized forms are conductive.
- the second electrode 14 may be formed from any of the materials that may be used for the first electrode 12 . However, because the second electrode 14 is often not exposed to a high temperature processing step, the second electrode 14 may be formed from other materials that may not be suitable for use as the first electrode 12 . Examples of those other materials are conductive metal nitrides, WN, aluminum, TiN, TaN, and polysilicon.
- the dielectric 16 may be formed from a material that will provide a high dielectric constant, such as an insulating transition metal binary, temery, or quarternery oxide.
- the dielectric may be formed by a chemical vapor deposition (CVD) of barium strontium titanate (BST), SrTiO 3 , Sr w Bi x Ta y O z , Ba x Sr l-x TiO 3 where 0 ⁇ x ⁇ 1, or Ta 2 O 5 , followed by heating the dielectric 16 to 400 degrees C. or more in the presence of oxygen-containing ambient, such as O 2 , N 2 O, O 3 , or NO.
- BST barium strontium titanate
- SrTiO 3 Sr w Bi x Ta y O z
- Ba x Sr l-x TiO 3 where 0 ⁇ x ⁇ 1, or Ta 2 O 5
- the substrate assembly 18 may be formed, for example, from borophosphosilicate glass (BPSG), TEOS oxide, SiO 2 , or Si 3 N 4 .
- the interconnect 20 may be formed, for example, from polysilicon, TiN, or tungsten. Alternatively, the interconnect 20 may be omitted and the first electrode 12 may be connected directly to the doped region 22 . Alternatively, the first electrode 12 may be connected to a metal contact or metal line rather than the doped region 22 , or the first electrode 12 may be left floating.
- the substrate assembly 18 may be formed from one or more layers. For example, in the illustrated embodiment a first substrate layer may be formed and planaraized. The first layer may be masked and etched, and the interconnect 20 formed in the first substrate layer. Thereafter, an additional substrate layer may be formed above the first layer and covering the interconnect 20 .
- FIG. 2 is a cross-sectional view of the capacitor 10 in an early stage of fabrication.
- the substrate assembly 18 may be formed from a first substrate layer 24 and a second substrate layer 26 .
- the first substrate layer 24 is formed first, and the interconnect 20 may be formed in the first substrate layer 24 at that time.
- the interconnect 20 may connect the capacitor 10 to another portion 22 of the device in which the capacitor 10 is formed, such as a doped region.
- the second substrate layer 26 may be formed on top of the first substrate layer 24 , and an opening 28 may be formed in the second substrate layer 26 at that time.
- the opening 28 may be formed, for example, by selectively masking the second substrate layer 26 so that only the portion of the second substrate layer 26 where the opening 28 is to be formed is exposed, by selectively and anisotropically etching the second substrate layer 26 to form the opening 28 , and then removing the mask.
- the first electrode 12 may be formed in the opening 28 by, for example, depositing a layer of material that will form the first electrode 12 , masking that layer, etching the material that is to be removed, and removing the mask to leave the first electrode 12 .
- FIG. 3 is a cross-sectional view of the capacitor 10 after the first electrode 12 has been removed from the top surface of the substrate assembly 18 .
- the removal may be performed by, for example, a mechanical abrasion step, such as chemical mechanical planarization (“CMP”).
- CMP chemical mechanical planarization
- a protective material such as photoresist, may be used to fill the opening 28 to prevent materials removed by the CMP from falling into the opening 28 .
- the removal can be performed by a blanket etch back process.
- FIG. 4 is a cross-sectional view of the capacitor 10 after a portion of the substrate assembly 18 has been removed to expose vertical portions of the first electrode 12 .
- the substrate assembly 18 may be removed by, for example, an etch that is selective to the substrate assembly 18 but which does not etch the first electrode 12 .
- the substrate assembly 18 may be etched so that the first electrode 12 remains partially recessed in the substrate assembly 18 , thereby providing structural stability to the capacitor 10 .
- FIG. 5 is a cross-sectional view of the capacitor 10 after the dielectric 16 and a second electrode 14 have been formed over the first electrode 12 , thereby completing the capacitor 10 .
- the dielectric 16 may be formed, for example, by forming a layer of the dielectric 16 on the entire surface, and then selectively removing the dielectric 16 so that it remains only where desired.
- the dielectric 16 may be deposited over the entire surface by sputtering or CVD.
- the dielectric 16 on the first electrode 12 may be masked, such as with photoresist, and the exposed dielectric may be removed with a selective etch. Alternatively, the insulating dielectric 16 need not be removed at all.
- the second electrode 14 may be formed after the dielectric 16 and in a manner similar to that used to form the dielectric 16 .
- the capacitor 10 may include a portion 30 of the second electrode 14 , known as a strap 30 , formed as a contact for connecting the second electrode 14 to another portion of the device in which the capacitor 10 is formed.
- another portion 32 of the second electrode 14 may connect to other capacitors so as to tie several second electrodes together at a common potential, such as ground.
- FIG. 6 is a cross-sectional view of the capacitor 10 after an additional layer 40 is formed over the capacitor 10 .
- the additional layer 40 may be used to separate the capacitor 10 from whatever may be formed above the capacitor 10 .
- the additional layer 40 may be formed, for example, by a CVD process and from the same materials used to form lower layers of the substrate assembly 18 .
- the additional layer 40 may be planarized, such as by CMP, and an interconnect 42 may be formed in the additional layer 40 to connect the second electrode 14 , via the strap 30 , to another portion of the device in which the capacitor 10 is formed.
- FIG. 7 is a cross-sectional view of an alternative embodiment of the capacitor 10 in which the dielectric 16 and the second electrode 14 are formed only within the first electrode 12 .
- the substrate assembly 18 may not be etched as described hereinabove with respect to FIG. 4 .
- the dielectric 16 and second electrode 14 may be formed in a manner similar to the first electrode 12 , such as by CVD followed by mechanical abrasion to remove unwanted material from the top surface of the substrate assembly 18 .
- FIG. 8 is a cross-sectional view of the capacitor 10 illustrated in FIG. 7 after an additional layer 40 has been formed and after an interconnect 42 has been formed connecting the second electrode 14 to another portion of the device in which the capacitor 10 is formed.
- the interconnect 42 is connected to the second electrode 14 without the use of the strap 30 (illustrated in FIGS. 5 and 6 ).
- FIG. 9 is a cross-sectional view of an alternative embodiment of the present invention formed as a post capacitor 10 .
- That embodiment includes the first electrode 12 , the second electrode 14 , and the dielectric 16 formed on a post 50 .
- the post 50 may be formed, for example, by forming a temporary layer on the substrate assembly 18 , forming an opening in the temporary layer, filling the opening with a material to form the post 50 , and removing the temporary layer to leave the post 50 .
- the post 50 may be formed, for example, from polysilicon.
- FIG. 10 is a cross-sectional view of an alternative embodiment of the present invention wherein the first and second electrodes 12 , 14 and the dielectric 16 have a non-smooth surface.
- the non-smooth surfaces increases the surface area of the first and second electrodes 12 , 14 and the dielectric 16 , thereby increasing the capacitance of the capacitor 10 .
- the capacitor 10 may be formed, for example, by using a non-smooth mold, such as hemispherical grain (HSG) polysilicon, on which the first electrode 12 may be formed.
- HSG hemispherical grain
- the first electrode 12 having an inverted hemispherical grain on the side formed on the HSG polysilicon (that is the outside in the illustrated embodiment), and an inverted hemispherical grain on the side opposite that formed on the HSG polysilicon (that is the inside in the illustrated embodiment).
- the mold may be removed and the dielectric 16 and second electrode 14 may be formed over the first electrode 12 , conforming to its non-smooth surface and assuming a similar non-smooth surface.
- the dielectric 16 and the second electrode 14 formed by that process have hemispherical grain on one side and inverted hemispherical grain on another side, in a manner analogous to the first electrode 12 . It is desirable that the first electrode 12 be set into a recess, such as a recessed interconnect 20 , so as to provide structural stability to the first electrode 12 .
- FIG. 11 is a cross-sectional view of the capacitor 10 illustrated in FIG. 10 in an early stage of fabrication wherein a layer of HSG polysilicon 60 is formed in the opening 28 and on the top surface of the substrate assembly 18 .
- the layer of HSG polysilicon 60 may be formed, for example, with a CVD process.
- the interconnect 20 is recessed below the bottom surface of the opening 26 .
- FIG. 12 is a cross-sectional view of the capacitor 10 after a conductive layer that will form the first electrode 12 is formed over the HSG polysilicon 60 .
- HSG polysilicon has a course, grainy surface, and when the layer that will form the first electrode 12 is formed on the HSG polysilicon 60 , that layer conforms to the HSG polysilicon 60 and assumes a similar, non-smooth surface.
- the non-smooth surface of the HSG polysilicon has a surface area that is between about 150% and about 200% greater than the surface area of smooth polysilicon. It is desirable to etch the HSG polysilicon 60 from the recessed interconnect 20 before the layer that will form the first electrode 12 is formed, as is done in the illustrated embodiment.
- the first electrode 12 will be in direct contact with the interconnect 20 . Otherwise, if the HSG polysilicon 60 is between the first conductor 12 and the interconnect 20 , it may oxidize and increase the resistance of between the interconnect 20 and the first electrode 12 . Furthermore, if HSG polysilicon 60 is supporting the first electrode 12 , the first electrode 12 may be damaged or destroyed when the HSG polysilicon 60 in removed in a subsequent fabrication step.
- FIG. 13 is a cross-sectional view of the capacitor 10 after the substrate assembly 18 is partially removed and the HSG polysilicon 60 is removed.
- the partial removal of the substrate assembly 18 exposes the HSG polysilicon 60 , which may then be removed with a selective etch, such as tetra methyl ammonium hydroxide, leaving the first electrode 12 .
- a selective etch such as tetra methyl ammonium hydroxide
- the dielectric 16 and the second electrode 14 may be formed to result in the capacitor illustrated in FIG. 10 .
- the dielectric 16 and second electrode 14 when formed over the first electrode 12 , will also have a grainy surface, thereby increasing their surface areas.
- FIG. 14 is a high level block diagram illustrating a system 61 including a first device 62 , a bus 64 , and a second device 66 .
- the system 61 may be, for example, a memory system or a computer system.
- the first device 62 may be a processor, and the second device 66 may be a memory.
- the first device 62 and the second device 66 may communicate via the bus 64 .
- the first and second devices 62 , 66 may include capacitors 10 , constructed according to the teaching of the present invention.
- the present invention also includes a method of forming structures and devices, such as capacitors.
- the method includes forming a first electrode selected from a group consisting of transition metals, conductive metal-oxides, and alloys thereof.
- the method also includes forming a second electrode and forming a dielectric between the first and second electrodes.
- the method includes many variations, as described in the teachings hereinabove.
- one of the interconnects 22 , 42 may be omitted and the corresponding conductor may be left to “float”.
- the foregoing description and the following claims are intended to cover all such modifications and variations.
Abstract
Methods of forming a capacitor are disclosed. The methods may comprise the steps of forming a substrate assembly and forming a first electrode on the substrate assembly. The first electrode may be formed to include at least one non-smooth surface and may be formed from a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. The methods may also comprise the step of forming a dielectric on the first electrode and an uppermost surface of the substrate assembly, and forming a second electrode on the dielectric. The second electrode may be formed to include at least one non-smooth surface. Also, the dielectric and the second electrode may be formed only within the first electrode.
Description
- The present application is a divisional of copending U.S. patent application Ser. No. 10/299,752, filed Nov. 19, 2002, which is a divisional of U.S. patent application Ser. No. 09/770,699, filed Jan. 26, 2001, and now issued as U.S. Pat. No. 6,960,513, which is a divisional of U.S. patent application Ser. No. 09/286,807, filed Apr. 6, 1999 and now issued as U.S. Pat. No. 6,696,718.
- Not Applicable.
- 1. Field of the Invention
- The present invention is directed generally to a capacitor and method for forming a capacitor and, more particularly, to a capacitor and method for forming a capacitor having an electrode formed from a transition metal, a conductive metal-oxide, alloys thereof, or combinations thereof.
- 2. Description of the Background
- Minimum feature sizes in integrated circuits are sufficiently small that some fabrication processes are no longer effective. For example, in many applications sputter deposition is not effective for filling openings. Furthermore, the smaller dimensions are requiring higher performance from components and devices. For example, greater capacitance is required from small capacitors. One way to obtain higher capacitance is to use dielectrics having greater dielectric constants. Often, however, it is necessary to heat the dielectric to high temperatures in order to obtain the higher dielectric constant, and such heating can have adverse effects on the electrodes used to form the capacitor. For example, the electrodes will often oxidize, and the oxide will act as a lower permittivity dielectric in series with a higher permittivity dielectric. As a result, the oxide formed from the electrode will increase the effective distance between the electrodes, thereby decreasing the capacitance.
- Therefore, the need exists for a capacitor and method for forming capacitors that do not suffer adverse effects when used with dielectrics having high dielectric constants.
- The present invention is directed to a capacitor including a first electrode selected from a group consisting of transition metals, conductive metal-oxides, alloys thereof, and combinations thereof. The capacitor also includes a second electrode and a dielectric between the first and second electrodes. The present invention may be used to form capacitors in integrated circuits, such as those in memory devices and processors.
- The present invention also includes a method of forming a capacitor. The method includes forming a first electrode selected from a group consisting of transition metals, conductive metal-oxides, alloys thereof, and combinations thereof. The method also includes forming a second electrode and forming a dielectric between the first and second electrodes.
- The present invention solves problems experienced with the prior art because it provides for capacitors having improved physical structures, such as higher capacitance, smaller physical size, and smaller footprint, by utilizing improved dielectric properties, including electrodes that do not form dielectrics during subsequent processing steps. Those and other advantages and benefits of the present invention will become apparent from the description of the preferred embodiments hereinbelow.
- For the present invention to be clearly understood and readily practiced, the present invention will be described in conjunction with the following figures, wherein:
-
FIG. 1 is a cross-sectional view of a capacitor constructed according to the teachings of the present invention; -
FIG. 2 is a cross-sectional view of a capacitor in an early stage of fabrication; -
FIG. 3 is a cross-sectional view of the capacitor ofFIG. 2 after the material forming the first electrode is removed from the top surface of the substrate assembly; -
FIG. 4 is a cross-sectional view of the capacitor ofFIG. 3 after a portion of the substrate assembly is removed from around the first electrode; -
FIG. 5 is a cross-sectional view of the capacitor ofFIG. 4 after a dielectric and second conductor, including a strap, are formed; -
FIG. 6 is a cross-sectional view of the capacitor ofFIG. 5 after an additional layer is formed over the capacitor; -
FIG. 7 is a cross-sectional view of an alternative embodiment of a capacitor wherein the dielectric and second electrode are formed only on the inside of the first electrode; -
FIG. 8 is a cross-sectional view of the capacitor ofFIG. 7 after an additional layer and interconnect are formed; -
FIG. 9 is a cross-sectional view of a post capacitor according to the teachings of the present invention; -
FIG. 10 is a cross-sectional view of the capacitor including the first electrode, second electrode, and dielectric are formed from a non-smooth material; -
FIG. 11 is a cross-sectional view of the capacitor ofFIG. 10 in an early stage of fabrication after a layer of hemispherical grain polysilicon is formed in the opening; -
FIG. 12 is a cross-sectional view of the capacitor ofFIG. 11 after the material forming the first electrode is formed; -
FIG. 13 is a cross-sectional view of the capacitor ofFIG. 12 after the substrate is partially removed and after the hemispherical grain polysilicon is removed; and -
FIG. 14 is a block diagram of a system including devices constructed according to the teachings of the present invention. - It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for purposes of clarity, other elements. Those of ordinary skill in the art will recognize that other elements may be desirable. However, because such elements are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements is not provided herein.
- Advantages of the present invention may be realized using a number of structures and technologies, such as doped silicon substrate, silicon-on-insulator, silicon-on-sapphire, and thin film transistor. The term “substrate”, as used herein, refers to a structure that is often the lowest layer of semiconductor material in a wafer or die, although in some technologies the substrate is not a semiconductor material. The term “substrate assembly”, as used herein, shall mean a substrate having one or more layers or structures formed thereon or therein. The substrate assembly may include one or more active or operable portions of a semiconductor device.
-
FIG. 1 is a cross-sectional view of acapacitor 10 formed according to the present invention. Thecapacitor 10 includes afirst electrode 12, asecond electrode 14, and a dielectric 16 formed between the first andsecond electrodes capacitor 10 is illustrated as a crown-shaped capacitor, although benefits of the present invention may be realized withcapacitors 10 having many forms, including flat capacitors and post capacitors. Thecapacitor 10 may be formed on asubstrate assembly 18, and may include aninterconnect 20 to, for example, adoped region 22. - The
first electrode 12 may be formed from a transition metal, such as Pt, Rh, Ir, Ru, and Pd; from metals that form conductive metal oxides, such as IrOx, RuOx and RhOx (where x<4); from conductive oxides; and from alloys of any of those materials. Thefirst electrode 12 may also be formed from any combination of the foregoing materials. Thefirst electrode 12 may also be formed from other materials that either do not oxidize during the formation of thecapacitor 10, or whose oxidized forms are conductive. - The
second electrode 14 may be formed from any of the materials that may be used for thefirst electrode 12. However, because thesecond electrode 14 is often not exposed to a high temperature processing step, thesecond electrode 14 may be formed from other materials that may not be suitable for use as thefirst electrode 12. Examples of those other materials are conductive metal nitrides, WN, aluminum, TiN, TaN, and polysilicon. - The dielectric 16 may be formed from a material that will provide a high dielectric constant, such as an insulating transition metal binary, temery, or quarternery oxide. For example, the dielectric may be formed by a chemical vapor deposition (CVD) of barium strontium titanate (BST), SrTiO3, SrwBixTayOz, BaxSrl-xTiO3 where 0<x<1, or Ta2O5, followed by heating the dielectric 16 to 400 degrees C. or more in the presence of oxygen-containing ambient, such as O2, N2O, O3, or NO.
- The
substrate assembly 18 may be formed, for example, from borophosphosilicate glass (BPSG), TEOS oxide, SiO2, or Si3N4. Theinterconnect 20 may be formed, for example, from polysilicon, TiN, or tungsten. Alternatively, theinterconnect 20 may be omitted and thefirst electrode 12 may be connected directly to the dopedregion 22. Alternatively, thefirst electrode 12 may be connected to a metal contact or metal line rather than the dopedregion 22, or thefirst electrode 12 may be left floating. Thesubstrate assembly 18 may be formed from one or more layers. For example, in the illustrated embodiment a first substrate layer may be formed and planaraized. The first layer may be masked and etched, and theinterconnect 20 formed in the first substrate layer. Thereafter, an additional substrate layer may be formed above the first layer and covering theinterconnect 20. -
FIG. 2 is a cross-sectional view of thecapacitor 10 in an early stage of fabrication. Thesubstrate assembly 18 may be formed from afirst substrate layer 24 and asecond substrate layer 26. Thefirst substrate layer 24 is formed first, and theinterconnect 20 may be formed in thefirst substrate layer 24 at that time. Theinterconnect 20 may connect thecapacitor 10 to anotherportion 22 of the device in which thecapacitor 10 is formed, such as a doped region. Thereafter, thesecond substrate layer 26 may be formed on top of thefirst substrate layer 24, and anopening 28 may be formed in thesecond substrate layer 26 at that time. Theopening 28 may be formed, for example, by selectively masking thesecond substrate layer 26 so that only the portion of thesecond substrate layer 26 where theopening 28 is to be formed is exposed, by selectively and anisotropically etching thesecond substrate layer 26 to form theopening 28, and then removing the mask. Thefirst electrode 12 may be formed in theopening 28 by, for example, depositing a layer of material that will form thefirst electrode 12, masking that layer, etching the material that is to be removed, and removing the mask to leave thefirst electrode 12. -
FIG. 3 is a cross-sectional view of thecapacitor 10 after thefirst electrode 12 has been removed from the top surface of thesubstrate assembly 18. The removal may be performed by, for example, a mechanical abrasion step, such as chemical mechanical planarization (“CMP”). In that example, a protective material, such as photoresist, may be used to fill theopening 28 to prevent materials removed by the CMP from falling into theopening 28. Alternatively, the removal can be performed by a blanket etch back process. -
FIG. 4 is a cross-sectional view of thecapacitor 10 after a portion of thesubstrate assembly 18 has been removed to expose vertical portions of thefirst electrode 12. Thesubstrate assembly 18 may be removed by, for example, an etch that is selective to thesubstrate assembly 18 but which does not etch thefirst electrode 12. Thesubstrate assembly 18 may be etched so that thefirst electrode 12 remains partially recessed in thesubstrate assembly 18, thereby providing structural stability to thecapacitor 10. -
FIG. 5 is a cross-sectional view of thecapacitor 10 after the dielectric 16 and asecond electrode 14 have been formed over thefirst electrode 12, thereby completing thecapacitor 10. The dielectric 16 may be formed, for example, by forming a layer of the dielectric 16 on the entire surface, and then selectively removing the dielectric 16 so that it remains only where desired. In particular, the dielectric 16 may be deposited over the entire surface by sputtering or CVD. The dielectric 16 on thefirst electrode 12 may be masked, such as with photoresist, and the exposed dielectric may be removed with a selective etch. Alternatively, the insulatingdielectric 16 need not be removed at all. Thesecond electrode 14 may be formed after the dielectric 16 and in a manner similar to that used to form the dielectric 16. In contrast to the embodiment illustrated inFIG. 1 , thecapacitor 10 may include aportion 30 of thesecond electrode 14, known as astrap 30, formed as a contact for connecting thesecond electrode 14 to another portion of the device in which thecapacitor 10 is formed. Similarly, anotherportion 32 of thesecond electrode 14 may connect to other capacitors so as to tie several second electrodes together at a common potential, such as ground. -
FIG. 6 is a cross-sectional view of thecapacitor 10 after anadditional layer 40 is formed over thecapacitor 10. Theadditional layer 40 may be used to separate thecapacitor 10 from whatever may be formed above thecapacitor 10. Theadditional layer 40 may be formed, for example, by a CVD process and from the same materials used to form lower layers of thesubstrate assembly 18. Theadditional layer 40 may be planarized, such as by CMP, and aninterconnect 42 may be formed in theadditional layer 40 to connect thesecond electrode 14, via thestrap 30, to another portion of the device in which thecapacitor 10 is formed. -
FIG. 7 is a cross-sectional view of an alternative embodiment of thecapacitor 10 in which the dielectric 16 and thesecond electrode 14 are formed only within thefirst electrode 12. In that embodiment, thesubstrate assembly 18 may not be etched as described hereinabove with respect toFIG. 4 . The dielectric 16 andsecond electrode 14 may be formed in a manner similar to thefirst electrode 12, such as by CVD followed by mechanical abrasion to remove unwanted material from the top surface of thesubstrate assembly 18. -
FIG. 8 is a cross-sectional view of thecapacitor 10 illustrated inFIG. 7 after anadditional layer 40 has been formed and after aninterconnect 42 has been formed connecting thesecond electrode 14 to another portion of the device in which thecapacitor 10 is formed. In the illustrated embodiment, theinterconnect 42 is connected to thesecond electrode 14 without the use of the strap 30 (illustrated inFIGS. 5 and 6 ). -
FIG. 9 is a cross-sectional view of an alternative embodiment of the present invention formed as apost capacitor 10. That embodiment includes thefirst electrode 12, thesecond electrode 14, and the dielectric 16 formed on apost 50. Thepost 50 may be formed, for example, by forming a temporary layer on thesubstrate assembly 18, forming an opening in the temporary layer, filling the opening with a material to form thepost 50, and removing the temporary layer to leave thepost 50. Thepost 50 may be formed, for example, from polysilicon. -
FIG. 10 is a cross-sectional view of an alternative embodiment of the present invention wherein the first andsecond electrodes second electrodes capacitor 10. Thecapacitor 10 may be formed, for example, by using a non-smooth mold, such as hemispherical grain (HSG) polysilicon, on which thefirst electrode 12 may be formed. Such a process results in thefirst electrode 12 having an inverted hemispherical grain on the side formed on the HSG polysilicon (that is the outside in the illustrated embodiment), and an inverted hemispherical grain on the side opposite that formed on the HSG polysilicon (that is the inside in the illustrated embodiment). Thereafter, the mold may be removed and the dielectric 16 andsecond electrode 14 may be formed over thefirst electrode 12, conforming to its non-smooth surface and assuming a similar non-smooth surface. The dielectric 16 and thesecond electrode 14 formed by that process have hemispherical grain on one side and inverted hemispherical grain on another side, in a manner analogous to thefirst electrode 12. It is desirable that thefirst electrode 12 be set into a recess, such as a recessedinterconnect 20, so as to provide structural stability to thefirst electrode 12. -
FIG. 11 is a cross-sectional view of thecapacitor 10 illustrated inFIG. 10 in an early stage of fabrication wherein a layer ofHSG polysilicon 60 is formed in theopening 28 and on the top surface of thesubstrate assembly 18. The layer ofHSG polysilicon 60 may be formed, for example, with a CVD process. Theinterconnect 20 is recessed below the bottom surface of theopening 26. -
FIG. 12 is a cross-sectional view of thecapacitor 10 after a conductive layer that will form thefirst electrode 12 is formed over theHSG polysilicon 60. HSG polysilicon has a course, grainy surface, and when the layer that will form thefirst electrode 12 is formed on theHSG polysilicon 60, that layer conforms to theHSG polysilicon 60 and assumes a similar, non-smooth surface. The non-smooth surface of the HSG polysilicon has a surface area that is between about 150% and about 200% greater than the surface area of smooth polysilicon. It is desirable to etch theHSG polysilicon 60 from the recessedinterconnect 20 before the layer that will form thefirst electrode 12 is formed, as is done in the illustrated embodiment. As a result, thefirst electrode 12 will be in direct contact with theinterconnect 20. Otherwise, if theHSG polysilicon 60 is between thefirst conductor 12 and theinterconnect 20, it may oxidize and increase the resistance of between theinterconnect 20 and thefirst electrode 12. Furthermore, ifHSG polysilicon 60 is supporting thefirst electrode 12, thefirst electrode 12 may be damaged or destroyed when theHSG polysilicon 60 in removed in a subsequent fabrication step. -
FIG. 13 is a cross-sectional view of thecapacitor 10 after thesubstrate assembly 18 is partially removed and theHSG polysilicon 60 is removed. The partial removal of thesubstrate assembly 18 exposes theHSG polysilicon 60, which may then be removed with a selective etch, such as tetra methyl ammonium hydroxide, leaving thefirst electrode 12. Thereafter, the dielectric 16 and thesecond electrode 14 may be formed to result in the capacitor illustrated inFIG. 10 . The dielectric 16 andsecond electrode 14, when formed over thefirst electrode 12, will also have a grainy surface, thereby increasing their surface areas. -
FIG. 14 is a high level block diagram illustrating asystem 61 including afirst device 62, abus 64, and asecond device 66. Thesystem 61 may be, for example, a memory system or a computer system. Thefirst device 62 may be a processor, and thesecond device 66 may be a memory. Thefirst device 62 and thesecond device 66 may communicate via thebus 64. The first andsecond devices capacitors 10, constructed according to the teaching of the present invention. - The present invention also includes a method of forming structures and devices, such as capacitors. The method includes forming a first electrode selected from a group consisting of transition metals, conductive metal-oxides, and alloys thereof. The method also includes forming a second electrode and forming a dielectric between the first and second electrodes. The method includes many variations, as described in the teachings hereinabove.
- Those of ordinary skill in the art will recognize that many modifications and variations of the present invention may be implemented. For example, one of the
interconnects
Claims (22)
1-80. (canceled)
81. A method, comprising:
forming a substrate assembly;
forming a first electrode on the substrate assembly, wherein the first electrode is formed to include at least one non-smooth surface and is formed from a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof;
forming a dielectric on the first electrode and an uppermost surface of the substrate assembly; and
forming a second electrode on the dielectric, wherein the second electrode is formed to include at least one non-smooth surface, and wherein the dielectric and the second electrode are formed only within the first electrode.
82. The method of claim 81 , wherein forming the substrate assembly includes forming a first substrate layer before forming the first electrode.
83. The method of claim 81 , wherein forming a first substrate layer further includes planarizing the deposited material.
84. The method of claim 81 , wherein the method futher comprises forming an additional substrate layer after forming the second electrode.
85. The method of claim 84 , wherein forming the additional substrate layer includes:
planarizing the additional layer; and
forming an interconnect in the additional layer.
86. The method of claim 85 , wherein planarizing the additional layer includes planarizing the additional layer by chemical mechanical polishing.
87. The method of claim 85 , wherein forming the interconnect includes forming the interconnect on the second electrode.
88. The method of claim 87 , wherein forming the interconnect on the second electrode includes forming the interconnect on a strap of the second electrode.
89. The method of claim 81 , wherein forming the first electrode includes forming the first electrode on an interconnect.
90. The method of claim 81 , wherein forming the first electrode includes depositing a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof on the substrate assembly.
91. The method of claim 90 , wherein depositing the material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof includes depositing a transition metal selected from the group consisting of Pt, Rh, Ir, Ru, and Pd.
92. The method of claim 90 , wherein depositing the material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof includes depositing a conductive oxide selected from the group consisting of IrOx, RuOx, and RhOx, wherein x<4.
93. The method of claim 81 , wherein forning the dielectric includes depositing an insulating metal oxide on the first electrode.
94. The method of claim 93 , wherein depositing the insulating metal oxide includes depositing a material selected from the group consisting of barium strontium titanate, SrTiO3, SrwBixTayOz, BaxSrl-xTiO3, where 0<x<1, and Ta2O5.
95. The method of claim 93 , wherein forming the dielectric further comprises heating the insulating metal oxide in the presence of an oxygen-containing ambient.
96. The method of claim 81 , wherein forming the second electrode includes depositing a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof on the dielectric.
97. The method of claim 96 , wherein depositing the material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof on the dielectric includes depositing a transition metal selected from the group consisting of Pt, Rh, Ir, Ru, and Pd on the dielectric.
98. The method of claim 96 , wherein depositing the material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof on the dielectric includes depositing a conductive oxide selected from the group consisting of IrOx, RuOx, and RhOx, wherein x<4.
99. The method of claim 81 , wherein forming the second electrode includes depositing a material selected from the group consisting of conductive metal nitrides, aluminum, and polysilicon on the dielectric.
100. The method of claim 99 , wherein depositing the material on the dielectric includes depositing a conductive metal nitride selected from the group comprising WN, TiN, and TaN on the dielectric.
101. The method of claim 81 , wherein forming the second electrode includes forming a strap.
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2002
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2005
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Also Published As
Publication number | Publication date |
---|---|
US20060097348A1 (en) | 2006-05-11 |
US7091101B2 (en) | 2006-08-15 |
US20030080369A1 (en) | 2003-05-01 |
US20010025974A1 (en) | 2001-10-04 |
US20030100164A1 (en) | 2003-05-29 |
US6689657B2 (en) | 2004-02-10 |
US6919257B2 (en) | 2005-07-19 |
US6960513B2 (en) | 2005-11-01 |
US20020173112A1 (en) | 2002-11-21 |
US7026222B2 (en) | 2006-04-11 |
US6696718B1 (en) | 2004-02-24 |
US20030100163A1 (en) | 2003-05-29 |
US7041570B2 (en) | 2006-05-09 |
US20030057472A1 (en) | 2003-03-27 |
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