US20060125017A1 - Stacked memory cell utilizing negative differential resistance devices - Google Patents

Stacked memory cell utilizing negative differential resistance devices Download PDF

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US20060125017A1
US20060125017A1 US11/345,248 US34524806A US2006125017A1 US 20060125017 A1 US20060125017 A1 US 20060125017A1 US 34524806 A US34524806 A US 34524806A US 2006125017 A1 US2006125017 A1 US 2006125017A1
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Tsu-Jae Liu
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Synopsys Inc
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    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/142—Contactless power supplies, e.g. RF, induction, or IR
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/39—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors

Definitions

  • This invention generally relates to semiconductor memory devices and technology, and in particular to static random access memory (SRAM) devices.
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • the DRAM memory cell consists of a single pass transistor and a capacitor (1T/1C), wherein information is stored in the form of charge on the capacitor.
  • the DRAM cell provides the most compact layout (with area ranging between 4F 2 and 8F 2 , where F is the minimum feature half-pitch defined by lithography), it requires frequent refreshing (typically on the order of once per millisecond) because the charge on the capacitor leaks away at a rate of approximately 10 ⁇ 15 Amperes per cell.
  • Static RAM does not require refreshing and is generally faster than DRAM (approaching 1 ns access times as compared to tens of ns for DRAM).
  • the SRAM cell is more complex, requiring either four n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and two p-channel MOSFETs, or four n-channel MOSFETs and two polycrystalline-silicon (poly-Si) load resistors, resulting in significantly larger cell size (typically greater than >80 F 2 ).
  • MOSFETs metal-oxide-semiconductor field-effect transistors
  • poly-Si polycrystalline-silicon
  • Negative differential resistance (NDR) devices have previously been proposed for compact static memory applications.
  • E. Goto in IRE Trans. Electronic Computers, March 1960, p. 25 disclosed an SRAM cell consisting of two resonant tunneling diodes (RTDs) and a pass transistor.
  • RTDs resonant tunneling diodes
  • the current first increases with increasing applied voltage, reaching a peak value, then decreases with increasing applied voltage over a range of applied voltages, exhibiting negative differential resistance over this range of applied voltages and reaching a minimum (“valley”) value.
  • the current again increases with increasing applied voltage.
  • the current-vs.-voltage characteristic is shaped like the letter “N”.
  • a key figure of merit for NDR devices is the ratio of the peak current to the valley current (PVCR).
  • PVCR peak current to the valley current
  • the PVCR of RTDs is generally not high enough to make it practical for low-power SRAM application, because in order for the RTDs in a Goto cell to have sufficient current drive, the valley current is too large, causing large static power dissipation.
  • RTDs require specialized fabrication process sequences so that the complexity of an integrated RTD/MOSFET SRAM process would be substantially higher than that of a conventional complementary MOS (CMOS) SRAM process, resulting in higher manufacturing cost.
  • CMOS complementary MOS
  • An object of the present invention is to provide a static random access memory (SRAM) cell of significantly smaller size as compared to a conventional six-transistor SRAM cell, while retaining the desirable operating characteristics of the conventional SRAM cell without significant increase in manufacturing cost.
  • SRAM static random access memory
  • the invention provides a semiconductor device comprising an n-channel insulated-gate field-effect transistor (IGFET) including a gate and source/drain electrodes, and two (preferably n-channel) NDR-FETs each including gate and source/drain electrodes, wherein the IGFET and NDR-FET elements are formed on a common substrate, with one of the source/drain electrodes of the IGFET semiconductor element connected to the drain electrode of a first NDR-FET and also to the source electrode of a second NDR-FET, the gate electrode of the IGFET connected to a first control terminal, the other one of the source/drain electrodes of the IGFET connected to a second control terminal, the drain electrode of the first NDR-FET connected to a power-supply terminal, the source electrode of the second NDR-FET connected to a grounded or negatively-biased terminal, and the gate electrodes of the NDR-FETs each biased at a constant voltage.
  • IGFET n-channel insulated-gate field-effect
  • the first NDR-FET, the second NDR-FET, and the IGFET access transistor that make up the SRAM cell can be formed in two or more semiconductor layers in a stacked configuration, thereby reducing the layout area requirements of the SRAM cell.
  • the first NDR-FET, the second NDR-FET, and the IGFET access transistor can be formed in two different semiconductor layers, such that one of the first and second NDR-FETs and the IGFET access transistor overlies another of the first and second NDR-FETs and the IGFET access transistor.
  • the first and second NDR-FETs and the IGFET access transistor can each be formed in a different semiconductor layer, such that the three transistors are arranged one above another (e.g., the first NDR-FET overlies the IGFET access transistor, and the second NDR-FET overlies the first NDR-FET).
  • FIG. 1 is a circuit diagram of a static random access memory (SRAM) cell consisting of the combination of two NDR-FET elements which form a bistable latch and one n-channel enhancement-mode IGFET access element;
  • SRAM static random access memory
  • FIG. 2 is a plot of the current vs. storage node voltage characteristic of the bistable latch formed by the combination of two NDR-FETs as shown in FIG. 1 ;
  • FIG. 3 is a schematic cross-sectional view of an NDR-FET element connected to an IGFET, showing the various layers shared by the two elements which are co-fabricated using a single process flow.
  • FIGS. 4A and 4B are cross-sectional views of SRAM cells consisting of the combination of two NDR-FET elements and one n-channel enhancement-mode IGFET access element formed in multiple stacked semiconductor layers.
  • FIG. 1 is a circuit diagram of a preferred embodiment of a static memory (SRAM) cell 100 consisting of two NDR-FET elements 120 , 130 which form a bistable latch 140 and one enhancement-mode IGFET access element 110 .
  • FIG. 2 is a current vs. storage node voltage plot illustrating the operational characteristics of the static memory cell of FIG. 1 .
  • the NDR-FET element of the present invention is preferably of the type disclosed in the following King et al. applications: Ser. No.
  • IGFET 110 is configured as a transfer gate, allowing a BIT line to be connected to a storage node under the control of a WORD line.
  • One of the source/drain electrodes of IGFET 110 is connected to the storage node at potential V SN , the other source/drain electrode of IGFET 110 is connected to the BIT line, and the gate electrode of IGFET 110 is connected to the WORD line.
  • the source electrode of first NDR-FET 120 is connected to a ground terminal, the gate electrode of first NDR-FET 120 is supplied with first bias voltage V BIAS1 , the drain electrode of the NDR-FET 120 is connected together with the source electrode of a second NDR-FET 130 to the storage node, the gate electrode of second NDR-FET 130 is supplied with a second bias voltage V BIAS2 and the drain electrode of second NDR-FET 130 is supplied with a positive voltage V DD .
  • the current flowing in the first NDR-FET, I NDR1 is dependent on the difference between its drain electrode potential and its source electrode potential, V SN , at first increasing rapidly as V SN increases, reaching a peak value when V SN is equal to a critical voltage V NDR1 , and rapidly decreasing to nearly zero as V SN increases beyond the critical voltage V NDR1 .
  • the bias voltage V BIAS1 is sufficiently high so as to ensure that first NDR-FET 120 is turned on for values of V SN ranging from 0 V (ground potential) to V NDR1 .
  • the current flowing in the second NDR-FET, I NDR2 is dependent on the difference between its drain electrode potential and its source electrode potential, V DD ⁇ V SN , at first increasing rapidly as V DD ⁇ V SN increases, reaching a peak value when V DD ⁇ V SN is equal to a critical voltage V NDR2 , and rapidly decreasing to nearly zero as V DD ⁇ V SN increases beyond the critical voltage V NDR2 .
  • the bias voltage V BIAS2 is ideally sufficiently high so as to ensure that second NDR-FET 130 is turned on for values of V DD ⁇ V SN ranging from 0 V (ground potential) to V NDR2 .
  • FIG. 2 shows the current I NDR1 vs. storage node voltage V SN characteristic curve of first NDR-FET 120 obtained by changing the storage node voltage V SN in a range between 0 and V DD , superimposed with the current I NDR2 VS. storage node voltage V SN characteristic curve of second NDR-FET 130 .
  • a stable operating point of circuit 140 is a point where the I NDR1 vs. V SN characteristic curve of the first NDR-FET crosses the the I NDR2 vs. V SN characteristic curve of the second NDR-FET and additionally the characteristic curves I NDR1 and I NDR2 have the same gradient sign (positive or negative). (The crossing point where the characteristic curves I NDR1 and I NDR2 have opposite gradient is not a stable operating point.)
  • circuit 140 is stable when the potential V SN at the storage node is one of two values 0 and V DD as shown in FIG. 2 . Accordingly, the circuit can be used as a bistable memory cell by applying a potential of one of the two values 0 and V DD to the BIT line as a write voltage. If the value of V SN increases slightly above that of the low (0 V) stable operating point, current I NDR1 flowing in first NDR-FET 120 becomes higher than the current I NDR2 flowing in second NDR-FET 130 , causing the value of V SN to be decreased toward 0 V (ground potential), to restore it to that of the stable operating point. Thus first NDR-FET 120 serves as a “pull-down” device.
  • second NDR-FET 130 serves as a “pull-up” device.
  • IGFET 110 is controlled by the WORD line as follows: when the WORD line potential is sufficiently high, IGFET 110 is turned on, connecting the BIT line to the storage node to allow data transfer (reading data from the storage node, or writing data to the storage node); when the WORD line potential is low, IGFET 110 is turned off, so that the storage node is electrically isolated from the BIT line. In this manner, a bistable latch 140 is realized with two series-connected NDR-FET elements, and a compact static memory cell is obtained by integrating latch 140 with a IGFET pass transistor 110 .
  • the peak currents of the NDR-FETs are preferably maximized.
  • the NDR-FET peak current and valley current are controlled by the gate bias voltage applied to the NDR-FET, it is possible to achieve a very low valley current by using a lower gate bias voltage when the SRAM cell is in storage mode to achieve low static power dissipation, and to achieve a very high peak current by using a higher gate bias voltage when the SRAM cell is in read mode to achieve fast read access time.
  • the NDR-FET PVCR can effectively be enhanced by several orders of magnitude.
  • V BIAS2 should ideally be sufficiently high so as to ensure that second (pull-up) NDR-FET 130 is turned on for values of V DD ⁇ V SN ranging from 0 V (ground potential) to V NDR2 . Accordingly, V BIAS2 should ideally be greater than or equal to V DD +V T , where V T . is the threshold voltage of second NDR-FET 130 . If second NDR-FET 130 is substantially an enhancement-mode device (i.e. V T >0 V), then V BIAS2 should be greater than V DD . Thus, a separate power supply voltage or a boosted supply (such as that provided by a charge pump circuit) would be needed. It should be noted that the charge pump circuit would not consume much power, as it would only supply a high voltage, with negligible current.
  • V BIAS1 should be sufficiently high so as to ensure that first (pull-down) NDR-FET 120 is turned on for values of V SN ranging from 0 V (ground potential) to V NDR1 . Therefore, V BIAS1 can be tied or coupled to V DD if desired to reduce constraints on the aforementioned charge pump circuit. Alternatively, V BIAS1 can be tied to V BIAS2 to simplify the cell architecture and layout.
  • FIG. 3 is a schematic cross-sectional view of an NDR-FET element connected to an IGFET, such as would exist in the preferred embodiment.
  • the NDR-FET and IGFET are formed to include and share many common layers, including at least a portion of the gate insulating film, gate film, interlayer insulator and metal, and hence can be readily fabricated together on a single substrate using a single process flow.
  • a common substrate 300 , a common isolation area 310 and common interlayer insulation layers 380 ( 380 ′) are used by NDR-FETs and IGFETs respectively.
  • a single gate electrode layer is used for gates 360 , 360 ′ and a single metal/contact layer 390 , 390 ′.
  • Source/drain regions 370 , 370 ′ are formed at the same time, and a common source/drain region 375 ′ is shared by the NDR-FET and IGFET. This latter region can serve as a storage node for example in the above embodiments.
  • An NDR charge trapping layer 330 is included only within an NDR-FET region, for the reasons set forth in the aforementioned referenced applications.
  • both devices can also share a gate insulation film 340 , 340 ′ in some implementations.
  • FIG. 4A is a schematic cross-sectional view of an SRAM cell 400 A consisting of two NDR-FET elements 411 and 412 , which form a bistable latch, and one enhancement-mode IGFET access element (“transfer element”) 420 .
  • the circuit implemented by SRAM cell 400 A is described above with respect to SRAM cell 100 in FIG. 1 .
  • SRAM cell 400 A depicts an exemplary implementation of SRAM cell 100 in which the devices forming SRAM cell 400 A are formed in a stacked configuration to reduce layout area consumed by SRAM cell 400 A in an actual integrated circuit (IC).
  • IC integrated circuit
  • IGFET access element 420 is formed in a first semiconductor layer 401 - 1
  • NDR-FET elements 411 and 412 are formed in a second semiconductor layer 401 - 2 (separated from first semiconductor layer 401 - 1 by an insulating layer 402 - 1 (e.g., oxide layer)), such that NDR-FET element 411 overlies IGFET access element 420 .
  • IGFET access element 420 includes source/drain regions R 5 and R 6 that are formed in first semiconductor layer 401 - 1 , with a dielectric layer D 3 formed on first semiconductor layer 401 - 1 between source/drain regions R 5 and R 6 , and with a gate G 3 formed on dielectric layer D 3 . Note that IGFET access element 420 is considered to be formed “in” first semiconductor layer 401 - 1 because source/drain regions R 5 and R 6 are formed in first semiconductor layer 401 - 1 (even through dielectric layer D 3 and gate G 3 are actually formed “on” first semiconductor layer 401 - 1 ).
  • NDR-FET element 411 includes a source/drain region R 1 and a source/drain region R 2 that is shared with NDR-FET element 412 .
  • NDR-FET element 411 further includes a dielectric layer D 1 formed on second semiconductor layer 401 - 2 between source/drain regions R 1 and R 2 , and a gate G 1 formed on dielectric layer D 1 .
  • NDR-FET element 412 includes source/drain regions R 2 and R 3 , a dielectric layer D 2 formed on second semiconductor layer 401 - 2 between source/drain regions R 2 and R 3 , and a gate G 2 formed on dielectric layer D 2 .
  • Dielectric layers D 1 and D 2 include charge trapping layers C 1 and C 2 , respectively, that provide the NDR characteristics for NDR-FET elements 411 and 412 described above.
  • a vertical interconnect (plug) 405 A connects source/drain region R 6 of IGFET access element 420 with source/drain region R 2 of NDR-FET elements 411 and 412 and forms a storage node for SRAM cell 400 A.
  • supply voltages V S1 and V S2 (e.g., ground potential and V DD , respectively) are connected across the series-connected NDR-FET elements 411 and 412 , and appropriate bias voltages V BIAS1 and V BIAS2 are supplied to gates G 1 and G 2 , respectively, to cause NDR-FET elements 411 and 412 to exhibit the desired bi-stable latch behavior.
  • gate G 3 and source/drain region R 5 of IGFET access element 420 are coupled to word (read/write) line WORD and a bit (data) line BIT, respectively, to control access and data communications with SRAM cell 400 A.
  • SRAM cell 400 A provides a compact implementation of an SRAM cell. Because NDR-FET element 411 overlies (i.e., is positioned above) IGFET access element 420 , the chip area (i.e., plan view area looking down at the chip) consumed by SRAM cell 400 A is essentially equivalent to a 2T (two transistor) cell. Note that although both NDR-FET elements 411 and 412 are depicted as being formed in the same semiconductor layer 401 - 2 for exemplary purposes (and to simplify manufacturing), any distribution of devices between semiconductor layers 401 - 1 and 401 - 2 can be used to achieve the benefit of the stacked configuration.
  • IGFET access element 420 could be formed in second semiconductor layer 401 - 2 and both NDR-FET elements 411 and 412 could be formed in first semiconductor layer 401 - 1 .
  • IGFET access element 420 could be formed with one of NDR-FET elements 411 and 412 in one of semiconductor layers 401 - 1 and 401 - 2 , with the other NDR-FET element being formed by itself in the other semiconductor layer.
  • Various other configurations will be readily apparent.
  • FIG. 4B is a schematic cross-sectional view of an SRAM cell 400 B consisting of the two NDR-FET elements 411 and 412 and the one enhancement-mode IGFET access element 420 described with respect to SRAM cell 400 A in FIG. 4A .
  • SRAM cell 400 B is formed in three semiconductor layers 401 - 1 , 401 - 2 , and 401 - 3 (which are separated by insulating layers 402 - 1 and 402 - 2 ). Therefore, IGFET access element 420 and NDR-FET elements 411 and 412 can be formed over one another so that SRAM cell 400 A effectively occupies the area of a 1T (one transistor) cell.
  • IGFET access element 420 (which includes source/drain regions R 5 and R 6 , dielectric layer D 3 , and gate G 3 ) is formed in first semiconductor layer 401 - 1 , NDR-FET element 411 (which includes source/drain regions R 1 and R 2 , dielectric layer D 1 (including charge trapping layer C 1 ), and gate GI) is formed in second semiconductor layer 401 - 2 , and NDR-FET element 412 (which includes source/drain regions R 3 and R 4 , dielectric layer D 2 (including charge trapping layer C 2 ), and gate G 2 ) is formed in third semiconductor layer 401 - 3 .
  • SRAM cell 400 B can include any distribution of NDR-FET elements 411 and 412 and IGFET access element 420 among semiconductor layers 401 - 1 , 401 - 2 , and 401 - 3 .
  • a vertical interconnect 405 B connects the source/drain regions R 2 , R 4 , and R 6 of NDR-FET element 412 , NDR-FET element 411 , and IGFET access element 420 , respectively, and forms storage node for SRAM cell 400 B. Because NDR-FET elements 411 and 412 and IGFET access element 420 all overlie one another (i.e., are formed one over the other in a single stack), SRAM cell 400 B implements the circuit of FIG. 1 in an extremely space-efficient manner.

Abstract

A memory cell includes two negative differential resistance (NDR) field effect transistors (FETs) forming a bistable latch, and an access transistor for allowing data to be passed to and from the storage node formed by the bistable latch. By stacking the NDR-FETs and the access transistor in two or more layers, area requirements for the memory cell can be reduced, thereby enabling increased circuit density in an integrated circuit (IC) incorporating the memory cell.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS Related Applications
  • The present application is a continuation-in-part of U.S. patent application Ser. No. 10/827,787, entitled “Method Of Making Memory Cell Utilizing Negative Differential Resistance Devices” filed Apr. 19, 2004 which is a divisional of U.S. patent application Ser. No. 10/029,077, entitled “Memory Cell Using Negative Differential Resistance Field Effect Transistors” filed Dec. 21, 2001, now U.S. Pat. No. 6,724,655.
  • The present application is also related to the following applications, all of which are filed simultaneously with parent application Ser. No. 10/029,077, and which are hereby incorporated by reference as if fully set forth herein:
  • An application Ser. No. 10/028,084 entitled “INSULATED-GATE FIELD-EFFECT TRANSISTOR INTEGRATED WITH NEGATIVE DIFFERENTIAL RESISTANCE (NDR) FET”; Attorney Docket No. PROG 2001-1; and
  • An application Ser. No. 10/028,394 entitled “DUAL MODE FET & LOGIC CIRCUIT HAVING NEGATIVE DIFFERENTIAL RESISTANCE MODE”; Attorney Docket No. PROG 2001-3, now U.S. Pat. No. 6,518,589;
  • An application Ser. No. 10/028,089 entitled “CHARGE PUMP FOR NEGATIVE DIFFERENTIAL RESISTANCE TRANSISTOR” Attorney Docket No. PROG 2001-4, now U.S. Pat. No. 6,594,193;
  • An application Ser. No. 10/028,085 entitled “IMPROVED NEGATIVE DIFFERENTIAL RESISTANCE FIELD EFFECT TRANSISTOR (NDR-FET) & CIRCUITS USING THE SAME”; Attorney Docket No. PROG 2001-5; now U.S. Pat. No. 6,559,470.
    • FIELD OF THE INVENTION
  • This invention generally relates to semiconductor memory devices and technology, and in particular to static random access memory (SRAM) devices.
    • BACKGROUND OF THE INVENTION
  • The rapid growth of the semiconductor industry over the past four decades has largely been enabled by continual advancements in manufacturing technology which have allowed the size of the transistor, the basic building block in integrated circuits (ICs), to be steadily reduced with each new generation of technology. As the transistor size is scaled down, the chip area required for a given circuit is reduced, so that more chips can be manufactured on a single silicon wafer substrate, resulting in lower manufacturing cost per chip; circuit operation speed also improves, because of reduced capacitance and higher transistor current density. State-of-the-art fabrication facilities presently manufacture ICs with minimum transistor feature size smaller than 100 nm, so that microprocessor products with transistor counts approaching 1 billion transistors per chip can be manufactured cost-effectively. High-density semiconductor memory devices have already reached the gigabit scale, led by dynamic random access memory (DRAM) technology. The DRAM memory cell consists of a single pass transistor and a capacitor (1T/1C), wherein information is stored in the form of charge on the capacitor. Although the DRAM cell provides the most compact layout (with area ranging between 4F2 and 8F2, where F is the minimum feature half-pitch defined by lithography), it requires frequent refreshing (typically on the order of once per millisecond) because the charge on the capacitor leaks away at a rate of approximately 10−15 Amperes per cell. This problem is exacerbated by technology scaling, because the transistor leakage current increases with decreasing channel length, and also because a reduction in cell capacitance results in a smaller number of stored charge carriers, so that more frequent refreshing is necessary. Thus, scaling of DRAM technology to much higher densities presents significant technological challenges.
  • Static RAM (SRAM) does not require refreshing and is generally faster than DRAM (approaching 1 ns access times as compared to tens of ns for DRAM). However, the SRAM cell is more complex, requiring either four n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and two p-channel MOSFETs, or four n-channel MOSFETs and two polycrystalline-silicon (poly-Si) load resistors, resulting in significantly larger cell size (typically greater than >80 F2). Innovations which provide significant reductions in SRAM cell size while allowing the SRAM cell to retain its favorable operating characteristics are therefore highly desirable.
  • Negative differential resistance (NDR) devices have previously been proposed for compact static memory applications. E. Goto in IRE Trans. Electronic Computers, March 1960, p. 25 disclosed an SRAM cell consisting of two resonant tunneling diodes (RTDs) and a pass transistor. For a variety of NDR devices including RTDs, the current first increases with increasing applied voltage, reaching a peak value, then decreases with increasing applied voltage over a range of applied voltages, exhibiting negative differential resistance over this range of applied voltages and reaching a minimum (“valley”) value. At yet higher applied voltages, the current again increases with increasing applied voltage. Thus, the current-vs.-voltage characteristic is shaped like the letter “N”. A key figure of merit for NDR devices is the ratio of the peak current to the valley current (PVCR). The higher the value of the PVCR, the more useful the NDR device is for variety of circuit applications. The PVCR of RTDs is generally not high enough to make it practical for low-power SRAM application, because in order for the RTDs in a Goto cell to have sufficient current drive, the valley current is too large, causing large static power dissipation. In addition, RTDs require specialized fabrication process sequences so that the complexity of an integrated RTD/MOSFET SRAM process would be substantially higher than that of a conventional complementary MOS (CMOS) SRAM process, resulting in higher manufacturing cost.
  • Accordingly, there exists a significant need for NDR devices with very high (>106) PVCR which can be easily integrated into a conventional CMOS technology, for compact, low-power, low-cost SRAM.
    • SUMMARY OF THE INVENTION
  • An object of the present invention is to provide a static random access memory (SRAM) cell of significantly smaller size as compared to a conventional six-transistor SRAM cell, while retaining the desirable operating characteristics of the conventional SRAM cell without significant increase in manufacturing cost.
  • For achieving the object, the invention provides a semiconductor device comprising an n-channel insulated-gate field-effect transistor (IGFET) including a gate and source/drain electrodes, and two (preferably n-channel) NDR-FETs each including gate and source/drain electrodes, wherein the IGFET and NDR-FET elements are formed on a common substrate, with one of the source/drain electrodes of the IGFET semiconductor element connected to the drain electrode of a first NDR-FET and also to the source electrode of a second NDR-FET, the gate electrode of the IGFET connected to a first control terminal, the other one of the source/drain electrodes of the IGFET connected to a second control terminal, the drain electrode of the first NDR-FET connected to a power-supply terminal, the source electrode of the second NDR-FET connected to a grounded or negatively-biased terminal, and the gate electrodes of the NDR-FETs each biased at a constant voltage. The point of connection between the drain electrode of the first NDR-FET and the source electrode of the second NDR-FET is the data storage node. This semiconductor device can function as a bistable memory cell, with access to the data storage node provided via the IGFET.
  • In various embodiments, the first NDR-FET, the second NDR-FET, and the IGFET access transistor that make up the SRAM cell can be formed in two or more semiconductor layers in a stacked configuration, thereby reducing the layout area requirements of the SRAM cell. In one embodiment, the first NDR-FET, the second NDR-FET, and the IGFET access transistor can be formed in two different semiconductor layers, such that one of the first and second NDR-FETs and the IGFET access transistor overlies another of the first and second NDR-FETs and the IGFET access transistor. In another embodiment, the first and second NDR-FETs and the IGFET access transistor can each be formed in a different semiconductor layer, such that the three transistors are arranged one above another (e.g., the first NDR-FET overlies the IGFET access transistor, and the second NDR-FET overlies the first NDR-FET).
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a circuit diagram of a static random access memory (SRAM) cell consisting of the combination of two NDR-FET elements which form a bistable latch and one n-channel enhancement-mode IGFET access element;
  • FIG. 2 is a plot of the current vs. storage node voltage characteristic of the bistable latch formed by the combination of two NDR-FETs as shown in FIG. 1;
  • FIG. 3 is a schematic cross-sectional view of an NDR-FET element connected to an IGFET, showing the various layers shared by the two elements which are co-fabricated using a single process flow.
  • FIGS. 4A and 4B are cross-sectional views of SRAM cells consisting of the combination of two NDR-FET elements and one n-channel enhancement-mode IGFET access element formed in multiple stacked semiconductor layers.
    • DETAILED DESCRIPTION OF THE INVENTION
  • A semiconductor device according a preferred embodiment of the invention will now be described with reference to FIGS. 1 and 2. FIG. 1 is a circuit diagram of a preferred embodiment of a static memory (SRAM) cell 100 consisting of two NDR- FET elements 120, 130 which form a bistable latch 140 and one enhancement-mode IGFET access element 110. FIG. 2 is a current vs. storage node voltage plot illustrating the operational characteristics of the static memory cell of FIG. 1. The NDR-FET element of the present invention is preferably of the type disclosed in the following King et al. applications: Ser. No. 09/603,101 entitled “A CMOS-PROCESS COMPATIBLE, TUNABLE NDR (NEGATIVE DIFFERENTIAL RESISTANCE) DEVICE AND METHOD OF OPERATING SAME” now U.S. Pat. No. 6,512,274; and Ser. No. 09/603,102 entitled “CHARGE TRAPPING DEVICE AND METHOD FOR IMPLEMENTING A TRANSISTOR HAVING A NEGATIVE DIFFERENTIAL RESISTANCE MODE” now U.S. Pat. No. 6,479,862; and Ser. No. 09/602,658 entitled “CMOS COMPATIBLE PROCESS FOR MAKING A TUNABLE NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE” now U.S. Pat. No. 6,596,617 all of which were filed Jun. 22, 2000 and which are hereby incorporated by reference as if fully set forth herein.
  • As is shown in FIG. 1, IGFET 110 is configured as a transfer gate, allowing a BIT line to be connected to a storage node under the control of a WORD line. One of the source/drain electrodes of IGFET 110 is connected to the storage node at potential VSN, the other source/drain electrode of IGFET 110 is connected to the BIT line, and the gate electrode of IGFET 110 is connected to the WORD line.
  • The source electrode of first NDR-FET 120 is connected to a ground terminal, the gate electrode of first NDR-FET 120 is supplied with first bias voltage VBIAS1, the drain electrode of the NDR-FET 120 is connected together with the source electrode of a second NDR-FET 130 to the storage node, the gate electrode of second NDR-FET 130 is supplied with a second bias voltage VBIAS2 and the drain electrode of second NDR-FET 130 is supplied with a positive voltage VDD. The current flowing in the first NDR-FET, INDR1, is dependent on the difference between its drain electrode potential and its source electrode potential, VSN, at first increasing rapidly as VSN increases, reaching a peak value when VSN is equal to a critical voltage VNDR1, and rapidly decreasing to nearly zero as VSN increases beyond the critical voltage VNDR1. The bias voltage VBIAS1 is sufficiently high so as to ensure that first NDR-FET 120 is turned on for values of VSN ranging from 0 V (ground potential) to VNDR1. The current flowing in the second NDR-FET, INDR2 is dependent on the difference between its drain electrode potential and its source electrode potential, VDD−VSN, at first increasing rapidly as VDD−VSN increases, reaching a peak value when VDD−VSN is equal to a critical voltage VNDR2, and rapidly decreasing to nearly zero as VDD−VSN increases beyond the critical voltage VNDR2. The bias voltage VBIAS2 is ideally sufficiently high so as to ensure that second NDR-FET 130 is turned on for values of VDD−VSN ranging from 0 V (ground potential) to VNDR2.
  • Next the preferred operation of bistable latch 140 in SRAM cell 100 of FIG. 1 will be described. FIG. 2 shows the current INDR1 vs. storage node voltage VSN characteristic curve of first NDR-FET 120 obtained by changing the storage node voltage VSN in a range between 0 and VDD, superimposed with the current INDR2 VS. storage node voltage VSN characteristic curve of second NDR-FET 130. A stable operating point of circuit 140 is a point where the INDR1 vs. VSN characteristic curve of the first NDR-FET crosses the the INDR2 vs. VSN characteristic curve of the second NDR-FET and additionally the characteristic curves INDR1 and INDR2 have the same gradient sign (positive or negative). (The crossing point where the characteristic curves INDR1 and INDR2 have opposite gradient is not a stable operating point.)
  • Therefore it is understood that circuit 140 is stable when the potential VSN at the storage node is one of two values 0 and VDD as shown in FIG. 2. Accordingly, the circuit can be used as a bistable memory cell by applying a potential of one of the two values 0 and VDD to the BIT line as a write voltage. If the value of VSN increases slightly above that of the low (0 V) stable operating point, current INDR1 flowing in first NDR-FET 120 becomes higher than the current INDR2 flowing in second NDR-FET 130, causing the value of VSN to be decreased toward 0 V (ground potential), to restore it to that of the stable operating point. Thus first NDR-FET 120 serves as a “pull-down” device. If the value of VSN falls slightly below that of the high (VDD) stable operating point, the current INDR2 flowing in second NDR-FET 130 becomes higher than the current INDR1 flowing in first NDR-FET 120, causing the value of VSN to be increased toward VDD, to restore it to that of the stable operating point. Thus second NDR-FET 130 serves as a “pull-up” device.
  • IGFET 110 is controlled by the WORD line as follows: when the WORD line potential is sufficiently high, IGFET 110 is turned on, connecting the BIT line to the storage node to allow data transfer (reading data from the storage node, or writing data to the storage node); when the WORD line potential is low, IGFET 110 is turned off, so that the storage node is electrically isolated from the BIT line. In this manner, a bistable latch 140 is realized with two series-connected NDR-FET elements, and a compact static memory cell is obtained by integrating latch 140 with a IGFET pass transistor 110.
  • It should be noted that in order to achieve low standby current in the SRAM cell, the valley currents of the NDR-FETs (i.e. INDR1 at VSN=VDD and INDR2 at VSN=0V) are preferably minimized, while in order to achieve a fast read access time, the peak currents of the NDR-FETs are preferably maximized. Since the NDR-FET peak current and valley current are controlled by the gate bias voltage applied to the NDR-FET, it is possible to achieve a very low valley current by using a lower gate bias voltage when the SRAM cell is in storage mode to achieve low static power dissipation, and to achieve a very high peak current by using a higher gate bias voltage when the SRAM cell is in read mode to achieve fast read access time. In this aspect, the NDR-FET PVCR can effectively be enhanced by several orders of magnitude.
  • As previously stated, the bias voltage VBIAS2 should ideally be sufficiently high so as to ensure that second (pull-up) NDR-FET 130 is turned on for values of VDD−VSN ranging from 0 V (ground potential) to VNDR2. Accordingly, VBIAS2 should ideally be greater than or equal to VDD+VT, where VT. is the threshold voltage of second NDR-FET 130. If second NDR-FET 130 is substantially an enhancement-mode device (i.e. VT>0 V), then VBIAS2 should be greater than VDD. Thus, a separate power supply voltage or a boosted supply (such as that provided by a charge pump circuit) would be needed. It should be noted that the charge pump circuit would not consume much power, as it would only supply a high voltage, with negligible current.
  • As previously stated, the bias voltage VBIAS1 should be sufficiently high so as to ensure that first (pull-down) NDR-FET 120 is turned on for values of VSN ranging from 0 V (ground potential) to VNDR1. Therefore, VBIAS1 can be tied or coupled to VDD if desired to reduce constraints on the aforementioned charge pump circuit. Alternatively, VBIAS1 can be tied to VBIAS2 to simplify the cell architecture and layout.
  • FIG. 3 is a schematic cross-sectional view of an NDR-FET element connected to an IGFET, such as would exist in the preferred embodiment. The NDR-FET and IGFET are formed to include and share many common layers, including at least a portion of the gate insulating film, gate film, interlayer insulator and metal, and hence can be readily fabricated together on a single substrate using a single process flow. For example, a common substrate 300, a common isolation area 310 and common interlayer insulation layers 380 (380′) are used by NDR-FETs and IGFETs respectively. Furthermore, a single gate electrode layer is used for gates 360, 360′ and a single metal/ contact layer 390, 390′. Source/ drain regions 370, 370′ are formed at the same time, and a common source/drain region 375′ is shared by the NDR-FET and IGFET. This latter region can serve as a storage node for example in the above embodiments. An NDR charge trapping layer 330 is included only within an NDR-FET region, for the reasons set forth in the aforementioned referenced applications. Finally, both devices can also share a gate insulation film 340, 340′ in some implementations.
  • FIG. 4A is a schematic cross-sectional view of an SRAM cell 400A consisting of two NDR- FET elements 411 and 412, which form a bistable latch, and one enhancement-mode IGFET access element (“transfer element”) 420. The circuit implemented by SRAM cell 400A is described above with respect to SRAM cell 100 in FIG. 1. SRAM cell 400A depicts an exemplary implementation of SRAM cell 100 in which the devices forming SRAM cell 400A are formed in a stacked configuration to reduce layout area consumed by SRAM cell 400A in an actual integrated circuit (IC). Specifically, IGFET access element 420 is formed in a first semiconductor layer 401-1, and NDR- FET elements 411 and 412 are formed in a second semiconductor layer 401-2 (separated from first semiconductor layer 401-1 by an insulating layer 402-1 (e.g., oxide layer)), such that NDR-FET element 411 overlies IGFET access element 420.
  • IGFET access element 420 includes source/drain regions R5 and R6 that are formed in first semiconductor layer 401-1, with a dielectric layer D3 formed on first semiconductor layer 401-1 between source/drain regions R5 and R6, and with a gate G3 formed on dielectric layer D3. Note that IGFET access element 420 is considered to be formed “in” first semiconductor layer 401-1 because source/drain regions R5 and R6 are formed in first semiconductor layer 401-1 (even through dielectric layer D3 and gate G3 are actually formed “on” first semiconductor layer 401-1). NDR-FET element 411 includes a source/drain region R1 and a source/drain region R2 that is shared with NDR-FET element 412. NDR-FET element 411 further includes a dielectric layer D1 formed on second semiconductor layer 401-2 between source/drain regions R1 and R2, and a gate G1 formed on dielectric layer D1. Similarly, NDR-FET element 412 includes source/drain regions R2 and R3, a dielectric layer D2 formed on second semiconductor layer 401-2 between source/drain regions R2 and R3, and a gate G2 formed on dielectric layer D2. Dielectric layers D1 and D2 include charge trapping layers C1 and C2, respectively, that provide the NDR characteristics for NDR- FET elements 411 and 412 described above. Finally, a vertical interconnect (plug) 405A connects source/drain region R6 of IGFET access element 420 with source/drain region R2 of NDR- FET elements 411 and 412 and forms a storage node for SRAM cell 400A.
  • As described above with respect to FIG. 1, supply voltages VS1 and VS2 (e.g., ground potential and VDD, respectively) are connected across the series-connected NDR- FET elements 411 and 412, and appropriate bias voltages VBIAS1 and VBIAS2 are supplied to gates G1 and G2, respectively, to cause NDR- FET elements 411 and 412 to exhibit the desired bi-stable latch behavior. As further described above with respect to FIG. 1, gate G3 and source/drain region R5 of IGFET access element 420 are coupled to word (read/write) line WORD and a bit (data) line BIT, respectively, to control access and data communications with SRAM cell 400A.
  • In this manner, SRAM cell 400A provides a compact implementation of an SRAM cell. Because NDR-FET element 411 overlies (i.e., is positioned above) IGFET access element 420, the chip area (i.e., plan view area looking down at the chip) consumed by SRAM cell 400A is essentially equivalent to a 2T (two transistor) cell. Note that although both NDR- FET elements 411 and 412 are depicted as being formed in the same semiconductor layer 401-2 for exemplary purposes (and to simplify manufacturing), any distribution of devices between semiconductor layers 401-1 and 401-2 can be used to achieve the benefit of the stacked configuration. For example, IGFET access element 420 could be formed in second semiconductor layer 401-2 and both NDR- FET elements 411 and 412 could be formed in first semiconductor layer 401-1. Alternatively, IGFET access element 420 could be formed with one of NDR- FET elements 411 and 412 in one of semiconductor layers 401-1 and 401-2, with the other NDR-FET element being formed by itself in the other semiconductor layer. Various other configurations will be readily apparent.
  • Note further that additional area reduction for a 3T SRAM cell can be achived via stacking of all three devices in the cell (i.e., arranging the three transistors one above another). FIG. 4B is a schematic cross-sectional view of an SRAM cell 400B consisting of the two NDR- FET elements 411 and 412 and the one enhancement-mode IGFET access element 420 described with respect to SRAM cell 400A in FIG. 4A. However, unlike SRAM cell 400A, which is formed in two semiconductor layers, SRAM cell 400B is formed in three semiconductor layers 401-1, 401-2, and 401-3 (which are separated by insulating layers 402-1 and 402-2). Therefore, IGFET access element 420 and NDR- FET elements 411 and 412 can be formed over one another so that SRAM cell 400A effectively occupies the area of a 1T (one transistor) cell.
  • For exemplary purposes, IGFET access element 420 (which includes source/drain regions R5 and R6, dielectric layer D3, and gate G3) is formed in first semiconductor layer 401-1, NDR-FET element 411 (which includes source/drain regions R1 and R2, dielectric layer D1 (including charge trapping layer C1), and gate GI) is formed in second semiconductor layer 401-2, and NDR-FET element 412 (which includes source/drain regions R3 and R4, dielectric layer D2 (including charge trapping layer C2), and gate G2) is formed in third semiconductor layer 401-3. Note, however, that in various other embodiments, SRAM cell 400B can include any distribution of NDR- FET elements 411 and 412 and IGFET access element 420 among semiconductor layers 401-1, 401-2, and 401-3. A vertical interconnect 405B connects the source/drain regions R2, R4, and R6 of NDR-FET element 412, NDR-FET element 411, and IGFET access element 420, respectively, and forms storage node for SRAM cell 400B. Because NDR- FET elements 411 and 412 and IGFET access element 420 all overlie one another (i.e., are formed one over the other in a single stack), SRAM cell 400B implements the circuit of FIG. 1 in an extremely space-efficient manner.
  • While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. It will be clearly understood by those skilled in the art that foregoing description is merely by way of example and is not a limitation on the scope of the invention, which may be utilized in many types of integrated circuits made with conventional processing technologies. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. Such modifications and combinations, of course, may use other features that are already known in lieu of or in addition to what is disclosed herein. It is therefore intended that the appended claims encompass any such modifications or embodiments. While such claims have been formulated based on the particular embodiments described herein, it should be apparent the scope of the disclosure herein also applies to any novel and non-obvious feature (or combination thereof) disclosed explicitly or implicitly to one of skill in the art, regardless of whether such relates to the claims as provided below, and whether or not it solves and/or mitigates all of the same technical problems described above. Finally, the applicants further reserve the right to pursue new and/or additional claims directed to any such novel and non-obvious features during the prosecution of the present application (and/or any related applications).

Claims (19)

1. A memory cell comprising:
a first negative differential resistance field effect transistor (NDR-FET);
a second NDR-FET connected in series with the first NDR-FET; and
an access transistor connected between a data line and a junction between the first NDR-FET and the second NDR-FET,
wherein at least one of the first NDR-FET, the second NDR-FET, and the access transistor overlies at least another of the first NDR-FET, the second NDR-FET, and the access transistor.
2. The memory cell of claim 1, wherein the access transistor is formed in a first semiconductor layer,
wherein the first NDR-FET and the second NDR-FET are formed in a second semiconductor layer, the second semiconductor layer overlying the first semiconductor layer, and
wherein one of the first NDR-FET and the second NDR-FET overlies the access transistor.
3. The memory cell of claim 2, wherein the first NDR-FET and the second NDR-FET share a common source/drain region.
4. The memory cell of claim 1, wherein the first NDR-FET and the second NDR-FET are formed in a first semiconductor layer,
wherein the access transistor is formed in a second semiconductor layer, the second semiconductor layer overlying the first semiconductor layer, and
wherein the access transistor overlies one of the first NDR-FET and the second NDR-FET.
5. The memory cell of claim 4, wherein the first NDR-FET and the second NDR-FET share a common source/drain region.
6. The memory cell of claim 1, wherein the first NDR-FET and the access transistor are formed in a first semiconductor layer,
wherein the second NDR-FET is formed in a second semiconductor layer, the second semiconductor layer overlying the first semiconductor layer, and
wherein the second NDR-FET overlies one of the first NDR-FET and the access transistor.
7. The memory cell of claim 1, wherein the first NDR-FET is formed in a first semiconductor layer,
wherein the second NDR-FET and the access transistor are formed in a second semiconductor layer, the second semiconductor layer overlying the first semiconductor layer, and
wherein one of the second NDR-FET and the access transistor overlies the first NDR-FET.
8. The memory cell of claim 1, wherein the first NDR-FET, the second NDR-FET, and the access transistor are arranged one above another.
9. The memory cell of claim 8, wherein the first NDR-FET is formed in a first semiconductor layer,
wherein the second NDR-FET is formed in a second semiconductor layer,
wherein the access transistor is formed in a third semiconductor layer,
wherein the first semiconductor layer overlies the second semiconductor layer, and
wherein the second semiconductor layer overlies the third semiconductor layer.
10. The memory cell of claim 8, wherein the first NDR-FET is formed in a first semiconductor layer,
wherein the second NDR-FET is formed in a second semiconductor layer,
wherein the access transistor is formed in a third semiconductor layer, and
wherein the third semiconductor layer overlies the first semiconductor layer and the second semiconductor layer overlies the third semiconductor layer.
11. The memory cell of claim 8, wherein the first NDR-FET is formed in a first semiconductor layer,
wherein the second NDR-FET is formed in a second semiconductor layer,
wherein the access transistor is formed in a third semiconductor layer, and
wherein the third semiconductor layer overlies the first semiconductor layer and the second semiconductor layer.
12. A method for making a memory cell, the method comprising:
forming a first negative differential resistance (NDR) field effect transistor (FET) in series with a second NDR-FET;
forming an access transistor for connecting a data line to a junction between the first NDR-FET and the second NDR-FET,
wherein at least one of the first NDR-FET, the second NDR-FET, and the access transistor overlies at least another of the first NDR-FET, the second NDR-FET, and the access transistor.
13. The method of claim 12, wherein forming the access transistor comprises forming the access transistor in a first semiconductor layer, the method further comprising:
forming an insulating layer over the access transistor;
forming a second semiconductor layer over the insulating layer, wherein forming the first NDR-FET in series with the second NDR-FET comprises forming the first NDR-FET and the second NDR-FET in the second semiconductor layer such that one of the first NDR-FET and the second NDR-FET overlies the access transistor; and
forming a vertical interconnect between a source/drain region of the access transistor and the junction between the first NDR-FET and the second NDR-FET.
14. The method of claim 13, wherein the junction between the first NDR-FET and the second NDR-FET comprises a shared source/drain region.
15. The method of claim 12, wherein forming the forming the first NDR-FET in series with the second NDR-FET comprises forming the first NDR-FET and the second NDR-FET in a first semiconductor layer, the method further comprising:
creating an insulating layer over the first NDR-FET and the second NDR-FET;
creating a second semiconductor layer over the insulating layer, wherein forming the access transistor comprises forming the access transistor in the second semiconductor layer such that the access transistor overlies one of the first NDR-FET and the second NDR-FET; and
forming a vertical interconnect between a source/drain region of the access transistor and the junction between the first NDR-FET and the second NDR-FET.
16. The method of claim 15, wherein the junction between the first NDR-FET and the second NDR-FET comprises a shared source/drain region.
17. The method of claim 12, wherein forming the access transistor comprises forming the access transistor in a first semiconductor layer, and
wherein forming the first NDR-FET in series with the second NDR-FET comprises:
forming the first NDR-FET in the first semiconductor layer;
creating an insulating layer over the access transistor and the first NDR-FET;
creating a second semiconductor layer over the insulating layer; and
forming the second NDR-FET in the second semiconductor layer,
wherein the second NDR-FET overlies one of the first NDR-FET and the access transistor.
18. The method of claim 12, wherein forming the access transistor comprises forming the access transistor in a first semiconductor layer, and
wherein forming the first NDR-FET in series with the second NDR-FET comprises:
creating a first insulating layer over the access transistor;
creating a second semiconductor layer over the first insulating layer;
forming the first NDR-FET in the second semiconductor layer such that the first NDR-FET overlies the access transistor;
creating a second insulating layer over the first NDR-FET;
creating a third semiconductor layer over the second insulating layer;
forming the second NDR-FET in the third semiconductor layer such that the second NDR-FET overlies the first NDR-FET; and
forming a vertical interconnect connecting a source/drain region of the second NDR-FET, a source/drain region of the first NDR-FET, and a source/drain region of the access transistor.
19. The method of claim 12, wherein forming the first NDR-FET in series with the second NDR-FET comprises:
forming the first NDR-FET in a first semiconductor layer;
creating a first insulating layer over the first NDR-FET;
creating a second semiconductor layer over the first insulating layer;
forming the second NDR-FET in the second semiconductor layer such that the second NDR-FET overlies the first NDR-FET;
creating a second insulating layer over the second NDR-FET;
creating a third semiconductor layer over the second insulating layer, wherein forming the access transistor comprises forming the access transistor in the third semiconductor layer such that the access transistor overlies the second NDR-FET; and
forming a vertical interconnect connecting a source/drain region of the access transistor, a source/drain region of the second NDR-FET, and a source/drain region of the first NDR-FET.
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050093110A1 (en) * 2002-08-21 2005-05-05 Smith Bradley P. Semiconductor device for reducing photovolatic current
US20060108627A1 (en) * 2004-11-24 2006-05-25 Samsung Electronics Co., Ltd. NAND flash memory devices including multi-layer memory cell transistor structures and methods of fabricating the same
US20080067573A1 (en) * 2006-09-14 2008-03-20 Young-Chul Jang Stacked memory and method for forming the same
US20130258746A1 (en) * 2012-03-29 2013-10-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20140264554A1 (en) * 2013-03-15 2014-09-18 Globalfoundries Singapore Pte. Ltd. Back-gated non-volatile memory cell
US20150078066A1 (en) * 2010-11-08 2015-03-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device and driving method of semiconductor memory device
TWI565044B (en) * 2013-03-15 2017-01-01 格羅方德半導體私人有限公司 Back-gated non-volatile memory cell
US20170186770A1 (en) * 2010-11-18 2017-06-29 Monolithic 3D Inc. 3d semiconductor memory device and structure
US11670714B2 (en) 2020-09-23 2023-06-06 Samsung Electronics Co., Ltd. Negative differential resistance device

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6724655B2 (en) * 2000-06-22 2004-04-20 Progressant Technologies, Inc. Memory cell using negative differential resistance field effect transistors
US6611452B1 (en) 2002-04-05 2003-08-26 T-Ram, Inc. Reference cells for TCCT based memory cells
US6864104B2 (en) * 2002-06-28 2005-03-08 Progressant Technologies, Inc. Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects
US6912151B2 (en) * 2002-06-28 2005-06-28 Synopsys, Inc. Negative differential resistance (NDR) based memory device with reduced body effects
US7098472B2 (en) * 2002-06-28 2006-08-29 Progressant Technologies, Inc. Negative differential resistance (NDR) elements and memory device using the same
US6567292B1 (en) 2002-06-28 2003-05-20 Progressant Technologies, Inc. Negative differential resistance (NDR) element and memory with reduced soft error rate
US6853035B1 (en) 2002-06-28 2005-02-08 Synopsys, Inc. Negative differential resistance (NDR) memory device with reduced soft error rate
US6795337B2 (en) * 2002-06-28 2004-09-21 Progressant Technologies, Inc. Negative differential resistance (NDR) elements and memory device using the same
US6847562B2 (en) * 2002-06-28 2005-01-25 Progressant Technologies, Inc. Enhanced read and write methods for negative differential resistance (NDR) based memory device
US7095659B2 (en) * 2002-06-28 2006-08-22 Progressant Technologies, Inc. Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device
US6812084B2 (en) * 2002-12-09 2004-11-02 Progressant Technologies, Inc. Adaptive negative differential resistance device
US6979580B2 (en) * 2002-12-09 2005-12-27 Progressant Technologies, Inc. Process for controlling performance characteristics of a negative differential resistance (NDR) device
US6980467B2 (en) 2002-12-09 2005-12-27 Progressant Technologies, Inc. Method of forming a negative differential resistance device
US6849483B2 (en) * 2002-12-09 2005-02-01 Progressant Technologies, Inc. Charge trapping device and method of forming the same
US6806117B2 (en) * 2002-12-09 2004-10-19 Progressant Technologies, Inc. Methods of testing/stressing a charge trapping device
US7012833B2 (en) * 2002-12-09 2006-03-14 Progressant Technologies, Inc. Integrated circuit having negative differential resistance (NDR) devices with varied peak-to-valley ratios (PVRs)
US7005711B2 (en) * 2002-12-20 2006-02-28 Progressant Technologies, Inc. N-channel pull-up element and logic circuit
US7202596B2 (en) * 2003-06-06 2007-04-10 Electrovac Ag Electron emitter and process of fabrication
KR100665299B1 (en) * 2004-06-10 2007-01-04 서울반도체 주식회사 Luminescent material
KR20070101857A (en) * 2004-12-06 2007-10-17 더 프레지던트 앤드 펠로우즈 오브 하바드 칼리지 Nanoscale wire-based data storage
US7505309B2 (en) * 2005-04-20 2009-03-17 Micron Technology, Inc. Static RAM memory cell with DNR chalcogenide devices and method of forming
US7417451B2 (en) * 2005-10-07 2008-08-26 Synopsys, Inc. Leakage power management with NDR isolation devices
US7266010B2 (en) * 2005-11-28 2007-09-04 Synopsys, Inc. Compact static memory cell with non-volatile storage capability
US7652923B2 (en) * 2007-02-02 2010-01-26 Macronix International Co., Ltd. Semiconductor device and memory and method of operating thereof
DE102008045037B4 (en) * 2008-08-29 2010-12-30 Advanced Micro Devices, Inc., Sunnyvale Static RAM cell structure and multiple contact scheme for connecting dual-channel transistors
US8525146B2 (en) 2010-12-06 2013-09-03 Hewlett-Packard Development Company, L.P. Electrical circuit component
US20170084326A1 (en) * 2014-07-08 2017-03-23 Daniel H. Morris A negative differential resistance based memory
FR3048809B1 (en) * 2016-03-11 2018-03-16 Commissariat A L'energie Atomique Et Aux Energies Alternatives SRAM MEMORY CELL COMPRISING AN N-TFET AND A P-TFET
US11031400B2 (en) * 2018-08-10 2021-06-08 Micron Technology, Inc. Integrated memory comprising secondary access devices between digit lines and primary access devices

Citations (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588736A (en) * 1969-06-30 1971-06-28 Ibm Three-terminal bulk negative resistance device operable in oscillatory and bistable modes
US3974486A (en) * 1975-04-07 1976-08-10 International Business Machines Corporation Multiplication mode bistable field effect transistor and memory utilizing same
US4047974A (en) * 1975-12-30 1977-09-13 Hughes Aircraft Company Process for fabricating non-volatile field effect semiconductor memory structure utilizing implanted ions to induce trapping states
US4143393A (en) * 1977-06-21 1979-03-06 International Business Machines Corporation High field capacitor structure employing a carrier trapping region
US4806998A (en) * 1986-06-30 1989-02-21 Thomson-Csf Heterojunction and dual channel semiconductor field effect transistor or negative transconductive device
US4945393A (en) * 1988-06-21 1990-07-31 At&T Bell Laboratories Floating gate memory circuit and apparatus
US5021841A (en) * 1988-10-14 1991-06-04 University Of Illinois Semiconductor device with controlled negative differential resistance characteristic
US5023836A (en) * 1988-07-20 1991-06-11 Fujitsu Limited Semiconductor memory device
US5032891A (en) * 1989-05-17 1991-07-16 Kabushiki Kaisha Toshiba Semiconductor memory device and manufacturing method thereof
US5084743A (en) * 1990-03-15 1992-01-28 North Carolina State University At Raleigh High current, high voltage breakdown field effect transistor
US5093699A (en) * 1990-03-12 1992-03-03 Texas A & M University System Gate adjusted resonant tunnel diode device and method of manufacture
US5130763A (en) * 1989-01-24 1992-07-14 U.S. Philips Corp. Integrated semiconductor device with an insulated-gate field effect transistor having a negative transconductance zone
US5162880A (en) * 1989-09-27 1992-11-10 Kabushiki Kaisha Toshiba Nonvolatile memory cell having gate insulation film with carrier traps therein
US5189499A (en) * 1990-02-21 1993-02-23 Sony Corporation Charge-coupled device and process of fabrication thereof
US5313117A (en) * 1991-07-22 1994-05-17 Nippon Telegraph And Telephone Corporation Semiconductor logic circuit using two n-type negative resistance devices
US5357134A (en) * 1991-10-31 1994-10-18 Rohm Co., Ltd. Nonvolatile semiconductor device having charge trap film containing silicon crystal grains
US5390145A (en) * 1993-04-15 1995-02-14 Fujitsu Limited Resonance tunnel diode memory
US5442194A (en) * 1994-01-07 1995-08-15 Texas Instruments Incorporated Room-temperature tunneling hot-electron transistor
US5448513A (en) * 1993-12-02 1995-09-05 Regents Of The University Of California Capacitorless DRAM device on silicon-on-insulator substrate
US5455432A (en) * 1994-10-11 1995-10-03 Kobe Steel Usa Diamond semiconductor device with carbide interlayer
US5463234A (en) * 1992-03-31 1995-10-31 Kabushiki Kaisha Toshiba High-speed semiconductor gain memory cell with minimal area occupancy
US5477169A (en) * 1994-06-20 1995-12-19 Motorola Logic circuit with negative differential resistance device
US5523603A (en) * 1990-04-16 1996-06-04 Digital Equipment Corporation Semiconductor device with reduced time-dependent dielectric failures
US5543652A (en) * 1992-08-10 1996-08-06 Hitachi, Ltd. Semiconductor device having a two-channel MISFET arrangement defined by I-V characteristic having a negative resistance curve and SRAM cells employing the same
US5606177A (en) * 1993-10-29 1997-02-25 Texas Instruments Incorporated Silicon oxide resonant tunneling diode structure
US5633178A (en) * 1993-11-29 1997-05-27 Sgs-Thomson Microelectronics S.A. Method of making volatile memory cell with interface charge traps
US5689458A (en) * 1995-06-08 1997-11-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having negative resistance element operated stably with single low power source
US5698997A (en) * 1995-09-28 1997-12-16 Mayo Foundation For Medical Education And Research Resonant tunneling diode structures for functionally complete low power logic
US5705827A (en) * 1991-12-25 1998-01-06 Nec Corporation Tunnel transistor and method of manufacturing same
US5732014A (en) * 1997-02-20 1998-03-24 Micron Technology, Inc. Merged transistor structure for gain memory cell
US5761114A (en) * 1997-02-19 1998-06-02 International Business Machines Corporation Multi-level storage gain cell with stepline
US5770958A (en) * 1996-04-04 1998-06-23 Nippon Telegraph And Telephone Corporation Periodic waveform generating circuit
US5773996A (en) * 1995-05-22 1998-06-30 Nippon Telegraph And Telephone Corporation Multiple-valued logic circuit
US5798965A (en) * 1996-04-12 1998-08-25 Lg Semicon Co., Ltd. Dynamic random access memory having no capacitor and method for fabricating the same
US5804475A (en) * 1994-11-14 1998-09-08 The United States Of America As Represented By The Secretary Of The Navy Method of forming an interband lateral resonant tunneling transistor
US5843812A (en) * 1993-10-28 1998-12-01 Goldstar Electron Co., Ltd. Method of making a PMOSFET in a semiconductor device
US5869845A (en) * 1997-06-26 1999-02-09 Texas Instruments Incorporated Resonant tunneling memory
US5883829A (en) * 1997-06-27 1999-03-16 Texas Instruments Incorporated Memory cell having negative differential resistance devices
US5883549A (en) * 1997-06-20 1999-03-16 Hughes Electronics Corporation Bipolar junction transistor (BJT)--resonant tunneling diode (RTD) oscillator circuit and method
US5895934A (en) * 1997-08-13 1999-04-20 The United States Of America As Represented By The Secretary Of The Army Negative differential resistance device based on tunneling through microclusters, and method therefor
US5903170A (en) * 1997-06-03 1999-05-11 The Regents Of The University Of Michigan Digital logic design using negative differential resistance diodes and field-effect transistors
US5907159A (en) * 1996-11-05 1999-05-25 Electronics And Telecommunications Research Institute Hot electron device and a resonant tunneling hot electron device
US5936265A (en) * 1996-03-25 1999-08-10 Kabushiki Kaisha Toshiba Semiconductor device including a tunnel effect element
US5942952A (en) * 1997-07-30 1999-08-24 Motorola, Inc. VCO with multiple negative differential resistance devices
US5945706A (en) * 1990-10-21 1999-08-31 Lg Semicon Co., Ltd. Memory device
US5959328A (en) * 1996-01-08 1999-09-28 Siemens Aktiengesellschaft Electrically programmable memory cell arrangement and method for its manufacture
US5962864A (en) * 1996-08-16 1999-10-05 Kabushiki Kaisha Toshiba Gated resonant tunneling device and fabricating method thereof
US6015739A (en) * 1997-10-29 2000-01-18 Advanced Micro Devices Method of making gate dielectric for sub-half micron MOS transistors including a graded dielectric constant
US6015978A (en) * 1996-03-01 2000-01-18 Matsushita Electric Industrial Co., Ltd. Resonance tunnel device
US6075265A (en) * 1997-06-27 2000-06-13 Siemens Aktiengesellschaft DRAM cell arrangement and method for its fabrication
US6077760A (en) * 1997-09-04 2000-06-20 National Science Council Structure and method of manufacturing single-crystal silicon carbide/single-crystal silicon heterojunctions with negative differential resistance characteristics
US6084796A (en) * 1996-05-30 2000-07-04 Axon Technologies Corporation Programmable metallization cell structure and method of making same
US6091077A (en) * 1996-10-22 2000-07-18 Matsushita Electric Industrial Co., Ltd. MIS SOI semiconductor device with RTD and/or HET
US6097036A (en) * 1995-03-08 2000-08-01 Hitachi, Llp Semiconductor logic element and apparatus using thereof
US6104631A (en) * 1997-12-17 2000-08-15 National Scientific Corp. Static memory cell with load circuit using a tunnel diode
US6128216A (en) * 1998-05-13 2000-10-03 Micron Technology Inc. High density planar SRAM cell with merged transistors
US6130559A (en) * 1997-04-04 2000-10-10 Board Of Regents Of The University Of Texas System QMOS digital logic circuits
US6150242A (en) * 1998-03-25 2000-11-21 Texas Instruments Incorporated Method of growing crystalline silicon overlayers on thin amorphous silicon oxide layers and forming by method a resonant tunneling diode
US6184539B1 (en) * 1996-11-12 2001-02-06 Micron Technology, Inc. Static memory cell and method of forming static memory cell
US6205054B1 (en) * 1998-12-14 2001-03-20 Global Alliance Inc. Nonvolatile memory
US6222766B1 (en) * 1999-01-12 2001-04-24 International Business Machiness Corporation EEPROM memory cell and method of fabricating the same
US6225165B1 (en) * 1998-05-13 2001-05-01 Micron Technology, Inc. High density SRAM cell with latched vertical transistors
US6246606B1 (en) * 1997-11-13 2001-06-12 Micron Technology, Inc. Memory using insulator traps
US20010005327A1 (en) * 1999-12-22 2001-06-28 Russell Duane Negative resistance device
US20010013621A1 (en) * 1999-12-09 2001-08-16 Kazuo Nakazato Memory Device
US20010019137A1 (en) * 2000-03-06 2001-09-06 Kabushiki Toshiba Semiconductor device and method of manufacturing the same
US6294412B1 (en) * 2000-06-09 2001-09-25 Advanced Micro Devices Silicon based lateral tunneling memory cell
US20010024841A1 (en) * 1998-05-13 2001-09-27 Noble Wendell P. High density vertical sram cell using bipolar latchup induced by gated diode breakdown
US6301147B1 (en) * 1997-12-17 2001-10-09 National Scientific Corporation Electronic semiconductor circuit which includes a tunnel diode
US6303942B1 (en) * 1998-03-17 2001-10-16 Farmer, Ii Kenneth Rudolph Multi-layer charge injection barrier and uses thereof
US6316965B1 (en) * 2000-06-15 2001-11-13 The United States Of America As Represented By The Secretary Of The Navy Non-volatile reprogrammable logic circuits by combining negative differential resistance devices and magnetic devices
US20010053568A1 (en) * 1998-09-24 2001-12-20 Gerald Deboy Method for manufacturing a semiconductor component
US20020000837A1 (en) * 1997-05-30 2002-01-03 Brent Keeth 256 meg dynamic random access memory
US6396731B1 (en) * 2001-03-30 2002-05-28 Taiwan Semiconductor Manufacturing Company, Ltd SRAM cell employing tunnel switched diode
US6404018B1 (en) * 1995-06-21 2002-06-11 Micron Technology, Inc. Static memory cell and method of manufacturing a static memory cell
US20020093030A1 (en) * 2001-01-16 2002-07-18 International Business Machines Corporation T-RAM array having a planar cell structure and method for fabricating the same
US20020100918A1 (en) * 2001-01-26 2002-08-01 Hsu Louis L. T-RAM array having a planar cell structure and method for fabricating the same
US20020109150A1 (en) * 2001-02-13 2002-08-15 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US6479862B1 (en) * 2000-06-22 2002-11-12 Progressant Technologies, Inc. Charge trapping device and method for implementing a transistor having a negative differential resistance mode
US6512274B1 (en) * 2000-06-22 2003-01-28 Progressant Technologies, Inc. CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same
US20030043660A1 (en) * 2001-08-22 2003-03-06 Raytheon Company ,A Delaware Corporation Method and system for generating a memory cell
US6596617B1 (en) * 2000-06-22 2003-07-22 Progressant Technologies, Inc. CMOS compatible process for making a tunable negative differential resistance (NDR) device
US20040026760A1 (en) * 2000-12-21 2004-02-12 Vincent Dessard Ultra-low power basic blocks and their uses
US6724655B2 (en) * 2000-06-22 2004-04-20 Progressant Technologies, Inc. Memory cell using negative differential resistance field effect transistors
US7312487B2 (en) * 2004-08-16 2007-12-25 International Business Machines Corporation Three dimensional integrated circuit

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990003646A1 (en) 1988-09-30 1990-04-05 Dallas Semiconductor Corporation Integrated circuit with compact load elements
JP2773474B2 (en) 1991-08-06 1998-07-09 日本電気株式会社 Semiconductor device
JP3613594B2 (en) 1993-08-19 2005-01-26 株式会社ルネサステクノロジ Semiconductor element and semiconductor memory device using the same
US5773328A (en) 1995-02-28 1998-06-30 Sgs-Thomson Microelectronics, Inc. Method of making a fully-dielectric-isolated fet
EP0747961A3 (en) 1995-06-07 1998-11-11 STMicroelectronics, Inc. Zero-power SRAM with patterned buried oxide isolation
US6229161B1 (en) 1998-06-05 2001-05-08 Stanford University Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches
JP4422914B2 (en) 1999-01-06 2010-03-03 レイセオン カンパニー Analog signal quantization method and apparatus using clock resonant tunneling diode pair
JP3475851B2 (en) 1999-04-28 2003-12-10 日本電気株式会社 Flip-flop circuit
US6366134B1 (en) 1999-09-16 2002-04-02 Texas Instruments Incorporated CMOS dynamic logic circuitry using quantum mechanical tunneling structures
US6440805B1 (en) 2000-02-29 2002-08-27 Mototrola, Inc. Method of forming a semiconductor device with isolation and well regions
US6320784B1 (en) 2000-03-14 2001-11-20 Motorola, Inc. Memory cell and method for programming thereof

Patent Citations (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588736A (en) * 1969-06-30 1971-06-28 Ibm Three-terminal bulk negative resistance device operable in oscillatory and bistable modes
US3974486A (en) * 1975-04-07 1976-08-10 International Business Machines Corporation Multiplication mode bistable field effect transistor and memory utilizing same
US4047974A (en) * 1975-12-30 1977-09-13 Hughes Aircraft Company Process for fabricating non-volatile field effect semiconductor memory structure utilizing implanted ions to induce trapping states
US4143393A (en) * 1977-06-21 1979-03-06 International Business Machines Corporation High field capacitor structure employing a carrier trapping region
US4806998A (en) * 1986-06-30 1989-02-21 Thomson-Csf Heterojunction and dual channel semiconductor field effect transistor or negative transconductive device
US4945393A (en) * 1988-06-21 1990-07-31 At&T Bell Laboratories Floating gate memory circuit and apparatus
US5023836A (en) * 1988-07-20 1991-06-11 Fujitsu Limited Semiconductor memory device
US5021841A (en) * 1988-10-14 1991-06-04 University Of Illinois Semiconductor device with controlled negative differential resistance characteristic
US5130763A (en) * 1989-01-24 1992-07-14 U.S. Philips Corp. Integrated semiconductor device with an insulated-gate field effect transistor having a negative transconductance zone
US5032891A (en) * 1989-05-17 1991-07-16 Kabushiki Kaisha Toshiba Semiconductor memory device and manufacturing method thereof
US5162880A (en) * 1989-09-27 1992-11-10 Kabushiki Kaisha Toshiba Nonvolatile memory cell having gate insulation film with carrier traps therein
US5189499A (en) * 1990-02-21 1993-02-23 Sony Corporation Charge-coupled device and process of fabrication thereof
US5093699A (en) * 1990-03-12 1992-03-03 Texas A & M University System Gate adjusted resonant tunnel diode device and method of manufacture
US5084743A (en) * 1990-03-15 1992-01-28 North Carolina State University At Raleigh High current, high voltage breakdown field effect transistor
US5523603A (en) * 1990-04-16 1996-06-04 Digital Equipment Corporation Semiconductor device with reduced time-dependent dielectric failures
US5945706A (en) * 1990-10-21 1999-08-31 Lg Semicon Co., Ltd. Memory device
US5313117A (en) * 1991-07-22 1994-05-17 Nippon Telegraph And Telephone Corporation Semiconductor logic circuit using two n-type negative resistance devices
US5357134A (en) * 1991-10-31 1994-10-18 Rohm Co., Ltd. Nonvolatile semiconductor device having charge trap film containing silicon crystal grains
US5705827A (en) * 1991-12-25 1998-01-06 Nec Corporation Tunnel transistor and method of manufacturing same
US5463234A (en) * 1992-03-31 1995-10-31 Kabushiki Kaisha Toshiba High-speed semiconductor gain memory cell with minimal area occupancy
US5543652A (en) * 1992-08-10 1996-08-06 Hitachi, Ltd. Semiconductor device having a two-channel MISFET arrangement defined by I-V characteristic having a negative resistance curve and SRAM cells employing the same
US5390145A (en) * 1993-04-15 1995-02-14 Fujitsu Limited Resonance tunnel diode memory
US5843812A (en) * 1993-10-28 1998-12-01 Goldstar Electron Co., Ltd. Method of making a PMOSFET in a semiconductor device
US5606177A (en) * 1993-10-29 1997-02-25 Texas Instruments Incorporated Silicon oxide resonant tunneling diode structure
US5633178A (en) * 1993-11-29 1997-05-27 Sgs-Thomson Microelectronics S.A. Method of making volatile memory cell with interface charge traps
US5448513A (en) * 1993-12-02 1995-09-05 Regents Of The University Of California Capacitorless DRAM device on silicon-on-insulator substrate
US5442194A (en) * 1994-01-07 1995-08-15 Texas Instruments Incorporated Room-temperature tunneling hot-electron transistor
US5477169A (en) * 1994-06-20 1995-12-19 Motorola Logic circuit with negative differential resistance device
US5455432A (en) * 1994-10-11 1995-10-03 Kobe Steel Usa Diamond semiconductor device with carbide interlayer
US5804475A (en) * 1994-11-14 1998-09-08 The United States Of America As Represented By The Secretary Of The Navy Method of forming an interband lateral resonant tunneling transistor
US6097036A (en) * 1995-03-08 2000-08-01 Hitachi, Llp Semiconductor logic element and apparatus using thereof
US5773996A (en) * 1995-05-22 1998-06-30 Nippon Telegraph And Telephone Corporation Multiple-valued logic circuit
US5689458A (en) * 1995-06-08 1997-11-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having negative resistance element operated stably with single low power source
US6404018B1 (en) * 1995-06-21 2002-06-11 Micron Technology, Inc. Static memory cell and method of manufacturing a static memory cell
US5698997A (en) * 1995-09-28 1997-12-16 Mayo Foundation For Medical Education And Research Resonant tunneling diode structures for functionally complete low power logic
US5959328A (en) * 1996-01-08 1999-09-28 Siemens Aktiengesellschaft Electrically programmable memory cell arrangement and method for its manufacture
US6015978A (en) * 1996-03-01 2000-01-18 Matsushita Electric Industrial Co., Ltd. Resonance tunnel device
US5936265A (en) * 1996-03-25 1999-08-10 Kabushiki Kaisha Toshiba Semiconductor device including a tunnel effect element
US5770958A (en) * 1996-04-04 1998-06-23 Nippon Telegraph And Telephone Corporation Periodic waveform generating circuit
US5798965A (en) * 1996-04-12 1998-08-25 Lg Semicon Co., Ltd. Dynamic random access memory having no capacitor and method for fabricating the same
US6261896B1 (en) * 1996-05-16 2001-07-17 Hyundai Electronics Industries Co., Ltd. Memory device and method of forming the same
US6084796A (en) * 1996-05-30 2000-07-04 Axon Technologies Corporation Programmable metallization cell structure and method of making same
US5962864A (en) * 1996-08-16 1999-10-05 Kabushiki Kaisha Toshiba Gated resonant tunneling device and fabricating method thereof
US6091077A (en) * 1996-10-22 2000-07-18 Matsushita Electric Industrial Co., Ltd. MIS SOI semiconductor device with RTD and/or HET
US5907159A (en) * 1996-11-05 1999-05-25 Electronics And Telecommunications Research Institute Hot electron device and a resonant tunneling hot electron device
US6184539B1 (en) * 1996-11-12 2001-02-06 Micron Technology, Inc. Static memory cell and method of forming static memory cell
US5761114A (en) * 1997-02-19 1998-06-02 International Business Machines Corporation Multi-level storage gain cell with stepline
US5732014A (en) * 1997-02-20 1998-03-24 Micron Technology, Inc. Merged transistor structure for gain memory cell
US6130559A (en) * 1997-04-04 2000-10-10 Board Of Regents Of The University Of Texas System QMOS digital logic circuits
US20020000837A1 (en) * 1997-05-30 2002-01-03 Brent Keeth 256 meg dynamic random access memory
US5903170A (en) * 1997-06-03 1999-05-11 The Regents Of The University Of Michigan Digital logic design using negative differential resistance diodes and field-effect transistors
US5883549A (en) * 1997-06-20 1999-03-16 Hughes Electronics Corporation Bipolar junction transistor (BJT)--resonant tunneling diode (RTD) oscillator circuit and method
US5869845A (en) * 1997-06-26 1999-02-09 Texas Instruments Incorporated Resonant tunneling memory
US5953249A (en) * 1997-06-27 1999-09-14 Texas Instruments Incorporated Memory cell having negative differential resistance devices
US6075265A (en) * 1997-06-27 2000-06-13 Siemens Aktiengesellschaft DRAM cell arrangement and method for its fabrication
US5883829A (en) * 1997-06-27 1999-03-16 Texas Instruments Incorporated Memory cell having negative differential resistance devices
US5942952A (en) * 1997-07-30 1999-08-24 Motorola, Inc. VCO with multiple negative differential resistance devices
US5895934A (en) * 1997-08-13 1999-04-20 The United States Of America As Represented By The Secretary Of The Army Negative differential resistance device based on tunneling through microclusters, and method therefor
US6077760A (en) * 1997-09-04 2000-06-20 National Science Council Structure and method of manufacturing single-crystal silicon carbide/single-crystal silicon heterojunctions with negative differential resistance characteristics
US6015739A (en) * 1997-10-29 2000-01-18 Advanced Micro Devices Method of making gate dielectric for sub-half micron MOS transistors including a graded dielectric constant
US6246606B1 (en) * 1997-11-13 2001-06-12 Micron Technology, Inc. Memory using insulator traps
US6104631A (en) * 1997-12-17 2000-08-15 National Scientific Corp. Static memory cell with load circuit using a tunnel diode
US6301147B1 (en) * 1997-12-17 2001-10-09 National Scientific Corporation Electronic semiconductor circuit which includes a tunnel diode
US6303942B1 (en) * 1998-03-17 2001-10-16 Farmer, Ii Kenneth Rudolph Multi-layer charge injection barrier and uses thereof
US6150242A (en) * 1998-03-25 2000-11-21 Texas Instruments Incorporated Method of growing crystalline silicon overlayers on thin amorphous silicon oxide layers and forming by method a resonant tunneling diode
US6225165B1 (en) * 1998-05-13 2001-05-01 Micron Technology, Inc. High density SRAM cell with latched vertical transistors
US20010024841A1 (en) * 1998-05-13 2001-09-27 Noble Wendell P. High density vertical sram cell using bipolar latchup induced by gated diode breakdown
US6128216A (en) * 1998-05-13 2000-10-03 Micron Technology Inc. High density planar SRAM cell with merged transistors
US20010053568A1 (en) * 1998-09-24 2001-12-20 Gerald Deboy Method for manufacturing a semiconductor component
US6205054B1 (en) * 1998-12-14 2001-03-20 Global Alliance Inc. Nonvolatile memory
US6222766B1 (en) * 1999-01-12 2001-04-24 International Business Machiness Corporation EEPROM memory cell and method of fabricating the same
US20010013621A1 (en) * 1999-12-09 2001-08-16 Kazuo Nakazato Memory Device
US6310799B2 (en) * 1999-12-22 2001-10-30 National University Of Ireland, Cork Negative resistance device
US20010005327A1 (en) * 1999-12-22 2001-06-28 Russell Duane Negative resistance device
US6690030B2 (en) * 2000-03-06 2004-02-10 Kabushiki Kaisha Toshiba Semiconductor device with negative differential resistance characteristics
US20010019137A1 (en) * 2000-03-06 2001-09-06 Kabushiki Toshiba Semiconductor device and method of manufacturing the same
US6294412B1 (en) * 2000-06-09 2001-09-25 Advanced Micro Devices Silicon based lateral tunneling memory cell
US6316965B1 (en) * 2000-06-15 2001-11-13 The United States Of America As Represented By The Secretary Of The Navy Non-volatile reprogrammable logic circuits by combining negative differential resistance devices and magnetic devices
US6596617B1 (en) * 2000-06-22 2003-07-22 Progressant Technologies, Inc. CMOS compatible process for making a tunable negative differential resistance (NDR) device
US6512274B1 (en) * 2000-06-22 2003-01-28 Progressant Technologies, Inc. CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same
US6479862B1 (en) * 2000-06-22 2002-11-12 Progressant Technologies, Inc. Charge trapping device and method for implementing a transistor having a negative differential resistance mode
US6724655B2 (en) * 2000-06-22 2004-04-20 Progressant Technologies, Inc. Memory cell using negative differential resistance field effect transistors
US20040026760A1 (en) * 2000-12-21 2004-02-12 Vincent Dessard Ultra-low power basic blocks and their uses
US6870229B2 (en) * 2000-12-21 2005-03-22 Universite Catholique De Louvain Ultra-low power basic blocks and their uses
US20020093030A1 (en) * 2001-01-16 2002-07-18 International Business Machines Corporation T-RAM array having a planar cell structure and method for fabricating the same
US20020100918A1 (en) * 2001-01-26 2002-08-01 Hsu Louis L. T-RAM array having a planar cell structure and method for fabricating the same
US20020109150A1 (en) * 2001-02-13 2002-08-15 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US6396731B1 (en) * 2001-03-30 2002-05-28 Taiwan Semiconductor Manufacturing Company, Ltd SRAM cell employing tunnel switched diode
US20030043660A1 (en) * 2001-08-22 2003-03-06 Raytheon Company ,A Delaware Corporation Method and system for generating a memory cell
US7312487B2 (en) * 2004-08-16 2007-12-25 International Business Machines Corporation Three dimensional integrated circuit

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7238579B2 (en) * 2002-08-21 2007-07-03 Freescale Semiconductor, Inc. Semiconductor device for reducing photovolatic current
US20050093110A1 (en) * 2002-08-21 2005-05-05 Smith Bradley P. Semiconductor device for reducing photovolatic current
US20060108627A1 (en) * 2004-11-24 2006-05-25 Samsung Electronics Co., Ltd. NAND flash memory devices including multi-layer memory cell transistor structures and methods of fabricating the same
US20080067573A1 (en) * 2006-09-14 2008-03-20 Young-Chul Jang Stacked memory and method for forming the same
US7683404B2 (en) * 2006-09-14 2010-03-23 Samsung Electronics Co., Ltd. Stacked memory and method for forming the same
US20150078066A1 (en) * 2010-11-08 2015-03-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device and driving method of semiconductor memory device
US20170186770A1 (en) * 2010-11-18 2017-06-29 Monolithic 3D Inc. 3d semiconductor memory device and structure
US10497713B2 (en) * 2010-11-18 2019-12-03 Monolithic 3D Inc. 3D semiconductor memory device and structure
US20130258746A1 (en) * 2012-03-29 2013-10-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9349722B2 (en) * 2012-03-29 2016-05-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device including a memory cell comprising a D/A converter
US20140264554A1 (en) * 2013-03-15 2014-09-18 Globalfoundries Singapore Pte. Ltd. Back-gated non-volatile memory cell
TWI565044B (en) * 2013-03-15 2017-01-01 格羅方德半導體私人有限公司 Back-gated non-volatile memory cell
US9444041B2 (en) * 2013-03-15 2016-09-13 Globalfoundries Singapore Pte. Ltd. Back-gated non-volatile memory cell
US11670714B2 (en) 2020-09-23 2023-06-06 Samsung Electronics Co., Ltd. Negative differential resistance device

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US6724655B2 (en) 2004-04-20
US20020054502A1 (en) 2002-05-09

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