US20060157688A1 - Methods of forming semiconductor constructions and integrated circuits - Google Patents
Methods of forming semiconductor constructions and integrated circuits Download PDFInfo
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- US20060157688A1 US20060157688A1 US11/351,637 US35163706A US2006157688A1 US 20060157688 A1 US20060157688 A1 US 20060157688A1 US 35163706 A US35163706 A US 35163706A US 2006157688 A1 US2006157688 A1 US 2006157688A1
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- 238000010276 construction Methods 0.000 title claims abstract description 103
- 238000000034 method Methods 0.000 title claims description 52
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 239000000463 material Substances 0.000 claims abstract description 149
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000010703 silicon Substances 0.000 claims description 73
- 229910052710 silicon Inorganic materials 0.000 claims description 72
- 239000013078 crystal Substances 0.000 claims description 47
- 239000002178 crystalline material Substances 0.000 claims description 42
- 229910052732 germanium Inorganic materials 0.000 claims description 41
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 32
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 239000000377 silicon dioxide Substances 0.000 claims description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims description 15
- 239000011521 glass Substances 0.000 claims description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 239000004033 plastic Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 abstract description 15
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 69
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 27
- 239000002019 doping agent Substances 0.000 description 26
- 230000015654 memory Effects 0.000 description 24
- 238000012545 processing Methods 0.000 description 21
- 230000037230 mobility Effects 0.000 description 19
- 239000012634 fragment Substances 0.000 description 11
- 239000003990 capacitor Substances 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 238000002425 crystallisation Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 238000004891 communication Methods 0.000 description 7
- 230000008025 crystallization Effects 0.000 description 7
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- -1 for example Chemical class 0.000 description 6
- 239000001307 helium Substances 0.000 description 6
- 229910052734 helium Inorganic materials 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000001953 recrystallisation Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 230000005670 electromagnetic radiation Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 230000001934 delay Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 238000005224 laser annealing Methods 0.000 description 4
- 229910008310 Si—Ge Inorganic materials 0.000 description 3
- 238000013459 approach Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000006880 cross-coupling reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 230000008520 organization Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 238000007725 thermal activation Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
- H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention includes a TFT-based logic circuit construction. Such construction includes a pair of first transistor devices, and a pair of second transistor devices over the first transistor devices. The first transistor devices have first active regions extending into a first semiconductive material, and the second transistor devices have second active regions extending into a second semiconductive material. At least one of the first and second semiconductive materials can comprise crystalline Si/Ge. The logic construction can comprise NOR circuitry and/or NAND circuitry, as well as higher level logic cells, such as latches. Further, the logic circuit construction can be associated with a semiconductor-on-insulator structure, and on versatile substrates. The invention includes three-dimensional logic cell layout configurations for enhanced wireability and logic cell density, which can lead to enhanced performance.
Description
- This patent resulted from a continuation application of U.S. patent application Ser. No. 11/130,742, which was filed May 17, 2005, and which is hereby incorporated by reference; which resulted from a continuation application of U.S. patent application Ser. No. 10/387,090, which was filed Mar. 11, 2003, issued as U.S. Pat. No. 6,900,667, and is hereby incorporated by reference.
- This disclosure relates generally to integrated circuits. In particular aspects, the invention pertains to logic devices. The logic devices can be utilized in electronic systems; and can be incorporated into, for example, processor devices for computer systems.
- SOI technology differs from traditional bulk semiconductor technologies in that the active semiconductor material of SOI technologies is typically much thinner than that utilized in bulk technologies. The active semiconductor material of SOI technologies will typically be formed as a thin film over an insulating material (typically oxide), with exemplary thicknesses of the semiconductor film being less than or equal to 2000 Å. In contrast, bulk semiconductor material will typically have a thickness of at least about 200 microns. The thin semiconductor of SOI technology can allow higher performance and lower power consumption to be achieved in integrated circuits than can be achieved with similar circuits utilizing bulk materials.
- An exemplary integrated circuit device that can be formed utilizing SOI technologies is a so-called thin film transistor (TFT), with the term “thin film” referring to the thin semiconductor film of the SOI construction. In particular aspects, the semiconductor material of the SOI construction can be silicon, and in such aspects the TFTs can be fabricated using recrystallized amorphous silicon or polycrystalline silicon. The silicon can be supported by an electrically insulative material (such as silicon dioxide), which in turn is supported by an appropriate substrate. Exemplary substrate materials include glass, bulk silicon and metal-oxides (such as, for example, Al2O3). If the semiconductor material comprises silicon, the term SOI is occasionally utilized to refer to a silicon-on-insulator construction, rather than the more general concept of a semiconductor-on-insulator construction. However, it is to be understood that in the context of this disclosure the term SOI refers to semiconductor-on-insulator constructions. Accordingly, the semiconductor material of an SOI construction referred to in the context of this disclosure can comprise other semiconductive materials in addition to, or alternatively to, silicon; including, for example, germanium.
- A problem associated with conventional TFT constructions is that grain boundaries and defects can limit carrier mobilities. Accordingly, carrier mobilities are frequently nearly an order of magnitude lower than they would be in bulk semiconductor devices. High voltage (and therefore high power consumption), and large areas are utilized for the TFTs, and the TFTs exhibit limited performance. TFTs thus have limited commercial application and currently are utilized primarily for large area electronics.
- Various efforts have been made to improve carrier mobility of TFTs. Some improvement is obtained for devices in which silicon is the semiconductor material by utilizing a thermal anneal for grain growth following silicon ion implantation and hydrogen passivation of grain boundaries (see, for example, Yamauchi, N. et al., “Drastically Improved Performance in Poly-Si TFTs with Channel Dimensions Comparable to Grain Size”, IEDM Tech. Digest, 1989, pp. 353-356). Improvements have also been made in devices in which a combination of silicon and germanium is the semiconductor material by optimizing the germanium and hydrogen content of silicon/germanium films (see, for example, King, T. J. et al, “A Low-Temperature (<=550° C.) Silicon-Germanium MOS TFT Technology for Large-Area Electronics”, IEDM Tech. Digest, 1991, pp. 567-570).
- Investigations have shown that nucleation, direction of solidification, and grain growth of silicon crystals can be controlled selectively and preferentially by excimer laser annealing, as well as by lateral scanning continuous wave laser irradiation/anneal for recrystallization (see, for example, Kuriyama, H. et al., “High Mobility Poly-Si TFT by a New Excimer Laser Annealing Method for Large Area Electronics”, IEDM Tech. Digest, 1991, pp. 563-566; Jeon, J. H. et al., “A New Poly-Si TFT with Selectively Doped Channel Fabricated by Novel Excimer Laser Annealing”, IEDM Tech. Digest, 2000, pp. 213-216; Kim, C. H. et al., “A New High -Performance Poly-Si TFT by Simple Excimer Laser Annealing on Selectively Floating a Si Layer”, IEDM Tech. Digest, 2001, pp. 753-756; Hara, A. et al, “Selective Single-Crystalline-Silicon Growth at the Pre-Defined Active Regions of TFTs on a Glass by a Scanning CW Layer Irradiation”, IEDM Tech. Digest, 2000, pp. 209-212; and Hara, A. et al., “High Performance Poly-Si TFTs on a Glass by a Stable Scanning CW Laser Lateral Crystallization”, IEDM Tech. Digest, 2001, pp. 747-750). Such techniques have allowed relatively defect-free large crystals to be grown, with resulting TFTs shown to exhibit carrier mobility over 300 cm2/V-second.
- Another technique which has shown promise for improving carrier mobility is metal-induced lateral recrystallization (MILC), which can be utilized in conjunction with an appropriate high temperature anneal (see, for example, Jagar, S. et al., “Single Grain TFT with SOI CMOS Performance Formed by Metal-Induced-Lateral-Crystallization”, IEDM Tech. Digest, 1999, p. 293-296; and Gu, J. et al., “High Performance Sub-100 nm Si TFT by Pattern-Controlled Crystallization of Thin Channel Layer and High Temperature Annealing”, DRC Conference Digest, 2002, pp. 49-50). A suitable post-recrystallization anneal for improving the film quality within silicon recrystallized by MILC is accomplished by exposing recrystallized material to a temperature of from about 850° C. to about 900° C. under an inert ambient (with a suitable ambient comprising, for example, N2). MILC can allow nearly single crystal silicon grains to be formed in predefined amorphous-silicon islands for device channel regions. Nickel-induced-lateral-recrystallization can allow device properties to approach those of single crystal silicon.
- The carrier mobility of a transistor channel region can be significantly enhanced if the channel region is made of a semiconductor material having a strained crystalline lattice (such as, for example, a silicon/germanium material having a strained lattice, or a silicon material having a strained lattice) formed over a semiconductor material having a relaxed lattice (such as, for example, a silicon/germanium material having a relaxed crystalline lattice). (See, for example, Rim, K. et al., “Strained Si NMOSFETs for High Performance CMOS Technology”, VLSI Tech. Digest, 2001, p. 59-60; Cheng, Z. et al., “SiGe-On-Insulator (SGOI) Substrate Preparation and MOSFET Fabrication for Electron Mobility Evaluation” 2001 IEEE SOI Conference Digest, October 2001, pp. 13-14; Huang, L. J. et al., “Carrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bonding”, VLSI Tech. Digest, 2001, pp. 57-58; and Mizuno, T. et al., “High Performance CMOS Operation of Strained-SOI MOSFETs Using Thin Film SiGe-on-Insulator Substrate”, VLSI Tech. Digest, 2002, p. 106-107.)
- The terms “relaxed crystalline lattice” and “strained crystalline lattice” are utilized to refer to crystalline lattices which are within a defined lattice configuration for the semiconductor material, or perturbed from the defined lattice configuration, respectively. In applications in which the relaxed lattice material comprises silicon/germanium having a germanium concentration of from 10% to 60%, mobility enhancements of 110% for electrons and 60-80% for holes can be accomplished by utilizing a strained lattice material in combination with the relaxed lattice material (see for example, Rim, K. et al., “Characteristics and Device Design of Sub-100 nm Strained SiN and PMOSFETs”, VLSI Tech. Digest, 2002, 00. 98-99; and Huang, L. J. et al., “Carrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bonding”, VLSI Tech. Digest, 2001, pp. 57-58).
- Performance enhancements of standard field effect transistor devices are becoming limited with progressive lithographic scaling in conventional applications. Accordingly, strained-lattice-channeled-field effect transistors on relaxed silicon/germanium offers an opportunity to enhance device performance beyond that achieved through conventional lithographic scaling. IBM recently announced the world's fastest communications chip following the approach of utilizing a strained crystalline lattice over a relaxed crystalline lattice (see, for example, “IBM Builds World's Fastest Communications Microchip”, Reuters U.S. Company News, Feb. 25, 2002; and Markoff, J., “IBM Circuits are Now Faster and Reduce Use of Power”, The New York Times, Feb. 25, 2002).
- Although various techniques have been developed for substantially controlling nucleation and grain growth processes of semiconductor materials, grain orientation control is lacking. Further, the post-anneal treatment utilized in conjunction with MILC can be unsuitable in applications in which a low thermal budget is desired. Among the advantages of the invention described below is that such can allow substantial control of crystal grain orientation within a semiconductor material, while lowering thermal budget requirements relative to conventional methods. Additionally, the quality of the grown crystal formed from a semiconductor material can be improved relative to that of conventional methods.
- In further aspects of the prior art, it is a continuing goal to reduce the area of various semiconductor constructions, especially logic building blocks, while maintaining suitable performance characteristics and wireability. Among the semiconductor constructions for which it would be desired to reduce device area are basic logic building block constructions, such as, for example, NOR constructions and NAND constructions, as well as higher level logic blocks, namely registers or latches, such as, for example, flip-flops. Additionally, it would be desired to improve wireability to reduce interconnect delays, and thereby improve logic device performance.
- In one aspect, the invention encompasses a logic construction. The construction includes a pair of first transistor devices having first active regions extending into a first semiconductive material. The construction also includes a second semiconductive material over the first transistor devices, and a pair of second transistor devices having second active regions extending into the second semiconductive material. At least one of the first and second semiconductive materials comprises Si/Ge, and in particular aspects at least one of the first and second semiconductive materials can be crystalline. Further, the active regions of the pair of first transistor devices within the crystalline Si/Ge material can be within a single crystal of the material. Also, the active regions of the pair of second transistor devices within the crystalline Si/Ge semiconductive material can be within a single crystal of the material. In particular aspects, the logic construction can include a NOR circuit, and in further aspects the construction can comprise a pair of NOR circuits in a cross-coupled latch. In other aspects, the construction can comprise a NAND circuit.
- The logic construction can be incorporated into electronic devices, such as, for example, processor devices and computer systems.
- Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
-
FIG. 1 is a diagrammatic, cross-sectional view of a fragment of a semiconductor construction shown at a preliminary stage of an exemplary process of the present invention. -
FIG. 2 is, a view of theFIG. 1 fragment shown at a processing stage subsequent to that ofFIG. 1 . -
FIG. 3 is a view of theFIG. 1 fragment shown at a processing stage subsequent to that ofFIG. 2 . -
FIG. 4 is. a view of theFIG. 1 fragment shown at a processing stage subsequent to that ofFIG. 3 . -
FIG. 5 is a view of theFIG. 1 fragment shown at a processing stage subsequent to that ofFIG. 4 . -
FIG. 6 is a view of theFIG. 1 fragment shown at a processing stage subsequent to that ofFIG. 5 . -
FIG. 7 is an expanded region of theFIG. 6 fragment shown at a processing stage subsequent to that ofFIG. 6 in accordance with an exemplary embodiment of the present invention, and shows an NMOS device. -
FIG. 8 is a view of theFIG. 7 fragment shown at a processing stage subsequent to that ofFIG. 7 . -
FIG. 9 is a view of an expanded region ofFIG. 6 shown at a processing stage subsequent to that ofFIG. 6 in accordance with an alternative embodiment relative to that ofFIG. 7 , and shows a PMOS device. -
FIG. 10 illustrates a circuit schematic of an exemplary NOR logic construction according to an aspect of the present invention. -
FIG. 11 is a fragmentary, diagrammatic cross-sectional side view of an exemplary NOR logic construction according to an aspect of the present invention. -
FIG. 12 is a diagrammatic top view of the exemplary NOR logic construction ofFIG. 11 , with the cross-section ofFIG. 11 being along the line 11-11 ofFIG. 12 . -
FIG. 13 illustrates a circuit schematic of an exemplary NAND logic construction according to an aspect of the present invention. -
FIG. 14 is a fragmentary, diagrammatic cross-sectional side view of an exemplary NAND logic construction according to an aspect of the present invention. -
FIG. 15 is a diagrammatic top view of the exemplary NAND logic construction ofFIG. 14 , with the cross-section ofFIG. 14 being along the line 14-14 ofFIG. 15 . -
FIG. 16 illustrates a circuit schematic of an exemplary two-NOR cross-coupled latch (flip-flop) logic construction according to an aspect of the present invention. -
FIG. 17 is a diagrammatic, fragmentary, top view of an exemplary two-NOR cross-coupled latch (flip-flop) logic construction according to an aspect of the present invention. -
FIG. 18 is a diagrammatic view of a computer illustrating an exemplary application of the present invention. -
FIG. 19 is a block diagram showing particular features of the motherboard of theFIG. 12 computer. -
FIG. 20 is a high-level block diagram of an electronic system according to an exemplary aspect of the present invention. -
FIG. 21 is a simplified block diagram of an exemplary memory device according to an aspect of the present invention. - The invention pertains to logic devices. Exemplary logic devices are described with reference to
FIGS. 10-17 . Prior to the discussion of the exemplary logic devices, a processing sequence for forming and utilizing preferred TFT-based Si/Ge materials and device structures is described with reference toFIGS. 1-9 . - Referring to
FIG. 1 , a fragment of asemiconductor construction 10 is illustrated at a preliminary processing stage. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. -
Construction 10 comprises a base (or substrate) 12 and aninsulator layer 14 over the base.Base 12 can comprise, for example, one or more of glass, aluminum oxide, silicon dioxide, metal and plastic. Additionally, and/or alternatively,base 12 can comprise a semiconductor material, such as, for example, a silicon wafer. -
Layer 14 comprises an electrically insulative material, and in particular applications can comprise, consist essentially of, or consist of silicon dioxide. In the shown construction,insulator layer 14 is in physical contact withbase 12. It is to be understood, however, that there can be intervening materials and layers provided betweenbase 12 andlayer 14 in other aspects of the invention (not shown). For example, a chemically passive thermally stable material, such as silicon nitride (Si3N4), can be incorporated betweenbase 12 andlayer 14.Layer 14 can have a thickness of, for example, from about 200 nanometers to about 500 nanometers, and can be referred to as a buffer layer. -
Layer 14 preferably has a planarized upper surface. The planarized upper surface can be formed by, for example, chemical-mechanical polishing. - A
layer 16 of semiconductive material is provided overinsulator layer 14. In the shown embodiment,semiconductive material layer 16 is formed in physical contact withinsulator 14.Layer 16 can have a thickness of, for example, from about 5 nanometers to about 10 nanometers.Layer 16 can, for example, comprise, consist essentially of, or consist of either doped or undoped silicon. Iflayer 16 comprises, consists essentially of, or consists of doped silicon, the dopant concentration can be from about 1014 atoms/cm3 to about 1020 atoms/cm3. The dopant can be either n-type or p-type, or a combination of n-type and p-type. - The silicon utilized in
layer 16 can be either polycrystalline silicon or amorphous silicon at the processing stage ofFIG. 1 . It can be advantageous to utilize amorphous silicon in that it is typically easier to deposit a uniform layer of amorphous silicon than to deposit a uniform layer of polycrystalline silicon. - Referring to
FIG. 2 ,material 16 is patterned into a plurality of discrete islands (or blocks) 18. Such can be accomplished utilizing, for example, photoresist (not shown) and photolithographic processing, together with an appropriate etch ofmaterial 16. - A
capping layer 20 is provided overislands 18 and over portions oflayer 14 exposed between the islands.Layer 20 can, for example, comprise, consist essentially of, or consist of one or both of silicon dioxide and silicon.Layer 20 can also comprise multiple layers of silicon dioxide, stress-free silicon oxynitride, and silicon. - After formation of capping
layer 20, small voids (nanovoids) and small crystals are formed in theislands 18. The formation of the voids and crystals can be accomplished byion implanting helium 22 intomaterial 16 and subsequently exposingmaterial 16 to laser-emitted electromagnetic radiation. The helium can aid in formation of the nanovoids; and the nanovoids can in turn aid in crystallization and stress relief within thematerial 16 during exposure to the electromagnetic radiation. The helium can thus allow crystallization to occur at lower thermal budgets than can be achieved without the helium implantation. The helium is preferably implanted selectively intoislands 18 and not into regions between the islands. The exposure ofconstruction 10 to electromagnetic radiation can comprise subjecting the construction to scanned continuous wave laser irradiation while the construction is held at an appropriate elevated temperature (typically from about 300° C. to about 450° C). The exposure to the electromagnetic radiation can complete formation of single crystal seeds withinislands 18. The laser irradiation is scanned along anaxis 24 in the exemplary shown embodiment. - The
capping layer 20 discussed previously is optional, but can beneficially assist in retaining helium withinislands 18 and/or preventing undesirable impurity contamination during the treatment with the laser irradiation. - Referring to
FIG. 3 ,islands 18 are illustrated after voids have been formed therein. Additionally, small crystals (not shown) have also been formed withinislands 18 as discussed above. - Capping layer 20 (
FIG. 2 ) is removed, and subsequently alayer 26 of semiconductive material is formed overislands 18.Layer 26 can comprise, consist essentially of, or consist of silicon and germanium; or alternatively can comprise, consist essentially of, or consist of doped silicon/germanium. The germanium concentration withinlayer 26 can be, for example, from about 10 atomic percent to about 60 atomic percent. In the shown embodiment,layer 26 physicallycontacts islands 18, and also physicallycontacts insulator layer 14 in gaps between the islands.Layer 26 can be formed to a thickness of, for example, from about 50 nanometers to about 100 nanometers, and can be formed utilizing a suitable deposition method, such as, for example, plasma-assisted chemical vapor deposition. - A
capping layer 28 is formed oversemiconductor layer 26. Cappinglayer 28 can comprise, for example, silicon dioxide. Alternatively, cappinglayer 28 can comprise, for example, a combination of silicon dioxide and stress-free silicon oxynitride. Cappinglayer 28 can protect a surface oflayer 26 from particles and contaminants that could otherwise fall onlayer 26. If the processing ofconstruction 10 occurs in an environment in which particle formation and/or incorporation of contaminants is unlikely (for example, an ultrahigh vacuum environment),layer 28 can be eliminated from the process.Layer 28 is utilized in the patterning of a metal (discussed below). Iflayer 28 is eliminated from the process, other methods besides those discussed specifically herein can be utilized for patterning the metal. - Referring to
FIG. 4 ,openings 30 are extended through cappinglayer 28 and to an upper surface ofsemiconductive material 26.Openings 30 can be formed by, for example, photolithographic processing to pattern a layer of photoresist (not shown) into a mask, followed by a suitable etch oflayer 28 and subsequent removal of the photoresist mask. - A
layer 32 of metal-containing material is provided withinopenings 30, and in physical contact with an upper surface ofsemiconductive material 26.Layer 32 can have a thickness of, for example, less than or equal to about 10 nanometers. The material oflayer 32 can comprise, consist essentially of, or consist of, for example, nickel.Layer 32 can be formed by, for example, physical vapor deposition.Layer 32 can be formed to be withinopenings 30 and not over material 28 (as is illustrated inFIG. 4 ) by utilizing deposition conditions which selectively form metal-containinglayer 32 on a surface ofmaterial 26 relative to a surface ofmaterial 28. Alternatively,material 32 can be deposited by a substantially non-selective process to form thematerial 32 over the surface ofmaterial 28 as well as over the surface ofmaterial 26 withinopenings 30, and subsequently material 32 can be selectively removed from over surfaces ofmaterial 28 while remaining withinopenings 30. Such selective removal can be accomplished by, for example, chemical-mechanical polishing, and/or by forming a photoresist mask (not shown) over thematerial 32 withinopenings 30, while leaving other portions ofmaterial 32 exposed, and subsequently removing such other portions to leave only the segments ofmaterial 32 withinopenings 30. The photoresist mask can then be removed. -
Oxygen 34 is ion implanted throughlayers layer 16 to oxidize the material oflayer 16. For instance, iflayer 16 consists of silicon, the oxygen can convert the silicon to silicon dioxide. Such swells the material oflayer 16, and accordingly fills the nanovoids that had been formed earlier. The oxygen preferably only partially oxidizeslayer 16, with the oxidation being sufficient to fill all, or at least substantially all, of the nanovoids; but leaving at least some of the seed crystals withinlayer 16 that had been formed with the laser irradiation discussed previously. In some aspects, the oxidation can convert a lower portion ofmaterial 16 to silicon dioxide while leaving an upper portion ofmaterial 16 as non-oxidized silicon. - The oxygen ion utilized as
implant 34 can comprise, for example, oxygen (O2) or ozone (O3). The oxygen ion implant can occur before or after formation ofopenings 30 and provision of metal-containinglayer 32. -
Construction 10 is exposed to continuous wave laser irradiation while being held at an appropriate temperature (which can be, for example, from about 300° C. to about 450° C.; or in particular applications can be greater than or equal to 550° C.) to cause transformation of at least some oflayer 26 to a crystalline form. The exposure to the laser irradiation comprises exposing the material ofconstruction 10 to laser-emitted electromagnetic radiation scanned along a shownaxis 36. Preferably, theaxis 36 along which the laser irradiation is scanned is the same axis that was utilized for scanning of laser irradiation in the processing stage ofFIG. 2 . - The crystallization of material 26 (which can also be referred to as a recrystallization of the material) is induced utilizing metal-containing
layer 32, and accordingly corresponds to an application of MILC. The MILC transformsmaterial 26 to a crystalline form and the seed layer provides the crystallographic orientation while undergoing partial oxidation. - The crystal orientation within crystallized
layer 26 can originate from the crystals initially formed inislands 18. Accordingly, crystal orientations formed withinlayer 26 can be controlled through control of the crystal orientations formed within thesemiconductive material 16 ofislands 18. - The oxidation of part of
material 16 which was described previously can occur simultaneously with the MILC arising from continuous wave laser irradiation. Partial oxidation ofseed layer 16 facilitates: (1) Ge enrichment into Si—Ge layer 26 (which improves carrier mobility); (2) stress-relief of Si—Ge layer 26; and (3) enhancement of recrystallization of Si—Ge layer 26. The crystallization ofmaterial 26 can be followed by an anneal ofmaterial 26 at a temperature of, for example, about 900° C. for a time of about 30 minutes, or by an appropriate rapid thermal anneal, to further ensure relaxed, defect-free crystallization ofmaterial 26. The annealing option can be dependent on the thermal stability of the material selected forsubstrate 12. -
FIG. 5 showsconstruction 10 after the processing described above with reference toFIG. 4 . Specifically, the voids that had been inmaterial 16 are absent due to the oxidation ofmaterial 16. Also,semiconductive material 26 has been transformed into a crystalline material (illustrated diagrammatically by the cross-hatching ofmaterial 26 inFIG. 5 ).Crystalline material 26 can consist of a single large crystal, and accordingly can be monocrystalline. Alternatively,crystalline material 26 can be polycrystalline. Ifcrystalline material 26 is polycrystalline, the crystals of the material will preferably be equal in size or larger than theblocks 18. In particular aspects, each crystal of the polycrystalline material can be about as large as one of the shownislands 18. Accordingly, the islands can be associated in a one-to-one correspondence with crystals of the polycrystalline material. - The shown
metal layers 32 are effectively in a one-to-one relationship withislands 18, and such one-to-one correspondence of crystals to islands can occur during the MILC. Specifically, single crystals can be generated relative to each ofislands 18 during the MILC process described with reference toFIG. 4 . It is also noted, however, that although the metal layers 32 are shown in a one-to-one relationship with the islands in the cross-sectional views ofFIGS. 4 and 5 , theconstruction 10 comprising the shown fragment should be understood to extend three dimensionally. Accordingly, theislands 18 andmetal layers 32 can extend in directions corresponding to locations into and out of the page relative to the shown cross-sectional view. There can be regions of the construction which are not shown where a metal layer overlaps with additional islands besides the shown islands. - Referring to
FIG. 6 , layers 28 and 32 (FIG. 5 ) are removed, and subsequently alayer 40 of crystalline semiconductive material is formed overlayer 26. In typical applications,layer 26 will have a relaxed crystalline lattice andlayer 40 will have a strained crystalline lattice. As discussed previously,layer 26 will typically comprise both silicon and germanium, with the germanium being present to a concentration of from about 10 atomic percent to about 60 atomic percent.Layer 40 can comprise, consist essentially of, or consist of either doped or undoped silicon; or alternatively can comprise, consist essentially of, or consist of either doped or undoped silicon/germanium. Iflayer 40 comprises silicon/germanium, the germanium content can be from about 10 atomic percent to about 60 atomic percent. -
Strained lattice layer 40 can be formed by utilizing methods similar to those described in, for example, Huang, L. J. et al., “Carrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bonding”, VLSI Tech. Digest, 2001, pp. 57-58; and Cheng, Z. et al., “SiGe-On-Insulator (SGOI) Substrate Preparation and MOSFET Fabrication for Electron Mobility Evaluation” 2001 IEEE SOI Conference Digest, October 2001, pp. 13-14. -
Strained lattice layer 40 can be large polycrystalline or monocrystalline. Ifstrained lattice layer 40 is polycrystalline, the crystals oflayer 40 can be large and in a one-to-one relationship with the large crystals of a polycrystallinerelaxed crystalline layer 26.Strained lattice layer 40 is preferably monocrystalline over the individual blocks 18. - The strained crystalline lattice of
layer 40 can improve mobility of carriers relative to thematerial 26 having a relaxed crystalline lattice. However, it is to be understood thatlayer 40 is optional in various aspects of the invention. - Each of
islands 18 can be considered to be associated with a separateactive region layers 26 and 40 (not shown). For instance, a trenched isolation region can be formed throughlayers layers material 14, and subsequently filling the trench with an appropriate insulative material such as, for example, silicon dioxide. - As discussed previously,
crystalline material 26 can be a single crystal extending across an entirety of theconstruction 10 comprising the shown fragment, and accordingly extending across all of the shown active regions. Alternatively,crystalline material 26 can be polycrystalline. Ifcrystalline material 26 is polycrystalline, the single crystals of the polycrystalline material will preferably be large enough so that only one single crystal extends across a given active region. In other words,active region 42 will preferably comprise a single crystal ofmaterial 26,active region 44 will comprise a single crystal of the material, and active region 46 will comprise a single crystal of the material, with the single crystals being separate and discrete relative to one another. -
FIG. 7 shows an expanded view ofactive region 44 at a processing stage subsequent to that ofFIG. 6 , and specifically shows atransistor device 50 associated withactive region 44 and supported bycrystalline material 26. -
Transistor device 50 comprises adielectric material 52 formed overstrained lattice 40, and agate 54 formed overdielectric material 52.Dielectric material 52 typically comprises silicon dioxide, andgate 54 typically comprises a stack including an appropriate conductive material, such as, for example, conductively-doped silicon and/or metal. - A
channel region 56 is beneathgate 54, and in the shown construction extends across strainedcrystalline lattice material 40. The channel region may also extend into relaxed crystalline lattice material 26 (as shown).Channel region 56 is doped with a p-type dopant. -
Transistor construction 50 additionally comprises source/drain regions 58 which are separated from one another bychannel region 56, and which are doped with n-type dopant to an n+ concentration (typically, a concentration of at least 1021 atoms/cm3). In the shown construction, source/drain regions 58 extend acrossstrained lattice layer 40 and intorelaxed lattice material 26. Although source/drain regions 58 are shown extending only partially throughrelaxed lattice layer 26, it is to be understood that the invention encompasses other embodiments (not shown) in which the source/drain regions extend all the way throughrelaxed material 26 and tomaterial 16. -
Channel region 56 and source/drain regions 58 can be formed by implanting the appropriate dopants intocrystalline materials field effect transistor 50. - An active region of
transistor device 50 extends across source/drain regions 58 andchannel region 56. Preferably the portion of the active region withincrystalline material 26 is associated with only one single crystal ofmaterial 26. Such can be accomplished by havingmaterial 26 be entirely monocrystalline. Alternatively,material 26 can be polycrystalline and comprise an individual single grain which accommodates the entire portion of the active region that is withinmaterial 26. The portion ofstrained lattice material 40 that is encompassed by the active region is preferably a single crystal, and can, in particular aspects, be considered an extension of the single crystal of therelaxed lattice material 26 of the active region. -
Crystalline materials material 16, have a total thickness of less than or equal to about 2000 Å. Accordingly the crystalline material can correspond to a thin film formed over an insulative material. The insulative material can be considered to beinsulative layer 14 alone, or a combination ofinsulative layer 14 and oxidized portions ofmaterial 16. - The
transistor structure 50 ofFIG. 7 corresponds to an n-type field effect transistor (NFET), and in such construction it can be advantageous to have strainedcrystalline material 40 consist of a strained silicon material having appropriate dopants therein. The strained silicon material can improve mobility of electrons throughchannel region 56, which can improve performance of the NFET device relative to a device lacking the strained silicon lattice. Although it can be preferred thatstrained lattice material 40 comprise silicon in an NFET device, it is to be understood that the strained lattice can also comprise other semiconductive materials. A strained silicon lattice can be formed by various methods. For instance, strained silicon could be developed by various means andlattice 40 could be created by lattice mismatch with other materials or by geometric conformal lattice straining on another substrate (mechanical stress). - As mentioned above,
strained lattice 40 can comprise other materials alternatively to, or additionally to, silicon. The strained lattice can, for example, comprise a combination of silicon and germanium. There can be advantages to utilizing the strained crystalline lattice comprising silicon and germanium relative to structures lacking any strained lattice. However, it is generally most preferable if the strained lattice consists of silicon alone (or doped silicon), rather than a combination of silicon and germanium for an NFET device. - A pair of
sidewall spacers 60 are shown formed along sidewalls ofgate 54, and aninsulative mass 62 is shown extending overgate 54 andmaterial 40.Conductive interconnects insulative mass 62 to electrically connect with source/drain regions 58.Interconnects transistor construction 50 with other circuitry external totransistor construction 50. Such other circuitry can include, for example, a bitline and a capacitor in applications in whichconstruction 50 is incorporated into dynamic random access memory (DRAM). -
FIG. 8 showsconstruction 10 at a processing stage subsequent to that ofFIG. 7 , and shows acapacitor structure 90 formed over and in electrical contact withconductive interconnect 64. The shown capacitor structure extends acrossgate 54 andinterconnect 63. -
Capacitor construction 90 comprises afirst capacitor electrode 92, asecond capacitor electrode 94, and adielectric material 96 betweencapacitor electrodes Capacitor electrodes electrodes electrode 92,conductive interconnect 64 and the source/drain region 58 electrically connected withinterconnect 64 comprise, or consist of, n-type doped semiconductive material. Accordingly, n-type doped semiconductive material extends from the source/drain region, through the interconnect, and through the capacitor electrode. -
Dielectric material 96 can comprise any suitable material, or combination of materials. Exemplary materials suitable for dielectric 106 are high dielectric constant materials including, for example, silicon nitride, aluminum oxide, TiO2, Ta2O5, ZrO2, etc. - The
conductive interconnect 63 is in electrical connection with abitline 97.Top capacitor electrode 94 is shown in electrical connection with an interconnect 98, which in turn connects with areference voltage 99, which can, in particular aspects, be ground. The construction ofFIG. 8 can be considered a DRAM cell, and such can be incorporated into an electronic system (such as, for example, a computer system) as a memory device. -
FIG. 9 showsconstruction 10 at a processing stage subsequent to that ofFIG. 6 and alternative to that described previously with reference toFIG. 7 . In referring toFIG. 9 , similar numbering will be used as is used above in describingFIG. 7 , where appropriate. - A
transistor construction 70 is shown inFIG. 9 , and such construction differs from theconstruction 50 described above with reference toFIG. 7 in thatconstruction 70 is a p-type field effect transistor (PFET) rather than the NFET ofFIG. 7 .Transistor device 70 comprises an n-type dopedchannel region 72 and p+-doped source/drain regions 74. In other words, the channel region and source/drain regions oftransistor device 70 are oppositely doped relative to the channel region and source/drain regions described above with reference to theNFET device 50 ofFIG. 7 . - The strained
crystalline lattice material 40 of thePFET device 70 can consist of appropriately doped silicon, or consist of appropriately doped silicon/germanium. It can be most advantageous if the strainedcrystalline lattice material 40 comprises appropriately doped silicon/germanium in a PFET construction, in that silicon/germanium can be a more effective carrier of holes with higher mobility than is silicon without germanium. - Devices similar to the transistor devices discussed above (
NFET device 50 ofFIG. 7 , andPFET device 70 ofFIG. 9 ) can be utilized in numerous constructions. For instance, similar devices can be utilized in logic devices. - Exemplary logic devices incorporating methodology of
FIGS. 1-9 are described inFIGS. 10-17 . Referring initially toFIG. 10 , such illustrates a circuit schematic of a two-input NOR logic construction. The construction includes a pair ofNFET transistors PFET transistor 154 in series with the NFET pair to provide clocking. A first input “A” is provided to a gate ofNFET device 150, and a second input “B” is provided to the transistor gate ofNFET device 152. Additionally, a clock input is provided to the gate ofPFET device 154. The NFET devices connect with one source/drain of the PFET device by the logic output node, and are between the PFET device (connected between VDD and the logic output) and VREF/GND. The other source/drain of the PFET device connects to VDD. -
FIG. 11 is a cross-sectional view of an exemplary construction corresponding to the circuit described above with reference toFIG. 10 . The construction ofFIG. 11 is referred to generally as 160. In referring toconstruction 160, similar numbering will be used as was utilized above in describing the constructions ofFIGS. 1-9 , where appropriate. In the specific construct ofFIG. 11 , the PFET device ofFIG. 10 is split into two “half-width”PFET devices FIG. 10 . Such can allow layout density and symmetry of the NOR logic building block to be achieved, as well as improve performance and wireability. One aspect of the potential improvement in performance obtained by utilizing methodologies of the present invention, is that such methodologies can reduce the amount and complexity of wiring. Such reduction can remove interconnect delay and other delays associated with wiring, which can translate into enhanced speed. -
Construction 160 includessubstrate 12,insulative material 14, and layers 16, 26 and 40 of the above-described constructions ofFIGS. 1-9 .Substrate 12 can comprise, for example, a semiconductive material (such as, for example, a monocrystalline silicon wafer), glass, aluminum oxide, silicon dioxide, metal and/or plastic.Insulative material 14 can comprise, for example, silicon nitride and/or silicon dioxide.Layers layer 40 can, in particular aspects, comprise Si/Ge in a strained crystalline lattice. -
Construction 160 further includes a pair ofNFET devices gates layer 40 and separated fromlayer 40 bygate oxide 52. -
NFET device 150 comprises source/drain regions layers NFET device 164 comprises source/drain regions layers drain region 168 is common todevices drain region 168 is shared betweendevices gates layer 26 is contained within a single crystal oflayer 26, and an entirety of the overlapping active regions withinlayer 40 is contained within a single crystal oflayer 40.Layers FIGS. 1-9 , comprise polycrystalline or monocrystalline materials. -
NFET constructions NFET construction 50 described with reference toFIG. 7 , and can be formed utilizing methodology analogous to that described previously for forming the construction ofFIG. 7 . It is noted that thelayers FIG. 7 to indicate that such layers are conductive, whereas thelayers FIG. 11 . The cross-hatching is not shown inFIG. 11 in order to simplify the drawing, but it is to be understood that thelayers FIG. 11 are similarly conductive to thelayers FIG. 7 . - A
conductive pedestal 172 extends upwardly from shared source/drain region 168.Pedestal 172 is in electrical connection with source/drain region 168, and in particular aspects comprises n-type doped semiconductive material, such as, for example, n-type doped silicon or n-type doped silicon/germanium.Pedestal 172 joins aconstruction 174 which supportsPFET devices Construction 174 comprises alayer 176 of semiconductive material.Layer 176 can comprise, consist essentially of, or consist of, for example, n-type doped silicon. In other aspects,layer 176 can comprise, consist essentially of, or consist of n-type doped silicon/germanium, with the germanium being present to a concentration of from about 10 atom % to about 60 atom %. In one aspect of the invention,pedestal 172 is formed by epitaxial growth over crystalline material oflayer 40, and subsequently layer 176 is formed by epitaxial growth frompedestal 172. - A
layer 178 is formed overlayer 176.Layer 178 can comprise, for example, appropriately-doped silicon or appropriately-doped silicon/germanium. In some aspects,layer 176 can comprise a relaxed crystalline lattice andlayer 178 can comprise a strained crystalline lattice. Accordingly, layers 176 and 178 can comprise identical constructions to those of thelayers -
PFET constructions gates layer 178 bygate oxide 52. -
PFET device 154 comprises p-type dopeddiffusion regions layers PFET construction 155 comprises source/drain regions layers drain region 186 is common to PFETdevices Devices layer 176 can be contained within a single crystal of the material oflayer 176, and an entirety of the overlapping active regions withinlayer 178 can be contained within a single crystal of the material oflayer 178. -
PFET constructions PFET construction 70 described with reference toFIG. 9 , and can be formed utilizing methodology analogous to that described previously for forming the construction ofFIG. 9 . It is noted that thelayers FIG. 9 to indicate that such layers are conductive, whereas thelayers FIG. 11 . The cross-hatching is not shown inFIG. 11 in order to simplify the drawing, but it is to be understood that thelayers FIG. 11 are similarly conductive to thelayers FIG. 9 . - An
insulative material 62 extends around various of the shown structures to electrically isolate and/or support the structures.Material 62 can comprise, for example, BPSG, SiO2, and/or silicon nitride. - A clock circuit is electrically connected with
gates drain regions drain regions NFET transistor devices NFET gates drain region 186, as well as with the n-type doped semiconductive material ofpedestal 172 connecting to the n+ source/drain region 168. - It is to be understood that various features are shown diagrammatically in
FIG. 11 in an effort to simplify the figure. For instance, sidewall spacers would typically be formed along sidewalls ofgates FIG. 11 . Also,gates gates layer 16 described in the embodiments ofFIGS. 1-9 ), can be formed in theconstruction 174, although such layer is not present in the shown embodiment -
FIG. 12 is a diagrammatic top view of theconstruction 160 and shows the overlap of thePFET gates lower NFET gates FIG. 12 also represents the orientations of various first metal interconnect wiring layers relative to all appropriate nodes ofNFET devices PFET devices - Referring next to
FIG. 13 , such illustrates a circuit schematic of an exemplary two-input NAND logic gate in accordance with an aspect of the present invention. The logic gate comprises a pair ofPFET transistor devices NFET device 200 to provide the clock input and to discharge the output potential node to ground when clocked. Source/drain regions ofPFET devices -
FIG. 14 is a cross-sectional view of aconstruction 210 comprising the two-input NAND circuit described with reference toFIG. 13 . In referring toconstruction 210, similar numbering will be used as was used above in describingFIGS. 1-9 , where appropriate. - In the specific construct of
FIG. 14 , the NFET device of the NAND circuit ofFIG. 13 is split into two “half-width” NFET devices (200 and 201), connected in parallel to provide the logical equivalent of the whole NFET of FIG. 13. Such can allow layout density and symmetry of the NAND building block to be achieved. -
Construction 210 comprisessubstrate 12,insulative material 14, and layers 16, 26 and 40.PFET devices gates layer 40.Gates layer 40 bygate oxide 52. -
PFET device 202 further comprises source/drain regions layers device 204 comprises source/drain regions layers drain region 218 is shared betweendevices Devices layer 26 can be within a single crystal of the material oflayer 26, and the entirety of the overlapping active regions withinlayer 40 can be within a single crystal of the material oflayer 40. The individual PFET constructions can be identical to thePFET construction 70 described with reference toFIG. 9 , and accordingly layer 26 can comprise a relaxed crystalline lattice, andlayer 40 can comprise a strained crystalline lattice. - A
conductive pedestal 224 extends upwardly from source/drain region 218 to astructure 230.Pedestal 224 can comprise, for example, a conductively-doped semiconductive material, and the shown exemplary pedestal is a p-type doped material. The semiconductive material ofpedestal 224 can be, for example, silicon or silicon/germanium.Pedestal 224 can be formed by epitaxial growth fromlayer 40, and accordingly can comprise a crystalline matrix. -
Structure 230 compriseslayers Layers layers Layers conductive pedestal 224 by epitaxial growth from a crystalline material withinpedestal 224. -
NFET devices structure 230.NFET device 200 comprises agate 240, andNFET device 201 comprises agate 242.NFET device 240 further comprises source/drain regions layers NFET device 201 comprises source/drain regions layers drain region 246 is shared betweendevices devices layer 234 is contained within a single crystal of Si/Ge material withinlayer 234, and an entirety of the overlapping active regions withinlayer 236 is contained within a single crystal of a strained crystalline material oflayer 236. - A clock circuit is in electrical connection with both of the
gates gates drain regions drain region 246 is in electrical connection with an output of the logic construction. It is noted that the output is also in electrical connection with the p-type doped semiconductor material ofpedestal 224, which in turn connects with source/drain region 218. Source/drain regions -
FIG. 15 is a diagrammatic top view of theconstruction 210, and illustrates the overlap ofNFET devices lower PFET devices FIG. 15 also represents the orientations of various first level metal wiring interconnect layers relative to all appropriate nodes ofPFET devices NFET devices - Referring to
FIG. 16 , a schematic diagram of a 2-NOR cross-coupled latch (also referred to as a flip-flop) is illustrated as an example of a higher level logic building block. The device comprises two inputs (A1 and B1). TheFIG. 16 device can be formed as a combination of devices of the type described inFIG. 10 . The flip-flop ofFIG. 16 is formed from a pair of NOR circuits ofFIG. 10 by cross-coupling the second NFET input gates (A2 and B2) of each NOR circuit. -
FIG. 17 illustrates a top view of a construction 300 with a compact two-level metal wireability scheme corresponding to the flip-flop ofFIG. 16 , and shows that such construction can be formed over a relatively small footprint of a substrate by stacking PFET and NFET devices relative to one another. The flip-flop ofFIG. 17 demonstrates twelve metal-one (M1) wiring levels horizontally and five metal-two (M2) levels vertically for interconnecting all appropriate nodes of the latch for full functionality and wireability. It should be noted that M1 wiring channels are grouped into six wiring channels to route VDD, ground and clock signals. It should also be noted that the three metal-two (M2) wiring channels bring VDD, ground and clock signal levels to M1 via M2-to-M1 contacts, while two other M2 wiring channels are used for A2 and B2 cross-coupling and to bring out the output levels A and B. The scheme, thereby, demonstrates a highly efficient and compact wireability of a higher level logic block, such as a latch. - The design of
FIGS. 11 and 12 is a two-input clocked NOR logic cell for device width (W) over length (L) ratio of 10:1. Since PFET gates are in parallel mode, the devices effectively supply twice (W/L equivalent of nearly 20:1) the current. Consequently, such design can approximately balance the mobility ratios of electrons and holes, even though the electrons can have nearly two-times the mobility of the holes. The stacked configuration can therefore allow dense logic cells to be formed. The stacked configuration can also allow wiring channels interconnecting devices to utilize only one level of metal interconnect (as shown inFIG. 12 ). The dense NAND logic cell layout ofFIGS. 14-15 is similar to the NOR cell ofFIGS. 11-12 , but utilizes stacked top devices which are NFET, while the bottom input devices are PFETs. The stacked approach ofFIGS. 11-12 and 14-15 can be utilized to develop various random logic cell libraries, including, for example, the cross-coupled dense flip-flop ofFIGS. 16 and 17 . - There are numerous advantages to utilizing only a single level of wiring in forming logic devices, including, for example, conservation of semiconductor device real estate, reduction of the number of process steps and masking levels utilized in forming logic devices, and reduction of interconnect delays.
- Utilization of Si/
Ge layer 26 can improve performance of the devices ofFIGS. 10-17 relative to prior art devices having source/drain regions extending into materials consisting of conductively-doped silicon. The performance of the devices can be further enhanced by utilizing alayer 26 having a relaxed crystalline lattice in combination with alayer 40 having a strained crystalline lattice for reasons similar to those discussed above with reference toFIGS. 1-9 . - Several of the figures show various different dopant levels, and utilize the designations p+, p, p−, n−, n and n+ to distinguish the levels. The difference in dopant concentration between the regions identified as being p+, p, and p− are typically as follows. A p+ region has a dopant concentration of at least about 1020 atoms/cm3, a p region has a dopant concentration of from about 1014 to about 1018 atoms/cm3, and a p− region has a dopant concentration in the order of or less than 1016 atoms/cm3. It is noted that regions identified as being n−, n and n+ will have dopant concentrations similar to those described above relative to the p−, p and p+ regions respectively, except, of course, the n regions will have an opposite-type conductivity enhancing dopant therein than do the p regions.
- The p+, p, and p− dopant levels are shown in the drawings only to illustrate differences in dopant concentration. It is noted that the term “p” is utilized herein to refer to both a dopant type and a relative dopant concentration. To aid in interpretation of this specification and the claims that follow, the term “p” is to be understood as referring only to dopant type, and not to a relative dopant concentration, except when it is explicitly stated that the term “p” refers to a relative dopant concentration. Accordingly, for purposes of interpreting this disclosure and the claims that follow, it is to be understood that the term “p-type doped” refers to a dopant type of a region and not a relative dopant level. Thus, a p-type doped region can be doped to any of the p+, p, and p− dopant levels discussed above. Similarly, an n-type doped region can be doped to any of the n+, n, and n− dopant levels discussed above.
-
FIG. 18 illustrates generally, by way of example, but not by way of limitation, an embodiment of acomputer system 400 according to an aspect of the present invention.Computer system 400 includes amonitor 401 or other communication output device, akeyboard 402 or other communication input device, and amotherboard 404.Motherboard 404 can carry amicroprocessor 406 or other data processing unit, and at least onememory device 408.Memory device 408 can comprise various aspects of the invention described above, including, for example, the DRAM unit cell described with reference toFIG. 8 .Memory device 408 can comprise an array of memory cells, and such array can be coupled with addressing circuitry for accessing individual memory cells in the array. Further, the memory cell array can be coupled to a read circuit for reading data from the memory cells. The addressing and read circuitry can be utilized for conveying information betweenmemory device 408 andprocessor 406. Such is illustrated in the block diagram of themotherboard 404 shown inFIG. 19 . In such block diagram, the addressing circuitry is illustrated as 410 and the read circuitry is illustrated as 412. Various components ofcomputer system 400, includingprocessor 406, can comprise one or more of the logic constructions described with reference toFIGS. 10-17 . - In particular aspects of the invention,
processor device 406 can correspond to a processor module, and associated random logic may be used in the implementation utilizing the teachings of the present invention. - In particular aspects of the invention,
memory device 408 can correspond to a memory module. For example, single in-line memory modules (SIMMS) and dual in-line memory modules (DIMMS) may be used in the implementation which utilize the teachings of the present invention. The memory device can be incorporated into any of a variety of designs which provide different methods of reading from and writing to memory cells of the device. One such method is the page mode operation. Page mode operations in a DRAM are defined by the method of accessing a row of a memory cell arrays and randomly accessing different columns of the array. Data stored at the row and column intersection can be read and output while that column is accessed. - An alternate type of device is the extended data output (EDO) memory which allows data stored at a memory array address to be available as output after the addressed column has been closed. This memory can increase some communication speeds by allowing shorter access signals without reducing the time in which memory output data is available on a memory bus. Other alternative types of devices include SDRAM, DDR SDRAM, SLDRAM, VRAM and Direct RDRAM, as well as others such as SRAM or Flash memories.
-
FIG. 20 illustrates a simplified block diagram of a high-level organization of various embodiments of an exemplaryelectronic system 700 of the present invention.System 700 can correspond to, for example, a computer system, a process control system, or any other system that employs a processor and associated memory.Electronic system 700 has functional elements, including a processor or arithmetic/logic unit (ALU) 702, acontrol unit 704, amemory device unit 706 and an input/output (I/O)device 708. Generally,electronic system 700 will have a native set of instructions that specify operations to be performed on data by theprocessor 702 and other interactions between theprocessor 702, thememory device unit 706 and the I/O devices 708. Thecontrol unit 704 coordinates all operations of theprocessor 702, thememory device 706 and the I/O devices 708 by continuously cycling through a set of operations that cause instructions to be fetched from thememory device 706 and executed. In various embodiments, thememory device 706 includes, but is not limited to, random access memory (RAM) devices, read-only memory (ROM) devices, and peripheral devices such as a floppy disk drive and a compact disk CD-ROM drive. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that any of the illustrated electrical components are capable of being fabricated to include DRAM cells and/or logic constructions in accordance with various aspects of the present invention. -
FIG. 21 is a simplified block diagram of a high-level organization of various embodiments of an exemplaryelectronic system 800. Thesystem 800 includes amemory device 802 that has an array ofmemory cells 804,address decoder 806,row access circuitry 808,column access circuitry 810, read/writecontrol circuitry 812 for controlling operations, and input/output circuitry 814. Thememory device 802 further includespower circuitry 816, andsensors 820, such as current sensors for determining whether a memory cell is in a low-threshold conducting state or in a high-threshold non-conducting state. The illustratedpower circuitry 816 includespower supply circuitry 880,circuitry 882 for providing a reference voltage,circuitry 884 for providing the first wordline with pulses,circuitry 886 for providing the second wordline with pulses, andcircuitry 888 for providing the bitline with pulses. Thesystem 800 also includes aprocessor 822, or memory controller for memory accessing. - The
memory device 802 receives control signals from theprocessor 822 over wiring or metallization lines. Thememory device 802 is used to store data which is accessed via I/O lines. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that thememory device 802 has been simplified to help focus on the invention. At least one of theprocessor 822 ormemory device 802 can include a DRAM cell and/or random logic construction of the type described previously in this disclosure. - The various illustrated systems of this disclosure are intended to provide a general understanding of various applications for the circuitry and structures of the present invention, and are not intended to serve as a complete description of all the elements and features of an electronic system using memory cells in accordance with aspects of the present invention. One of the ordinary skill in the art will understand that the various electronic systems can be fabricated in single-package processing units, or even on a single semiconductor chip, in order to reduce the communication time between the processor and the memory device(s).
- Applications for memory cells and logic constructions can include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Such circuitry can further be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and others.
- In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.
Claims (30)
1-87. (canceled)
88. A method of forming a semiconductor construction, comprising:
providing a first crystalline material which includes silicon and germanium;
forming a pair of first transistor devices having first active regions extending into the first crystalline material, the first transistor devices sharing a source/drain region;
providing a second crystalline material which includes silicon and germanium;
forming a conductive interconnect in electrical contact with the shared source/drain region and in electrical connection with a second crystalline material; and
forming a pair of second transistor devices having second active regions extending into the second crystalline material.
89. The method of claim 88 wherein the first and second transistor devices are part of a pair of NOR circuits in a cross-coupled latch.
90. The method of claim 88 wherein the first transistor devices are PFET devices and wherein the second transistor devices are NFET devices.
91. The method of claim 88 wherein the first transistor devices are NFET devices and wherein the second transistor devices are PFET devices.
92. The method of claim 88 wherein the first crystalline material is part of an SOI construction supported by a substrate.
93. The method of claim 92 wherein the substrate comprises a semiconductive material.
94. The method of claim 92 wherein the substrate comprises glass.
95. The method of claim 92 wherein the substrate comprises aluminum oxide.
96. The method of claim 92 wherein the substrate comprises silicon dioxide.
97. The method of claim 92 wherein the substrate comprises a metal.
98. The method of claim 92 wherein the substrate comprises a plastic.
99. The method of claim 88 wherein the first crystalline material comprises from about 10 to about 60 atomic percent germanium.
100. The method of claim 88 wherein the second crystalline material comprises from about 10 to about 60 atomic percent germanium.
101. The method of claim 88 wherein the first active regions are entirely contained within a single crystal of the first crystalline material.
102. The method of claim 101 wherein the first crystalline material is polycrystalline.
103. The method of claim 101 wherein the first crystalline material is monocrystalline.
104. The method of claim 88 wherein the second active regions are entirely contained within a single crystal of the second crystalline material.
105. The method of claim 104 wherein the second crystalline material is polycrystalline.
106. The method of claim 104 wherein the second crystalline material is monocrystalline.
107. The method of claim 88 wherein the first transistor devices have gates over the first crystalline material; wherein the first crystalline material has a relaxed crystalline lattice; and further comprising providing a strained crystalline lattice layer between the relaxed crystalline lattice and the gates.
108. The method of claim 107 wherein the strained crystalline lattice includes silicon.
109. The method of claim 107 wherein the strained crystalline lattice includes silicon and germanium.
110. A method of forming integrated circuit, comprising:
providing a first crystalline material which includes silicon and germanium;
forming a pair of first transistor devices having first active regions extending into the first crystalline material, the active regions of the first transistor devices overlapping so that the pair of first transistor devices have a common source/drain region; the active regions of the pair of first transistor devices being entirely contained within a single crystal of the first crystalline material;
forming a second crystalline material which includes silicon and germanium, and which is electrically coupled with the common source/drain region; and
forming a pair of second transistor devices having second active regions extending into the second crystalline material.
111. The method of claim 110 wherein the first transistor devices are PFET devices and wherein the second transistor devices are NFET devices.
112. The method of claim 110 wherein the first transistor devices are NFET devices and wherein the second transistor devices are PFET devices.
113. The method of claim 110 wherein the first crystalline material comprises from about 10 to about 60 atomic percent germanium.
114. The method of claim 110 wherein the second crystalline material comprises from about 10 to about 60 atomic percent germanium.
115. The method of claim 110 wherein the second active regions overlap so that the second transistor devices have a shared source/drain region; and wherein the second active regions are entirely contained within a single crystal of the second crystalline material.
116. The method of claim 110 wherein the first transistor devices have gates over the first crystalline material; wherein the first crystalline material has a relaxed crystalline lattice; and further comprising forming a strained crystalline lattice layer between the relaxed crystalline lattice and the gates.
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US11/351,637 US20060157688A1 (en) | 2003-03-11 | 2006-02-10 | Methods of forming semiconductor constructions and integrated circuits |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/387,090 US6900667B2 (en) | 2003-03-11 | 2003-03-11 | Logic constructions and electronic devices |
US11/130,742 US20060011978A1 (en) | 2003-03-11 | 2005-05-17 | Semiconductor constructions and integrated circuits |
US11/351,637 US20060157688A1 (en) | 2003-03-11 | 2006-02-10 | Methods of forming semiconductor constructions and integrated circuits |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/130,742 Continuation US20060011978A1 (en) | 2003-03-11 | 2005-05-17 | Semiconductor constructions and integrated circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060157688A1 true US20060157688A1 (en) | 2006-07-20 |
Family
ID=32961820
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/387,090 Expired - Lifetime US6900667B2 (en) | 2003-03-11 | 2003-03-11 | Logic constructions and electronic devices |
US11/130,742 Abandoned US20060011978A1 (en) | 2003-03-11 | 2005-05-17 | Semiconductor constructions and integrated circuits |
US11/351,637 Abandoned US20060157688A1 (en) | 2003-03-11 | 2006-02-10 | Methods of forming semiconductor constructions and integrated circuits |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/387,090 Expired - Lifetime US6900667B2 (en) | 2003-03-11 | 2003-03-11 | Logic constructions and electronic devices |
US11/130,742 Abandoned US20060011978A1 (en) | 2003-03-11 | 2005-05-17 | Semiconductor constructions and integrated circuits |
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US (3) | US6900667B2 (en) |
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