|Número de publicación||US20060197125 A1|
|Tipo de publicación||Solicitud|
|Número de solicitud||US 11/415,784|
|Fecha de publicación||7 Sep 2006|
|Fecha de presentación||2 May 2006|
|Fecha de prioridad||7 Jun 2002|
|También publicado como||US7074623, US7109516, US20040031979, US20050280103, US20060186510, US20060197123, US20060197124, US20060197126|
|Número de publicación||11415784, 415784, US 2006/0197125 A1, US 2006/197125 A1, US 20060197125 A1, US 20060197125A1, US 2006197125 A1, US 2006197125A1, US-A1-20060197125, US-A1-2006197125, US2006/0197125A1, US2006/197125A1, US20060197125 A1, US20060197125A1, US2006197125 A1, US2006197125A1|
|Inventores||Thomas Langdo, Matthew Currie, Glyn Braithwaite, Richard Hammond, Anthony Lochtefeld, Eugene Fitzgerald|
|Cesionario original||Amberwave Systems Corporation|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citas de patentes (99), Citada por (10), Clasificaciones (48), Eventos legales (1)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
This application claims the benefit of U.S. Provisional Application 60/386,968 filed Jun. 7, 2002, U.S. Provisional Application 60/404,058 filed Aug. 15, 2002, and U.S. Provisional Application 60/416,000 filed Oct. 4, 2002; the entire disclosures of these three provisional applications are hereby incorporated by reference.
This invention relates to devices and structures comprising strained semiconductor layers and insulator layers.
Strained silicon-on-insulator structures for semiconductor devices combine the benefits of two advanced approaches to performance enhancement: silicon-on-insulator (SOI) technology and strained silicon (Si) technology. The strained silicon-on-insulator configuration offers various advantages associated with the insulating substrate, such as reduced parasitic capacitances and improved isolation. Strained Si provides improved carrier mobilities. Devices such as strained Si metal-oxide-semiconductor field-effect transistors (MOSFETs) combine enhanced carrier mobilities with the advantages of insulating substrates.
Strained-silicon-on-insulator substrates are typically fabricated as follows. First, a relaxed silicon-germanium (SiGe) layer is formed on an insulator by one of several techniques such as separation by implantation of oxygen (SIMOX), wafer bonding and etch back; wafer bonding and hydrogen exfoliation layer transfer; or recrystallization of amorphous material. Then, a strained Si layer is epitaxially grown to form a strained-silicon-on-insulator structure, with strained Si disposed over SiGe. The relaxed-SiGe-on-insulator layer serves as the template for inducing strain in the Si layer. This induced strain is typically greater than 10−3.
This structure has limitations. It is not conducive to the production of fully-depleted strained-semiconductor-on-insulator devices in which the layer over the insulating material must be thin enough [<300 angstroms (Å)] to allow for full depletion of the layer during device operation. Fully depleted transistors may be the favored version of SOI for MOSFET technologies beyond the 90 nm technology node. The relaxed SiGe layer adds to the total thickness of this layer and thus makes it difficult to achieve the thicknesses required for fully depleted silicon-on-insulator device fabrication. The relaxed SiGe layer is not required if a strained Si layer can be produced directly on the insulating material. Thus, there is a need for a method to produce strained silicon—or other semiconductor—layers directly on insulating substrates.
Double gate MOSFETs have the potential for superior performance in comparison to standard single-gate bulk or single-gate SOI MOSFET devices. This is due to the fact that two gates (one above and one below the channel) allow much greater control of channel charge then a single gate. This configuration has the potential to translate to higher drive current and lower stand-by leakage current.
Fin-field-effect transistors (finFETs), like double-gate MOSFETs, typically have two gates (one on either side of the channel, where the channel is here oriented vertically) allowing much greater control of channel charge than in a single gate device. This configuration also has the potential to translate to higher drive current and lower stand-by leakage current. Devices related to the finFET, such as the wrap-around gate FET (gate on both sides of as well as above the channel) allow even more channel charge control and hence even more potential for improved drive current and leakage current performance.
The bipolar-CMOS (BiCMOS) process is a combination of both the bipolar transistor and MOSFET/CMOS processes. Individually, the CMOS process allows low power dissipation, high packing density and the ability to integrate complexity with high-speed yields. A major contribution to power dissipation in CMOS circuits originates from driving the load capacitance that is usually the gate of sequentially linked logic cells. The size of these gates may be kept sufficiently small, but when driving higher loads (such as input/output buffers or data buses) the load or capacitance of such devices is substantially larger and therefore requires greater gate width (hence area) of transistor, which inevitably drives down the switching speed of the MOSFET.
The bipolar transistor has significant advantages in terms of the drive current per unit active area and reduced noise signal. Additionally, the switching speed is enhanced due to the effectively exponential output current swing with respect to input signal. This means that the transconductance of a bipolar transistor is significantly higher than that of a MOS transistor when the same current is passed. Higher transconductance enables the charging process to take place approximately ten times more quickly in emitter coupled logic circuits, or high fan out/load capacitance.
Pure bipolar technology has not replaced the high packing density microprocessor CMOS process for a number of reasons, including issues of yield and the increased area required for device isolation. However, integration of bipolar and CMOS may provide the best aspects of the composite devices.
The advantages of BiCMOS process may be summarized as follows:
The present invention includes a strained-semiconductor-on-insulator (SSOI) substrate structure and methods for fabricating the substrate structure. MOSFETs fabricated on this substrate will have the benefits of SOI MOSFETs as well as the benefits of strained Si mobility enhancement. For example, the formation of BiCMOS structures on SSOI substrates provides the combined benefits of BiCMOS design platforms and enhanced carrier mobilities. SSOI substrates also enable enhanced carrier mobilities, process simplicity, and better device isolation for double-gate MOSFETs and finFETs.
By eliminating the SiGe relaxed layer traditionally found beneath the strained Si layer, the use of SSOI technology is simplified. For example, issues such as the diffusion of Ge into the strained Si layer during high temperature processes are avoided.
This approach enables the fabrication of well-controlled, epitaxially-defined, thin strained semiconductor layers directly on an insulator layer. Tensile strain levels of ˜10−3 or greater are possible in these structures, and are not diminished after thermal anneal cycles. In some embodiments, the strain-inducing relaxed layer is not present in the final structure, eliminating some of the key problems inherent to current strained Si-on-insulator solutions. This fabrication process is suitable for the production of enhanced-mobility substrates applicable to partially or fully depleted SSOI technology.
In an aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon and a fin-field-effect transistor disposed over the substrate. The fin-field-effect-transistor includes a source region and a drain region disposed in contact with the dielectric layer, the source and the drain regions including a strained semiconductor material. The fin-field-effect-transistor also includes at least one fin extending between the source and the drain regions, the fin including a strained semiconductor material. A gate is disposed above the strained semiconductor layer, extending over at least one fin and between the source and the drain regions. A gate dielectric layer is disposed between the gate and the fin.
One or more of the following features may be included. The fin may include at least one of a group II, a group III, a group IV, a group V, of a group VI element. The strained semiconductor layer may be tensilely strained and may include, e.g., tensilely strained silicon. The strained semiconductor layer may be compressively strained and may include, e.g., compressively strained germanium.
In another aspect, the invention features a method for forming a structure, the method including providing a substrate having a dielectric layer disposed thereon, and a first strained semiconductor layer disposed in contact with the dielectric layer. A fin-field-effect transistor is formed on the substrate by patterning the first strained semiconductor layer to define a source region, a drain region, and at least one fin disposed between the source and the drain regions. A dielectric layer is formed, at least a portion of the dielectric layer being disposed over the fin, and a gate is formed over the dielectric layer portion disposed over the fin.
One or more of the following features may be included. The first strained semiconductor layer may include at least one of a group II, a group III, a group IV, a group V, or a group VI element. The strained semiconductor layer may be tensilely strained and may include, e.g., tensilely strained silicon. The strained semiconductor layer may be compressively strained and may include, e.g., compressively strained germanium.
In another aspect, the invention features a structure including a dielectric layer disposed over a substrate; and a transistor formed over the dielectric layer. The transistor includes a first gate electrode in contact with the dielectric layer, a strained semiconductor layer disposed over the first gate electrode; and a second gate electrode disposed over the strained semiconductor layer.
One or more of the following features may be included. The strained semiconductor layer may include at least one of a group II, a group III, a group IV, a group V, and a group VI elements.
The strained semiconductor layer may be tensilely strained and may include, e.g., tensilely strained silicon. The strained semiconductor layer may be compressively strained and may include, e.g., compressively strained germanium. The strained semiconductor layer may have a strain level greater than 10−3.
A first gate insulator layer may be disposed between the first gate electrode and the strained semiconductor layer. A second gate insulator layer may be disposed between the strained semiconductor layer and the second gate electrode. The strained semiconductor layer may include a source. The strained semiconductor layer may include a drain. A sidewall spacer may be disposed proximate the second gate electrode. The sidewall spacer may include a dielectric or a conductive material.
In another aspect, the invention features a method for forming a structure, the method including forming a substrate having a first gate electrode layer disposed over a substrate insulator layer, a first gate insulator layer disposed over the first gate electrode layer, and a strained semiconductor layer disposed over the first gate insulator layer. A second gate insulator layer is formed over the strained semiconductor layer, and a second gate electrode layer is formed over the second gate insulator layer. A second gate electrode is defined by removing a portion of the second gate insulator layer. A dielectric sidewall spacer is formed proximate the second gate electrode. A portion of the strained semiconductor layer, a portion of the first gate insulator layer, and a portion of the first gate electrode layer are removed to define a vertical structure disposed over the substrate insulator layer, the vertical structure including a strained layer region, a first gate insulator region, and a first gate electrode layer region disposed under the second gate electrode. A first gate electrode is defined by laterally shrinking the first gate electrode layer region.
One or more of the following features may be included. The strained semiconductor layer may be tensilely strained and may include, e.g., tensilely strained silicon. The strained semiconductor layer may be compressively strained and may include compressively strained germanium. A conductive sidewall spacer may be formed proximate the dielectric sidewall spacer. A source and/or a drain may be defined in the strained semiconductor layer.
In another aspect, the invention features a structure including a strained semiconductor layer disposed over a dielectric layer and a bipolar transistor. The bipolar transistor includes a collector disposed in a portion of the strained semiconductor layer, a base disposed over the collector, and an emitter disposed over the base.
One or more of the following features may be included. The strained layer may be tensilely strained and may include, e.g., tensilely strained silicon. The strained layer may be compressively strained.
In another aspect, the invention features a relaxed substrate including a bulk material, a strained layer disposed in contact with the relaxed substrate; and a bipolar transistor. The bipolar transistor includes a collector disposed in a portion of the strained layer, a base disposed over the collector, and an emitter disposed over the base. The strain of the strained layer is not induced by the underlying substrate.
One or more of the following features may be included. The strained layer may be tensilely strained and may include, e.g., tensilely strained silicon. The strained layer may be compressively strained.
In another aspect, the invention features a structure including a relaxed substrate including a bulk material, a strained layer disposed in contact with the relaxed substrate; and a bipolar transistor including. The bipolar transistor includes a collector disposed in a portion of the strained layer, a base disposed over the collector, and an emitter disposed over the base. The strain of the strained layer is independent of a lattice mismatch between the strained layer and the relaxed substrate.
One or more of the following features may be included. The strained layer may be tensilely strained and may include, e.g., tensilely strained silicon. The strained layer may be compressively strained.
In another aspect, the invention includes a method for forming a structure, the method including providing a substrate having a strained semiconductor layer disposed over a dielectric layer, defining a collector in a portion of the strained semiconductor layer; forming a base over the collector; and forming an emitter over the base.
In another aspect, the invention includes method for forming a structure, the method including providing a first substrate having a strained layer disposed thereon, the strained layer including a first semiconductor material. The strained layer is bonded to a second substrate, the second substrate including a bulk material. The first substrate is removed from the strained layer, with the strained layer remaining bonded to the bulk semiconductor material. A collector is defined in a portion of the strained layer. A base is formed over the collector; and an emitter is formed over the base. The strain of the strained layer is not induced by the second substrate and the strain is independent of lattice mismatch between the strained layer and the second substrate.
In another aspect, the invention features a method for forming a structure, the method including providing a relaxed substrate comprising a bulk material and a strained layer disposed in contact with the relaxed substrate, the strain of the strained layer not being induced by the underlying substrate and the strain being independent of a lattice mismatch between the strained layer and the relaxed substrate. A collector is defined in a portion of the strained layer. A base is formed over the collector, and an emitter is formed over the base.
In another aspect, the invention features a method for forming a structure, the method includes providing a substrate having a strained semiconductor layer disposed over a substrate dielectric layer and forming a transistor in the strained layer. Forming the transistor includes forming a gate dielectric layer above a portion of the strained semiconductor layer, forming a gate contact above the gate dielectric layer, and forming a source region and a drain region in a portion of the strained semiconductor layer, proximate the gate dielectric layer. A portion of the strained layer and the substrate dielectric layer are removed to expose a portion of the substrate. A collector is defined in the exposed portion of the substrate. A base is formed over the collector; and an emitter is formed over the base.
Like-referenced features represent common features in corresponding drawings.
An SSOI structure may be formed by wafer bonding followed by cleaving.
A relaxed layer 16 is disposed over graded buffer layer 14. Relaxed layer 16 may be formed of uniform Si1-xGex having a Ge content of, for example, 10-80% (i.e., x=0.1−0.8), and a thickness T2 of, for example, 0.2-2 μm. In some embodiments, Si1-xGex may include Si0.70Ge0.30 and T2 may be approximately 1.5 μm. Relaxed layer 16 may be fully relaxed, as determined by triple axis X-ray diffraction, and may have a threading dislocation density of <1×106 dislocations/cm2, as determined by etch pit density (EPD) analysis. Because threading dislocations are linear defects disposed within a volume of crystalline material, threading dislocation density may be measured as either the number of dislocations intersecting a unit area within a unit volume or the line length of dislocation per unit volume. Threading dislocation density, therefore, may be expressed in either units of dislocations/cm2 or cm/cm3. Relaxed layer 16 may have a surface particle density of, e.g., less than about 0.3 particles/cm2. Further, relaxed layer 16 produced in accordance with the present invention may have a localized light-scattering defect level of less than about 0.3 defects/cm2 for particle defects having a size (diameter) greater than 0.13 microns, a defect level of about 0.2 defects/cm2 for particle defects having a size greater than 0.16 microns, a defect level of about 0.1 defects/cm2 for particle defects having a size greater than 0.2 microns, and a defect level of about 0.03 defects/cm2 for defects having a size greater than 1 micron. Process optimization may enable reduction of the localized light-scattering defect levels to about 0.09 defects/cm2 for particle defects having a size greater than 0.09 microns and to 0.05 defects/cm2 for particle defects having a size greater than 0.12 microns.
Substrate 12, graded layer 14, and relaxed layer 16 may be formed from various materials systems, including various combinations of group II, group III, group IV, group V, and group VI elements. For example, each of substrate 12, graded layer 14, and relaxed layer 16 may include a III-V compound. Substrate 12 may include gallium arsenide (GaAs), graded layer 14 and relaxed layer 16 may include indium gallium arsenide (InGaAs) or aluminum gallium arsenide (AlGaAs). These examples are merely illustrative, and many other material systems are suitable.
A strained semiconductor layer 18 is disposed over relaxed layer 16. Strained layer 18 may include a semiconductor such as at least one of a group II, a group III, a group IV, a group V, and a group VI element. Strained semiconductor layer 18 may include, for example, Si, Ge, SiGe, GaAs, indium phosphide (InP), and/or zinc selenide (ZnSe). In some embodiments, strained semiconductor layer 18 may include approximately 100% Ge, and may be compressively strained. Strained semiconductor layer 18 comprising 100% Ge may be formed over, e.g., relaxed layer 16 containing uniform Si1-xGex having a Ge content of, for example, 50-80% (i.e., x=0.5−0.8), preferably 70% (x=0.7). Strained layer 18 has a thickness T3 of, for example, 50-1000 Å. In an embodiment, T3 may be approximately 200-500 Å.
Strained layer 18 may be formed by epitaxy, such as by atmospheric-pressure CVD (APCVD), low- (or reduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHVCVD), by molecular beam epitaxy (MBE), or by atomic layer deposition (ALD). Strained layer 18 containing Si may be formed by CVD with precursors such as silane, disilane, or trisilane. Strained layer 18 containing Ge may be formed by CVD with precursors such as germane or digermane. The epitaxial growth system may be a single-wafer or multiple-wafer batch reactor. The growth system may also utilize a low-energy plasma to enhance layer growth kinetics. Strained layer 18 may be formed at a relatively low temperature, e.g., less than 700° C., to facilitate the definition of an abrupt interface 17 between strained layer 18 and relaxed layer 16. This abrupt interface 17 may enhance the subsequent separation of strained layer 18 from relaxed layer 16, as discussed below with reference to
In an embodiment in which strained layer 18 contains substantially 100% Si, strained layer 18 may be formed in a dedicated chamber of a deposition tool that is not exposed to Ge source gases, thereby avoiding cross-contamination and improving the quality of the interface between strained layer 18 and relaxed layer 16. Furthermore, strained layer 18 may be formed from an isotopically pure silicon precursor(s). Isotopically pure Si has better thermal conductivity than conventional Si. Higher thermal conductivity may help dissipate heat from devices subsequently formed on strained layer 18, thereby maintaining the enhanced carrier mobilities provided by strained layer 18.
After formation, strained layer 18 has an initial misfit dislocation density, of, for example, 0-105 cm/cm2. In an embodiment, strained layer 18 has an initial misfit dislocation density of approximately 0 cm/cm2. Because misfit dislocations are linear defects generally lying within a plane between two crystals within an area, they may be measured in terms of total line length per unit area. Misfit dislocation density, therefore, may be expressed in units of dislocations/cm or cm/cm2. In one embodiment, strained layer 18 is tensilely strained, e.g., Si formed over SiGe. In another embodiment, strained layer 18 is compressively strained, e.g., Ge formed over SiGe.
Strained layer 18 may have a surface particle density of, e.g., less than about 0.3 particles/cm2. As used herein, “surface particle density” includes not only surface particles but also light-scattering defects, and crystal-originated pits (COPs), and other defects incorporated into strained layer 18. Further, strained layer 18 produced in accordance with the present invention may have a localized light-scattering defect level of less than about 0.3 defects/cm2 for particle defects having a size (diameter) greater than 0.13 microns, a defect level of about 0.2 defects/cm2 for particle defects having a size greater than 0.16 microns, a defect level of about 0.1 defects/cm2 for particle defects having a size greater than 0.2 microns, and a defect level of about 0.03 defects/cm2 for defects having a size greater than 1 micron. Process optimization may enable reduction of the localized light-scattering defect levels to about 0.09 defects/cm2 for particle defects having a size greater than 0.09 microns and to 0.05 defects/cm2 for particle defects having a size greater than 0.12 microns. These surface particles may be incorporated in strained layer 18 during the formation of strained layer 18, or they may result from the propagation of surface defects from an underlying layer, such as relaxed layer 16.
In alternative embodiments, graded layer 14 may be absent from the structure. Relaxed layer 16 may be formed in various ways, and the invention is not limited to embodiments having graded layer 14. In other embodiments, strained layer 18 may be formed directly on substrate 12. In this case, the strain in layer 18 may be induced by lattice mismatch between layer 18 and substrate 12, induced mechanically, e.g., by the deposition of overlayers, such as Si3N4, or induced by thermal mismatch between layer 18 and a subsequently grown layer, such as a SiGe layer. In some embodiments, a uniform semiconductor layer (not shown), having a thickness of approximately 0.5 μm and comprising the same semiconductor material as substrate 12, is disposed between graded buffer layer 14 and substrate 12. This uniform semiconductor layer may be grown to improve the material quality of layers subsequently grown on substrate 12, such as graded buffer layer 14, by providing a clean, contaminant-free surface for epitaxial growth. In certain embodiments, relaxed layer 16 may be planarized prior to growth of strained layer 18 to eliminate the crosshatched surface roughness induced by graded buffer layer 14. (See, e.g., M. T. Currie, et al., Appl. Phys. Lett., 72 (14) p. 1718 (1998), incorporated herein by reference.) The planarization may be performed by a method such as chemical mechanical polishing (CMP), and may improve the quality of a subsequent bonding process (see below) because it minimizes the wafer surface roughness and increases wafer flatness, thus providing a greater surface area for bonding.
In some embodiments, such as when strained layer 18 comprises nearly 100% Ge, a thin layer 21 of another material, such as Si, may be formed over strained layer 18 prior to bonding (see discussion with respect to
In some embodiments, strained layer 18 may be planarized by, e.g., CMP, to improve the quality of the subsequent bond. Strained layer 18 may have a low surface roughness, e.g., less than 0.5 nm root mean square (RMS). Referring to
Handle wafer 50 and epitaxial wafer 8 are cleaned by a wet chemical cleaning procedure to facilitate bonding, such as by a hydrophilic surface preparation process to assist the bonding of a semiconductor material, e.g., strained layer 18, to a dielectric material, e.g., dielectric layer 52. For example, a suitable prebonding surface preparation cleaning procedure could include a modified megasonic RCA SCl clean containing ammonium hydroxide, hydrogen peroxide, and water (NH4OH:H2O2:H2O) at a ratio of 1:4:20 at 60° C. for 10 minutes, followed by a deionized (DI) water rinse and spin dry. The wafer bonding energy should be strong enough to sustain the subsequent layer transfer (see
In certain embodiments, wet oxidation may not completely remove the relaxed layer portion 80. Here, a localized rejection of Ge may occur during oxidation, resulting in the presence of a residual Ge-rich SiGe region at the oxidation front, on the order of, for example, several nanometers in lateral extent. A surface clean may be performed to remove this residual Ge. For example, the residual Ge may be removed by a dry oxidation at, e.g., 600° C., after the wet oxidation and strip described above. Another wet clean may be performed in conjunction with—or instead of—the dry oxidation. Examples of possible wet etches for removing residual Ge include a Piranha etch, i.e., a wet etch that is a mixture of sulfuric acid and hydrogen peroxide (H2SO4:H2O2) at a ratio of, for example, 3:1. An HF dip may be performed after the Piranha etch. Alternatively, an RCA SC1 clean may be used to remove the residual Ge. The process of Piranha or RCA SC1 etching and HF removal of resulting oxide may be repeated more than once. In an embodiment, relaxed layer portion including, e.g., SiGe, is removed by etching and annealing under a hydrochloric acid (HCl) ambient.
In the case of a strained Si layer, the surface Ge concentration of the final strained Si surface is preferably less than about 1×1012 atoms/cm2 when measured by a technique such as total reflection x-ray fluorescence (TXRF) or the combination of vapor phase decomposition (VPD) with a spectroscopy technique such as graphite furnace atomic absorption spectroscopy (GFAAS) or inductively-coupled plasma mass spectroscopy (ICP-MS). In some embodiments, after cleaving, a planarization step or a wet oxidation step may be performed to remove a portion of the damaged relaxed layer portion 80 as well as to increase the smoothness of its surface. A smoother surface may improve the uniformity of subsequent complete removal of a remainder of relaxed layer portion 80 by, e.g., wet chemical etching. After removal of relaxed layer portion 80, strained layer 18 may be planarized. Planarization of strained layer 18 may be performed by, e.g., CMP; an anneal at a temperature greater than, for example, 800° C., in a hydrogen (H2) or hydrochloric acid (HCl) containing ambient; or cluster ion beam smoothing.
In an embodiment, dielectric layer 52 has a Tm greater than that of SiO2. During subsequent processing, e.g., MOSFET formation, SSOI substrate 100 may be subjected to high temperatures, i.e., up to 1100° C. High temperatures may result in the relaxation of strained layer 18 at an interface between strained layer 18 and dielectric layer 52. The use of dielectric layer with a Tm greater than 1700° C. may help keep strained layer 18 from relaxing at the interface between strained layer 18 and dielectric layer 52 when SSOI substrate is subjected to high temperatures.
In an embodiment, the misfit dislocation density of strained layer 18 may be lower than its initial dislocation density. The initial dislocation density may be lowered by, for example, performing an etch of a top surface 92 of strained layer 18. This etch may be a wet etch, such as a standard microelectronics clean step such as an RCA SCl, i.e., hydrogen peroxide, ammonium hydroxide, and water (H2O2+NH4OH+H2O), which at, e.g., 80° C. may remove silicon.
The presence of surface particles on strained layer 18, as described above with reference to
In some embodiments, strained semiconductor layer 18 includes Si and is substantially free of Ge; further, any other layer disposed in contact with strained semiconductor layer 18 prior to device processing, e.g., dielectric layer 52, is also substantially free of Ge.
Strained semiconductor-on-insulator substrate 100 may be further processed by CMOS SOI MOSFET fabrication methods. For example, referring to
In some embodiments, strained semiconductor layer 18 may be compressively strained when, for example, layer 18 includes strained Ge. Compressively strained layers may be prone to undulation when subjected to large temperature changes. The risk of such undulation may be reduced by reducing the thermal budget of a process for fabricating devices, such as transistor 200. The thermal budget may reduced by, for example, using atomic layer deposition (ALD) to deposit gate dielectric layer 210. Furthermore, a maximum temperature for forming gate 212 may be limited to, e.g., 600° C. by, for example, the use of materials comprising metal or metal compounds, rather than polysilicon or other gate materials that may require higher formation and/or dopant activation temperatures.
Semiconductor layer 256 a-256 c has a low resistivity of, e.g., 0.001 ohm-cm, that facilitates the formation of low-resistance contacts. To achieve this low resistivity, semiconductor layer 256 a-256 c is, for example, epitaxial silicon doped with, for example, arsenic to a concentration of 1×1020 atoms/cm3. Semiconductor layer 256 a-256 c may be doped in situ, during deposition. In alternative embodiments, semiconductor layer 256 a-256 c may be doped after deposition by ion implantation or by gas-, plasma- or solid-source diffusion. In some embodiments, the doping of semiconductor layer 256 a-256 c and the formation of source 262 and drain 266 are performed simultaneously. Portions of semiconductor layer 256 a, 256 c disposed over source 262 and drain 266 may have top surfaces substantially free of facets. In an embodiment, portions of source 262, drain 266, and/or gate 259 may be etched away to define recess prior to deposition of semiconductor layer 256 a-256 c, and semiconductor layer 256 a-256 c may then be deposited in the recesses thus formed.
Referring also to
In some embodiments, during formation, contact layer 276 a-276 c may consume substantially all of semiconductor layer 256 a-256 c. A bottommost boundary 278 a of contact layer 276 a, therefore, shares an interface 280 a with strained layer 18 in source 262, and a bottommost boundary 278 c of contact layer 276 c, therefore, shares an interface 280 c with strained layer 18 in drain 266. A bottommost boundary 278 b of contact layer 276 b shares an interface 280 b with gate 259.
In other embodiments, contact layer portions 276 a, 276 c, disposed over source 262 and drain 266, may extend into strained layer 18. Interfaces 280 a, 280 c between contact layer 276 a, 276 c and strained layer 18 are then disposed within source 262 and drain 266, respectively, above bottommost boundaries 282 a, 282 c of strained layer 18. Interfaces 280 a, 280 c have a low contact resistivity, e.g., less than approximately 5×10−7 Ω-cm2. In certain other embodiments, during formation, contact layer 276 a-276 c may not consume all of semiconductor layer 256 a-256 c (see
Because strained layer 18 includes a strained material, carrier mobilities in strained layer 18 are enhanced, facilitating lower sheet resistances. This strain also results in a reduced energy bandgap, thereby lowering the contact resistivity between the metal-semiconductor alloy and the strained layer.
In alternative embodiments, an SSOI structure may include, instead of a single strained layer, a plurality of semiconductor layers disposed on an insulator layer. For example, referring to
Referring also to
In an alternative embodiment, thin strained layer 84 may contain Si1-xGex with lower Ge content than relaxed layer 16. In this embodiment, thin strained layer 84 may act as a diffusion barrier during the wet oxidation process. For example, if the composition of relaxed layer 16 is 20% Ge (Si0.80Ge0.20), thin strained layer 84 may contain 10% Ge (Si0.90Ge0.10) to provide a barrier to Ge diffusion from the higher Ge content relaxed layer 16 during the oxidation process. In another embodiment, thin strained layer 84 may be replaced with a thin graded Si1-zGez layer in which the Ge composition (z) of the graded layer is decreased from relaxed layer 16 to the strained layer 18.
Referring again to
In addition to the transistors described above with reference to
A finFET (or any variant of the basic finFET structure such as the wrap-around gate FET, tri-gate FET, or omega FET) may be fabricated on SSOI substrate 100 as described below. The finFET and related devices include two gates located on either side of a FET channel region. Unlike in a traditional planar FET, this channel region is raised above the wafer surface: the channel (or portions of the channel) falls in a plane perpendicular to the wafer surface. There may in addition be gates above and/or below the channel region, such as in the wrap-around gate FET.
During the introduction of dopants into source and drain mesa regions 602, 604, a plurality of gate dopants 634 are also introduced into gate 622 and gate contact area 624. Gate dopants 634 serve to increase a conductivity of gate electrode material 620. Gate dopants 630 may be, for example, implanted arsenic or phosphorous ions for an n-type finFET.
Dopants for both n-type and p-type finFETs may be implanted at an angle of 20-50°, with zero degrees being normal to SSOI substrate 100. Implanting at an angle may be desired in order to implant ions into a side of exposed fins 600 and also into a side of the vertical surfaces of gate electrode material 620.
After the RIE definition of sidewall spacers 642, the portions of gate insulator layer 610 exposed by the RIE of gate electrode material 620 may be removed from top surfaces of source 630, and drain 632 by, e.g., a dip in hydrofluoric acid (HF), such as for 5-30 seconds in a solution containing, e.g., 0.5-5% HF. Alternately, this removal may be via RIE, with an etchant species such as, e.g., CHF3.
In an alternative embodiment, gate dielectric material may be removed from the top surfaces of the source and drain mesa regions immediately after the RIE of the gate electrode. In some embodiments, raised source and drain regions may be formed, as described above with reference to
Double Gate MOSFETs
A first gate insulator layer 700 is formed over strained layer 18. First gate insulator layer 700 may include SiO2 or a high-k dielectric like HfO2 or HiSiON, and may be grown or deposited. First gate insulator layer 700 may have a thickness T11 of, e.g., 10-100 Å. A first gate electrode layer 702 is formed over first gate insulator layer 700. First gate electrode layer 702 may include a conductive material, for example, doped polycrystalline silicon or tungsten, and may have a thickness T12 of, for example, 500-2000 Å.
Heterojunction Bipolar Transistor
A total thickness T21 of collector 810 may be increased to improve performance by subsequent additional deposition of a material that is lattice matched to the original strained layer 18 portion. The additional material may be, for example, SiGe lattice-matched to strained layer 18.
In some embodiments, the base doping may be significantly higher, e.g., ≧1020 atoms/cm3. In such embodiments, the outdiffusion of dopants from base 1010 may be deleterious to device performance, and therefore the p-type doping of base 1010 may be reduced within base 1010 in regions adjacent to an emitter 1110/base 1010 interface (see
In an embodiment, base 1010 contains an element with a concentration of 1×1018-1×1020 atoms/cm3 that suppresses the diffusion of dopants out of base 1010 during subsequent high temperature processing steps. A suitable element for diffusion suppression may be, for example, carbon. In another embodiment, base 1010 may be formed of SiGe, with the Ge content of base 1010 being not uniform across the thickness of base 1010. In this case, the Ge content of base 1010 may be graded in concentration, with higher Ge content at base-collector interface 1014 and lower Ge content at a base upper surface 1016. In other embodiments, the Ge content of base 1010 can have a trapezoidal or triangular profile.
Emitter 1110 has two regions: an upper emitter region 1111 and a lower emitter region 1112. Lower emitter region 1112 has a thickness T23 of 10-2000 Å and is doped with a same doping type as collector 810 (and hence the opposite doping type of base 1010). For example, lower emitter region 1112 and collector 810 may be doped n-type and base 1010 may be doped p-type. Lower emitter region 1112 may be doped at a concentration of 1×1017-5×1018 atoms/cm3, for example 1×1018 atoms/cm3. Upper emitter region 1111 has a thickness T24 of, for example, 100-4000 Å and is doped the same doping type as lower emitter region 1112. Upper emitter region 1111 may be doped at a concentration of 1×1019-1×1021 atoms/cm3, for example 1×1020-5×1020 atoms/cm3. An HBT 1200 includes collector 810, base 1010, and emitter 1110.
After formation of emitter 1110, metal contacts (not shown) may be made to each of collector 810, base 1010, and emitter 1110. Mask 910 may be removed or further patterned during the formation of metal contacts. HBT 1200 may be a standalone device or may be interconnected to other devices fabricated on SSOI substrate 100, such as, for example, transistor 200 (see
In an embodiment, HBT 1200 may be formed on SSOS substrate 420 (see
In another embodiment, HBT 1200 may be formed on a region of SSOI substrate 100 (see
Formation of SSOI Substrate by Use of a Porous Semiconductor Substrate
The bonding of strained silicon layer 18 to dielectric layer 52 has been experimentally demonstrated. For example, strained layer 18 having a thickness of 54 nanometers (nm) along with ˜350 nm of Si0.70Ge0.30 have been transferred by hydrogen exfoliation to Si handle wafer 50 having dielectric layer 52 formed from thermal SiO2 with a thickness of approximately 100 nm. The implant conditions were a dose of 4×1016 ions/cm3 of H2 + at 75 keV. The anneal procedure was 1 hour at 550° C. to split the SiGe layer, followed by a 1 hour, 800° C. strengthening anneal. The integrity of strained Si layer 18 and good bonding to dielectric layer 52 after layer transfer and anneal were confirmed with cross-sectional transmission electron microscopy (XTEM). An SSOI structure 100 was characterized by XTEM and analyzed via Raman spectroscopy to determine the strain level of the transferred strained Si layer 18. An XTEM image of the transferred intermediate SiGe/strained Si/SiO2 structure showed transfer of the 54 nm strained Si layer 18 and ˜350 nm of the Si0.70Ge0.30 relaxed layer 16. Strained Si layer 18 had a good integrity and bonded well to SiO2 54 layer after the annealing process.
XTEM micrographs confirmed the complete removal of relaxed SiGe layer 16 after oxidation and HF etching. The final structure includes strained Si layer 18 having a thickness of 49 nm on dielectric layer 52 including SiO2 and having a thickness of 100 nm.
Raman spectroscopy data enabled a comparison of the bonded and cleaved structure before and after SiGe layer 16 removal. Based on peak positions the compostion of the relaxed SiGe layer and strain in the Si layer may be calculated. See, for example, J. C. Tsang, et al., J. Appl. Phys. 75 (12) p. 8098 (1994), incorporated herein by reference. The fabricated SSOI structure 100 had a clear strained Si peak visible at ˜511/cm. Thus, the SSOI structure 100 maintained greater than 1% tensile strain in the absence of the relaxed SiGe layer 16. In addition, the absence of Ge—Ge, Si—Ge, and Si—Si relaxed SiGe Raman peaks in the SSOI structure confirmed the complete removal of SiGe layer 16.
In addition, the thermal stability of the strained Si layer was evaluated after a 3 minute 1000° C. rapid thermal anneal (RTA) to simulate an aggregate thermal budget of a CMOS process. A Raman spectroscopy comparision was made of SSOI structure 100 as processed and after the RTA step. A scan of the as-bonded and cleaved sample prior to SiGe layer removal was used for comparision. Throughout the SSOI structure 100 fabrication processs and subsequent anneal, the strained Si peak was visible and the peak position did not shift. Thus, the strain in SSOI structure 100 was stable and was not diminished by thermal processing. Furthermore, bubbles or flaking of the strained Si surface 18 were not observed by Nomarski optical microscopy after the RTA, indicating good mechanical stability of SSOI structure 100.
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.
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|Clasificación de EE.UU.||257/288, 438/197, 257/E21.448, 257/E29.295, 257/E21.568, 257/E21.703, 257/E21.415, 257/E29.298, 257/E21.564, 257/E27.112, 257/E29.297, 257/E21.57|
|Clasificación internacional||H01L21/762, H01L21/8234, H01L29/76, H01L21/84, H01L21/337, H01L27/12, H01L29/786, H01L21/336, H01L31/00|
|Clasificación cooperativa||H01L29/78687, H01L29/78684, H01L29/66795, H01L21/76254, H01L21/84, H01L27/1203, H01L21/76275, H01L21/76264, H01L29/785, H01L29/66772, H01L29/66916, H01L29/7842, H01L21/76259, H01L29/78603|
|Clasificación europea||H01L29/66M6T6T3, H01L29/66M6T6F16F, H01L29/66M6T6F15C, H01L29/78R, H01L29/786G, H01L21/762D20, H01L27/12B, H01L21/762D8F, H01L21/762D8B, H01L29/786A, H01L29/786G2, H01L21/84, H01L29/78S|
|11 Jul 2006||AS||Assignment|
Owner name: AMBERWAVE SYSTEMS CORPORATION, NEW HAMPSHIRE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LOCHTEFELD, ANTHONY J.;LANGDO, THOMAS A.;CURRIE, MATTHEWT.;AND OTHERS;REEL/FRAME:017909/0768;SIGNING DATES FROM 20030815 TO 20050418