US20060199346A1 - Source/Drain Extensions Having Highly Activated and Extremely Abrupt Junctions - Google Patents
Source/Drain Extensions Having Highly Activated and Extremely Abrupt Junctions Download PDFInfo
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- US20060199346A1 US20060199346A1 US11/379,426 US37942606A US2006199346A1 US 20060199346 A1 US20060199346 A1 US 20060199346A1 US 37942606 A US37942606 A US 37942606A US 2006199346 A1 US2006199346 A1 US 2006199346A1
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- source
- drain
- semiconductor wafer
- sidewall spacers
- dopants
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- 239000004065 semiconductor Substances 0.000 claims abstract description 69
- 239000002019 doping agent Substances 0.000 claims abstract description 51
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 37
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 8
- 125000006850 spacer group Chemical group 0.000 claims description 57
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 42
- 229910021332 silicide Inorganic materials 0.000 claims description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 239000007943 implant Substances 0.000 claims description 11
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- 238000002844 melting Methods 0.000 claims description 7
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 2
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- 238000004380 ashing Methods 0.000 description 2
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- 229910052681 coesite Inorganic materials 0.000 description 2
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
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- 101100107923 Vitis labrusca AMAT gene Proteins 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed. Also, a transistor source/drain region 80, 90 having a SiGe source/drain extension 90 that contains evenly distributed dopants, is highly doped, and has highly abrupt edges.
Description
- This invention relates to transistor source/drain extensions in semiconductor wafers.
-
FIG. 1 is a cross-sectional view of a partially fabricated semiconductor wafer in accordance with the present invention. -
FIGS. 2A 2Q are cross-sectional diagrams of a process for forming transistors in accordance with the present invention. - The present invention is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
- Referring to the drawings,
FIG. 1 is a cross-sectional view of a partially fabricatedsemiconductor wafer 10 in accordance with the present invention. In the example application,CMOS transistors semiconductor substrate 20 having anNMOS region 30 and aPMOS region 40. However, it is within the scope of the invention to use asemiconductor wafer 10 that contains any one of a variety of semiconductor devices, such as bipolar junction transistors, capacitors, or diodes. - The
example CMOS transistors trench isolation structures 50 formed within the NMOS andPMOS regions semiconductor wafer 10 is a single-crystalline substrate that is doped to be n-type and p-type; however, it may be formed by fabricating an epitaxial silicon layer on a single-crystal substrate. - In general, transistors are comprised of a gate, source, and drain. More specifically, as shown in
FIG. 1 , the active portion of thetransistors drain regions drains 80 and source/drain extensions 90. In addition, the active portion of thetransistors gate oxide 100 and agate polysilicon electrode 110. - The
example PMOS transistor 120 is a p-channel MOS transistor. Therefore it is formed within a n-well region 40 of thesemiconductor wafer 10. In addition, the deep sources anddrains 80 and the source anddrain extensions 90 have p-type dopants. The source anddrain extensions 90 may be lightly doped (LDD), medium doped (MDD), or highly doped (HDD). The PMOS transistor gate is created from p-type dopedpolysilicon 110 and a gate oxide dielectric 100. - Similarly, the
example NMOS transistor 130 is an n-channel MOS transistor. Therefore it is formed within a p-well region 30 of thesemiconductor wafer 10. In addition, the deep sources anddrains 80 and the source anddrain extensions 90 have n-type dopants. Similar toPMOS transistor 120, the source anddrain extensions 90 ofNMOS transistor 130 may be lightly doped (LDD), medium doped (MDD), or highly doped (HDD). The NMOS transistor gate is created from n-type dopedpolysilicon 110 and a gate oxide dielectric 100. - A sidewall spacer structure comprising
offset layers drain extensions 90 and the silicide 190 (described more fully below). The source/drain extension regions 90 are formed using thegate stack extension sidewall spacers 140 as a mask. Thesilicides 190 are formed using thegate stack contact sidewall spacers 150 as a mask. It is to be noted that the deep sources/drains 80 are formed using disposable deep source/drain sidewall spacers 142, 144 (FIGS. 2C-2E ), as described more fully below. - Immediately above and surrounding the transistors is a layer of
dielectric insulation 160. The composition ofdielectric insulation 160 may be any suitable material such as SiO2 or organosilicate glass (OSG). Thedielectric material 160 electrically insulates themetal contacts 170 that electrically connect theCMOS transistors FIG. 1 to other active or passive devices (not shown) located throughout thesemiconductor wafer 10. An optional dielectric liner (not shown) may be formed before the placement of thedielectric insulation layer 160. If used, the dielectric liner may be any suitable material such as silicon nitride. - In the example application, the
contacts 170 are comprised of W; however, any suitable material (such as Cu, Ti, or Al) may be used. In addition, anoptional liner material 180 such as Ti, TiN, or Ta (or any combination or layer stack thereof) may be used to reduce the contact resistance at the interface between theliner 180 and thesilicided regions 190 of thegate polysilicon layer 110 and the source/drain extensions 90. - Subsequent fabrication will create the back-end portion (not shown) of the
semiconductor wafer 10. The back-end generally contains one or more interconnect layers (and possibly via layers) that properly route electrical signals and power though out the completed integrated circuits. - The source/
drain extensions 90 are preferably made of SiGe. In addition, the source/drain extensions 90 contain a high level of dopants that are evenly distributed. More specifically,PMOS transistors 120 have highly activated SiGe source/drain extensions 90 that are evenly doped with B at a concentration above 2×1020 atoms/cc. However, it is within the scope of the invention to use any suitable dopant or dopant mixture, such as BF2 at a concentration above 2×1020 atoms/cc. Similarly,NMOS transistors 130 have highly activated SiGe source/drain extensions 90 that are evenly doped with P at a concentration above 4×1020 atoms/cc or As at a concentration above 4×1020 atoms/cc. However, it is within the scope of the invention to use any suitable dopant or dopant mixture, such as As plus P at a concentration above 8×1020 atoms/cc. - In addition, the SiGe source/
drain extensions 90 have highly abrupt edges. More specifically, the SiGe source/drain extensions 90 have abrupt junctions where dopants have negligible diffusion across the boundary with thesilicon substrate - These heavily doped (i.e. highly activated) SiGe source/
drain extensions 90 having evenly distributed dopants and highly abrupt edges have a lowered sheet resistance and thereby improved scalability. The improved scalability comes from a reduction in junction depth and an increase in the gradient of the dopant profile at the junction. - Referring again to the drawings,
FIGS. 2A 2Q are cross-sectional views of a partially fabricated semiconductor wafer illustrating a process for formingtransistors -
FIG. 2A is a cross-sectional view of the semiconductor wafer 10 after the formation of the p-wells 30, n-wells 40, shallowtrench isolation structures 50, and thegate stack semiconductor substrate 20. The fabrication processes used to form thesemiconductor wafer 10 shown inFIG. 2A are those that are standard in the industry. - In the example application, the
semiconductor substrate 20 is silicon; however any suitable material such as germanium or gallium arsenide may be used. The example gatesilicon oxide layer 100 is silicon dioxide formed with a thermal oxidation process. However, thegate dielectric layer 100 may be any suitable material, such as nitrided silicon oxide, silicon nitride, or a high-k gate dielectric material, and may be formed using any one of a variety of processes such as an oxidation process or thermal nitridation. - The
gate polysilicon electrode 110 is comprised of polycrystalline silicon in the example application. However, it is within the scope of the invention to use other materials such as an amorphous silicon, a silicon alloy, or other suitable materials. Thegate polysilicon layer 110 may be formed using any process technique such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). - The gate stack may be created through a variety of processes. For example, the gate stack may be created by forming a layer of photoresist over the semiconductor wafer, patterning the photoresist, and then using the patterned photoresist to etch the layer of
silicon oxide 100 and the layer ofpolysilicon 110. The gate stack may be etched using an suitable etch process, such as an anisotropic etch. - Generally, the next step in the fabrication of the
transistors FIG. 2B , the source/drain extensionsidewall spacer layer 140 is now formed on the outer surface of thegate stack sidewall spacer layer 140 is comprised of oxide. However, the source/drain extensionsidewall spacer layer 140 may be comprised of any suitable material, such as an oxynitride, silicon dioxide, nitride, or any other dielectric material or layers of dielectric materials. In addition, the extensionsidewall spacer layer 140 may be formed with any suitable process, such as thermal oxidation, deposited oxide, CVD, or PVD. - Next, disposable deep source/
drain sidewall spacers sidewall spacer layer 140, as shown inFIG. 2C . These sidewall spacers are considered disposable because they will not be left on thefinal semiconductor wafer 10. The deep source/drain sidewall spacers FIG. 2C , the preferred deep source/drain sidewall spacers are comprised of anoxide layer 142 and asilicon nitride layer 144 that are formed with a CVD process and subsequently anisotropically etched. However, it is within the scope of the invention to use more layers (i.e. a spacer oxide layer, a silicon nitride layer, and a final oxide layer) or less layers (i.e. just an oxide layer or a nitride layer) to create the deep source/drain sidewall spacers - The deep source/drain sidewall spacer layers are now etched to create the deep source/
drain sidewall spacers FIG. 2D . In the example application, the deep source/drain sidewall layers 142 and 144 are etched with a standard anisotropic plasma etch. This etch may be performed using any suitable machine such as an etching machine made by Applied Materials. Thenitride layer 144 is etched first, using suitable anisotropic etch chemistry such as CF4. Then, theoxide layer 142 is etched (generally in the same etch machine) using any suitable anisotropic etch chemistry such as CF4+Ar. The formation of the deep source/drain sidewall spacers semiconductor wafer 10 is subjected to a standard post-etch cleaning process (i.e. using a FSI Mercury machine with a wet chemistry of Piranha+SC1). - The next step is to use the disposable deep source/
drain sidewall spacers 142, 144 (as well as the gate silicon layer 110) as a template for the implantation of dopants into the locations for the deep sources and drains. The implantation of dopants into the locations for the deep sources and drains 80, shown inFIG. 2E , may be accomplished through any one of a variety of processes, such as deep ion implantation or deep diffusion. The dopants used to create the deep sources and drains 80 for PMOS transistors are typically boron and for NMOS transistors are typically arsenic; however, other dopants or combinations for dopants may be used. - The implantation of the dopants is self-aligned with respect to the outer edges of the deep source/
drain sidewall spacers drain sidewall spacers 144. - Now the disposable deep source/
drain sidewall spacers sidewall spacers semiconductor wafer 10 at this stage in the manufacturing process is shown inFIG. 2F . - In the example application, the source/
drain regions 80 are activated by a source/drain anneal step. However, this anneal step may be performed at any stage in the manufacturing process, such as before the removal of the deep source/drain sidewall spacers - Now, as shown in
FIG. 2G , the source/drainextension sidewall spacer 140 is reshaped to create the final source/drain extensionsidewall spacer structures 140. In the example application the source/drain extensionsidewall spacer layer 140 is reshaped using an anisotropic etch process; however, any suitable process may be used. - These source/drain
extension sidewall spacers 140 are now used as a template to facilitate the proper placement of the source/drain extensions 90, as shown inFIG. 2H . The first step in the formation of the source/drain extensions 90 is etching thesemiconductor wafer drain extensions 90. Any suitable manufacturing process may be used to etch the wafer surface, such as an anisotropic silicon etch using an AMAT plasma etcher. It is to be noted that this plasma etch may also slightly reduce the height of thegate polysilicon layer 110. - The next step in the formation of the source/
drain extensions 90 in the example application is the deposition of SiGe on the exposed silicon surfaces. More specifically, any suitable process such as selective epitaxial deposition is used to deposit SiGe into the recesses for the source/drain extensions 90 and thegate polysilicon 110. Preferably, SiGe is deposited so that the original thickness of the source/drain extension 90 is restored, as shown inFIG. 2I . However, it is within the scope of the invention to create source/drain extensions 90 having a higher or lower surface than the original surface of thesemiconductor wafer - The composition of the SiGe deposited in the recesses of the source/
drain extensions 90 can be adjusted to accommodate a targeted melting point. In general, a higher Ge content results in a lower melting point for the deposited SiGe material. Preferably, the SiGe that is deposited contains 20% Ge by volume and a melting point of approximately 1300° C. Therefore, the melting point of the SiGe source/drain extensions 90 is lower than the melting point of the silicon (20, 30, 40, 80, and 110) and the other materials (50, 140) of thesemiconductor wafer 10 at this stage of the manufacturing process. - The next step in the formation of the source/
drain extensions 90 is ion implantation of dopant species into the source/drain extensions 90. A standard mask process is used to facilitate the implantation of dopants into the SiGe source/drain extensions 90 of the NMOS transistors that are different than the dopants implanted into the SiGe source/drain extensions 90 of the PMOS transistors. As shown inFIG. 2J ,photoresist material 200 is deposited over thesemiconductor wafer 10 and then patterned to expose the PMOS transistor 120 (and simultaneously protect the NMOS transistor). Now, any suitable process such as such as ion implantation or plasma doping may be used to implant dopants into the SiGe source/drain extensions 90 of thePMOS transistor 120. Preferably, B is implanted into the SiGe source/drain extensions 90 of thePMOS transistor 120; however, any other dopant such as BF2 may be deposited. In addition, B is preferably deposited at a concentration above 2×1020 atoms/cc. It is to be noted that the energy setting of the ion implanter will determine the depth at which the majority of dopants will reside at this stage in the manufacturing process. - Now the patterned
photoresist 200 is removed from thesemiconductor wafer 10 with a standard ashing process. Next, a layer ofphotoresist 200 is reapplied to thesemiconductor wafer 10 and patterned to expose the NMOS transistors 130 (and simultaneously protect the PMOS transistor 120), as shown inFIG. 2K . The ion implantation process is repeated and dopant is now deposited in the SiGe source/drain extensions 90 of theNMOS transistor 130. Preferably, the dopant is As that is deposited at a concentration above 4×1020 atoms/cc. However, other suitable dopants may be deposited, such as P at a concentration above 4×1020 atoms/cc or As plus P at a concentration above 8×1020 atoms/cc. Once the SiGe source/drain extensions 90 of theNMOS transistor 130 are implanted with dopants, a standard ashing process is used to remove thephotoresist 200, as shown inFIG. 2L . - The dopants within the SiGe source/
drain extensions 90 are now activated by an annealing process. This post extension implant anneal step is preferably performed with a continuous wave (CW) laser annealing process. For example, a CO2 laser annealer may be used for a duration between 200 μs and 5 ms at a power density between 0.2 kW/mm2 and 1 kW/mm2 (but preferably at 0.5 kW/mm2). The laser radiation will cause the dopants to rapidly diffuse. The resultant SiGe source/drain extensions 90 will have evenly distributed and highly activated dopants. - In addition, the SiGe source/
drain extensions 90 will have extremely abrupt junctions. The extremely abrupt junctions are formed by the present invention because the melting point of the SiGe source/drain extensions 90 is lower than the other components of the semiconductor wafer 10 (preventing almost all of the dopants from crossing into thesilicon wafer 30, 40). Therefore, only the SiGe source/drain extensions 90 will melt during the laser annealing process. - It is within the scope of the invention to use other suitable processes for this annealing step. For example, a pulsed laser anneal, a flash anneal, or an arc lamp anneal may be used.
- An optional additional anneal is now performed to reduce the crystal damage within the
semiconductor wafer 10. This additional anneal may be performed using any suitable process such as a flash RTA. - The next step in the example manufacturing process is the silicide loop. The purpose of the silicide loop is the creation of silicide 190 (see
FIG. 1 ). However, thesemiconductor wafer 10 is prepared for the silicide loop by formingcontact sidewall spacers 150, which will be used to facilitate the proper placement of thesilicide 190. As shown inFIG. 2L , the first step in the formation of the preferredcontact sidewall spacers 150 is the deposition of theoxide layer 152. Theoxide layer 152 may be deposited by any suitable process such as CVD. Next, thenitride layer 154 is deposited over theoxide layer 152. Thenitride layer 154 may also be deposited by any suitable process such as CVD. It is within the scope of the invention to use more layers (i.e. a spacer oxide layer, a silicon nitride layer, and a final oxide layer) or less layers (i.e. just an oxide layer or a nitride layer) to create the contact sidewall spacers. - The contact sidewall spacer layers 152, 154 are now etched to create the
contact sidewall spacers 150, as shown inFIG. 2N . In the example application, the contactsidewall nitride layer 154 is etched with a standard anisotropic dry etch. Then the contactsidewall oxide layer 152 is etched with a standard wet or dry etch. The formation of thecontact sidewall spacers 150 is now complete and thesemiconductor wafer 10 is subjected to a standard post-etch cleaning process. The active silicon surfaces of thesemiconductor wafer 10 are now exposed and ready for further processing. - The first step of the silicide loop is the deposition of an
interface layer 210 over the top surface of thesemiconductor wafer 10, as shown inFIG. 2O . Theinterface layer 210 is preferably comprised of Ni; however, other suitable materials such as Co may be used. - An optional capping layer (not shown) may also be formed over the
interface layer 210. If used, the capping layer acts as a passivation layer that prevents the diffusion of oxygen from ambient into theinterface layer 210. The capping layer may be any suitable material, such as TiN. - The second step of the silicide loop is an anneal. The
semiconductor wafer 10 may be annealed with any suitable process, such as RTA. This anneal process will cause a silicide 190 (i.e. a Ni-rich silicide or Ni mono-silicide) to form over all active surfaces that are in contact with theinterface layer 210; namely, at the surface of the source/drain extensions 90, the surface of thewell regions gate electrodes 110. Thesesilicide regions 190 are shown inFIG. 2P . - It is to be noted that the
interface layer 210 will only react with the active substrate (i.e. exposed Si); namely, the source/drain extensions 90, thegate electrode 110, and the unmodified surfaces ofwell regions silicide 190 formed by this annealing process is considered a self-aligned silicide (salicide). - The third step in the silicide loop is the removal of the
interface layer 210, as shown inFIG. 2Q . The interface layer 210 (and the capping layer, if used) are removed using any suitable process such as a wet etch process (i.e. using a fluid mixture of sulfuric acid, hydrogen peroxide, and water). - The fourth step of the silicide loop is to perform a second anneal (such as a RTA) to further react the
silicide 190 with the exposed surfaces ofwell regions gate electrode 110, and the extension sources and drains 90. If the initial anneal process of the silicide loop did not complete the silicidation process, this second anneal will ensure the formation of a mono-silicide NiSi—which lowers the sheet resistance of thesilicide 190. - The fabrication of the
semiconductor wafer 10 now continues using standard manufacturing processes. Generally, the next step is the formation of the dielectric layer. Referring toFIG. 1 , thedielectric insulator layer 160 may be formed using plasma-enhanced chemical vapor deposition (PECVD) or another suitable process. Thedielectric insulator 160 may be comprised of any suitable material such as SiO2 or OSG. - The
contacts 170 are formed by etching thedielectric insulator layer 160 to expose the desired gate, source and/or drain location. An example etch process for creating the contact holes is an anisotropic etch. The etched holes are usually filled with aliner 180 before forming thecontacts 170 in order to improve the electrical interface between thesilicide 190 and thecontact 170. Then thecontacts 170 are formed within theliner 180; creating the initial portion of the electrical interconnections from thetransistors semiconductor substrate 10. - The fabrication of the final integrated circuit now continues with the fabrication of the back-end structure (not shown). As discussed above, the back-end structure contains the metal interconnect layers of the integrated circuit. Once the fabrication process is complete, the integrated circuit will be tested and packaged.
- Various additional modifications to the invention as described above are within the scope of the claimed invention. As an example, the
semiconductor wafer 10 may be subjected to a wafer cleaning process after any step in the manufacturing process to remove contamination from the wafer. In addition, an anneal process may be performed after any step in the above-described fabrication process. When used, the anneal process can improve the microstructure of materials and thereby improve the quality of the semiconductor structure. - Furthermore, the
silicides 190 may be comprised of other materials such as titanium, tungsten, tantalum, or other conventional silicide materials or combinations of silicide materials. Similarly, instead of depositing SiGe, other suitable materials such as amorphous silicon (αSi) may be deposited in the recesses of the source/drain extensions 90 to form αSi source/drain extensions 90. Moreover, this invention may be implemented in other semiconductor structures such as capacitors or diodes, and also in different transistor structures such as biCMOS and bipolar transistors. - While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.
Claims (28)
1. A method for making a transistor within a semiconductor wafer, comprising:
forming a gate stack, said gate stack having a gate silicon oxide layer coupled to said semiconductor wafer and a gate polysilicon layer coupled to said gate silicon oxide layer;
forming source/drain extension sidewall spacers coupled to said gate stack;
forming deep source/drain sidewall spacers coupled to said source/drain extension sidewall spacers;
implanting dopants into said semiconductor wafer at deep source/drain locations;
removing said deep source/drain sidewall spacers;
reshaping said source/drain extension sidewall spacers;
etching a recess in a surface of said semiconductor wafer at source/drain extension locations;
depositing SiGe within each said recess to form SiGe source/drain extensions;
implanting dopants into said SiGe source/drain extensions; and
performing a first post extension implant anneal of said semiconductor wafer.
2. The method of claim 1 further comprising:
performing a second post extension implant anneal of said semiconductor wafer;
forming contact sidewall spacers coupled to said etched source/drain extension sidewall spacers; and
performing a silicide loop to form a silicide within exposed top surfaces of said SiGe source/drain extensions and said gate polysilicon layer.
3. The method of claim 2 wherein said step of performing a second post extension implant anneal of said semiconductor wafer comprises a flash RTA.
4. The method of claim 2 wherein said step of forming contact sidewall spacers comprises:
forming a layer of oxide over said semiconductor wafer;
forming a layer of silicon nitride over said layer of oxide; and
etching said layers of oxide and nitride to form said contact sidewall spacers.
5. The method of claim 2 wherein said step of performing a silicide loop comprises:
forming an interface layer over said semiconductor wafer;
performing a first silicide anneal to form said silicide on said exposed top surfaces of said SiGe source/drain extensions and said gate polysilicon layer;
removing said interface layer; and
performing a second silicide anneal to recrystalize said silicide.
6. The method of claim 5 wherein said interface layer comprises nickel.
7. The method of claim 1 further comprising:
annealing said semiconductor wafer to create deep source/drains before said step of removing said deep source/drain sidewall spacers.
8. The method of claim 1 further comprising:
annealing said semiconductor wafer to create deep source/drains after said step of removing said deep source/drain sidewall spacers.
9. The method of claim 1 wherein said step of forming source/drain extension sidewall spacers comprises forming a layer of oxide and then a layer of nitride over said semiconductor wafer.
10. The method of claim 1 wherein said step of forming deep source/drain sidewall spacers comprises:
forming a layer of oxide over said semiconductor wafer; and
forming a layer of nitride over said layer of oxide.
11. The method of claim 1 wherein said step of implanting dopants into said semiconductor wafer at deep source/drain locations comprises implanting B dopants at a concentration above 2×1020 atoms/cc.
12. The method of claim 1 wherein said step of implanting dopants into said semiconductor wafer at deep source/drain locations comprises implanting P dopants at a concentration above 4×1020 atoms/cc.
13. The method of claim 1 wherein said step of implanting dopants into said semiconductor wafer at deep source/drain locations comprises implanting As dopants at a concentration above 4×1020 atoms/cc.
14. The method of claim 1 wherein said step of implanting dopants into said semiconductor wafer at deep source/drain locations comprises implanting a mixture of As and P dopants at a concentration above 8×1020 atoms/cc.
15. The method of claim 1 wherein said deposited SiGe contains approximately 20% Ge.
16. The method of claim 1 wherein said deposited SiGe has a melting point of approximately 1300° C.
17. The method of claim 1 wherein said step of performing a first post extension implant anneal of said semiconductor wafer comprises a continuous wave laser anneal.
18. The method of claim 1 wherein said step of performing a first post extension implant anneal of said semiconductor wafer comprises a pulsed laser anneal.
19. The method of claim 1 wherein said step of performing a first post extension implant anneal of said semiconductor wafer comprises a flash anneal.
20. The method of claim 1 wherein said step of performing a first post extension implant anneal of said semiconductor wafer comprises a arc lamp anneal.
21. The method of claim 1 wherein said step of reshaping said source/drain extension sidewall spacers comprises anisotropically etching said source/drain extension sidewall spacers.
22. A transistor source/drain region, comprising:
a deep source/drain; and
a source/drain extension coupled to said deep source/drain, said source/drain extension having SiGe that contains evenly distributed dopants, is highly doped, and has highly abrupt edges.
23. The transistor source/drain region of claim 22 wherein said evenly distributed dopants are B with a concentration above 2×1020 atoms/cc.
24. The transistor source/drain region of claim 22 wherein said evenly distributed dopants are P with a concentration above 4×1020 atoms/cc.
25. The transistor source/drain region of claim 22 wherein said evenly distributed dopants are As with a concentration above 4×1020 atoms/cc.
26. The transistor source/drain region of claim 22 wherein said evenly distributed dopants are a mixture of As and P with a concentration above 8×1020 atoms/cc.
27. A method for making a transistor within a semiconductor wafer, comprising:
forming a gate stack, said gate stack having a gate silicon oxide layer coupled to said semiconductor wafer and a gate polysilicon layer coupled to said gate silicon oxide layer;
forming source/drain extension sidewall spacers coupled to said gate stack;
forming deep source/drain sidewall spacers coupled to said source/drain extension sidewall spacers;
implanting dopants into said semiconductor wafer at deep source/drain locations;
removing said deep source/drain sidewall spacers;
reshaping said source/drain extension sidewall spacers;
etching a recess in a surface of said semiconductor wafer at source/drain extension locations;
depositing amorphous silicon within each said recess to form αSi source/drain extensions;
implanting dopants into said αSi source/drain extensions; and
performing a first post extension implant anneal of said semiconductor wafer.
28. The method of claim 27 further comprising:
performing a second post extension implant anneal of said semiconductor wafer;
forming contact sidewall spacers coupled to said etched source/drain extension sidewall spacers; and
performing a silicide loop to form a silicide within exposed top surfaces of said αSi source/drain extensions and said gate polysilicon layer.
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Also Published As
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US7247535B2 (en) | 2007-07-24 |
US20070099388A1 (en) | 2007-05-03 |
US7666748B2 (en) | 2010-02-23 |
US20060073665A1 (en) | 2006-04-06 |
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