US20060211178A1 - Fabrication of lean-free stacked capacitors - Google Patents
Fabrication of lean-free stacked capacitors Download PDFInfo
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- US20060211178A1 US20060211178A1 US11/405,340 US40534006A US2006211178A1 US 20060211178 A1 US20060211178 A1 US 20060211178A1 US 40534006 A US40534006 A US 40534006A US 2006211178 A1 US2006211178 A1 US 2006211178A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- A—HUMAN NECESSITIES
- A23—FOODS OR FOODSTUFFS; TREATMENT THEREOF, NOT COVERED BY OTHER CLASSES
- A23L—FOODS, FOODSTUFFS, OR NON-ALCOHOLIC BEVERAGES, NOT COVERED BY SUBCLASSES A21D OR A23B-A23J; THEIR PREPARATION OR TREATMENT, e.g. COOKING, MODIFICATION OF NUTRITIVE QUALITIES, PHYSICAL TREATMENT; PRESERVATION OF FOODS OR FOODSTUFFS, IN GENERAL
- A23L7/00—Cereal-derived products; Malt products; Preparation or treatment thereof
- A23L7/10—Cereal-derived products
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- A—HUMAN NECESSITIES
- A23—FOODS OR FOODSTUFFS; TREATMENT THEREOF, NOT COVERED BY OTHER CLASSES
- A23P—SHAPING OR WORKING OF FOODSTUFFS, NOT FULLY COVERED BY A SINGLE OTHER SUBCLASS
- A23P30/00—Shaping or working of foodstuffs characterised by the process or apparatus
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
- B65G—TRANSPORT OR STORAGE DEVICES, e.g. CONVEYORS FOR LOADING OR TIPPING, SHOP CONVEYOR SYSTEMS OR PNEUMATIC TUBE CONVEYORS
- B65G21/00—Supporting or protective framework or housings for endless load-carriers or traction elements of belt or chain conveyors
- B65G21/10—Supporting or protective framework or housings for endless load-carriers or traction elements of belt or chain conveyors movable, or having interchangeable or relatively movable parts; Devices for moving framework or parts thereof
- B65G21/12—Supporting or protective framework or housings for endless load-carriers or traction elements of belt or chain conveyors movable, or having interchangeable or relatively movable parts; Devices for moving framework or parts thereof to allow adjustment of position of load-carrier or traction element as a whole
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
Definitions
- the present invention relates generally to integrated circuit fabrication, and more particularly, to fabrication of lean-free stacked capacitors that may be used for DRAM (dynamic random access memory).
- DRAM dynamic random access memory
- FIG. 1 shows a simplified schematic of a DRAM (dynamic random access memory) cell 100 including a switching transistor 102 and a storage capacitor 104 .
- a DRAM includes an array of such DRAM cells.
- the switching transistor 102 is an NMOSFET (N-channel metal oxide semiconductor field effect transistor)
- the gate of the NMOSFET 102 is coupled to a word-line 106 of the DRAM
- the drain of the NMOSFET 102 is coupled to a bit-line 108 of the DRAM.
- the DRAM cells along a same column are coupled to a same bit-line, and the DRAM cells along a same row are coupled to a same word-line.
- the source of the NMOSFET 102 is coupled to a storage node of the storage capacitor 104 .
- the other node of the storage capacitor 104 is coupled to a ground node.
- the bit-line 108 is coupled to a sense amplifier 110 .
- the voltage across the storage capacitor 104 determines the logical level “1” or “0” stored within the DRAM cell 100 .
- the sense amplifier 110 outputs such a stored logical level at the storage node of the storage capacitor 104 .
- a parasitic capacitance 112 at the bit-line 108 , disadvantageously deteriorates the voltage signal, Vsignal, to the sense amplifier 110 since Vsignal is directly proportional to Cs/Cp, with Cs being the capacitance of the storage capacitor 104 and Cp being the capacitance of the parasitic capacitor 112 .
- the capacitance, Cs, of the storage capacitor 104 is desired to be maximized to provide sufficient voltage signal, Vsignal, to the sense amplifier 110 and for enhancing retention time for the DRAM cell 100 .
- the area occupied by the DRAM cell 100 is also desired to be minimized.
- a stacked capacitor having electrodes formed vertically upwards is used for the storage capacitor 104 of the DRAM cell 100 .
- ⁇ is the dielectric constant of the dielectric between the two electrodes, and d is the thickness of such a dielectric.
- FIG. 2 illustrates a cross-sectional view of a first stacked capacitor 112 and a second stacked capacitor 114 .
- the first stacked capacitor 112 includes a first electrode 116 coupled, via a conductive plug structure 118 , to a junction of a switching transistor (not shown for clarity of illustrate in FIG. 2 ) for a first DRAM cell formed with a semiconductor substrate 120 .
- the second stacked capacitor 114 includes a first electrode 122 coupled, via a conductive plug structure 124 , to a junction of a switching transistor (not shown for clarity of illustrate in FIG. 2 ) for a second DRAM cell formed with the semiconductor substrate 120 .
- the area of overlap between the first and second electrodes is desired to be maximized.
- the height of the first and second electrodes is desired to be maximized.
- the adjacent first electrodes 116 and 122 that are exposed during fabrication may lean towards each-other with the support dielectric 126 being disposed just toward the bottom of the electrodes 116 and 122 .
- the area occupied by the DRAM is desired to be further minimized with advancement of IC (integrated circuit) fabrication technology.
- the first electrodes 116 and 122 are desired to be disposed closer together.
- Such exposed and leaning electrodes 116 and 122 when disposed close enough together may disadvantageously contact each-other during fabrication resulting in malfunction of the DRAM.
- FIG. 3 U.S. Patent Application Publication No. US 2003/0085420 to Ito et al. discloses stacked capacitors 142 and 144 with support beams 146 disposed above the layer of support dielectric 126 for preventing leaning of the first electrodes 116 and 122 .
- FIG. 4 shows a cross-sectional view across line A-A of FIG. 3 through the support beams 146 .
- Elements having the same reference number in FIGS. 2, 3 , 4 , 5 , 6 , and 7 refer to elements having similar structure and function.
- support beams 146 are formed on the four sides of a first electrode 116 .
- each support beam 146 is disposed between two adjacent first electrodes 116 and 122 , well above the bottom support dielectric 126 .
- the support beams 146 prevent the exposed top portions of two adjacent first electrodes 116 and 122 from leaning against each other during fabrication of the stacked capacitors 142 and 144 .
- FIGS. 5, 6 , and 7 illustrate cross-sectional views across line A-A of FIG. 3 during fabrication of the support beams 146 .
- a material comprising the support beams 146 is first patterned on a sacrificial dielectric material 148 .
- openings 150 , 152 , 154 , and 156 are each formed around an intersection point of the support beams 146 .
- a respective first electrode is formed at the walls of each of the openings 150 , 152 , 154 , and 156 .
- FIG. 7 shows the example first electrodes 116 and 122 .
- the sacrificial dielectric material 148 is etched away, and the gate electric 128 and the second electrode 130 are formed onto exposed surfaces of the first electrodes and the support beams 146 .
- the support beams 146 are formed before the stacked capacitors are formed within the openings 150 , 152 , 154 , and 156 .
- subsequent etching steps may decrease the width (w) and the thickness of the support beams 146 .
- the width and the thickness of the support beams 146 are more difficult to control in the prior art.
- support structures for preventing leaning of adjacent first electrodes of stacked capacitors are formed after formation of the first electrodes.
- openings are formed through layers of materials including a layer of support material displaced from a bottom of the openings.
- a respective first electrode is formed for a respective capacitor within each of the openings.
- the layer of support material is patterned to form support structures around the first electrodes, after formation of the first electrodes within the openings.
- At least one of the layers of materials toward the top of the first electrodes is etched away such that a top portion of the first electrodes is exposed and such that the support material is exposed.
- Masking spacers are formed with a masking material around the exposed top portions of the first electrodes.
- a mask structure of the masking material remains on joining portions of the support material. Exposed portions of the support material are etched away such that the support structures including the joining portions are formed from the remaining support material. Each joining portion is disposed between the first electrodes of adjacent capacitors.
- the masking material is deposited with a thickness that is greater than 1 ⁇ 2 of a length of the joining portions, before forming the masking spacers.
- the support structures include a respective disc that may be a circular disc surrounding each first electrode. Also for such an example embodiment, the respective disc surrounding each first electrode is further etched such that a respective beam remains for each of the joining portions as the support structures.
- a layer of mount material is formed to surround the openings toward the bottom of the openings.
- the support structures are disposed between the mount material and the top of the first electrodes.
- the layers of materials are etched away except for the support structures, the mount material, and the first electrodes.
- a capacitor dielectric is formed on exposed surfaces of such remaining structures, and a second electrode is formed on the capacitor dielectric.
- the openings are formed through a plurality of mold layers, with a respective etch rate of each mold layer successively increasing toward a bottom of the openings.
- the openings are not substantially narrow toward the bottom of the openings.
- the support structures for preventing leaning of the first electrodes of the stacked capacitors are formed after the first electrodes are fabricated within the openings. Thus, less subsequent etching steps do not deteriorate the structural integrity of the support structures.
- masking spacers are formed using the first electrodes for easily patterning the support structures around the first electrodes.
- FIG. 1 shows a simplified schematic of a DRAM (dynamic random access memory) cell, according to the prior art
- FIG. 2 shows a cross-sectional view of stacked capacitors used for DRAM with just a mount material surrounding a bottom of the stacked capacitors, according to the prior art
- FIG. 3 shows a cross-sectional view of stacked capacitors with support beams disposed between adjacent stacked capacitors for preventing leaning of first electrodes of such capacitors, according to the prior art
- FIG. 4 shows a cross-sectional view across line A-A of FIG. 3 , according to the prior art
- FIGS. 5, 6 , and 7 show the cross-sectional view of FIG. 4 during fabrication of the supports beams and the first electrodes of the stacked capacitors, according to the prior art
- FIG. 8 shows two directions, B-B and C—C, across a top view of a semiconductor substrate for illustrating cross-sectional views of stacked capacitors formed across such directions, according to an embodiment of the present invention
- FIGS. 9A, 10A , 11 A, 12 A, 13 A, 14 A, 15 A, 16 A, 18 A, 19 A, 20 A, 21 A, and 23 A show cross-sectional views along the B-B direction of FIG. 8 for illustrating fabrication of stacked capacitors, according to an embodiment of the present invention
- FIGS. 9B, 10B , 11 B, 12 B, 13 B, 14 B, 15 B, 16 B, 18 B, 19 B, 20 B, 21 B, and 23 B show cross-sectional views along the C-C direction of FIG. 8 for illustrating fabrication of stacked capacitors, according to an embodiment of the present invention
- FIG. 17 shows a top view of first electrodes of the stacked capacitors formed after FIGS. 16A and 16B , according to an embodiment of the present invention
- FIG. 22 shows a top view of the support structures including circular discs surrounding the first electrodes after FIGS. 21A and 21B , according to an embodiment of the present invention
- FIG. 24 shows a top view of the support structures comprising support beams disposed between adjacent first electrodes after further etching of the circular discs of FIG. 22 , according to another embodiment of the present invention
- FIGS. 26A, 27A , 28 A, 29 A, 30 A, and 31 A show cross-sectional views along the B-B direction of FIG. 8 for illustrating fabrication of stacked capacitors, with openings formed through mold layers having different etch rates according to another embodiment of the present invention
- FIG. 32 shows the cross-sectional view similar to FIG. 31A but with the circular discs surrounding the first electrodes etched away after FIG. 30A .
- FIGS. 1-32 refer to elements having similar structure and function.
- FIGS. 9A, 10A , 11 A, 12 A, 13 A, 14 A, 15 A, 16 A, 18 A, 19 A, 20 A, 21 A, and 23 A show cross-sectional views along a B-B direction of FIG. 8 for fabrication of stacked capacitors, according to an embodiment of the present invention.
- FIGS. 9B, 10B , 11 B, 12 B, 13 B, 14 B, 15 B, 16 B, 18 B, 19 B, 20 B, 21 B, and 23 B show cross-sectional views along a C-C direction of FIG. 8 for fabrication of stacked capacitors, according to an embodiment of the present invention.
- the stacked capacitors are part of the DRAM fabricated on the semiconductor substrate 202 .
- the B-B direction of FIG. 8 crosses through a plurality of word-lines of such a DRAM, and the C-C direction of FIG. 8 crosses through a plurality of bit-lines of such a DRAM.
- a plurality of STI (shallow trench isolation) structures 204 are formed into the semiconductor substrate 202 .
- the STI structures 204 are comprised of a dielectric material such as silicon dioxide (SiO 2 ) in an embodiment of the present invention.
- a first switching transistor 206 and a second switching transistor 208 are formed in an active device area of the semiconductor substrate 202 between the STI structures 204 .
- the first and second switching transistors 206 and 208 share a drain junction 210 . Additionally, a first source junction 212 is formed for the first switching transistor 206 , and a second source junction 214 is formed for the second switching transistor 208 . Such junctions 210 , 212 , and 214 are doped with an N-type dopant for forming an NMOSFET (N-channel metal oxide semiconductor field effect transistor) for each of the first and second switching transistors 206 and 208 , in an example embodiment of the present invention.
- NMOSFET N-channel metal oxide semiconductor field effect transistor
- a first gate stack comprised of a first gate dielectric 216 , a first gate structure 218 , and a first gate mask 220 , is formed for the first NMOSFET 206 .
- a second gate stack comprised of a second gate dielectric 222 , a second gate structure 224 , and a second gate mask 226 , is formed for the second NMOSFET 208 .
- a repeating pattern of such gate stacks are formed across the semiconductor substrate 202 such that such gate stacks are also formed onto the STI structures 204 in FIG. 9A .
- the gate dielectrics 216 and 222 are comprised of silicon dioxide (SiO 2 ), the gate structures 218 and 224 are comprised of polysilicon, and the gate masks 220 and 226 are comprised of silicon nitride (SiN).
- Each of the gate structures 218 and 224 forms a word-line across a row of DRAM cells.
- the STI structures 204 are formed across the C-C direction of FIG. 8 after the formation of the NMOSFETs 206 and 208 in FIG. 9A .
- spacer structures 228 are formed onto sidewalls of each of the gate stacks.
- Such spacer structures 228 are comprised of a dielectric material such as silicon dioxide (SiO 2 ) in an example embodiment of the present invention.
- first conductive plugs 230 are formed from a SAC (self aligned contact) process with the exposed junctions 210 , 212 , and 214 .
- SAC self aligned contact
- FIG. 10B the first conductive plugs 230 are also formed across the C-C direction of FIG. 8 from such a SAC process with exposed regions of the semiconductor substrate 202 .
- a first ILD (inter-level dielectric) layer 232 surrounds the first conductive plugs 230 in FIG. 9B .
- the first ILD layer 232 is comprised of a dielectric material such as BPSG (borophosphosilicate glass) in an example embodiment of the present invention.
- the first conductive plugs 230 are comprised of polysilicon in an example embodiment of the present invention.
- a second ILD (inter-level dielectric) layer 234 and a third ILD (inter-level dielectric) layer 236 are deposited.
- the second ILD layer 234 is comprised of BPSG (borophosphosilicate glass)
- the third ILD layer 236 is comprised of a dielectric material such as PSG (phosphosilicate glass) formed from a HDP (high density plasma) deposition process, in an example embodiment of the present invention.
- Openings 238 are formed through the second and third ILD layers 234 and 236 over the first conductive plugs 230 disposed above the source junctions 212 and 214 .
- Second conductive plugs 240 are formed within the openings 238 and over the first conductive plugs 230 .
- bit-line stacks each comprised of a bit-line 242 and a bit-line mask 244 , are patterned on the second ILD layer 234 .
- Spacer structures 246 are formed at the sidewalls of the bit-line stacks.
- the second conductive plugs 240 are formed over the first conductive plugs 230 .
- the bit-lines 242 are comprised of tungsten (W), and the bit-line masks 244 are comprised of silicon nitride (SiN), in an example embodiment of the present invention.
- the second conductive plugs 240 are comprised of polysilicon, in an example embodiment of the present invention.
- each of the bit lines 242 is coupled to the drain junctions for a column of DRAM cells.
- a fourth ILD (inter-level dielectric) layer 252 is deposited onto exposed surfaces of the third ILD layer 236 , the second conductive plugs 240 , and the bit-lines masks 244 .
- the fourth ILD layer 252 is comprised of PTEOS (phosphorous doped tetraethylorthosilicate) based oxide, in an example embodiment of the present invention.
- a fifth ILD (inter-level dielectric) layer 254 is deposited onto the fourth ILD layer 252 .
- the fifth ILD layer 254 is comprised of silicon nitride (SiN), in an example embodiment of the present invention.
- a first mold layer 256 is deposited onto the fifth ILD layer 254 .
- the first mold layer 256 is comprised of BPSG (borophosphosilicate glass) or a PTEOS (phosphorous doped tetraethylorthosilicate) based oxide, in an example embodiment of the present invention.
- a layer of support material 258 is deposited onto the first mold layer 256 .
- the layer of support material 258 is comprised of silicon nitride (SiN), in an example embodiment of the present invention.
- a second mold layer 260 is deposited onto the layer of support material 258 .
- the second mold layer 260 is comprised of PTEOS (phosphorous doped tetraethylorthosilicate) based oxide, in an example embodiment of the present invention.
- a photo-resist layer 262 is patterned for forming a plurality of openings 264 through the layers of materials 252 , 254 , 256 , 258 , and 260 .
- the photo-resist layer 262 is deposited and patterned on the second mold layer 260 .
- Each of the openings 264 is formed over one of the second conductive plugs 240 that are exposed through the openings 264 .
- a layer of first electrode material 265 is deposited onto exposed surfaces including any sidewall and bottom wall of the openings 264 .
- the layer of first electrode material 265 is comprised of polysilicon in an example embodiment of the present invention.
- a sacrificial dielectric material 266 is blanket deposited to fill the openings 264 .
- the sacrificial dielectric material 266 is comprised of USG (un-doped silica glass), in an example embodiment of the present invention.
- the sacrificial dielectric material 266 , the first electrode material 265 , and the photo-resist layer 262 are polished down by a CMP (chemical mechanical polishing) process until the first mold layer 260 is exposed.
- the first electrode material 265 becomes separated within each of the openings 264 to form a respective first electrode 265 A, 265 B, 265 C, and 265 D within each of the openings 264 .
- the second mold layer 260 is etched away until the support material 258 is exposed as an etch-stop layer.
- a top portion of the sacrificial dielectric 266 within the openings 264 is etched away substantially to the layer of the support material 258 , in an example embodiment of the present invention.
- the present invention may also be practiced when the sacrificial dielectric 266 within the openings 264 is not etched away or is etched away to any level.
- FIG. 17 shows a top view of the first electrodes 265 A, 265 B, 265 C, and 265 D in FIGS. 16A and 16B .
- the first electrodes 265 A, 265 B, 265 C, and 265 D are formed as part of an array of such electrodes for a DRAM.
- FIG. 17 illustrates just an array of 3 ⁇ 3 first electrodes for forming an array of 3 ⁇ 3 stacked capacitors, for simplicity and clarity of illustration. However, a typical DRAM is formed with an array of more numerous stacked capacitors.
- the first electrodes 265 A, 265 B, 265 C, and 265 D are formed as circular cylinders in an example embodiment of the present invention. However, the present invention may be practiced for other types of shapes of the first electrodes 265 A, 265 B, 265 C, and 265 D.
- Each such circular first electrode has a diameter “w”. Any two adjacent first electrodes (such as 265 A and 265 B for example) in the B-B direction are separated by a distance of “d 1 ”, and any two adjacent first electrodes (such as 265 A and 265 C for example) in the C-C direction are separated by a distance of “d 2 ”.
- a layer of mask material 272 is blanket deposited onto exposed surfaces of the first electrodes 265 A, 265 B, 265 C, and 265 D, the support material 258 , and the sacrificial material 266 .
- the layer of mask material 272 is comprised of PTEOS (phosphorous doped tetraethylorthosilicate) based oxide, whereas the support material 258 is comprised of silicon nitride (SiN), in an example embodiment of the present invention.
- the layer of mask material 272 has a thickness “t” that is greater than (1 ⁇ 2)*d 2 , in an example embodiment of the present invention.
- the mask material 272 is etched back to form masking spacers 274 around each of the exposed top portions of the first electrodes 265 A and 265 B in the B-B direction of FIG. 19A , and within the first electrodes 265 A, 265 C, and 265 D in the C-C direction of FIG. 19B .
- mask structures 276 comprised of the masking material 272 , remain to cover joining portions 278 of the support material 258 along the d 2 distance. Such mask structures 276 are formed because the layer of mask material 272 was deposited with a thickness “t” that is greater than (1 ⁇ 2)*d 2 in FIGS. 18A and 18B .
- the support material 258 remains during etch back of the mask material 272 because the mask material 272 has a different etch rate from the support material 258 during the etch back process for forming the masking spacers 274 and the mask structures 276 .
- another etch process is used to etch away any exposed portion of the support material 258 that is not covered under the masking spacers 274 or the mask structures 276 .
- support structures comprised of the remaining support material 258 are formed around the first electrodes 265 A, 265 B, 265 C, and 265 D.
- the masking spacers 274 , the mask structures 276 , the first mold layer 256 , and the sacrificial dielectric 266 are etched away.
- the fifth ILD layer 254 acts as an etch stop layer during etching away of the first mold layer 256 such that the fourth and fifth ILD layers 252 and 254 remain to surround the bottom of the first electrodes 265 A, 265 B, 265 C, and 265 D.
- FIG. 22 shows a top view of the first electrodes 265 A, 265 B, 265 C, and 265 D in FIGS. 21A and 21B .
- each of the first electrodes has a respective circular disc (comprised of the support material 258 ) surrounding the outside of the first electrode.
- a first circular disc 282 surrounds the outside of the first electrode 265 A
- a second circular disc 284 surrounds the outside of the second electrode 265 B, in FIGS. 21A and 22 .
- a joining portion 278 (comprised of the support material 258 ) is formed between each of two nearest adjacent first electrodes.
- a joining portion 278 is formed between the two nearest adjacent first electrodes 265 A and 265 C in FIGS. 21B and 22 .
- a capacitor dielectric 292 is deposited onto exposed surfaces of the first electrodes, the support structures comprised of the remaining support material 258 , and the fifth ILD layer 254 .
- the capacitor dielectric 292 is comprised of a dielectric material having a dielectric constant that is higher than that of silicon dioxide (SiO 2 ), such as a metal oxide for example, in an example embodiment of the present invention.
- SiO 2 silicon dioxide
- a material for a second electrode 294 of the stacked capacitors is deposited onto the capacitor dielectric 292 .
- the second electrode 294 is comprised of polysilicon, in an example embodiment of the present invention.
- each stacked capacitor formed according to the present invention is comprised of a respective one of the first electrodes (such as 265 A, 265 B, 265 C, or 265 D for example), the capacitor dielectric 292 , and the common second electrode 294 .
- the stacked capacitors are formed in an array configuration in an example embodiment of the present application.
- each of such first electrodes is coupled via the conductive plugs 240 and 230 to a source junction of a corresponding switching transistor.
- each of such first electrodes may be applied as a storage node of a storage capacitor for a DRAM cell.
- the second electrode 294 is a common electrode that may be coupled to the ground node within the DRAM cell.
- Capacitance of such stacked capacitors of the present invention may be maximized with a relatively high height of such first electrodes.
- the circular discs (comprised of the remaining support material 258 ) surrounding each of the first electrodes 265 A, 265 B, 265 C, and 265 D forms support structures that prevent such first electrodes from leaning towards each-other.
- a joining portion 278 is disposed between any two nearest adjacent first electrodes to prevent such closely disposed first electrodes from leaning towards each-other.
- the first electrodes 265 A, 265 B, 265 C, and 265 D may be formed to be vertically high without leaning against each-other, to effectively increase the area and thus the capacitance of the stacked capacitors.
- the fourth ILD layer 252 , the fifth ILD layer 254 , the first mold layer 256 , the layer of support material 258 , and the second mold layer 260 are deposited to have thicknesses of 700 ⁇ (angstroms), 500 ⁇ , 20,000 ⁇ , 1,000 ⁇ , and 5,000-10,000 ⁇ , respectively, in an example embodiment of the present invention.
- the fourth and fifth ILD layers 252 and 254 comprise mount materials surrounding the bottom of the first electrodes 265 A, 265 B, 265 C, and 265 D. Such mount materials 252 and 254 provide further support such that the first electrodes 265 A, 265 B, 265 C, and 265 D remain vertically standing and separated from each-other.
- the area of overlap between a first electrode and the second electrode 292 is desired to be maximized.
- the support structures comprised of the remaining support material 258 are disposed at a level between the mounting materials 252 and 254 and the top of the first electrodes.
- the thickness of the mounting materials 252 and 254 may be minimized without the first electrodes leaning against each-other, for further maximizing capacitance.
- FIG. 24 illustrates another embodiment of the present invention for further increasing capacitance of the stacked capacitors.
- at least one further etching step is performed to increase the area of any opening 298 disposed between four nearest first electrodes. Such further etching may occur during subsequent fabrication steps for forming other structures of the DRAM. Alternatively, a subsequent etch step may be intentionally added for increasing the area of the openings 298 .
- the circular discs surrounding the first electrodes are etched away while each of the joining portions 278 turns into a joining beam 278 between two nearest adjacent first electrodes, as illustrated in FIG. 24 .
- the sidewalls of the first electrodes are further exposed.
- the circular discs 282 and 284 no longer exist in the B-B direction of FIG. 25 , thus further increasing the area of overlap between the second electrode 294 and the first electrodes 265 A and 265 B.
- Such increased area of overlap advantageously results in increased capacitance of the stacked capacitors.
- the joining beams 278 still remain between two nearest adjacent first electrodes (such as between 265 A and 265 C in the C-C direction of FIG. 24 ) to prevent leaning of the first electrodes.
- FIGS. 27A, 28A , 29 A, 30 A, and 31 A show cross-sectional views along the B-B direction of FIG. 8 for fabrication of the stacked capacitors according to another embodiment of the present invention.
- FIGS. 27B, 28B , 29 B, 30 B, and 31 B show cross-sectional views along the C-C direction of FIG. 8 for fabrication of stacked capacitors, according to such an alternative embodiment of the present invention.
- FIG. 13A Comparing FIG. 13A with FIG. 26A and comparing FIG. 13B with FIG. 26B , the perfectly vertical sidewalls of the openings 264 in FIGS. 13A and 13B are for the ideal situation.
- the openings 264 become narrower toward the bottom of the openings 264 , as illustrated in FIGS. 26A and 26B .
- Such narrowed openings 264 are disadvantageously more prone to leaning, and the first electrodes formed within such narrowed openings having less area of contact with the underlying contact plugs 240 .
- a first mold layer 302 is deposited on the fifth ILD layer 254 .
- a second mold layer 304 is deposited on the first mold layer 302
- the layer of support material 258 is deposited on the second mold layer 304 .
- a third mold layer 306 is deposited on the layer of support material 258 .
- the fourth and fifth ILD layers 252 and 254 and the layer of support material 258 in FIGS. 27A and 27B are similar as that of FIGS. 12A and 12B .
- the first mold layer 302 is comprised of BPSG (borophosphosilicate glass)
- the second mold layer 304 is comprised of PTEOS (phosphorous doped tetraethylorthosilicate) based oxide
- the third mold layer 306 is comprised of PTEOS (phosphorous doped tetraethylorthosilicate) based oxide, in an example embodiment of the present invention.
- the first, second, and third mold layers 302 , 304 , and 306 are deposited with thicknesses of 7,000 ⁇ (angstroms), 13,000 ⁇ , and 5,000 ⁇ , respectively, in an example embodiment of the present invention.
- a photo-resist layer 308 is patterned for forming a plurality of openings 310 through the layers of materials 252 , 254 , 256 , 302 , 304 , 258 , and 306 .
- the photo-resist layer 308 is deposited and patterned on the third mold layer 306 .
- Each of the openings 310 is formed over one of the second conductive plugs 240 that become exposed through the openings 310 .
- the bottom first mold layer 302 has a higher etch rate than the upper second mold layer 304 in an etch process for etching the first and second mold layers 302 and 304 when forming the openings 310 . Because the bottom first mold layer 302 etches away faster in such an etch process, the openings 310 do not narrow significantly toward the bottom of the openings 310 .
- the first electrodes 265 A, 265 B, 265 C, and 265 D are formed on the walls of the openings, similar to FIGS. 15A and 15B .
- the masking spacers 274 and the mask structures 276 comprised of a mask material are formed, similar to FIGS. 19A and 19B .
- any portion of the support material 258 that is not covered under the masking spacers 274 or the mask structures 276 is etched away to form the support structures comprised of the remaining support material 258 , similar to FIGS. 20A and 20B .
- the masking spacers 274 , the mask structures 276 , the first and second mold layers 302 and 304 , and the sacrificial dielectric 266 are etched away, similar to FIGS. 21A and 21B .
- the capacitor dielectric 292 and the second electrode 294 are formed onto exposed surfaces of the first electrodes, the support structures comprised of the remaining support material 258 , and the fifth ILD layer 254 , similar to FIGS. 23A and 23B .
- the circular discs around each of the first electrodes is etched away such that just the support beams 278 remain, similar to FIGS. 24 and 25 .
- the circular discs 282 and 284 are no longer present around the first electrodes 265 A and 265 B along the B-B direction in FIG. 32 .
- the support beams 278 are still present in the C-C direction between any two nearest adjacent first electrodes as illustrated in FIG. 31B to prevent leaning of the first electrodes towards each-other.
- the array of stacked capacitors is illustrated and described herein as being applied for storage capacitors of a DRAM.
- the array of stacked capacitors fabricated according to the present invention may be applied for any other application requiring maximized capacitance of highly integrated capacitors.
- any dimension, number, and material specified or illustrated herein is by way of example only.
- any shape described or illustrated herein is by way of example only.
- circular discs 282 and 284 of the remaining support material 258 are described and illustrated herein as being formed around the circular first electrodes 265 A, 265 B, 265 C, and 265 D.
- discs of the remaining support material 258 may also be rectangular if the first electrodes were formed to have a rectangular cross-section.
Abstract
For fabricating lean-free stacked capacitors, openings are formed through layers of materials including a layer of support material displaced from a bottom of the openings. A respective first electrode is formed for a respective capacitor within each of the openings. The layer of support material is patterned to form support structures around the first electrodes. Masking spacers are formed around exposed top portions of the first electrodes, and exposed portions of the support material are etched away to form the support structures. Such stacked capacitors are applied within a DRAM (dynamic random access memory).
Description
- The present application is a divisional of an earlier filed copending patent application with Ser. No. 10/853,628 filed on May 25, 2004, for which priority is claimed. This earlier filed copending patent application with Ser. No. 10/853,628 is in its entirety incorporated herewith by reference.
- The present application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. P2004-8770, filed on Feb. 10, 2004, which is incorporated herein by reference in its entirety. A certified copy of Korean Patent Application No. P2004-8770 is contained in the parent copending patent application with Ser. No. 10/853,628.
- The present invention relates generally to integrated circuit fabrication, and more particularly, to fabrication of lean-free stacked capacitors that may be used for DRAM (dynamic random access memory).
-
FIG. 1 shows a simplified schematic of a DRAM (dynamic random access memory)cell 100 including aswitching transistor 102 and astorage capacitor 104. A DRAM includes an array of such DRAM cells. When theswitching transistor 102 is an NMOSFET (N-channel metal oxide semiconductor field effect transistor), the gate of theNMOSFET 102 is coupled to a word-line 106 of the DRAM, and the drain of theNMOSFET 102 is coupled to a bit-line 108 of the DRAM. - In a typical DRAM array, the DRAM cells along a same column are coupled to a same bit-line, and the DRAM cells along a same row are coupled to a same word-line. The source of the NMOSFET 102 is coupled to a storage node of the
storage capacitor 104. The other node of thestorage capacitor 104 is coupled to a ground node. The bit-line 108 is coupled to asense amplifier 110. - The voltage across the
storage capacitor 104 determines the logical level “1” or “0” stored within theDRAM cell 100. Thesense amplifier 110 outputs such a stored logical level at the storage node of thestorage capacitor 104. Aparasitic capacitance 112, at the bit-line 108, disadvantageously deteriorates the voltage signal, Vsignal, to thesense amplifier 110 since Vsignal is directly proportional to Cs/Cp, with Cs being the capacitance of thestorage capacitor 104 and Cp being the capacitance of theparasitic capacitor 112. - The capacitance, Cs, of the
storage capacitor 104 is desired to be maximized to provide sufficient voltage signal, Vsignal, to thesense amplifier 110 and for enhancing retention time for theDRAM cell 100. On the other-hand, the area occupied by theDRAM cell 100 is also desired to be minimized. Thus, a stacked capacitor having electrodes formed vertically upwards is used for thestorage capacitor 104 of theDRAM cell 100. - Capacitance of a capacitor formed with two electrodes is generally expressed as follows:
C=Aε/d
C is the capacitance of the capacitor, and A is an area of overlap between the two electrodes. In addition, ε is the dielectric constant of the dielectric between the two electrodes, and d is the thickness of such a dielectric. -
FIG. 2 illustrates a cross-sectional view of a first stackedcapacitor 112 and a second stackedcapacitor 114. The first stackedcapacitor 112 includes afirst electrode 116 coupled, via aconductive plug structure 118, to a junction of a switching transistor (not shown for clarity of illustrate inFIG. 2 ) for a first DRAM cell formed with asemiconductor substrate 120. Similarly, the second stackedcapacitor 114 includes afirst electrode 122 coupled, via aconductive plug structure 124, to a junction of a switching transistor (not shown for clarity of illustrate inFIG. 2 ) for a second DRAM cell formed with thesemiconductor substrate 120. - A layer of support dielectric 126 surrounds the
first electrodes such electrodes first electrodes second electrode 130 is formed onto the capacitor dielectric 128, and thesecond electrode 130 is typically coupled to the ground node of thestorage capacitor 104 as illustrated inFIG. 1 . ILD (inter-level dielectric)layers FIG. 2 . - For maximizing capacitance of the
stacked capacitors first electrodes electrodes - In addition, the area occupied by the DRAM is desired to be further minimized with advancement of IC (integrated circuit) fabrication technology. Thus, the
first electrodes electrodes - Referring to
FIG. 3 , U.S. Patent Application Publication No. US 2003/0085420 to Ito et al. discloses stackedcapacitors support beams 146 disposed above the layer of support dielectric 126 for preventing leaning of thefirst electrodes FIG. 4 shows a cross-sectional view across line A-A ofFIG. 3 through thesupport beams 146. Elements having the same reference number inFIGS. 2, 3 , 4, 5, 6, and 7 refer to elements having similar structure and function. - Referring to
FIGS. 3 and 4 ,support beams 146 are formed on the four sides of afirst electrode 116. In addition, eachsupport beam 146 is disposed between two adjacentfirst electrodes support beams 146 prevent the exposed top portions of two adjacentfirst electrodes capacitors -
FIGS. 5, 6 , and 7 illustrate cross-sectional views across line A-A ofFIG. 3 during fabrication of thesupport beams 146. Referring toFIG. 5 , a material comprising thesupport beams 146 is first patterned on a sacrificialdielectric material 148. Referring toFIGS. 5 and 6 ,openings support beams 146. Referring toFIG. 7 , a respective first electrode is formed at the walls of each of theopenings FIG. 7 shows the examplefirst electrodes dielectric material 148 is etched away, and the gate electric 128 and thesecond electrode 130 are formed onto exposed surfaces of the first electrodes and thesupport beams 146. - With such a prior art process, the
support beams 146 are formed before the stacked capacitors are formed within theopenings support beams 146, subsequent etching steps may decrease the width (w) and the thickness of thesupport beams 146. Thus, the width and the thickness of thesupport beams 146 are more difficult to control in the prior art. - Accordingly, in a general aspect of the present invention, support structures for preventing leaning of adjacent first electrodes of stacked capacitors are formed after formation of the first electrodes.
- In an embodiment of the present invention, openings are formed through layers of materials including a layer of support material displaced from a bottom of the openings. A respective first electrode is formed for a respective capacitor within each of the openings. The layer of support material is patterned to form support structures around the first electrodes, after formation of the first electrodes within the openings.
- In an example embodiment for forming the support structures, at least one of the layers of materials toward the top of the first electrodes is etched away such that a top portion of the first electrodes is exposed and such that the support material is exposed. Masking spacers are formed with a masking material around the exposed top portions of the first electrodes. A mask structure of the masking material remains on joining portions of the support material. Exposed portions of the support material are etched away such that the support structures including the joining portions are formed from the remaining support material. Each joining portion is disposed between the first electrodes of adjacent capacitors.
- Further for such an example embodiment, the masking material is deposited with a thickness that is greater than ½ of a length of the joining portions, before forming the masking spacers. Additionally for such an example embodiment, the support structures include a respective disc that may be a circular disc surrounding each first electrode. Also for such an example embodiment, the respective disc surrounding each first electrode is further etched such that a respective beam remains for each of the joining portions as the support structures.
- In yet another embodiment of the present invention, a layer of mount material is formed to surround the openings toward the bottom of the openings. In that case, the support structures are disposed between the mount material and the top of the first electrodes.
- For further forming the capacitors, the layers of materials are etched away except for the support structures, the mount material, and the first electrodes. A capacitor dielectric is formed on exposed surfaces of such remaining structures, and a second electrode is formed on the capacitor dielectric.
- In another embodiment of the present invention, the openings are formed through a plurality of mold layers, with a respective etch rate of each mold layer successively increasing toward a bottom of the openings. Thus, the openings are not substantially narrow toward the bottom of the openings.
- Such stacked capacitors may be advantageously applied to form a capacitor array for a DRAM (dynamic random access memory). In that case, each of the openings is formed onto a respective conductive plug coupled to a junction of a respective switching transistor, and the first electrode is a storage node for each capacitor.
- In this manner, the support structures for preventing leaning of the first electrodes of the stacked capacitors are formed after the first electrodes are fabricated within the openings. Thus, less subsequent etching steps do not deteriorate the structural integrity of the support structures. In addition, because the first electrodes are available for forming the support structures, masking spacers are formed using the first electrodes for easily patterning the support structures around the first electrodes.
- These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.
-
FIG. 1 shows a simplified schematic of a DRAM (dynamic random access memory) cell, according to the prior art; -
FIG. 2 shows a cross-sectional view of stacked capacitors used for DRAM with just a mount material surrounding a bottom of the stacked capacitors, according to the prior art; -
FIG. 3 shows a cross-sectional view of stacked capacitors with support beams disposed between adjacent stacked capacitors for preventing leaning of first electrodes of such capacitors, according to the prior art; -
FIG. 4 shows a cross-sectional view across line A-A ofFIG. 3 , according to the prior art; -
FIGS. 5, 6 , and 7 show the cross-sectional view ofFIG. 4 during fabrication of the supports beams and the first electrodes of the stacked capacitors, according to the prior art; -
FIG. 8 shows two directions, B-B and C—C, across a top view of a semiconductor substrate for illustrating cross-sectional views of stacked capacitors formed across such directions, according to an embodiment of the present invention; -
FIGS. 9A, 10A , 11A, 12A, 13A, 14A, 15A, 16A, 18A, 19A, 20A, 21A, and 23A show cross-sectional views along the B-B direction ofFIG. 8 for illustrating fabrication of stacked capacitors, according to an embodiment of the present invention; -
FIGS. 9B, 10B , 11B, 12B, 13B, 14B, 15B, 16B, 18B, 19B, 20B, 21B, and 23B show cross-sectional views along the C-C direction ofFIG. 8 for illustrating fabrication of stacked capacitors, according to an embodiment of the present invention; -
FIG. 17 shows a top view of first electrodes of the stacked capacitors formed afterFIGS. 16A and 16B , according to an embodiment of the present invention; -
FIG. 22 shows a top view of the support structures including circular discs surrounding the first electrodes afterFIGS. 21A and 21B , according to an embodiment of the present invention; -
FIG. 24 shows a top view of the support structures comprising support beams disposed between adjacent first electrodes after further etching of the circular discs ofFIG. 22 , according to another embodiment of the present invention; -
FIG. 25 shows the cross-sectional view similar toFIG. 23A but without the circular discs surrounding the first electrodes, according to the embodiment ofFIG. 24 ; -
FIGS. 26A, 27A , 28A, 29A, 30A, and 31A show cross-sectional views along the B-B direction ofFIG. 8 for illustrating fabrication of stacked capacitors, with openings formed through mold layers having different etch rates according to another embodiment of the present invention; -
FIGS. 26B, 27B , 28B, 29B, 30B, and 31B show cross-sectional views along the C-C direction ofFIG. 8 for illustrating fabrication of stacked capacitors, with openings formed through mold layers having different etch rates according to the alternative embodiment of the present invention; and -
FIG. 32 shows the cross-sectional view similar toFIG. 31A but with the circular discs surrounding the first electrodes etched away afterFIG. 30A . - The figures referred to herein are drawn for clarity of illustration and are not necessarily drawn to scale. Elements having the same reference number in
FIGS. 1-32 refer to elements having similar structure and function. - Referring to
FIG. 8 , a DRAM (dynamic random access memory) is fabricated onto asemiconductor substrate 202, comprised of a silicon wafer for example.FIGS. 9A, 10A , 11A, 12A, 13A, 14A, 15A, 16A, 18A, 19A, 20A, 21A, and 23A show cross-sectional views along a B-B direction ofFIG. 8 for fabrication of stacked capacitors, according to an embodiment of the present invention.FIGS. 9B, 10B , 11B, 12B, 13B, 14B, 15B, 16B, 18B, 19B, 20B, 21B, and 23B show cross-sectional views along a C-C direction ofFIG. 8 for fabrication of stacked capacitors, according to an embodiment of the present invention. - In an example embodiment of the present invention, the stacked capacitors are part of the DRAM fabricated on the
semiconductor substrate 202. The B-B direction ofFIG. 8 crosses through a plurality of word-lines of such a DRAM, and the C-C direction ofFIG. 8 crosses through a plurality of bit-lines of such a DRAM. - Referring to
FIGS. 9A and 9B , a plurality of STI (shallow trench isolation)structures 204 are formed into thesemiconductor substrate 202. TheSTI structures 204 are comprised of a dielectric material such as silicon dioxide (SiO2) in an embodiment of the present invention. Referring toFIG. 9A , afirst switching transistor 206 and asecond switching transistor 208 are formed in an active device area of thesemiconductor substrate 202 between theSTI structures 204. - Further referring to
FIG. 9A , the first andsecond switching transistors drain junction 210. Additionally, afirst source junction 212 is formed for thefirst switching transistor 206, and asecond source junction 214 is formed for thesecond switching transistor 208.Such junctions second switching transistors - A first gate stack, comprised of a
first gate dielectric 216, afirst gate structure 218, and afirst gate mask 220, is formed for thefirst NMOSFET 206. In addition, a second gate stack, comprised of asecond gate dielectric 222, asecond gate structure 224, and asecond gate mask 226, is formed for thesecond NMOSFET 208. A repeating pattern of such gate stacks are formed across thesemiconductor substrate 202 such that such gate stacks are also formed onto theSTI structures 204 inFIG. 9A . - In an example embodiment of the present invention, the
gate dielectrics gate structures gate structures FIG. 9B , theSTI structures 204 are formed across the C-C direction ofFIG. 8 after the formation of theNMOSFETs FIG. 9A . - Referring to
FIG. 10A ,spacer structures 228 are formed onto sidewalls of each of the gate stacks.Such spacer structures 228 are comprised of a dielectric material such as silicon dioxide (SiO2) in an example embodiment of the present invention. Thereafter, firstconductive plugs 230 are formed from a SAC (self aligned contact) process with the exposedjunctions FIG. 10B , the firstconductive plugs 230 are also formed across the C-C direction ofFIG. 8 from such a SAC process with exposed regions of thesemiconductor substrate 202. - A first ILD (inter-level dielectric)
layer 232 surrounds the firstconductive plugs 230 inFIG. 9B . Thefirst ILD layer 232 is comprised of a dielectric material such as BPSG (borophosphosilicate glass) in an example embodiment of the present invention. The firstconductive plugs 230 are comprised of polysilicon in an example embodiment of the present invention. - Referring to
FIG. 11A afterFIG. 10A , a second ILD (inter-level dielectric)layer 234 and a third ILD (inter-level dielectric)layer 236 are deposited. Thesecond ILD layer 234 is comprised of BPSG (borophosphosilicate glass), and thethird ILD layer 236 is comprised of a dielectric material such as PSG (phosphosilicate glass) formed from a HDP (high density plasma) deposition process, in an example embodiment of the present invention.Openings 238 are formed through the second and third ILD layers 234 and 236 over the firstconductive plugs 230 disposed above thesource junctions conductive plugs 240 are formed within theopenings 238 and over the first conductive plugs 230. - Referring to
FIG. 11B , a plurality of bit-line stacks, each comprised of a bit-line 242 and a bit-line mask 244, are patterned on thesecond ILD layer 234.Spacer structures 246 are formed at the sidewalls of the bit-line stacks. There-after, the secondconductive plugs 240 are formed over the first conductive plugs 230. The bit-lines 242 are comprised of tungsten (W), and the bit-line masks 244 are comprised of silicon nitride (SiN), in an example embodiment of the present invention. In addition, the secondconductive plugs 240 are comprised of polysilicon, in an example embodiment of the present invention. Further referring toFIGS. 11A and 11B , each of the bit lines 242 is coupled to the drain junctions for a column of DRAM cells. - Referring to
FIGS. 12A and 12B afterFIGS. 11A and 11B , a fourth ILD (inter-level dielectric)layer 252 is deposited onto exposed surfaces of thethird ILD layer 236, the secondconductive plugs 240, and the bit-lines masks 244. Thefourth ILD layer 252 is comprised of PTEOS (phosphorous doped tetraethylorthosilicate) based oxide, in an example embodiment of the present invention. - In addition, a fifth ILD (inter-level dielectric)
layer 254 is deposited onto thefourth ILD layer 252. Thefifth ILD layer 254 is comprised of silicon nitride (SiN), in an example embodiment of the present invention. Thereafter, afirst mold layer 256 is deposited onto thefifth ILD layer 254. Thefirst mold layer 256 is comprised of BPSG (borophosphosilicate glass) or a PTEOS (phosphorous doped tetraethylorthosilicate) based oxide, in an example embodiment of the present invention. - Furthermore, a layer of
support material 258 is deposited onto thefirst mold layer 256. The layer ofsupport material 258 is comprised of silicon nitride (SiN), in an example embodiment of the present invention. Thereafter, asecond mold layer 260 is deposited onto the layer ofsupport material 258. Thesecond mold layer 260 is comprised of PTEOS (phosphorous doped tetraethylorthosilicate) based oxide, in an example embodiment of the present invention. - Referring to
FIGS. 13A and 13B afterFIGS. 12A and 12B , a photo-resistlayer 262 is patterned for forming a plurality ofopenings 264 through the layers ofmaterials layer 262 is deposited and patterned on thesecond mold layer 260. Each of theopenings 264 is formed over one of the secondconductive plugs 240 that are exposed through theopenings 264. - Referring to
FIGS. 14A and 14B afterFIGS. 13A and 13B , a layer offirst electrode material 265 is deposited onto exposed surfaces including any sidewall and bottom wall of theopenings 264. The layer offirst electrode material 265 is comprised of polysilicon in an example embodiment of the present invention. Thereafter, a sacrificialdielectric material 266 is blanket deposited to fill theopenings 264. The sacrificialdielectric material 266 is comprised of USG (un-doped silica glass), in an example embodiment of the present invention. - Referring to
FIGS. 15A and 15B afterFIGS. 14A and 14B , the sacrificialdielectric material 266, thefirst electrode material 265, and the photo-resistlayer 262 are polished down by a CMP (chemical mechanical polishing) process until thefirst mold layer 260 is exposed. In this manner, thefirst electrode material 265 becomes separated within each of theopenings 264 to form a respectivefirst electrode openings 264. - Referring to
FIGS. 16A and 16B afterFIGS. 15A and 15B , thesecond mold layer 260 is etched away until thesupport material 258 is exposed as an etch-stop layer. In addition, a top portion of thesacrificial dielectric 266 within theopenings 264 is etched away substantially to the layer of thesupport material 258, in an example embodiment of the present invention. However, the present invention may also be practiced when thesacrificial dielectric 266 within theopenings 264 is not etched away or is etched away to any level. - In this manner, a top portion of the
first electrodes FIG. 17 shows a top view of thefirst electrodes FIGS. 16A and 16B . Referring toFIG. 17 , thefirst electrodes FIG. 17 illustrates just an array of 3×3 first electrodes for forming an array of 3×3 stacked capacitors, for simplicity and clarity of illustration. However, a typical DRAM is formed with an array of more numerous stacked capacitors. - Further referring to
FIGS. 16A, 16B , and 17, thefirst electrodes first electrodes - Referring to
FIGS. 18A and 18B afterFIGS. 16A and 16B , a layer ofmask material 272 is blanket deposited onto exposed surfaces of thefirst electrodes support material 258, and thesacrificial material 266. The layer ofmask material 272 is comprised of PTEOS (phosphorous doped tetraethylorthosilicate) based oxide, whereas thesupport material 258 is comprised of silicon nitride (SiN), in an example embodiment of the present invention. In addition, referring toFIGS. 16A, 16B , 18A, and 18B, the layer ofmask material 272 has a thickness “t” that is greater than (½)*d2, in an example embodiment of the present invention. - Referring to
FIGS. 19A and 19B afterFIGS. 18A and 18B , themask material 272 is etched back to form maskingspacers 274 around each of the exposed top portions of thefirst electrodes FIG. 19A , and within thefirst electrodes FIG. 19B . Further referring toFIG. 19B ,mask structures 276, comprised of the maskingmaterial 272, remain to cover joiningportions 278 of thesupport material 258 along the d2 distance.Such mask structures 276 are formed because the layer ofmask material 272 was deposited with a thickness “t” that is greater than (½)*d2 inFIGS. 18A and 18B . - Further referring to
FIGS. 19A and 19B , thesupport material 258 remains during etch back of themask material 272 because themask material 272 has a different etch rate from thesupport material 258 during the etch back process for forming the maskingspacers 274 and themask structures 276. Thus, referring toFIGS. 20A and 20B , another etch process is used to etch away any exposed portion of thesupport material 258 that is not covered under the maskingspacers 274 or themask structures 276. In this manner, support structures comprised of the remainingsupport material 258 are formed around thefirst electrodes - Referring to
FIGS. 21A and 21B afterFIGS. 20A and 20B , the maskingspacers 274, themask structures 276, thefirst mold layer 256, and thesacrificial dielectric 266 are etched away. Thefifth ILD layer 254 acts as an etch stop layer during etching away of thefirst mold layer 256 such that the fourth and fifth ILD layers 252 and 254 remain to surround the bottom of thefirst electrodes -
FIG. 22 shows a top view of thefirst electrodes FIGS. 21A and 21B . Referring toFIGS. 21A, 21B , and 22, each of the first electrodes has a respective circular disc (comprised of the support material 258) surrounding the outside of the first electrode. For example, a firstcircular disc 282 surrounds the outside of thefirst electrode 265A, and a secondcircular disc 284 surrounds the outside of thesecond electrode 265B, inFIGS. 21A and 22 . In addition, a joining portion 278 (comprised of the support material 258) is formed between each of two nearest adjacent first electrodes. For example, a joiningportion 278 is formed between the two nearest adjacentfirst electrodes FIGS. 21B and 22 . - Referring to
FIGS. 23A and 23B afterFIGS. 21A and 21B , acapacitor dielectric 292 is deposited onto exposed surfaces of the first electrodes, the support structures comprised of the remainingsupport material 258, and thefifth ILD layer 254. Thecapacitor dielectric 292 is comprised of a dielectric material having a dielectric constant that is higher than that of silicon dioxide (SiO2), such as a metal oxide for example, in an example embodiment of the present invention. Thereafter, a material for asecond electrode 294 of the stacked capacitors is deposited onto thecapacitor dielectric 292. Thesecond electrode 294 is comprised of polysilicon, in an example embodiment of the present invention. - Accordingly, each stacked capacitor formed according to the present invention is comprised of a respective one of the first electrodes (such as 265A, 265B, 265C, or 265D for example), the
capacitor dielectric 292, and the commonsecond electrode 294. Referring toFIG. 22 , the stacked capacitors are formed in an array configuration in an example embodiment of the present application. In one example application of such stacked capacitors, referring toFIGS. 1, 23A , and 23B, each of such first electrodes is coupled via theconductive plugs second electrode 294 is a common electrode that may be coupled to the ground node within the DRAM cell. - Capacitance of such stacked capacitors of the present invention may be maximized with a relatively high height of such first electrodes. Referring to
FIG. 22 , the circular discs (comprised of the remaining support material 258) surrounding each of thefirst electrodes portion 278 is disposed between any two nearest adjacent first electrodes to prevent such closely disposed first electrodes from leaning towards each-other. - Thus, the
first electrodes fourth ILD layer 252, thefifth ILD layer 254, thefirst mold layer 256, the layer ofsupport material 258, and thesecond mold layer 260 are deposited to have thicknesses of 700 Å (angstroms), 500 Å, 20,000 Å, 1,000 Å, and 5,000-10,000 Å, respectively, in an example embodiment of the present invention. - Furthermore, the fourth and fifth ILD layers 252 and 254 comprise mount materials surrounding the bottom of the
first electrodes Such mount materials first electrodes - For further maximizing capacitance, the area of overlap between a first electrode and the
second electrode 292 is desired to be maximized. The support structures comprised of the remainingsupport material 258 are disposed at a level between the mountingmaterials materials -
FIG. 24 illustrates another embodiment of the present invention for further increasing capacitance of the stacked capacitors. Referring toFIGS. 22 and 24 , note that at least one further etching step is performed to increase the area of anyopening 298 disposed between four nearest first electrodes. Such further etching may occur during subsequent fabrication steps for forming other structures of the DRAM. Alternatively, a subsequent etch step may be intentionally added for increasing the area of theopenings 298. - In any case, with such further etching, the circular discs surrounding the first electrodes are etched away while each of the joining
portions 278 turns into a joiningbeam 278 between two nearest adjacent first electrodes, as illustrated inFIG. 24 . With etching away of the circular discs of the insulatingmaterial 258, the sidewalls of the first electrodes are further exposed. - Comparing
FIGS. 23A and 25 , thecircular discs FIG. 25 , thus further increasing the area of overlap between thesecond electrode 294 and thefirst electrodes FIGS. 23B and 24 , the joiningbeams 278 still remain between two nearest adjacent first electrodes (such as between 265A and 265C in the C-C direction ofFIG. 24 ) to prevent leaning of the first electrodes. -
FIGS. 27A, 28A , 29A, 30A, and 31A show cross-sectional views along the B-B direction ofFIG. 8 for fabrication of the stacked capacitors according to another embodiment of the present invention.FIGS. 27B, 28B , 29B, 30B, and 31B show cross-sectional views along the C-C direction ofFIG. 8 for fabrication of stacked capacitors, according to such an alternative embodiment of the present invention. - Comparing
FIG. 13A withFIG. 26A and comparingFIG. 13B withFIG. 26B , the perfectly vertical sidewalls of theopenings 264 inFIGS. 13A and 13B are for the ideal situation. However, in reality, because of the high aspect ratio of theopenings 264, theopenings 264 become narrower toward the bottom of theopenings 264, as illustrated inFIGS. 26A and 26B . Such narrowedopenings 264 are disadvantageously more prone to leaning, and the first electrodes formed within such narrowed openings having less area of contact with the underlying contact plugs 240. - To address such disadvantages, referring to
FIGS. 27A and 27B , after the fourth and fifth ILD layers 252 and 254 are deposited, afirst mold layer 302 is deposited on thefifth ILD layer 254. Thereafter, asecond mold layer 304 is deposited on thefirst mold layer 302, and the layer ofsupport material 258 is deposited on thesecond mold layer 304. In addition, athird mold layer 306 is deposited on the layer ofsupport material 258. - The fourth and fifth ILD layers 252 and 254 and the layer of
support material 258 inFIGS. 27A and 27B are similar as that ofFIGS. 12A and 12B . Thefirst mold layer 302 is comprised of BPSG (borophosphosilicate glass), thesecond mold layer 304 is comprised of PTEOS (phosphorous doped tetraethylorthosilicate) based oxide, and thethird mold layer 306 is comprised of PTEOS (phosphorous doped tetraethylorthosilicate) based oxide, in an example embodiment of the present invention. The first, second, and third mold layers 302, 304, and 306 are deposited with thicknesses of 7,000 Å (angstroms), 13,000 Å, and 5,000 Å, respectively, in an example embodiment of the present invention. - Referring to
FIGS. 28A and 28B afterFIGS. 27A and 27B , a photo-resistlayer 308 is patterned for forming a plurality ofopenings 310 through the layers ofmaterials layer 308 is deposited and patterned on thethird mold layer 306. Each of theopenings 310 is formed over one of the secondconductive plugs 240 that become exposed through theopenings 310. - In the embodiment of the present invention, the bottom
first mold layer 302 has a higher etch rate than the uppersecond mold layer 304 in an etch process for etching the first and second mold layers 302 and 304 when forming theopenings 310. Because the bottomfirst mold layer 302 etches away faster in such an etch process, theopenings 310 do not narrow significantly toward the bottom of theopenings 310. - Referring to
FIGS. 29A and 29B afterFIGS. 28A and 28B , thefirst electrodes FIGS. 15A and 15B . Referring toFIGS. 30A and 30B afterFIGS. 29A and 29B , the maskingspacers 274 and themask structures 276 comprised of a mask material are formed, similar toFIGS. 19A and 19B . In addition, any portion of thesupport material 258 that is not covered under the maskingspacers 274 or themask structures 276 is etched away to form the support structures comprised of the remainingsupport material 258, similar toFIGS. 20A and 20B . - Referring to
FIGS. 31A and 31B afterFIGS. 30A and 30B , the maskingspacers 274, themask structures 276, the first and second mold layers 302 and 304, and thesacrificial dielectric 266 are etched away, similar toFIGS. 21A and 21B . Thereafter, thecapacitor dielectric 292 and thesecond electrode 294 are formed onto exposed surfaces of the first electrodes, the support structures comprised of the remainingsupport material 258, and thefifth ILD layer 254, similar toFIGS. 23A and 23B . - Comparing
FIG. 32 toFIG. 31 , the circular discs around each of the first electrodes is etched away such that just the support beams 278 remain, similar toFIGS. 24 and 25 . Thus, thecircular discs first electrodes FIG. 32 . Similar toFIG. 24 , the support beams 278 are still present in the C-C direction between any two nearest adjacent first electrodes as illustrated inFIG. 31B to prevent leaning of the first electrodes towards each-other. - The foregoing is by way of example only and is not intended to be limiting. For example, the array of stacked capacitors is illustrated and described herein as being applied for storage capacitors of a DRAM. However, the array of stacked capacitors fabricated according to the present invention may be applied for any other application requiring maximized capacitance of highly integrated capacitors. In addition, any dimension, number, and material specified or illustrated herein is by way of example only.
- Furthermore, any shape described or illustrated herein is by way of example only. For example,
circular discs support material 258 are described and illustrated herein as being formed around the circularfirst electrodes support material 258 may also be rectangular if the first electrodes were formed to have a rectangular cross-section. - Additionally, it is to be understood that terms and phrases such as “on” and “bottom” as used herein refer to relative location and orientation of various portions of the structures with respect to one another, and are not intended to suggest that any particular absolute orientation with respect to external objects is necessary or required. For example, when one layer of material is stated to be deposited “on” another layer of material, the present invention may be practiced when an intervening layer of material is also present between such layers of materials.
- The present invention is limited only as defined in the following claims and equivalents thereof.
Claims (10)
1. An array of capacitors, comprising:
a plurality of stacked capacitors each respectively having a first electrode; and
a plurality of support structures including a respective disc surrounding each first electrode and including joining portions that are disposed between the first electrodes of adjacent capacitors.
2. The array of capacitors of claim 1 , further comprising:
a respective masking spacer disposed on each disc and a respective mask structure disposed on each joining portion.
3. The array of capacitors of claim 1 , further including:
a layer of mount material surrounding the first electrodes toward the bottom of the first electrodes.
4. The array of capacitors of claim 3 , wherein the support structures are disposed between the mount material and the top of the first electrode.
5. The array of capacitors of claim 4 , wherein the mount material and the support structures are comprised of silicon nitride.
6. The array of capacitors of claim 1 , wherein the support structures are comprised of silicon nitride.
7. The array of capacitors of claim 1 , wherein the respective disc surrounding each first electrode is a circular disc.
8. The array of capacitors of claim 1 , wherein each of the capacitors is formed onto a respective conductive plug coupled to a junction of a respective switching transistor.
9. The array of capacitors of claim 8 , wherein the array of capacitors is formed as part of a DRAM (dynamic random access memory).
10. The array of capacitors of claim 9 , wherein the first electrode is a storage node for each capacitor.
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US11/405,340 US20060211178A1 (en) | 2004-02-10 | 2006-04-17 | Fabrication of lean-free stacked capacitors |
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KR1020040008770A KR100568733B1 (en) | 2004-02-10 | 2004-02-10 | Capacitor having enhanced structural stability, Method of manufacturing the capacitor, Semiconductor device having the capacitor, and Method of manufacturing the semiconductor device |
KRP2004-8770 | 2004-02-10 | ||
US10/853,628 US7153740B2 (en) | 2004-02-10 | 2004-05-25 | Fabrication of lean-free stacked capacitors |
US11/405,340 US20060211178A1 (en) | 2004-02-10 | 2006-04-17 | Fabrication of lean-free stacked capacitors |
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US (2) | US7153740B2 (en) |
JP (1) | JP4704014B2 (en) |
KR (1) | KR100568733B1 (en) |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5811848A (en) * | 1996-08-16 | 1998-09-22 | United Microelectronics Corporation | Capacitor structure for a semiconductor memory device |
US20030085420A1 (en) * | 2001-11-06 | 2003-05-08 | Kabushiki Kaisha Toshiba | Semiconductor memory and method of producing the same |
US6667502B1 (en) * | 1999-08-31 | 2003-12-23 | Micron Technology, Inc. | Structurally-stabilized capacitors and method of making of same |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100311050B1 (en) * | 1999-12-14 | 2001-11-05 | 윤종용 | Method for manufacturing electrode of capacitor |
KR100449030B1 (en) | 2002-01-24 | 2004-09-16 | 삼성전자주식회사 | Stack Capacitor and Method of Fabricating the Same |
JP2003234419A (en) * | 2002-02-08 | 2003-08-22 | Mitsubishi Electric Corp | Manufacturing method for semiconductor device and the same manufactured by the method |
JP4047631B2 (en) | 2002-05-28 | 2008-02-13 | エルピーダメモリ株式会社 | Semiconductor integrated circuit device having crown-structured capacitor and manufacturing method thereof |
US6784479B2 (en) * | 2002-06-05 | 2004-08-31 | Samsung Electronics Co., Ltd. | Multi-layer integrated circuit capacitor electrodes |
KR100538098B1 (en) * | 2003-08-18 | 2005-12-21 | 삼성전자주식회사 | Semiconductor device including a capacitor having improved structural stability and enhanced capacitance, and Method for manufacturing the same |
US7067385B2 (en) * | 2003-09-04 | 2006-06-27 | Micron Technology, Inc. | Support for vertically oriented capacitors during the formation of a semiconductor device |
-
2004
- 2004-02-10 KR KR1020040008770A patent/KR100568733B1/en active IP Right Grant
- 2004-05-25 US US10/853,628 patent/US7153740B2/en active Active
- 2004-06-30 TW TW093119359A patent/TWI333680B/en active
- 2004-07-28 CN CNB2004100586902A patent/CN100481393C/en active Active
- 2004-11-03 DE DE102004053095A patent/DE102004053095B4/en active Active
- 2004-11-24 JP JP2004339574A patent/JP4704014B2/en active Active
-
2006
- 2006-04-17 US US11/405,340 patent/US20060211178A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5811848A (en) * | 1996-08-16 | 1998-09-22 | United Microelectronics Corporation | Capacitor structure for a semiconductor memory device |
US6667502B1 (en) * | 1999-08-31 | 2003-12-23 | Micron Technology, Inc. | Structurally-stabilized capacitors and method of making of same |
US20030085420A1 (en) * | 2001-11-06 | 2003-05-08 | Kabushiki Kaisha Toshiba | Semiconductor memory and method of producing the same |
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US7829410B2 (en) | 2007-11-26 | 2010-11-09 | Micron Technology, Inc. | Methods of forming capacitors, and methods of forming DRAM arrays |
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US20110018098A1 (en) * | 2007-11-26 | 2011-01-27 | Micron Technology, Inc. | Semiconductor Constructions |
US20090146256A1 (en) * | 2007-12-05 | 2009-06-11 | Elpida Memory, Inc. | Method of forming semiconductor device including capacitor and semiconductor device including capacitor |
US7897474B2 (en) * | 2007-12-05 | 2011-03-01 | Elpida Memory, Inc. | Method of forming semiconductor device including capacitor and semiconductor device including capacitor |
US20090184393A1 (en) * | 2008-01-21 | 2009-07-23 | Industrial Technology Research Institute | Memory capacitor and manufacturing method thereof |
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US7696056B2 (en) | 2008-05-02 | 2010-04-13 | Micron Technology, Inc. | Methods of forming capacitors |
US8623725B2 (en) | 2008-05-02 | 2014-01-07 | Micron Technology, Inc. | Methods of forming capacitors |
US20100025362A1 (en) * | 2008-05-02 | 2010-02-04 | Micron Technology, Inc. | Method of Forming Capacitors |
US7618874B1 (en) | 2008-05-02 | 2009-11-17 | Micron Technology, Inc. | Methods of forming capacitors |
US8241987B2 (en) | 2008-05-02 | 2012-08-14 | Micron Technology, Inc. | Methods of forming capacitors |
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US8318578B2 (en) | 2008-05-02 | 2012-11-27 | Micron Technology, Inc. | Method of forming capacitors |
US20100176486A1 (en) * | 2009-01-13 | 2010-07-15 | Elpida Memory, Inc. | Semiconductor device and method of manufacturing the same |
US20100203699A1 (en) * | 2009-02-09 | 2010-08-12 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device |
US20100258907A1 (en) * | 2009-04-08 | 2010-10-14 | Elpida Memory, Inc. | Semiconductor device and method of manufacturing the same |
US20120217560A1 (en) * | 2011-02-28 | 2012-08-30 | Kyungmun Byun | Semiconductor Memory Devices Including Support Patterns |
US20140367755A1 (en) * | 2011-02-28 | 2014-12-18 | Samsung Electronics Co., Ltd. | Semiconductor memory devices including support patterns |
US9147685B2 (en) * | 2011-02-28 | 2015-09-29 | Samsung Electronics Co., Ltd. | Semiconductor memory devices including support patterns |
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Also Published As
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TWI333680B (en) | 2010-11-21 |
KR20050080670A (en) | 2005-08-17 |
US7153740B2 (en) | 2006-12-26 |
DE102004053095A1 (en) | 2005-08-25 |
US20050176210A1 (en) | 2005-08-11 |
DE102004053095B4 (en) | 2010-06-10 |
KR100568733B1 (en) | 2006-04-07 |
JP2005229097A (en) | 2005-08-25 |
CN100481393C (en) | 2009-04-22 |
JP4704014B2 (en) | 2011-06-15 |
CN1655339A (en) | 2005-08-17 |
TW200527585A (en) | 2005-08-16 |
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