US20060238263A1

US20060238263A1 - Detection Of A Closed Loop Voltage

Info

Publication number: US20060238263A1
Application number: US11/428,325
Authority: US
Inventors: Vincent Tso; James Ho
Original assignee: Exar Corp
Current assignee: Exar Corp
Priority date: 2004-09-30
Filing date: 2006-06-30
Publication date: 2006-10-26
Also published as: US20060066359A1; US7102393B2

Abstract

To detect whether a closed-loop's voltage is out of range, a voltage detector includes first and second transistors that deliver first and second currents respectively to first and second high impedance nodes. The voltage detector further includes third and fourth transistors that draw third and fourth currents respectively from the first and second nodes. The first and second currents are scaled replicas of a current flowing through a current source of a voltage-to-current converter that converts the close-loop's voltage to a current and supplies a first voltage to the first and second transistors. The third and fourth currents are scaled replicas of a different current flowing through a current mirror of the voltage-to-current converter and that supplies a second voltage to the third and fourth transistors.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application is a division of and claims priority from application Ser. No. 10/956,357 filed Sep. 30, 2004, entitled “Detection of a Closed Loop Voltage,” the content of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to electronic circuits, and more particularly to detection of a control voltage in a closed loop circuit, such as a phase locked or delay locked loop.
The increasing speed with which multiple types of data, such as text, audio and video, are transported over existing communication networks has brought to the fore the reliability with which such data transportation is carried out. In accordance with one conventional method, to ensure reliable data transfer, the data is first encoded with a reference clock signal at the transmitting end of the network to generate a composite signal. Thereafter, the composite signal is transmitted over the network to the receiving end. At the receiving end, the data and clock signals are recovered from the composite signal to ensure that the data and clock signals remain synchronous with respect to each other.
The clock and data recovery is typically carried out, for example, by a delay locked loop or a phase locked loop. In operation, a phase locked loop maintains a fixed relationship between the phase and frequency of the signal it receives and those of the signal it generates. FIG. 1 is a simplified block diagram of a conventional phase locked loop (PLL) 10 adapted to maintain a fixed relationship between the phase and frequency of signal CLK and signal Ref_Clk. PLL 10 includes, among other components, phase detector 12, charge pump 14, loop filter 16 and voltage controlled oscillator (VCO) 18. The extracted clock signal Clk is supplied at the output terminal of VCO 18. Once in a locked state, the phase and frequency of signal Clk generated by PLL 10 is locked to those of signal Ref_Clk received by PLL 10. The operation of PLL 10 is described further below.
Phase detector 12 receives signals Ref_Clk and Clk, and in response, generates signal A that corresponds to the difference between the phases of these two signals. Charge pump 14 receives signal A and in response generates and delivers to node B a current signal whose duration varies depending on the magnitude of signal A. Loop filter 16 filters out the high frequency components of signal I and delivers a filtered-out voltage signal to VCO 18.
If signal Ref_Clk leads signal Clk in phase—indicating that the VCO is running relatively slowly—signal A causes charge pump 14 to increase its output current until VCO 18 achieves an oscillation frequency at which signal Clk is frequency-locked and phase-locked with signal Ref_Clk. If, on the other hand, signal Ref_Clk lags signal Clk in phase—indicating that the VCO is running relatively fast—signal A causes charge pump 14 to reduce its output current until VCO 18 achieves an oscillation frequency at which signal Clk is frequency-locked and phase-locked with signal Ref_Clk. Signal Clk is considered to be locked to signal Vref if its frequency is within a predetermined frequency range of signal Ref_Clk. Signal Clk is considered to be out-of-lock with signal Ref_Clk if its frequency is outside the predetermined frequency range of signal Ref_Clk.
FIG. 2 is a simplified block diagram of another conventional PLL 30 that includes, among other components, phase/frequency detector 32, charge pump 34, loop filter 36, voltage to current (VTI) converter 38, current controlled oscillator (ICO) 40, and out-of-range voltage detection circuitry 42. In PLL 30, voltage Vcont is generated by charge pump 34. Out-of-range voltage detection circuitry 42 is adapted to detect whether voltage Vcont is within a range defined by voltage Vbg. Determination of voltage Vcont provides insight into the loop dynamics, enables control of the loop voltage, and allows PLL 30 to be calibrated. In response, voltage detection circuitry 42 generates voltage signals Vcom1 and Vcom2. VTI converter 38, using voltage Vref, converts the voltage Vcont to a current I, and delivers this current to ICO 40.
FIG. 3 is a transistor schematic diagram of VTI circuit 38, as known in the prior art. VTI circuit 38 is shown as including a differential amplifier formed by NMOS transistors 120, 122 and resistor 118, current source 200, current mirrors 205, 210, 215, 220, 225, and biasing transistor 106. Assume current source 200, which is a cascade current source generates a current of 21 that flows through PMOS transistors 102, 104. Current mirrors 205, 220, and 225 mirror this current, and therefore, a current of 21 also flows through PMOS transistors 108, 128, and 130. Part of the current 21 mirrored in transistor 128 flows through PMOS transistor 124—shown as current I+DI—the remainder of this current flows through transistor 120—shown as current I−DI. Similarly, part of the current 21 mirrored in transistor 130 flows through PMOS transistor 126—shown as current I−DI—the remainder of this current flows through transistor 122—shown as current I+DI. Because the same current flows through both PMOS transistor 124 and NMOS 132, a current of I+DI flows through transistor 132. Moreover, because the same current flows through NMOS transistors 132, and 134, a current of I+DI flows through transistor 134.
NMOS transistors 114, and 116 are scaled relative to NMOS transistor 112, such that each conduct a current of I. If voltage Vcont is greater than voltage Vref, more current, e.g., I+DI flows through transistor 122 and less current, e.g., I−DI flows through transistor 120. Similarly, if voltage Vcont is smaller than voltage Vref, more current flows through transistor 120 and less current flows through transistor 122. Because the current through transistors 114 and 116 is adapted to be I, a current of DI flows through resistor 118 and transistor 116. It is understood that depending on the relative sizes of voltages Vcont and Vref, shown current DI may have a positive or a negative value. The difference 2DI between current I−DI flowing through transistor 126 and current of I+DI flowing through transistor 134, flows to terminal Icnt1 if current DI is negative, or from terminal Icnt1 if DI is positive. Therefore, the difference between voltages Vcont and Vref, results in change in the current 2DI flowing into or out of terminal Icntl.
FIG. 4 shows the change in the current flowing through terminal Icntl as a function of the difference between voltages Vcnt and Vref. The current flow through terminal Icnt varies linearly as a function of the difference between voltages Vcnt and Vref, so long as this voltage difference is between±Vd . A constant current of 2I flows through this terminal if the magnitude of the difference between voltages Vcnt and Vref exceeds Vd.
FIG. 5 is a schematic diagram of voltage detection circuitry 42, as known in the prior art. Band-gap voltage generator 52 generates reference voltage Vbg that is applied to positive input terminal Inp of operational amplifier (op-amp) 54. The output voltage of op-amp 54 is applied to the gate terminal of PMOS transistor 60. Upper boundary voltage Vcom_hi is applied to the positive input terminal Inp of voltage comparator 66, and lower boundary voltage Vcom_lo is applied to the positive input terminal Inp of voltage comparator 68. Voltage signal Vcont is applied to the negative input terminals Inn of both voltage comparators 66 and 68. If voltage Vcont is greater than voltage Vcom_hi, output signals Vcom1 and Vcom2 make a high-to-low transition. If voltage Vcont is smaller than voltage Vcom_lo, output signals Vcom1 and Vcom2 make a low-to-high transition. If voltage Vcont is between voltages Vcom_lo and Vcom_hi, output signal Vcom1 remains high and output signal Vcom2 remains low.
As seen from FIG. 5, out-of-range detection circuitry 42 requires, among other components, one op-amp, two voltage comparators, as well as a band-gap circuit. Therefore, out-of-range detection circuitry 42 is relatively large, i.e., consumes a relatively large semiconductor surface area, and also consumes a relatively large power.

BRIEF SUMMARY OF THE INVENTION

To detect whether a closed-loop voltage, such as the closed-loop voltage of a PLL or DLL, is out of range, a voltage detector includes first and second transistors that deliver first and second currents respectively to first and second high impedance nodes. The voltage detector further includes third and fourth transistors that draw third and fourth currents respectively from the first and second nodes. The first and second currents are scaled replicas of a current flowing through a current source of a voltage-to-current converter that converts the close-loop voltage to a current and supplies a first voltage to the first and second transistors. The third and fourth currents are scaled replicas of a different current flowing through a current mirror of the voltage-to-current converter and that supplies a second voltage to the third and fourth transistors.
The first transistor has a gate terminal that receives a first voltage generated by the voltage-to-current converter and, in response, generates a first current that is equal to a scaled replica of the first current generated by the voltage-to-current converter. The drain terminal of the first transistor is coupled to a first output node of the voltage detector. The second transistor has a gate terminal that receives the first voltage and, in response, generate a second current that is equal to a scaled replica of the first current generated by the voltage-to-current converter. The drain terminal of the second transistor is coupled to a second output node of the voltage detector. The third transistor has a gate terminal that receives a second voltage generated by the voltage-to-current converter, and in response, generates a third current that is a scaled replica of the second current generated by the voltage-to-current converter. The drain terminal of the third transistor is coupled to the first output node of the voltage detector. The fourth transistor has a gate terminal that receives the second voltage and, in response, generates a fourth current that is a scaled replica of the second current generated by the voltage-to-current converter. The drain terminal of the fourth transistor is coupled to the second output node of the voltage detector. Each of the first and second output nodes is a high impedance node.
In some embodiments, if for example, both the first and second output nodes are at a first voltage level, the voltage detector detects a first out-of-range condition, e.g., the closed loop control voltage is smaller than the lower limit of the loop's voltage range. If, for example, both the first and second output nodes are at a second voltage level, the voltage detector detects a second out-of-range condition, e.g., the closed loop control voltage is smaller than the lower limit of the loop's voltage range. If, for example, the first output node is at a first voltage level, and the second output node is at a second voltage level, the voltage detector detects that closed-loop voltage is within the lower and upper limits of the loop's voltage range.
In accordance with another embodiment of the present invention, the voltage detector is adapted to include N programmable current mirrors each receiving a programmable bit to determine which one of the equal division of the loop's voltage range matches the closed loop voltage. To achieve this, each programmable current mirror delivers its current to an output node via a different one of N current paths. In some embodiments, the m^thcurrent path is adapted to generate a current having a size that is equal to ½^mof a current supplied by a voltage-to-current converter coupled to the voltage detector. The voltage detector also includes a current mirror that mirrors another current flowing in the voltage-to-current converter and draws current from the output node. To determine which one of the equal division of the loop's voltage range matches the closed loop voltage, the logic states of the programmable bits are varied to determine their effects on the output node voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram of a phase/frequency locked loop, as known in the prior art.
FIG. 2 is a simplified block diagram of another phase/frequency locked loop having disposed therein a voltage detection circuitry, as known in the prior art.
FIG. 3 is a transistor schematic diagram of the voltage-to-current converter disposed in the phase/frequency locked loop of FIG. 2, as known in the prior art.
FIG. 4 shows the change in the current flowing through the output terminal of the voltage-to-current converter of FIG. 2, as a function of the difference between the applied voltages.
FIG. 5 is a block diagram of the voltage detection circuitry disposed in the phase/frequency locked loop of FIG. 2, as known in the prior art.
FIG. 6 is a simplified block diagram of a phase/frequency locked loop having disposed therein a voltage detection circuitry, in accordance with one embodiment of the present invention.
FIG. 7 is a transistor schematic diagram of the voltage-to-current converter coupled to a voltage detection circuitry, in accordance with one embodiment of the present invention.
FIG. 8 is a transistor schematic diagram of the voltage-to-current converter coupled to a voltage detection circuitry, in accordance with another embodiment of the present invention.
FIG. 9 shows the closed-loop voltage range divided into four equal divisions.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 6 is a simplified block diagram of a PLL 300 that includes, among other components, a phase/frequency detector 32, a charge pump 34, a loop filter 36, a voltage to current (VTI) converter 38, a current controlled oscillator (ICO) 40, and detection circuitry 310. Detection circuitry 310, in accordance with the present invention, receives voltage signals V1 and V2 from VTI converter 38 and generates voltage signals Vcom1, and Vcom2. Voltage signals Vcom1 and Vcom2 are applied to high-impedance nodes, e.g., to gate terminals of MOS transistors disposed in CMOS inverters, and indicate whether PLL 300 is out of a predefined tuning range. In other words, signals Vcom1 and Vcom2 detect whether an out-of-range condition is present in the loop. For example, a relatively low voltage level on signal Vcom1 indicates that voltage Vcont is greater than the upper range of PLL 30's tuning range. Similarly, a relatively high voltage level on signal Vcom2 indicates that voltage Vcont is smaller than the lower range of PLL 30's tuning range. Phase detector 32, charge pump 34, low-pass filter 36, and ICO 40 are known and are not described below.
FIG. 7 is a transistor schematic diagram of VTI circuit 38 coupled to detection circuitry 310 of the present invention. Detection circuitry 310 is adapted to detect whether voltage Vcont is within or outside a range defined by the loop's tuning range. It is understood that the tuning range defines the range in which the PLL, or any other close loop circuitry, such a delay locked-loop or frequency locked loop, remains in the closed loop state. In other words, for example, PLL 300 no longer operates in a closed-loop mode if the voltage Vcont is outside the PLL's tuning range. In FIG. 4, the tuning range is defined by ±Vd. VTI circuit 38 receives voltage signals Vref and Vcnt and, in response, generates current signal Icnt1, and voltage signals V1 and V2. Current signal Ibias_1 biases transistor 106, and current signal Ibias_2 biases the transistors disposed in current source 200. VTI circuit 38 is shown as including a differential amplifier formed by transistors 120, 122 and resistor 118, current source 200, current mirrors 205, 210, 215, 220, 225, and biasing transistor 106. To ensure robustness, the closed-loop voltage of a PLL is typically adapted to operate within, for example, 80% of the PLL's tuning range.
Current source 200, which is a cascade current source generates a current of 2I that flows through PMOS transistors 102, 104. Current mirrors 205, 220, and 225 mirror this current, and therefore, a current of 2I also flows through PMOS transistors 108, 128, and 130. Part of the current 2I mirrored in transistor 128 flows through PMOS transistor 124—shown as current I+DI—the remainder of this current flows through transistor 120—shown as current I−DI. Similarly, part of the current 2I mirrored in PMOS transistor 130 flows through transistor 126—shown as current I−DI—the remainder of this current flows through NMOS transistor 122—shown as current I+DI. Because the same current flows through both PMOS transistor 124 and NMOS 132, a current of I+DI flows through transistor 132. Moreover, because the same current flows through NMOS transistors 132, and 134, a current of I+DI flows through transistor 134.
If voltage Vcont is greater than voltage Vref, more current flows through transistor 122 and less current flows through transistor 120. Similarly, if voltage Vcont is smaller than voltage Vref, more current flows through transistor 120 and less current flows through transistor 122. It is understood that depending on the relative sizes of voltages Vcont and Vref, shown current DI may have a positive or a negative value. The difference 2DI between current I−DI flowing through transistor 126 and current of I+DI flowing through transistor 134, flows to terminal Icnt1 if DI is negative, or from terminal Icnt1 if DI is positive. Therefore, the difference between voltages Vcont and Vref, results in a change in the current 2DI flowing into or out of terminal Icnt1.
VTI circuit 38 generates first and second voltages V1, and V2 that are applied to detection circuit 310. Detection circuit 310 is shown as including PMOS transistors 400, 405, and NMOS transistors 410, and 415. PMOS transistor 400 may have a channel-width to channel-length ratio, i.e., W/L, selected to be L times the W/L ratio of transistor 102. Similarly, PMOS transistor 405 may have a W/L ratio selected to be M times the W/L ratio of transistor 102. It is understood that L and M may be equal to 1. Moreover, each of transistors 400, and 405 may be scaled so as to have additional current driving capability that is K times the current driving capability of transistor 102, and each of transistors 410, and 415 maybe scaled so as to have current driving capability that is K times the current driving capability of transistor 132. For example, scaling of PMOS transistor 400 may be achieved by connecting a number of such transistors in parallel. Therefore, transistors 400 may be selected to have a driving capability of KL times the driving capability of transistor 102. Transistors 405 may be selected to have a driving capability of KM times the driving capability of transistor 102. Transistors 410, and 415 may each be selected to have a driving capability of K times the driving capability of transistor 132. Accordingly, all four transistors 400, 405, 410, and 415 may be scaled by the same factor K.
Consequently, if current 2I flows through transistor 102 and current I+DI flows through transistor 132, current 2I*KL flows through transistor 400, current 2I*KM flows through transistor 405, and current (I+DI)*K flows through each of transistors 410, and 415. Because node A carrying voltage signal Vcom1 is a high impedance node, if the current flow through transistor 400 is greater than the current flow through transistor 410, node A is pulled to the positive supply voltage Posa. If the current flow through transistor 400 is smaller than the current flow through transistor 410, node A is pulled to the negative supply voltage Nega. Similarly, because node B carrying voltage signal Vcom2 is also a high impedance node, if the current flow through transistor 405 is greater than the current flow through transistor 415, node B is pulled to the positive supply voltage Posa. If the current flow through transistor 405 is smaller than the current flow through transistor 415, node B is pulled to the negative supply voltage Nega.
By decoding the voltages on nodes A and B, detection circuit 30 detects whether an out-of range condition is present. For example, if both voltages Vcom1 and Vcom2 are at supply voltage Posa, an out-of-range condition is detected thus indicating that the loop voltage Vcont is smaller than the lower tuning range of the PLL. Similarly, if for example, both voltages Vcom1 and Vcom2 are at supply voltage Nega, an out-of-range condition is detected thus indicating that the loop voltage Vcont is greater than the upper tuning range of the PLL. If, for example, voltage Vcom1 is at supply voltage Posa and Vcom2 is at supply voltage Nega, no out-of-range condition is detected indicating that the loop voltage Vcont is within the lower and upper tuning range of the PLL. It is understood that in a differential closed-loop, charge pump 34 is a differential charge pump outputting a pair of differential signals, thus causing a pair of differential voltages (not shown), in place of voltages Vcont and Vref, to be applied to the gate terminals of transistors 120, and 122.
FIG. 8 is a transistor schematic diagram of VTI circuit 38 coupled to detection circuitry 400, in accordance with another embodiment of the present invention. Detection circuitry 400 is adapted to divide the closed loop's tuning range into an even and equal number of divisions and identify the division in which closed loop control voltage (hereinafter alternatively referred to as closed loop voltage or control voltage) Vcont falls. Detection circuitry 400 is shown as including four programmable current mirrors, namely programmable current mirrors 600, 605, 610, and 615. Programmable current mirrors 600, 605, 610, 615 are respectively programmed using bits bit_3, bit_2, bit_1, and bit_0, thus enabling the ratio of the current flowing through these current mirrors compared to that flowing through transistor 580, to be binary weighted so as to digitize the relative position of the closed loop voltage. The accuracy of the position is dictated only by the matching of the current mirrors. As described above, the digitized value of the loop voltage may be used for diagnostic, calibration or for gain control purposes.
Programmable current mirror 615 includes PMOS transistors 565 and 540 and NMOS transistor 535. The gate terminals of transistors 535 and 565 receives the bit_0 voltage signal. The source terminal of transistor 535 is coupled to the gate terminal of transistor 102. The drain terminal of transistor 565 is coupled to the drain terminal of transistor 535 and to gate terminal of transistor 540. The source terminal of transistor 565 is coupled to the positive supply voltage Posa. The drain terminal of transistor 540 is coupled to the drain terminal of transistor 580. The gate terminal of transistor 580 is coupled to the gate terminals of transistors 132, 134. The source terminal of transistor 580 is coupled to the supply terminal Nega. Programmable current mirrors 600, 605 and 610 are similar to programmable current mirror 615.
Voltage detection circuitry 400 is shown as receiving four programmable bits. Accordingly, it is adapted to determine in which of the 16 equal divisions of the closed-loop's tuning range, the closed loop voltage Vcont falls. It is understood that a voltage detection circuitry, in accordance with the present invention, may include more or fewer programmable current mirrors than 4. In general, if voltage detection circuitry 400 is adapted to include N such programmable current mirrors, the closed-loop's voltage range is divided into 2^Nequal divisions. This enables the determination and matching of the closed loop voltage Vcont to one of the 2^Nvoltage divisions of the closed-loop's voltage range. In other words, the closed loop voltage may be determined with a resolution of 2^N.
Assume that it is decided to determine which one of the four voltage divisions of the loop's voltage range matches the loop voltage Vcont. FIG. 9 shows that the loop's voltage range as being divided into 4 equal parts. In other words, it is decided to determine whether:
−Vd≦VCO>−Vc or
−Vc≦VCO>0 or
0≦VCO>Vc or
Vc≦VCO≦Vd
To determine this, bits Bit_2 and bit_3 are set and maintained at 0 and are not changed thereafter. Each of bit_0 and bit_1 is also initially set to 0. Therefore, in programmable current mirror 615, transistor 535 is turned off and transistor 565 is turned on, thereby causing PMOS transistor 540 to be off (i.e., in non-conductive state). Because bit_1 is also equal to 0, transistor 530 of programmable current mirror 610 is also off. For similar reasons transistors 510 and 520 are also off. Therefore, no current flows to node 0 via transistors 510, 520, 530, and 540. This, in turn, causes transistor 580 to pull node 0 to ground. Next, bit_0 is set to 1, and bit_1 is maintained at 0. This causes transistor 540 to conduct current and transistor 530 to remain off. Programmable current mirror 615 is selected such that the current through transistor 540 when this transistor is in a conducting state, is equal to ½ of the current flow through transistor 102. Accordingly, because it is assumed that the current flow through transistor 102 is equal to 21, the current flow through transistor 540 is equal to 1. Because the current flow through transistor 132 is equal to I+DI, the current flow through transistor 580 is also equal to I+DI. Therefore, assuming DI is positive and is less than 0.51, the current flow through transistor 540, namely I, is less than the current flow through transistor 580, namely I+DI. This causes node D to be at the Nega voltage potential.
It is understood that node 0 is a high impedance node. In FIG. 8, node 0 is shown as being coupled to the input terminal of inverter 650 generating an output voltage Test_out used in the detection of the VCO voltage. It is understood that in other embodiments, node O may be coupled to another device.
Next, bit _‘ 0 is set to 0, and bit_1 is set to 1. This causes transistor 530 to conduct current and transistor 540 not to conduct current. Programmable current mirror 615 is selected such that the current through transistor 530 when this transistor is in a conducting state, is equal to ¼ of the current flow through transistor 102. Accordingly, because it is assumer that the current flow through transistor 102 is equal to 2I, the current flow through transistor 540 is equal to ½I. Because the current flow through transistor 132 is equal to I+DI, the current flow through transistor 580 is also equal to I+DI. Therefore, assuming DI is positive, the current flow through transistor 540, namely ½I, is less than the current flow through transistor 580, namely I+DI. This causes node D to be at the Nega voltage potential.
Next, bit_0 and bit_1 are both set to 1. This causes transistors 530 and 540 to conduct current. Accordingly, the current flowing to node O is equal to 1.51, while the current flowing out of node O to transistor 580 is I+DI. Because DI is assumed to be less than 0.51, node O is pulled to the positive supply voltage Posa, therefore, indicating that the closed loop voltage Vcont is between voltages Vc and Vd, as seen in FIG. 9.
It is understood, that in the above exemplary embodiment, depending on the voltage Vcont, the relative size of DI compared to I varies. Thus depending on the voltage Vcont, different combinations of bit_0 and bit_1 may cause node D to be pulled up to the supply voltage Posa or pulled down to the supply voltage Nega in accordance with another combination of bit_0 and bit_1.
It is also understood that if it is decided to determine the closed loop voltage Vcont using a 4-bit resolution, i.e., to determine which one of the sixteen equal division of the loop's voltage range matches this voltage, all the 16 combinations of the four bits bit_0, bit_1, bit_2, and bit_3 are used. Therefore, bits bit_2 and bit_3 are also varied. It is further understood that to determine the closed loop voltage Vcont using an N-bit resolution, i.e., to determine which one of the 2^Nequal division of the loop's voltage range matches this voltage, N programmable current mirrors similar to those shown in FIG. 8 is used.
The above embodiments of the present invention are illustrative and not limiting. Various alternatives and equivalents are possible. The invention is not limited by the type of the closed control loop, e.g. phase locked loop, delay-locked loop, or otherwise, which may use the voltage detection circuitry, in accordance with the present invention. The invention is not limited by the number of programmable current mirrors used to detect the position of the closed loop voltage within the closed loop's range. The invention is not limited by the type of the voltage-to-current converter that supplies voltages to the voltage detection circuitry of the present invention. The invention is not limited by the frequency of the reference or the oscillator clock signals. The invention is not limited by the type of integrated circuit in which the present invention may be disposed. Nor is the invention limited to any specific type of process technology, e.g., CMOS, Bipolar, or BICMOS that may be used to manufacture the present invention. Other additions, subtractions or modifications are obvious in view of the present invention and are intended to fall within the scope of the appended claims.

Claims

1-4. (canceled)

5. A voltage detector coupled to a voltage-to-current converter and adapted to receive a first voltage and a second voltage generated by the voltage-to-current converter, the voltage detector comprising:

N programmable current mirrors each adapted to receive the first voltage and further to receive a different one of N programmable bits, wherein each programmable current mirror is adapted to supply a different proportion of a first current generated by a current source to a first output node having a high impedance; and

a current mirror adapted to receive the second voltage and generate a current that flows out of the first node.

6. The voltage detector of claim 5 wherein each said proportion is a different number greater than 1.

7. The voltage detector of claim 5 wherein each said proportion is a different fraction of 1.

8. The voltage detector of claim 7 wherein a first one of the N programmable current mirrors is adapted to generate a current that is ½ of the first current, and wherein an m^thone of the programmable current mirrors is adapted to generate a current that is ½^mof the first current, wherein m is an integer varying from 1 to N.

9. The voltage detector of claim 8 wherein each programmable current mirrors further comprises:

a first transistor having a gate terminal adapted to receive an associated programmable bit, a source voltage coupled to a first supply voltage;

a second transistor having a gate terminal adapted to receive the associated programmable bit, a drain terminal coupled to the drain terminal of the first transistor, and a source terminal coupled to receive the first voltage;

a third transistor having a gate terminal coupled to the source terminal of the second transistor, a source terminal coupled to the first voltage supply, and a drain terminal coupled to the first output node.

10. The voltage detector of claim 9 wherein the current mirror further comprises:

a first transistor having a gate terminal coupled to receive the second voltage, a source terminal coupled to the second voltage supply, and a drain terminal coupled to the first output node.

11-14. (canceled)

15. A method of detecting a closed loop voltage, the method comprising:

forming N current paths each having an associated programmable bit and each adapted to deliver a current having a size defined a by different proportion of a first current in response to programming of its associated programmable bit, wherein the current flowing through each of the N current paths is delivered to a first output node having a high impedance;

a current mirror having a size that is proportional to a size of a second current source and adapted to draw current from the first output node;

determining the voltages generated on the first output node in response to varying the programming state of the N programmable bits; and

detecting the closed loop voltage using the determined voltages of the first output node.

16. The method of claim 15 wherein an m^thcurrent path is adapted to generate a current having a size that is equal to ½^mof the first current.