US20060252264A1 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- US20060252264A1 US20060252264A1 US11/416,209 US41620906A US2006252264A1 US 20060252264 A1 US20060252264 A1 US 20060252264A1 US 41620906 A US41620906 A US 41620906A US 2006252264 A1 US2006252264 A1 US 2006252264A1
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- silicide
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 131
- 238000004519 manufacturing process Methods 0.000 title claims description 36
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 170
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 123
- 229910052751 metal Inorganic materials 0.000 claims abstract description 106
- 239000002184 metal Substances 0.000 claims abstract description 106
- 239000012535 impurity Substances 0.000 claims abstract description 83
- 238000009792 diffusion process Methods 0.000 claims abstract description 72
- -1 silicide compound Chemical class 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 239000010410 layer Substances 0.000 claims description 100
- 238000009413 insulation Methods 0.000 claims description 98
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 64
- 229920005591 polysilicon Polymers 0.000 claims description 64
- 230000001681 protective effect Effects 0.000 claims description 27
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 26
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 26
- 238000010438 heat treatment Methods 0.000 claims description 25
- 239000011229 interlayer Substances 0.000 claims description 17
- 229910017052 cobalt Inorganic materials 0.000 claims description 14
- 239000010941 cobalt Substances 0.000 claims description 14
- 229910052763 palladium Inorganic materials 0.000 claims description 14
- 229910052759 nickel Inorganic materials 0.000 claims description 13
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 12
- 229910052735 hafnium Inorganic materials 0.000 claims description 11
- 229910052726 zirconium Inorganic materials 0.000 claims description 11
- 239000010408 film Substances 0.000 description 284
- 238000000034 method Methods 0.000 description 27
- 229910052710 silicon Inorganic materials 0.000 description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 22
- 239000010703 silicon Substances 0.000 description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 230000002159 abnormal effect Effects 0.000 description 13
- 229910052814 silicon oxide Inorganic materials 0.000 description 13
- 230000015271 coagulation Effects 0.000 description 11
- 238000005345 coagulation Methods 0.000 description 11
- 238000000137 annealing Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910021334 nickel silicide Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910012990 NiSi2 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
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- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
- H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device in which a silicide film is formed at a gate electrode and impurity diffusion layers and manufacturing method thereof.
- siliciding is carried out by forming a silicide film at the same time on the gate electrode surface and the impurity diffusion layer surface after forming a gate insulation film, gate electrode, sidewall insulation film and impurity diffusion layer of a transistor, by forming a metal layer on polysilicon of the gate electrode and on the impurity diffusion layer and subjecting this to heat treatment.
- a silicide film is formed on a diffusion layer, and a dummy silicide film is formed on a gate.
- the first inter-layer insulation film and the dummy silicide film are removed by planarization using CMP to make the first inter-layer insulation film and a polysilicon electrode flat.
- a Co film is deposited, heat treatment is performed, and a silicide film is formed through siliciding of the upper section of a polysilicon electrode.
- a semiconductor device including: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate and containing a gate electrode; impurity diffusion layers formed at both sides, in a cross-section in a gate length direction of the gate electrode, of a region on which the semiconductor element is formed of the semiconductor substrate; first silicide films formed respectively at the surface of the impurity diffusion layers, composed of a silicide compound of a first metal; and a second silicide film, formed at least at the surface of the gate electrode, composed of a silicide compound of a second metal different to the first metal, wherein the silicide compound of the second metal has a silicidation temperature lower than the silicidation temperature of the silicide compound of the first metal.
- the combination of the first metal and the second metal may be, in order, nickel and palladium, cobalt and palladium, or cobalt and nickel.
- the silicidation temperatures of the cobalt silicide compound (CoSi 2 ), nickel silicide compound (NiSi), and palladium silicide compound (Pd 2 Si) are of high temperatures in this order (Kusano, “Semiconductor Encyclopedia”, Kogyo Chosakai Publishing, Dec. 20th, 1999, P 521; Sano, The 52nd Lecture of the Japan Society of Applied Physics, Lecture Proceedings (spring 2005), P 958; and S. S. Lau et al, Interactins in the Co/Si thin-film system. I. Kinetics, J. appl.
- the silicide compound of the second metal can be composed taking NiSi as a main component.
- the silicide compound of the second metal may contain NiSi 2 .
- the second silicide film of the gate electrode can be configured from a silicide compound of the second metal that is of a silicidation temperature that is lower than that of the silicide compound of the first metal. Therefore, for example, after forming a first silicide film on the surface of the impurity diffusion layers, in the event that the second silicide film is formed in a separate step, it is possible to form the second silicide film using a lower temperature. Because of this, it is possible to prevent abnormal growth and coagulation of the first silicide film during forming of the second silicide film of the gate electrode after forming the first silicide film. As a result, it is possible to prevent high resistance of the impurity diffusion layers of the semiconductor device and increases in junction leakage.
- a semiconductor device including: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate and containing a gate electrode; impurity diffusion layers formed at both sides, in a cross-section in a gate length direction of the gate electrode, of a region on which the semiconductor element is formed of the semiconductor substrate; first silicide films formed respectively at the surface of the impurity diffusion layers, composed of a silicide compound of a first metal; and a second silicide film, formed at least at the surface of the gate electrode, composed of a silicide compound of a second metal different to the first metal, wherein the silicide compound of the second metal has a silicidation temperature lower than the silicidation temperature of the silicide compound of the first metal.
- the whole of the gate electrode is composed of the second silicide film.
- a state where the whole of the gate electrode is composed of the second silicide film is referred to as fully silicided.
- the semiconductor element may further include a gate insulation film formed between the semiconductor substrate and the gate electrode.
- the gate electrode can be composed of the second silicide film from the surface so as to span a surface making contact with the gate insulation film.
- the second silicide film of the gate electrode can be configured from a silicide compound of the second metal that is of a silicidation temperature that is lower than that of the silicide compound of the first metal. It is therefore possible to perform siliciding of the gate electrode at a low temperature using the second metal. Because of this, it is possible to make the film thickness of the second silicide film the desired thickness without the occurrence of abnormal growth in the first silicide film at the impurity diffusion layer. As a result, it is possible for the gate electrode to be fully silicided without influencing the impurity diffusion layers.
- the gate electrode In the event of using a semiconductor material such as polysilicon as the gate electrode material, there are cases where a depletion layer occurs in the polysilicon of the gate electrode in the vicinity of the interface with the gate insulation film. When a depletion layer occurs, a sufficient electric field is not applied to the gate insulation film even if a gate voltage is applied, and it is difficult to induce carriers in the channel region. The effect of this is that the threshold voltage is raised and variation in threshold voltages is substantial. According to the present invention, the gate electrode is fully silicided, and the gate electrode does not contain semiconductor so that this kind of problem is therefore resolved.
- the semiconductor element further includes a gate insulation film containing a film formed between the semiconductor substrate and the gate electrode, containing Hr or Zr, and being in contact with the gate electrode.
- the film containing Hf or Zr can be a high dielectric constant insulation film (high-k film).
- high-k film high dielectric constant insulation film
- the current drive performance of the transistor can be improved and the gate leakage current can be reduced.
- Fermi Level Pinning occurs in the event where the gate insulation film is composed of a high dielectric constant insulation film and the gate electrode is made of polysilicon.
- Fermi level pinning can be considered to be where, in the vicinity of the interface of the side of the gate insulation film within the gate electrode, metal constituting a high dielectric constant insulation film diffuses to within the polysilicon constituting the gate electrode so that levels are formed based on bonds between the silicon and the metal.
- Fermi level pinning is such that it is easy for a P-type MOSFET having a gate electrode composed of polysilicon containing P-type impurity to occur.
- the gate insulation film is constructed of a film containing Hf or Zr
- the problems of increase in threshold voltage and variation in the threshold voltage are more prevalent than in the case of using silicon oxide film as the gate insulation film.
- the second silicide film can be fully silicided and this kind of depletion layer problem can be resolved.
- the current drive performance of the transistor can be improved and the gate leakage current can be reduced.
- the film contains Hf or Zr and is not a high dielectric constant insulation film, the effect of resolving this depletion layer problem is obtained, and the present invention can be applied to cases where the film is not a high dielectric constant insulation film.
- a method of manufacturing a semiconductor device including: preparing a structure comprising a semiconductor element and impurity diffusion layers formed at both sides of a region on which the semiconductor element is formed of the semiconductor substrate, the semiconductor element including a gate electrode composed of polysilicon; forming first silicide films composed of a silicide compound of a first metal at the surface of the impurity diffusion layers; and forming a second silicide film composed of a silicide compound of a second metal different to the first metal at least at the surface of the polysilicon of the gate electrode, wherein, in the forming the second silicide film, the second silicide film is formed under lower temperature conditions than the temperature used in the forming the first silicide film.
- the second silicide film of the gate electrode is formed under temperature conditions that are lower than the forming of the first silicide film. Therefore, for example, in the event that the second silicide film is formed in a separate process after forming the first silicide film at the surface of the impurity diffusion layer, it is possible to form the second silicide film at a low temperature. Because of this, it is possible to prevent abnormal growth and coagulation of the first silicide film during forming of the second silicide film of the gate electrode after forming the first silicide film. As a result, it is possible to prevent high resistance of the impurity diffusion layers of the semiconductor device and increases in junction leakage.
- the forming the first silicide film may include: forming a film of the first metal on the entire surface of the semiconductor substrate in such a manner as to be in contact with the impurity diffusion layers; and siliciding the surface of the impurity diffusion layers by carrying out heat treatment under a first temperature condition.
- the forming the second silicide film may also include: forming a film of the second metal on the entire surface of the semiconductor substrate in such a manner as to be in contact with the polysilicon of the gate insulation film; and siliciding at least the surface of the polysilicon by carrying out heat treatment under a second temperature condition lower than the first temperature condition.
- the second temperature condition a temperature condition lower than the silicidation temperature of the silicide compound of the first metal.
- the second temperature condition a lower temperature than the silicidation temperature of the silicide compound of the first metal, after forming the first silicide film, it is possible to prevent abnormal growth and coagulation of the first silicide film during forming of the second silicide film of the gate electrode. As a result, it is possible to prevent high resistance of the impurity diffusion layers of the semiconductor device and increases in junction leakage.
- the present invention in the semiconductor device with a silicide film formed at the gate electrode and impurity diffusion layers, it is possible to suppress abnormal growth and coagulation of the silicide film of the impurity diffusion layers.
- FIG. 1 is a cross-sectional view showing a configuration for a semiconductor device of an embodiment of the present invention.
- FIGS. 2A to 2 C are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of the embodiment of the present invention.
- FIGS. 3A and 3B are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of the embodiment of the present invention.
- FIGS. 4A to 4 C are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of the embodiment of the present invention.
- FIGS. 5A to 5 C are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of a further embodiment of the present invention.
- FIGS. 6A to 6 C are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of another embodiment of the present invention.
- FIGS. 7A and 7B are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of the other embodiment of the present invention.
- FIGS. 8A to 8 C are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of the other embodiment of the present invention.
- FIG. 9 is a cross-sectional view showing a configuration for a semiconductor device of a still further embodiment of the present invention.
- FIGS. 10A to 10 C are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of the still further embodiment of the present invention.
- FIG. 11 is another cross-sectional view showing a configuration for a semiconductor device of the still further embodiment of the present invention.
- FIG. 1 is a cross-sectional view showing a configuration for a semiconductor device of this embodiment.
- semiconductor device 100 is a CMOS (Complementary Metal Oxide Semiconductor) device containing an N-type MOSFET 118 and a P-type MOSFET 120 . Further, this CMOS device constitutes the internal circuit of an LSI.
- CMOS Complementary Metal Oxide Semiconductor
- the semiconductor device 100 contains a silicon substrate 102 provided with a P-well 102 a of a P-type conductor and an N-well 102 b of an N-type conductor, and an element isolation region 104 for isolating the P-well 102 a and the N-well 102 b .
- the N-type MOSFET 118 and the P-type MOSFET 120 are formed at the P-well 102 a and the N-well 102 b , respectively.
- An inter-layer insulation film 134 covering the side of the N-type MOSFET 118 and the P-type MOSFET 120 is formed on the silicon substrate 102 .
- a pair of impurity diffusion layers 121 is provided at the P-well 102 a , with a channel region being formed between these impurity diffusion layers 121 .
- a gate semiconductor element constructed from a gate insulation film 106 , a gate electrode 132 provided on the gate insulation film 106 , and a sidewall insulation film 116 is provided on the channel region.
- a pair of impurity diffusion layers 122 is provided at the N-well 102 b , with a channel region being formed between these impurity diffusion layers 122 .
- a gate constructed from a gate insulation film 106 , a gate electrode 132 provided on the gate insulation film 106 , and a sidewall insulation film 116 is provided on the channel region.
- First silicide films 130 constituted of a silicide compound of a first metal is formed at the surfaces of the impurity diffusion layers 121 and the impurity diffusion layers 122 .
- the gate electrode 132 contains a second silicide film 131 composed of a silicide compound of a second metal, where the silicidation temperature of which is lower than that of the silicide compound of the first metal.
- the combination of the first metal and the second metal may be, in this order, nickel and palladium, cobalt and palladium, or cobalt and nickel.
- the silicidation temperature of the cobalt silicide compound (CoSi 2 ) is approximately 550 to 600 degrees centigrade
- the silicidation temperature of the nickel silicide compound (NiSi) is approximately 400 to 500 degrees centigrade
- the silicidation temperature of the palladium silicide compound (Pd 2 Si) is approximately 300 degrees centigrade (Kusano, Sano, or S. S. Lau et al.)
- the second silicide film 131 of the gate electrode 132 is formed in a step separate from this.
- the second silicide film 131 is made from the silicide compound of the second metal whose silicidation temperature is lower than that of the silicide compound of the first metal.
- the second silicide film 131 can therefore be formed at a lower temperature than the silicidation temperature of the silicide compound of the first metal of the first silicide film 130 . Because of this, it is possible to prevent abnormal growth and coagulation of the first silicide film 130 during formation of the second silicide film 131 of the gate electrode 132 after forming the first silicide film 130 .
- FIGS. 2A to 2 C, 3 A, 3 B, and 4 A to 4 C are cross-sectional views of processes showing a procedure for manufacturing the semiconductor device 100 of this embodiment.
- a P-well 102 a is formed by ion implantation of a P-type impurity
- an N-well 102 b is formed by ion implantation of an N-type impurity.
- the element isolation region 104 may also be formed using other well-known methods such as, for example, LOCOS techniques, etc.
- channel regions are formed at the P-well 102 a and the N-well 102 b using well-known technology.
- a punch-through stopper region may be formed by ion implantation of N-type impurity and P-type impurity below the channel regions of the P-well 102 a and the N-well 102 b , respectively. It is possible to suppress the short channel effect by forming this kind of punch-through stopper region.
- the gate insulation film 106 is formed on the surface of the silicon substrate 102 .
- the gate insulation film 106 may be formed, for example, from a silicon oxide film (of a film thickness of, for example, approximately 1 nm to 2 nm) formed by subjecting the surface of the silicon substrate 102 to thermal oxidation.
- a polysilicon film 114 (of a film thickness of, for example, approximately 5 nm to 15 nm) is formed on the gate insulation film 106 .
- a protective film 140 (of a film thickness of, for example, 3 nm to 10 nm) is formed on the polysilicon film 114 . Any configuration can be taken for the protective film 140 provided that the protective film 140 function as a hard mask preventing siliciding the polysilicon film 114 during siliciding of the impurity diffusion layers of the surface of the silicon substrate 102 in the subsequent step.
- the protective film 140 may be a silicon nitride film formed by, for example, CVD (Chemical vapor deposition). In this way, it is possible to obtain the structure shown in FIG. 2A .
- sidewall insulation films 116 are formed respectively at the sidewalls of the gate insulation film 106 , the polysilicon film 114 , and the protective film 140 .
- the sidewall insulation film 116 can be formed by, for example, anisotropic etching using fluorocarbon gas, etc.
- the surface layer of the P-well 102 a is doped with N-type impurity such as P and As etc. using the gate electrode and the sidewall insulation film 116 as a mask so as to form the impurity diffusion layers 121 .
- the surface layer of the N-well 102 b is doped with P-type impurity such as B and BF 2 etc. using the gate electrode and the sidewall insulation film 116 as a mask so as to form the impurity diffusion layers 122 .
- P-type impurity such as B and BF 2 etc.
- the gate electrode and the sidewall insulation film 116 as a mask so as to form the impurity diffusion layers 122 .
- the source region and the drain region are formed.
- activation of the impurities is carried out by performing heat treatment in a non-oxidation atmosphere ( FIG. 2C ).
- a first metal layer 142 (of a film thickness of, for example, 5 nm to 10 nm) is formed over the whole surface on the silicon substrate 102 ( FIG. 3A ) using sputtering techniques, etc.
- the first metal can be taken to be, for example, nickel.
- the first silicide film 130 (of a film thickness of, for example, 10 nm to 20 nm) is formed on the surface of the impurity diffusion layers 121 and the impurity diffusion layers 122 ( FIG. 3B ).
- the protective film 140 is provided on the polysilicon film 114 and a silicide layer is therefore not formed on the polysilicon film 114 .
- the inter-layer insulation film 134 is formed on the whole of the surface of the silicon substrate 102 so as to bury the protective film 140 ( FIG. 4A ).
- the inter-layer insulation film 134 can be taken to be, for example, a silicon oxide film.
- the inter-layer insulation film 134 may be a multi-layered film of a silicon nitride film formed on the silicon substrate 102 and a silicon oxide film formed thereon.
- the upper part of the inter-layer insulation film 134 and the protective film 140 are removed by CMP (chemical mechanical polishing) and the polysilicon film 114 is exposed ( FIG. 4B ).
- CMP chemical mechanical polishing
- a second metal layer 144 (of a film thickness of, for example, approximately 10 nm to 30 nm) is formed on the inter-layer insulation film 134 ( FIG. 4C ).
- the second metal can be taken to be, for example, palladium.
- the whole of the polysilicon film 114 is fully silicided by the second metal layer 144 and the gate electrode 132 is formed.
- fully silicided means a state where the whole of the gate electrode 132 is constituted by the second silicide film 131 .
- the gate insulation film 106 is directly in contact with the second silicide film 131 .
- the semiconductor device 100 of the configuration shown in FIG. 1 is formed as a result of the above procedure.
- the semiconductor device is formed in which the polysilicon film 114 is silicided in accordance with the second heat treatment condition above. Then, the cross section of the gate electrode 132 of the semiconductor device is observed by a TEM (Transmission Electron Microscope). As the result, it is confirmed that the polysilicon film 114 is fully silicided and silicon cannot be observed.
- TEM Transmission Electron Microscope
- the heat treatment during siliciding of the polysilicon film 114 is carried out at a temperature lower than the silicidation temperature of the first metal constituting the first silicide film 130 . Because of this, it is possible to prevent abnormal growth and coagulation of the first silicide film 130 . As a result, it is possible to prevent high resistance of the impurity diffusion layers 121 and impurity diffusion layers 122 of the semiconductor device 100 and increases in junction leakage. Moreover, as the gate 132 is fully silicided, it is possible to prevent the occurrence of depletion layers at the gate electrode 132 and prevent rising of the threshold voltage and variation in threshold voltages.
- first metal is nickel and the second metal is palladium but other examples such as the first metal of cobalt and the second metal of palladium, or the first metal of cobalt and the second metal of nickel, are also possible.
- the conditions for heat treatment in each case may be, for example, as shown in the following.
- the first heat treatment may be as shown in the following.
- the second heat treatment may be as shown in the following.
- the first heat treatment may be as shown in the following.
- the second heat treatment may be as shown in the following:
- the gate electrode 132 it is therefore possible to make the gate electrode 132 fully silicided without carrying out high-temperature heat treatment because the silicidation temperature of the second metal is low. Because of this, it is possible to prevent the occurrence of depletion layers at the gate electrode 132 and prevent rising of the threshold voltage and variation in threshold voltages.
- part of the procedure for manufacturing the semiconductor device 100 is different to the first embodiment.
- the following is a description with reference to FIGS. 5A to 5 C of a method for manufacturing a semiconductor device of this embodiment.
- FIGS. 5A to 5 C are cross-sectional views of processes showing part of a procedure for manufacturing the semiconductor device 100 of this embodiment.
- a structure that is the same as the structure shown in FIG. 3B is formed using the same procedure described with reference to FIGS. 2A to 2 C, 3 A and 3 B in the first embodiment.
- the protective film 140 is selectively removed by, for example, dry etching, and the polysilicon film 114 is exposed ( FIG. 5A ).
- the second metal layer 144 (of a film thickness of, for example, 5 nm to 10 nm) is formed over the whole surface on the silicon substrate 102 ( FIG. 5B ). After this, second heat treatment is carried out.
- the metal composing the second metal layer 144 and the conditions for the second heat treatment are the same as described for the first embodiment.
- the polysilicon film 114 is fully silicided by the second metal layer 144 and gate electrode 132 is formed.
- unconverted second metal layer 144 is then removed by wet etching, and the semiconductor device 100 of this embodiment is obtained ( FIG. 5C ).
- part of the procedure for manufacturing the semiconductor device 100 is different to the first embodiment.
- the following is a description with reference to FIGS. 6A to 6 C, 7 A, 7 B and 8 A to 8 C of a method for manufacturing a semiconductor device of this embodiment.
- FIGS. 6A to 6 C, 7 A, 7 B and 8 A to 8 C are cross-sectional views of processes showing part of a procedure for manufacturing the semiconductor device 100 of this embodiment.
- the element isolation region 104 , the P-well 102 a , and the N-well 102 b are formed on the silicon substrate 102 , and the gate insulation film 106 and the polysilicon film 114 are formed on the silicon substrate 102 ( FIG. 6A ).
- This embodiment differs from the first embodiment in that a protective film 140 is not formed on the polysilicon film 114 .
- the surface layer of the P-well 102 a is doped with N-type impurity such as P and As etc. using the gate electrode and the sidewall insulation film 116 as a mask so as to form the impurity diffusion layers 121 .
- the surface layer of the N-well 102 b is doped with P-type impurity such as B and BF 2 etc. using the gate electrode and the sidewall insulation film 116 as a mask so as to form the impurity diffusion layers 122 ( FIG. 6C ).
- a first metal layer 142 (of a film thickness of, for example, 5 nm to 10 nm) is formed over the whole surface on the silicon substrate 102 ( FIG. 7A ) using sputtering techniques, etc.
- the first heat treatment is then carried out.
- the first silicide film 130 is formed at the surface of the impurity diffusion layers 121 and the impurity diffusion layers 122
- a silicide film 146 (of a film thickness of, for example, 10 nm to 20 nm) is formed at the surface of the polysilicon film 114 ( FIG. 7B ).
- the inter-layer insulation film 134 is formed on the whole of the surface of the silicon substrate 102 so as to bury the silicide film 146 ( FIG. 8A ). After this, the upper part of the inter-layer insulation film 134 and the silicide film 146 are removed by CMP and the polysilicon film 114 is exposed ( FIG. 8B ). Next, a second metal layer 144 is formed on the inter-layer insulation film 134 . The second heat treatment is then carried out. In this embodiment, the metal constituting the first metal layer 142 , the first heat treatment conditions, the metal constituting the second metal layer 144 , and the second heat treatment conditions can be made the same as described for the first embodiment.
- the polysilicon film 114 is fully silicided by the second metal layer 144 and the gate electrode 132 is formed.
- the semiconductor device 100 of the same configuration as shown in FIG. 1 for the first embodiment can also be formed in this embodiment.
- This embodiment differs from the first embodiment in that the gate insulation film 106 is constituted from a multi-layered film.
- the following is a description with reference to FIG. 9 of a structure for the semiconductor device of this embodiment.
- FIG. 9 is across-sectional view showing a structure for the semiconductor device 100 of this embodiment.
- the gate insulation film 106 contains a multi-layered film of the silicon oxide film 105 and the high dielectric constant insulation film 108 stacked in this order.
- the high dielectric constant insulation film 108 is a film having a higher relative dielectric constant than the silicon oxide film 105 and may be a so-called “high-k film”.
- the high dielectric constant insulation film 108 may be constructed from a material of a relative dielectric constant of 10 or more.
- the high dielectric constant insulation film 108 may be made from a compound of one or two or more elements selected from a group of Hf and Zr and one or two or more elements selected from a group of Si, O and N.
- the high dielectric constant insulation film 108 may be composed of, for example, HfSiO or HfAlO, or a nitride thereof.
- the N-type MOSFEF 118 and the P-type MOSFET 120 can be composed of the same material as the high dielectric constant insulation film 108 or may be composed of different material.
- the gate insulation film 106 can be given a configuration that does not have the silicon oxide film 105 .
- metal included in the high dielectric constant insulation film 108 can be prevented from diffusing etc. to the silicon substrate 102 by providing the silicon oxide film 105 between the high dielectric constant insulation film 108 and the silicon substrate 102 .
- the silicon oxide film 105 may contain nitrogen.
- FIGS. 10A to 10 C are cross-sectional views of processes showing part of a procedure for manufacturing the semiconductor device 100 of this embodiment.
- the element isolation region 104 , the P-well 102 a and the N-well 102 b are formed on the silicon substrate 102 as described in the first embodiment.
- the silicon oxide film 105 is formed on the silicon substrate 102 .
- the high dielectric constant insulation film 108 (of a film thickness of, for example, approximately 1 nm) is formed on the silicon oxide film 105 .
- the high dielectric constant insulation film 108 may be formed using CVD techniques or ALD techniques (Atomic Layer Deposition techniques) etc.
- annealing is carried out using gas containing nitrogen such as, for example, ammonia, etc.
- a treatment temperature of 900 to 1000 degrees centigrade and a treatment time of 40 seconds etc. are adopted as conditions. It is then possible to suppress crystallization of the high dielectric constant insulation film 108 by carrying out this annealing.
- the polysilicon film 114 and the protective film 140 are formed on the high dielectric constant insulation film 108 ( FIG. 10A ).
- the silicon oxide film 105 , the high dielectric constant insulation film 108 , the polysilicon film 114 and the protective film 140 are selectively dry etched to form the gate shape ( FIG. 10B ).
- the first silicide film 130 is formed on the surface of the impurity diffusion layers 121 and the impurity diffusion layers 122 .
- the inter-layer insulation film 134 is formed on the silicon substrate 102 , and the polysilicon film 114 is exposed using CMP, the polysilicon film 114 is fully silicided by the second silicide film and the gate electrode 132 is formed.
- the semiconductor device 100 of the configuration shown in FIG. 9 is formed as a result.
- the protective film 140 is formed on the polysilicon film 114 and the first silicide film 130 is formed, it is possible to selectively remove the protective film 140 by etching.
- the semiconductor device 100 of the configuration shown in FIG. 11 is obtained as a result.
- the high dielectric constant insulation film 108 has a composition including Hr or Zr is shown but the high dielectric constant insulation film 108 is by no means limited in this respect, and configuration using various other well-known materials as so-called high-k films is also possible.
- an example is shown of the high dielectric constant insulation film 108 may be a film including Hf or Zr regardless of the relative dielectric constant thereof. Even the film that is not high-k film but includes Hf or Zr is used, an effect of resolving the depletion layer problem is obtained.
- the gate electrode 132 is shown to be fully silicided but the present invention is also applicable to configurations where the gate electrode 132 is not fully silicided.
- the second silicide film 131 is formed in a separate step to the step where the first silicide film 130 is formed and it is possible to form the second silicide film 131 at low temperature. It is therefore possible to make the film thickness of the second silicide film 131 the desired thickness. In this case also, it is also possible to suppress abnormal growth and coagulation of the impurity diffusion layers 121 formed before siliciding of the polysilicon film 114 and first silicide film 130 of the impurity diffusion layers 122 . As a result, it is possible to make the film thickness of the second silicide film 131 thick, and to make the resistance of the gate electrode 132 low.
- the polysilicon film 114 is not fully silicided, after forming the polysilicon film 114 , it is possible to ion-inject the polysilicon film 114 formed as a film on the P-well 102 a with N-type impurity, and ion-implant the polysilicon film 114 formed as a film on the N-well 102 b with P-type impurity.
- This ion implantation may be carried out after forming the polysilicon film 114 and before patterning into an electrode shape, or may be carried out at the same time during forming of the impurity diffusion layers 121 and the impurity diffusion layers 122 after patterning into an electrode shape. Further, it is also possible to carry out similar processing in the event of fully siliciding the polysilicon film 114 . However, in this case, the processing of ion implantation of the polysilicon film 114 with impurities can be omitted as well.
- siliciding is carried out by ramp annealing but is it also possible for one or both of the silicide compound of the first metal and the second metal silicide compound to be silicided by furnace annealing.
- the second metal silicide compound can be formed under temperature conditions lower than the silicidation temperature of the first siliciding compound.
Abstract
A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate and containing a gate electrode; impurity diffusion layers formed at both sides, in a cross-section in a gate length direction of the gate electrode, of a region on which the semiconductor element is formed of the semiconductor substrate; first silicide films formed respectively at the surface of the impurity diffusion layers, composed of a silicide compound of a first metal; and a second silicide film, formed at least at the surface of the gate electrode, composed of a silicide compound of a second metal different to the first metal. The silicide compound of the second metal has a silicidation temperature lower than the silicidation temperature of the silicide compound of the first metal.
Description
- This application is based on Japanese patent application NO. 2005-135188, the content of which is incorporated hereinto by reference.
- 1. Technical Field
- The present invention relates to a semiconductor device in which a silicide film is formed at a gate electrode and impurity diffusion layers and manufacturing method thereof.
- 2. Related Art
- Technology by which the surface of a gate electrode of a transistor constructed from polysilicon or the surface of an impurity diffusion layer constituting source region or drain region of a transistor is silicided for realizing low resistance of these regions is well-known. It is possible to make operation of a transistor high-speed by making components of the transistor low resistance.
- Conventionally, siliciding is carried out by forming a silicide film at the same time on the gate electrode surface and the impurity diffusion layer surface after forming a gate insulation film, gate electrode, sidewall insulation film and impurity diffusion layer of a transistor, by forming a metal layer on polysilicon of the gate electrode and on the impurity diffusion layer and subjecting this to heat treatment.
- However, the appropriate conditions for siliciding the gate electrode and the impurity diffusion layer are different. By then forming these at the same time, there may be problems with, for example, crystal defects and abnormal growth occurring at the impurity diffusion layer.
- The following method for manufacturing a semiconductor device is disclosed in Japanese Laid-open patent publication NO. 2004-273556. In the first siliciding, a silicide film is formed on a diffusion layer, and a dummy silicide film is formed on a gate. After depositing a first inter-layer insulation film, the first inter-layer insulation film and the dummy silicide film are removed by planarization using CMP to make the first inter-layer insulation film and a polysilicon electrode flat. After this, a Co film is deposited, heat treatment is performed, and a silicide film is formed through siliciding of the upper section of a polysilicon electrode. It is disclosed that in this way, it is possible to form a silicide film on the impurity diffusion layer and the silicide film on the upper part of the gate under different conditions, with appropriate adjustment of characteristics of the gate upper section silicide film and the silicide film on the diffusion layer.
- However, in the method described in Japanese Laid-open patent publication NO. 2004-273556, heat treatment at a high-temperature is carried out while forming the silicide film on the upper part of the gate. There are therefore problems such as abnormal growth of the silicide film formed at the impurity diffusion layer or the occurrence of coagulation that divides grains. Problems therefore occur such as the impurity diffusion layer being of high-resistance or of bonding leakage increasing, etc.
- According to the present invention, there is provided a semiconductor device including: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate and containing a gate electrode; impurity diffusion layers formed at both sides, in a cross-section in a gate length direction of the gate electrode, of a region on which the semiconductor element is formed of the semiconductor substrate; first silicide films formed respectively at the surface of the impurity diffusion layers, composed of a silicide compound of a first metal; and a second silicide film, formed at least at the surface of the gate electrode, composed of a silicide compound of a second metal different to the first metal, wherein the silicide compound of the second metal has a silicidation temperature lower than the silicidation temperature of the silicide compound of the first metal.
- The combination of the first metal and the second metal may be, in order, nickel and palladium, cobalt and palladium, or cobalt and nickel. The silicidation temperatures of the cobalt silicide compound (CoSi2), nickel silicide compound (NiSi), and palladium silicide compound (Pd2Si) are of high temperatures in this order (Kusano, “Semiconductor Encyclopedia”, Kogyo Chosakai Publishing, Dec. 20th, 1999, P 521; Sano, The 52nd Lecture of the Japan Society of Applied Physics, Lecture Proceedings (spring 2005), P 958; and S. S. Lau et al, Interactins in the Co/Si thin-film system. I. Kinetics, J. appl. Phys. 49(7), July 1978, pp 4005-4010.) In the event that the second metal is nickel, the silicide compound of the second metal can be composed taking NiSi as a main component. However, in this case also, the silicide compound of the second metal may contain NiSi2.
- In this way, the second silicide film of the gate electrode can be configured from a silicide compound of the second metal that is of a silicidation temperature that is lower than that of the silicide compound of the first metal. Therefore, for example, after forming a first silicide film on the surface of the impurity diffusion layers, in the event that the second silicide film is formed in a separate step, it is possible to form the second silicide film using a lower temperature. Because of this, it is possible to prevent abnormal growth and coagulation of the first silicide film during forming of the second silicide film of the gate electrode after forming the first silicide film. As a result, it is possible to prevent high resistance of the impurity diffusion layers of the semiconductor device and increases in junction leakage.
- According to the present invention, there is provided a semiconductor device including: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate and containing a gate electrode; impurity diffusion layers formed at both sides, in a cross-section in a gate length direction of the gate electrode, of a region on which the semiconductor element is formed of the semiconductor substrate; first silicide films formed respectively at the surface of the impurity diffusion layers, composed of a silicide compound of a first metal; and a second silicide film, formed at least at the surface of the gate electrode, composed of a silicide compound of a second metal different to the first metal, wherein the silicide compound of the second metal has a silicidation temperature lower than the silicidation temperature of the silicide compound of the first metal.
- By adopting this configuration, it is possible to form the second silicide film of the gate electrode at a lower temperature than the silicidation temperature of the silicide compound of the first metal. Because of this, it is possible to prevent abnormal growth and coagulation of the first silicide film during forming of the second silicide film of the gate electrode after forming the first silicide film. As a result, it is possible to prevent high resistance of the impurity diffusion layers of the semiconductor device and increases in junction leakage.
- With the semiconductor device of the present invention, it is possible for the whole of the gate electrode to be composed of the second silicide film. In the following, a state where the whole of the gate electrode is composed of the second silicide film is referred to as fully silicided. The semiconductor element may further include a gate insulation film formed between the semiconductor substrate and the gate electrode. As for the fully silicided gate electrode, the gate electrode can be composed of the second silicide film from the surface so as to span a surface making contact with the gate insulation film.
- According to the semiconductor device of the present invention, the second silicide film of the gate electrode can be configured from a silicide compound of the second metal that is of a silicidation temperature that is lower than that of the silicide compound of the first metal. It is therefore possible to perform siliciding of the gate electrode at a low temperature using the second metal. Because of this, it is possible to make the film thickness of the second silicide film the desired thickness without the occurrence of abnormal growth in the first silicide film at the impurity diffusion layer. As a result, it is possible for the gate electrode to be fully silicided without influencing the impurity diffusion layers.
- In the event of using a semiconductor material such as polysilicon as the gate electrode material, there are cases where a depletion layer occurs in the polysilicon of the gate electrode in the vicinity of the interface with the gate insulation film. When a depletion layer occurs, a sufficient electric field is not applied to the gate insulation film even if a gate voltage is applied, and it is difficult to induce carriers in the channel region. The effect of this is that the threshold voltage is raised and variation in threshold voltages is substantial. According to the present invention, the gate electrode is fully silicided, and the gate electrode does not contain semiconductor so that this kind of problem is therefore resolved.
- In the semiconductor device of the present invention, the semiconductor element further includes a gate insulation film containing a film formed between the semiconductor substrate and the gate electrode, containing Hr or Zr, and being in contact with the gate electrode.
- Here, the film containing Hf or Zr can be a high dielectric constant insulation film (high-k film). By using the high dielectric constant insulation film as the gate insulation film, it is possible to make Equivalent Oxide Thickness of the gate insulation film thin even if the physical thickness of the gate insulation film is made thick to a certain extent so as to bring about a physically and structurally stable gate insulation film. As a result, the current drive performance of the transistor can be improved and the gate leakage current can be reduced.
- However, according to recent research, in the event where the gate insulation film is composed of a high dielectric constant insulation film and the gate electrode is made of polysilicon, it is known that a phenomenon referred to as Fermi Level Pinning occurs (C. Hobbs et al, “Fermi Level Pinning at the PolySi/Metal Oxide Interface”, 2003 Symposium on VLSI Technology Digest of Technical Papers, 4-89114-035-6/03). Fermi level pinning can be considered to be where, in the vicinity of the interface of the side of the gate insulation film within the gate electrode, metal constituting a high dielectric constant insulation film diffuses to within the polysilicon constituting the gate electrode so that levels are formed based on bonds between the silicon and the metal. In particular, in the case of using a film containing Hf or Zr, Fermi level pinning is such that it is easy for a P-type MOSFET having a gate electrode composed of polysilicon containing P-type impurity to occur.
- Because of this, in the case where the gate insulation film is constructed of a film containing Hf or Zr, in the vicinity of the interface of the gate insulation film in the gate electrode, it is easy for the kind of depletion layer described above to be generated within the polysilicon. Conventionally, in the event of employing a high dielectric constant insulation film as a gate insulation film, the problems of increase in threshold voltage and variation in the threshold voltage are more prevalent than in the case of using silicon oxide film as the gate insulation film.
- However, according to the present invention, at the gate electrode, the second silicide film can be fully silicided and this kind of depletion layer problem can be resolved. As a result, the current drive performance of the transistor can be improved and the gate leakage current can be reduced. In the event that the film contains Hf or Zr and is not a high dielectric constant insulation film, the effect of resolving this depletion layer problem is obtained, and the present invention can be applied to cases where the film is not a high dielectric constant insulation film.
- According to the present invention, there is provided a method of manufacturing a semiconductor device, including: preparing a structure comprising a semiconductor element and impurity diffusion layers formed at both sides of a region on which the semiconductor element is formed of the semiconductor substrate, the semiconductor element including a gate electrode composed of polysilicon; forming first silicide films composed of a silicide compound of a first metal at the surface of the impurity diffusion layers; and forming a second silicide film composed of a silicide compound of a second metal different to the first metal at least at the surface of the polysilicon of the gate electrode, wherein, in the forming the second silicide film, the second silicide film is formed under lower temperature conditions than the temperature used in the forming the first silicide film.
- In this way, the second silicide film of the gate electrode is formed under temperature conditions that are lower than the forming of the first silicide film. Therefore, for example, in the event that the second silicide film is formed in a separate process after forming the first silicide film at the surface of the impurity diffusion layer, it is possible to form the second silicide film at a low temperature. Because of this, it is possible to prevent abnormal growth and coagulation of the first silicide film during forming of the second silicide film of the gate electrode after forming the first silicide film. As a result, it is possible to prevent high resistance of the impurity diffusion layers of the semiconductor device and increases in junction leakage.
- In the manufacturing method of the present invention, the forming the first silicide film may include: forming a film of the first metal on the entire surface of the semiconductor substrate in such a manner as to be in contact with the impurity diffusion layers; and siliciding the surface of the impurity diffusion layers by carrying out heat treatment under a first temperature condition. The forming the second silicide film may also include: forming a film of the second metal on the entire surface of the semiconductor substrate in such a manner as to be in contact with the polysilicon of the gate insulation film; and siliciding at least the surface of the polysilicon by carrying out heat treatment under a second temperature condition lower than the first temperature condition.
- In this way, in the forming of the second silicide film, by making the second temperature condition low, after forming the first silicide film it is possible to prevent abnormal growth and coagulation of the first silicide film during forming of the second silicide film of the gate electrode. As a result, it is possible to prevent high resistance of the impurity diffusion layers of the semiconductor device and increases in junction leakage.
- In the method of manufacturing a semiconductor device of the present invention, in the forming of the second silicide film, it is possible to make the second temperature condition a temperature condition lower than the silicidation temperature of the silicide compound of the first metal.
- In this way, by making the second temperature condition a lower temperature than the silicidation temperature of the silicide compound of the first metal, after forming the first silicide film, it is possible to prevent abnormal growth and coagulation of the first silicide film during forming of the second silicide film of the gate electrode. As a result, it is possible to prevent high resistance of the impurity diffusion layers of the semiconductor device and increases in junction leakage.
- According to the present invention, in the semiconductor device with a silicide film formed at the gate electrode and impurity diffusion layers, it is possible to suppress abnormal growth and coagulation of the silicide film of the impurity diffusion layers.
- The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a cross-sectional view showing a configuration for a semiconductor device of an embodiment of the present invention. -
FIGS. 2A to 2C are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of the embodiment of the present invention. -
FIGS. 3A and 3B are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of the embodiment of the present invention. -
FIGS. 4A to 4C are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of the embodiment of the present invention. -
FIGS. 5A to 5C are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of a further embodiment of the present invention. -
FIGS. 6A to 6C are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of another embodiment of the present invention. -
FIGS. 7A and 7B are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of the other embodiment of the present invention. -
FIGS. 8A to 8C are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of the other embodiment of the present invention. -
FIG. 9 is a cross-sectional view showing a configuration for a semiconductor device of a still further embodiment of the present invention. -
FIGS. 10A to 10C are cross-sectional views of steps showing a manufacturing procedure for a semiconductor device of the still further embodiment of the present invention. -
FIG. 11 is another cross-sectional view showing a configuration for a semiconductor device of the still further embodiment of the present invention. - The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed.
- The following is a description of a preferred embodiment of the present invention. The description is given using the drawings. In all of the drawings, the same elements of the configuration are given the same numerals and descriptions thereof are not repeated.
-
FIG. 1 is a cross-sectional view showing a configuration for a semiconductor device of this embodiment. In this embodiment,semiconductor device 100 is a CMOS (Complementary Metal Oxide Semiconductor) device containing an N-type MOSFET 118 and a P-type MOSFET 120. Further, this CMOS device constitutes the internal circuit of an LSI. - The
semiconductor device 100 contains asilicon substrate 102 provided with a P-well 102 a of a P-type conductor and an N-well 102 b of an N-type conductor, and anelement isolation region 104 for isolating the P-well 102 a and the N-well 102 b. The N-type MOSFET 118 and the P-type MOSFET 120 are formed at the P-well 102 a and the N-well 102 b, respectively. Aninter-layer insulation film 134 covering the side of the N-type MOSFET 118 and the P-type MOSFET 120 is formed on thesilicon substrate 102. - A pair of impurity diffusion layers 121 is provided at the P-well 102 a, with a channel region being formed between these impurity diffusion layers 121. A gate (semiconductor element) constructed from a
gate insulation film 106, agate electrode 132 provided on thegate insulation film 106, and asidewall insulation film 116 is provided on the channel region. Similarly, a pair of impurity diffusion layers 122 is provided at the N-well 102 b, with a channel region being formed between these impurity diffusion layers 122. A gate constructed from agate insulation film 106, agate electrode 132 provided on thegate insulation film 106, and asidewall insulation film 116 is provided on the channel region. -
First silicide films 130 constituted of a silicide compound of a first metal is formed at the surfaces of the impurity diffusion layers 121 and the impurity diffusion layers 122. In this embodiment, thegate electrode 132 contains asecond silicide film 131 composed of a silicide compound of a second metal, where the silicidation temperature of which is lower than that of the silicide compound of the first metal. Here, the combination of the first metal and the second metal may be, in this order, nickel and palladium, cobalt and palladium, or cobalt and nickel. The silicidation temperature of the cobalt silicide compound (CoSi2) is approximately 550 to 600 degrees centigrade, the silicidation temperature of the nickel silicide compound (NiSi) is approximately 400 to 500 degrees centigrade, and the silicidation temperature of the palladium silicide compound (Pd2Si) is approximately 300 degrees centigrade (Kusano, Sano, or S. S. Lau et al.) In this embodiment, as will be described in the following, after forming thefirst silicide film 130 on the impurity diffusion layers 121 and the impurity diffusion layers 122, thesecond silicide film 131 of thegate electrode 132 is formed in a step separate from this. Thesecond silicide film 131 is made from the silicide compound of the second metal whose silicidation temperature is lower than that of the silicide compound of the first metal. Thesecond silicide film 131 can therefore be formed at a lower temperature than the silicidation temperature of the silicide compound of the first metal of thefirst silicide film 130. Because of this, it is possible to prevent abnormal growth and coagulation of thefirst silicide film 130 during formation of thesecond silicide film 131 of thegate electrode 132 after forming thefirst silicide film 130. - The following is a description with reference to
FIGS. 2A to 2C, 3A, 3B, and 4A to 4C of a method for manufacturing the semiconductor device of this embodiment. -
FIGS. 2A to 2C, 3A, 3B, and 4A to 4C are cross-sectional views of processes showing a procedure for manufacturing thesemiconductor device 100 of this embodiment. - First, after forming the
element isolation region 104 at thesilicon substrate 102 using, for example, STI (Shallow Trench Isolation), a P-well 102 a is formed by ion implantation of a P-type impurity, and an N-well 102 b is formed by ion implantation of an N-type impurity. Theelement isolation region 104 may also be formed using other well-known methods such as, for example, LOCOS techniques, etc. Continuing on, channel regions are formed at the P-well 102 a and the N-well 102 b using well-known technology. A punch-through stopper region may be formed by ion implantation of N-type impurity and P-type impurity below the channel regions of the P-well 102 a and the N-well 102 b, respectively. It is possible to suppress the short channel effect by forming this kind of punch-through stopper region. - Next, the
gate insulation film 106 is formed on the surface of thesilicon substrate 102. Here, thegate insulation film 106 may be formed, for example, from a silicon oxide film (of a film thickness of, for example, approximately 1 nm to 2 nm) formed by subjecting the surface of thesilicon substrate 102 to thermal oxidation. - After this, a polysilicon film 114 (of a film thickness of, for example, approximately 5 nm to 15 nm) is formed on the
gate insulation film 106. Continuing on, a protective film 140 (of a film thickness of, for example, 3 nm to 10 nm) is formed on thepolysilicon film 114. Any configuration can be taken for theprotective film 140 provided that theprotective film 140 function as a hard mask preventing siliciding thepolysilicon film 114 during siliciding of the impurity diffusion layers of the surface of thesilicon substrate 102 in the subsequent step. Theprotective film 140 may be a silicon nitride film formed by, for example, CVD (Chemical vapor deposition). In this way, it is possible to obtain the structure shown inFIG. 2A . - Next, selective etching is performed to form the shape of the gate in such a manner that predetermined regions of the
gate insulation film 106, thepolysilicon film 114 and theprotective film 140 remain are left (FIG. 2B ). - After this, on the P-well 102 a and the N-well 102 b,
sidewall insulation films 116 are formed respectively at the sidewalls of thegate insulation film 106, thepolysilicon film 114, and theprotective film 140. Thesidewall insulation film 116 can be formed by, for example, anisotropic etching using fluorocarbon gas, etc. Continuing on, on the P-well 102 a, the surface layer of the P-well 102 a is doped with N-type impurity such as P and As etc. using the gate electrode and thesidewall insulation film 116 as a mask so as to form the impurity diffusion layers 121. Further, on the N-well 102 b, the surface layer of the N-well 102 b is doped with P-type impurity such as B and BF2 etc. using the gate electrode and thesidewall insulation film 116 as a mask so as to form the impurity diffusion layers 122. In this way, the source region and the drain region are formed. After this, activation of the impurities is carried out by performing heat treatment in a non-oxidation atmosphere (FIG. 2C ). - Next, a first metal layer 142 (of a film thickness of, for example, 5 nm to 10 nm) is formed over the whole surface on the silicon substrate 102 (
FIG. 3A ) using sputtering techniques, etc. Here, the first metal can be taken to be, for example, nickel. After this, the following first heat treatment (sintering) is carried out. - (a-1) Ramp annealing is carried out for approximately 30 seconds at a temperature of approximately 450 degrees centigrade.
- (a-2) Unconverted
first metal layer 142 is removed by wet etching. - From the above processing, the first silicide film 130 (of a film thickness of, for example, 10 nm to 20 nm) is formed on the surface of the impurity diffusion layers 121 and the impurity diffusion layers 122 (
FIG. 3B ). At this time, theprotective film 140 is provided on thepolysilicon film 114 and a silicide layer is therefore not formed on thepolysilicon film 114. - To continue, the
inter-layer insulation film 134 is formed on the whole of the surface of thesilicon substrate 102 so as to bury the protective film 140 (FIG. 4A ). Here, theinter-layer insulation film 134 can be taken to be, for example, a silicon oxide film. Alternatively, theinter-layer insulation film 134 may be a multi-layered film of a silicon nitride film formed on thesilicon substrate 102 and a silicon oxide film formed thereon. - Next, the upper part of the
inter-layer insulation film 134 and theprotective film 140 are removed by CMP (chemical mechanical polishing) and thepolysilicon film 114 is exposed (FIG. 4B ). After this, a second metal layer 144 (of a film thickness of, for example, approximately 10 nm to 30 nm) is formed on the inter-layer insulation film 134 (FIG. 4C ). Here, the second metal can be taken to be, for example, palladium. After this, the following second heat treatment (sintering) is carried out. - (b-1) Ramp annealing is carried out for approximately ten minutes at a temperature of approximately 300 degrees centigrade.
- (b-2) Unconverted
second metal layer 144 is removed by wet etching. - In the above processing, the whole of the
polysilicon film 114 is fully silicided by thesecond metal layer 144 and thegate electrode 132 is formed. Here, fully silicided means a state where the whole of thegate electrode 132 is constituted by thesecond silicide film 131. Namely, this means that thepolysilicon film 114 is substantially 100% silicided, and the silicon cannot be observed. Here, thegate insulation film 106 is directly in contact with thesecond silicide film 131. Thesemiconductor device 100 of the configuration shown inFIG. 1 is formed as a result of the above procedure. - The semiconductor device is formed in which the
polysilicon film 114 is silicided in accordance with the second heat treatment condition above. Then, the cross section of thegate electrode 132 of the semiconductor device is observed by a TEM (Transmission Electron Microscope). As the result, it is confirmed that thepolysilicon film 114 is fully silicided and silicon cannot be observed. - According to the method of manufacturing the
semiconductor device 100 of this embodiment, after forming thefirst silicide film 130, the heat treatment during siliciding of thepolysilicon film 114 is carried out at a temperature lower than the silicidation temperature of the first metal constituting thefirst silicide film 130. Because of this, it is possible to prevent abnormal growth and coagulation of thefirst silicide film 130. As a result, it is possible to prevent high resistance of the impurity diffusion layers 121 and impurity diffusion layers 122 of thesemiconductor device 100 and increases in junction leakage. Moreover, as thegate 132 is fully silicided, it is possible to prevent the occurrence of depletion layers at thegate electrode 132 and prevent rising of the threshold voltage and variation in threshold voltages. - In the above example, an example is shown where the first metal is nickel and the second metal is palladium but other examples such as the first metal of cobalt and the second metal of palladium, or the first metal of cobalt and the second metal of nickel, are also possible. The conditions for heat treatment in each case may be, for example, as shown in the following.
- (i) In the case where the first metal is cobalt and the second metal is palladium:
- The first heat treatment may be as shown in the following.
- (a-1) Ramp annealing is carried out for approximately 30 seconds at a temperature of approximately 600 degrees centigrade;
- (a-2) Unconverted
first metal layer 142 is removed by wet etching. - The second heat treatment may be as shown in the following.
- (b-1) Ramp annealing is carried out for approximately ten minutes at a temperature of approximately 300 degrees centigrade.
- (b-2) Unconverted
second metal layer 144 is removed by wet etching. - (ii) In the case where the first metal is cobalt and the second metal is nickel:
- The first heat treatment may be as shown in the following.
- (a-1) Ramp annealing is carried out for approximately 30 seconds at a temperature of approximately 600 degrees centigrade.
- (a-2) Unconverted
first metal layer 142 is removed by wet etching. - The second heat treatment may be as shown in the following:
- (b-1) Ramp annealing is carried out for approximately 60 seconds at a temperature of approximately 450 degrees centigrade.
- (b-2) Unconverted
second metal layer 144 is removed by wet etching. - In the above, by using a metal of a silicidation temperature that is lower than the silicidation temperature of the first metal constituting the
first silicide film 130 as the second metal constituting thegate electrode 132, it is possible to make the heat treatment temperature during siliciding of thegate electrode 132 lower. As a result, it is possible to suppress abnormal growth and coagulation of the previously formedfirst silicide film 130 at the impurity diffusion layers 121 and the impurity diffusion layers 122. It is therefore possible to prevent high resistance of the impurity diffusion layers 121 and the impurity diffusion layers 122 of thesemiconductor device 100 and increases in junction leakage. Moreover, it is therefore possible to make thegate electrode 132 fully silicided without carrying out high-temperature heat treatment because the silicidation temperature of the second metal is low. Because of this, it is possible to prevent the occurrence of depletion layers at thegate electrode 132 and prevent rising of the threshold voltage and variation in threshold voltages. - In this embodiment, part of the procedure for manufacturing the
semiconductor device 100 is different to the first embodiment. The following is a description with reference toFIGS. 5A to 5C of a method for manufacturing a semiconductor device of this embodiment.FIGS. 5A to 5C are cross-sectional views of processes showing part of a procedure for manufacturing thesemiconductor device 100 of this embodiment. - In this embodiment also, a structure that is the same as the structure shown in
FIG. 3B is formed using the same procedure described with reference toFIGS. 2A to 2C, 3A and 3B in the first embodiment. Theprotective film 140 is selectively removed by, for example, dry etching, and thepolysilicon film 114 is exposed (FIG. 5A ). - Next, the second metal layer 144 (of a film thickness of, for example, 5 nm to 10 nm) is formed over the whole surface on the silicon substrate 102 (
FIG. 5B ). After this, second heat treatment is carried out. The metal composing thesecond metal layer 144 and the conditions for the second heat treatment are the same as described for the first embodiment. - In the above processing, the
polysilicon film 114 is fully silicided by thesecond metal layer 144 andgate electrode 132 is formed. Continuing on, unconvertedsecond metal layer 144 is then removed by wet etching, and thesemiconductor device 100 of this embodiment is obtained (FIG. 5C ). - In this embodiment, it is possible to obtain the same effects as for the first embodiment. This makes it possible to simplify the manufacturing process for the
semiconductor device 100. - In this embodiment, part of the procedure for manufacturing the
semiconductor device 100 is different to the first embodiment. The following is a description with reference toFIGS. 6A to 6C, 7A, 7B and 8A to 8C of a method for manufacturing a semiconductor device of this embodiment.FIGS. 6A to 6C, 7A, 7B and 8A to 8C are cross-sectional views of processes showing part of a procedure for manufacturing thesemiconductor device 100 of this embodiment. - First, as described in the first embodiment, the
element isolation region 104, the P-well 102 a, and the N-well 102 b are formed on thesilicon substrate 102, and thegate insulation film 106 and thepolysilicon film 114 are formed on the silicon substrate 102 (FIG. 6A ). This embodiment differs from the first embodiment in that aprotective film 140 is not formed on thepolysilicon film 114. - Next, selective etching is performed to form the gate shape in such a manner that predetermined regions of the
gate insulation film 106 and thepolysilicon film 114 are left (FIG. 6B ). - Next, on the P-well 102 a and the N-well 102 b, sidewall insulation films are formed respectively at the sidewalls of the
gate insulation film 106 and thepolysilicon film 114. After this, on the P-well 102 a, the surface layer of the P-well 102 a is doped with N-type impurity such as P and As etc. using the gate electrode and thesidewall insulation film 116 as a mask so as to form the impurity diffusion layers 121. Further, on the N-well 102 b, the surface layer of the N-well 102 b is doped with P-type impurity such as B and BF2 etc. using the gate electrode and thesidewall insulation film 116 as a mask so as to form the impurity diffusion layers 122 (FIG. 6C ). - Next, a first metal layer 142 (of a film thickness of, for example, 5 nm to 10 nm) is formed over the whole surface on the silicon substrate 102 (
FIG. 7A ) using sputtering techniques, etc. The first heat treatment is then carried out. As a result, thefirst silicide film 130 is formed at the surface of the impurity diffusion layers 121 and the impurity diffusion layers 122, and a silicide film 146 (of a film thickness of, for example, 10 nm to 20 nm) is formed at the surface of the polysilicon film 114 (FIG. 7B ). - Next, the
inter-layer insulation film 134 is formed on the whole of the surface of thesilicon substrate 102 so as to bury the silicide film 146 (FIG. 8A ). After this, the upper part of theinter-layer insulation film 134 and thesilicide film 146 are removed by CMP and thepolysilicon film 114 is exposed (FIG. 8B ). Next, asecond metal layer 144 is formed on theinter-layer insulation film 134. The second heat treatment is then carried out. In this embodiment, the metal constituting thefirst metal layer 142, the first heat treatment conditions, the metal constituting thesecond metal layer 144, and the second heat treatment conditions can be made the same as described for the first embodiment. - In the above processing, the
polysilicon film 114 is fully silicided by thesecond metal layer 144 and thegate electrode 132 is formed. As a result, thesemiconductor device 100 of the same configuration as shown inFIG. 1 for the first embodiment can also be formed in this embodiment. - In this embodiment, it is possible to obtain the same effects as for the first embodiment. This makes it possible to simplify the manufacturing process for the
semiconductor device 100. - This embodiment differs from the first embodiment in that the
gate insulation film 106 is constituted from a multi-layered film. The following is a description with reference toFIG. 9 of a structure for the semiconductor device of this embodiment.FIG. 9 is across-sectional view showing a structure for thesemiconductor device 100 of this embodiment. In this embodiment also, thegate insulation film 106 contains a multi-layered film of thesilicon oxide film 105 and the high dielectricconstant insulation film 108 stacked in this order. - The high dielectric
constant insulation film 108 is a film having a higher relative dielectric constant than thesilicon oxide film 105 and may be a so-called “high-k film”. For example, the high dielectricconstant insulation film 108 may be constructed from a material of a relative dielectric constant of 10 or more. Specifically, the high dielectricconstant insulation film 108 may be made from a compound of one or two or more elements selected from a group of Hf and Zr and one or two or more elements selected from a group of Si, O and N. The high dielectricconstant insulation film 108 may be composed of, for example, HfSiO or HfAlO, or a nitride thereof. By using this kind of material, it is possible to make the relative dielectric constant of the high dielectricconstant insulation film 108 high and to bring about superior heat resistance. Because of this, the size of the MOSFET can be reduced and reliability can be improved. The N-type MOSFEF 118 and the P-type MOSFET 120 can be composed of the same material as the high dielectricconstant insulation film 108 or may be composed of different material. - The
gate insulation film 106 can be given a configuration that does not have thesilicon oxide film 105. However, metal included in the high dielectricconstant insulation film 108 can be prevented from diffusing etc. to thesilicon substrate 102 by providing thesilicon oxide film 105 between the high dielectricconstant insulation film 108 and thesilicon substrate 102. Further, thesilicon oxide film 105 may contain nitrogen. - The following is a description with reference to
FIG. 10 of a method for manufacturing a semiconductor device of this embodiment.FIGS. 10A to 10C are cross-sectional views of processes showing part of a procedure for manufacturing thesemiconductor device 100 of this embodiment. - In this embodiment, first, as described in the first embodiment, the
element isolation region 104, the P-well 102 a and the N-well 102 b are formed on thesilicon substrate 102 as described in the first embodiment. Next, thesilicon oxide film 105 is formed on thesilicon substrate 102. Continuing on, the high dielectric constant insulation film 108 (of a film thickness of, for example, approximately 1 nm) is formed on thesilicon oxide film 105. The high dielectricconstant insulation film 108 may be formed using CVD techniques or ALD techniques (Atomic Layer Deposition techniques) etc. After this, annealing is carried out using gas containing nitrogen such as, for example, ammonia, etc. A treatment temperature of 900 to 1000 degrees centigrade and a treatment time of 40 seconds etc. are adopted as conditions. It is then possible to suppress crystallization of the high dielectricconstant insulation film 108 by carrying out this annealing. - Continuing on, the
polysilicon film 114 and theprotective film 140 are formed on the high dielectric constant insulation film 108 (FIG. 10A ). - Next, the
silicon oxide film 105, the high dielectricconstant insulation film 108, thepolysilicon film 114 and theprotective film 140 are selectively dry etched to form the gate shape (FIG. 10B ). - Next, on the P-well 102 a and the N-well 102 b, sidewall insulation films are formed respectively at the sidewalls of the
silicon oxide film 105, the high dielectricconstant insulation film 108, thepolysilicon film 114, and theprotective film 140. After this, the impurity diffusion layers 121 are formed on the P-well 102 a and the impurity diffusion layers 122 are formed on the N-well 102 b (FIG. 10C ). - After this, as described for the first embodiment, the
first silicide film 130 is formed on the surface of the impurity diffusion layers 121 and the impurity diffusion layers 122. Next, after theinter-layer insulation film 134 is formed on thesilicon substrate 102, and thepolysilicon film 114 is exposed using CMP, thepolysilicon film 114 is fully silicided by the second silicide film and thegate electrode 132 is formed. Thesemiconductor device 100 of the configuration shown inFIG. 9 is formed as a result. - In this embodiment, it is possible to obtain the same effects as for the first embodiment. Further, as described above, in the event of using the high dielectric
constant insulation film 108 as thegate insulation film 106, a so-called “Fermi level pinning” phenomenon occurs, and in the event that thegate electrode 132 is configured usingpolysilicon film 114, a problem occurs where a depletion layer occurs at thepolysilicon film 114. However, in this embodiment, thegate electrode 132 is fully silicided. It is therefore possible to prevent the occurrence of a depletion layer at thegate electrode 132, and it is possible to obtain the benefits of improved current drive performance of the transistor and reduced leakage current as a result of using the high dielectricconstant insulation film 108. - In this embodiment also, as described for the third embodiment, it is possible to remove the
silicide film 146 afterwards when the process in which theprotective film 140 is not formed on thepolysilicon film 114 and thesilicide film 146 is formed on the surface of thepolysilicon film 114 during forming of thefirst silicide film 130 is used. It is therefore also possible to obtain thesemiconductor device 100 of the same configuration as shown inFIG. 9 . - In this embodiment, as described for the second embodiment, after the
protective film 140 is formed on thepolysilicon film 114 and thefirst silicide film 130 is formed, it is possible to selectively remove theprotective film 140 by etching. Thesemiconductor device 100 of the configuration shown inFIG. 11 is obtained as a result. - In the above, a description is given of embodiments and practical examples of the present invention with reference to the drawings but this merely illustrates examples of the present invention, and various other configurations can also be adopted.
- For example, in the fourth embodiment, a configuration where the high dielectric
constant insulation film 108 has a composition including Hr or Zr is shown but the high dielectricconstant insulation film 108 is by no means limited in this respect, and configuration using various other well-known materials as so-called high-k films is also possible. Further, in this embodiment, an example is shown of the high dielectricconstant insulation film 108 may be a film including Hf or Zr regardless of the relative dielectric constant thereof. Even the film that is not high-k film but includes Hf or Zr is used, an effect of resolving the depletion layer problem is obtained. - Further, in the above embodiments, the
gate electrode 132 is shown to be fully silicided but the present invention is also applicable to configurations where thegate electrode 132 is not fully silicided. According to the present invention, thesecond silicide film 131 is formed in a separate step to the step where thefirst silicide film 130 is formed and it is possible to form thesecond silicide film 131 at low temperature. It is therefore possible to make the film thickness of thesecond silicide film 131 the desired thickness. In this case also, it is also possible to suppress abnormal growth and coagulation of the impurity diffusion layers 121 formed before siliciding of thepolysilicon film 114 andfirst silicide film 130 of the impurity diffusion layers 122. As a result, it is possible to make the film thickness of thesecond silicide film 131 thick, and to make the resistance of thegate electrode 132 low. - In the event that the
polysilicon film 114 is not fully silicided, after forming thepolysilicon film 114, it is possible to ion-inject thepolysilicon film 114 formed as a film on the P-well 102 a with N-type impurity, and ion-implant thepolysilicon film 114 formed as a film on the N-well 102 b with P-type impurity. This ion implantation may be carried out after forming thepolysilicon film 114 and before patterning into an electrode shape, or may be carried out at the same time during forming of the impurity diffusion layers 121 and the impurity diffusion layers 122 after patterning into an electrode shape. Further, it is also possible to carry out similar processing in the event of fully siliciding thepolysilicon film 114. However, in this case, the processing of ion implantation of thepolysilicon film 114 with impurities can be omitted as well. - Moreover, in the above embodiment, an example is shown where siliciding is carried out by ramp annealing but is it also possible for one or both of the silicide compound of the first metal and the second metal silicide compound to be silicided by furnace annealing. In this event, the second metal silicide compound can be formed under temperature conditions lower than the silicidation temperature of the first siliciding compound.
- It is apparent that the present invention is not limited to the above embodiment, and may be modified and changed without departing from the scope and spirit of the invention.
Claims (19)
1. A semiconductor device comprising:
a semiconductor substrate;
a semiconductor element formed on said semiconductor substrate and containing a gate electrode;
impurity diffusion layers formed at both sides, in a cross-section in a gate length direction of said gate electrode, of a region on which said semiconductor element is formed of said semiconductor substrate;
first silicide films formed respectively at the surface of said impurity diffusion layers, composed of a silicide compound of a first metal; and
a second silicide film, formed at least at the surface of said gate electrode, composed of a silicide compound of a second metal different to said first metal,
wherein said silicide compound of said second metal has a silicidation temperature lower than the silicidation temperature of said silicide compound of said first metal.
2. The semiconductor device according to claim 1 ,
wherein the combination of said first metal and said second metal is, in order, nickel and palladium, cobalt and palladium, or cobalt and nickel.
3. The semiconductor device according to claim 1 ,
wherein the whole of said gate electrode is constituted by said second silicide film.
4. The semiconductor device according to claim 2 ,
wherein the whole of said gate electrode is constituted by said second silicide film.
5. The semiconductor device according to claim 1 ,
wherein said semiconductor element further includes a gate insulation film formed between said semiconductor substrate and said gate electrode,
wherein said gate insulation film includes a film, containing Hf or Zr, provided so as to be connected to said gate electrode.
6. The semiconductor device according to claim 2 ,
wherein said semiconductor element further includes a gate insulation film formed between said semiconductor substrate and said gate electrode,
wherein said gate insulation film includes a film, containing Hf or Zr, provided so as to be connected to said gate electrode.
7. The semiconductor device according to claim 3 ,
wherein said semiconductor element further includes a gate insulation film formed between said semiconductor substrate and said gate electrode,
wherein said gate insulation film includes a film, containing Hf or Zr, provided so as to be connected to said gate electrode.
8. A semiconductor device comprising:
a semiconductor substrate;
a semiconductor element formed on said semiconductor substrate and containing a gate electrode;
impurity diffusion layers formed at both sides, in a cross-section in a gate length direction of said gate electrode, of a region on which said semiconductor element is formed of said semiconductor substrate;
first silicide films formed respectively at the surface of said impurity diffusion layers, composed of a silicide compound of a first metal; and
a second silicide film, formed at least at the surface of said gate electrode, composed of a silicide compound of a second metal different to said first metal,
wherein said silicide compound of said second metal has a silicidation temperature lower than the silicidation temperature of said silicide compound of said first metal.
wherein the combination of said first metal and said second metal is, in order, nickel and palladium, cobalt and palladium, or cobalt and nickel.
9. The semiconductor device according to claim 8 ,
wherein the whole of said gate electrode is constituted by said second silicide film.
10. The semiconductor device according to claim 8 ,
wherein said semiconductor element further includes a gate insulation film formed between said semiconductor substrate and said gate electrode,
wherein said gate insulation film includes a film, containing Hf or Zr, provided so as to be connected to said gate electrode.
11. A method of manufacturing a semiconductor device, comprising:
preparing a structure comprising a semiconductor element and impurity diffusion layers formed at both sides of a region on which said semiconductor element is formed of said semiconductor substrate, said semiconductor element including a gate electrode composed of polysilicon;
forming first silicide films composed of a silicide compound of a first metal at the surface of said impurity diffusion layers; and
forming a second silicide film composed of a silicide compound of a second metal different to said first metal at least at the surface of said polysilicon of said gate electrode,
wherein, in said forming the second silicide film, said second silicide film is formed under lower temperature conditions than the temperature used in said forming the first silicide film.
12. The method of manufacturing a semiconductor device according to claim 11 ,
wherein said forming the first silicide film comprises:
forming a film of said first metal on the entire surface of said semiconductor substrate in such a manner as to be in contact with said impurity diffusion layers; and
siliciding the surface of said impurity diffusion layers by carrying out heat treatment under a first temperature condition, and
wherein said forming the second silicide film comprises:
forming a film of said second metal on the entire surface of said semiconductor substrate in such a manner as to be in contact with said polysilicon of said gate insulation film; and
siliciding at least the surface of said polysilicon by carrying out heat treatment under a second temperature condition lower than said first temperature condition.
13. The method of manufacturing a semiconductor device according to claim 12 ,
wherein, in said forming the second silicide film, said second temperature condition is a temperature condition lower than the silicidation temperature of said silicide compound of said first metal.
14. The method of manufacturing a semiconductor device according to claim 12 ,
wherein, in said forming the second silicide film, the whole of said polysilicon film is changed to said second silicide film.
15. The method of manufacturing a semiconductor device according to claim 13 ,
wherein, in said forming the second silicide film, the whole of said polysilicon film is changed to said second silicide film.
16. The method of manufacturing a semiconductor device according to claim 12 , further comprising:
forming a protective film at the surface of said gate electrode before said forming the first silicide film; and
removing said protective film so as to expose said polysilicon of said gate electrode after said forming the first silicide film and before said forming the second silicide film.
17. The method of manufacturing a semiconductor device according to claim 14 , further comprising:
forming a protective film at the surface of said gate electrode before said forming the first silicide film; and
removing said protective film so as to expose said polysilicon of said gate electrode after said forming the first silicide film and before said forming the second silicide film.
18. The method of manufacturing a semiconductor device according to claim 16 ,
further comprising, before said forming the second silicide film,
forming an inter-layer insulation film at the whole of the surface of said semiconductor substrate in such a manner as to bury said protective film,
wherein said removing the protective film, said inter-layer insulation film and said protective film are removed by planarization to expose said polysilicon of said gate electrode.
19. The method of manufacturing a semiconductor device according to claim 17 ,
further comprising, before said forming the second silicide film,
forming an inter-layer insulation film at the whole of the surface of said semiconductor substrate in such a manner as to bury said protective film,
wherein said removing the protective film, said inter-layer insulation film and said protective film are removed by planarization to expose said polysilicon of said gate electrode.
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070049015A1 (en) * | 2005-09-01 | 2007-03-01 | Hasan Nejad | Silicided recessed silicon |
US20080085576A1 (en) * | 2006-07-21 | 2008-04-10 | Lee Han C | Manufacturing Method for Semiconductor Device |
US7687342B2 (en) | 2005-09-01 | 2010-03-30 | Micron Technology, Inc. | Method of manufacturing a memory device |
US7696567B2 (en) | 2005-08-31 | 2010-04-13 | Micron Technology, Inc | Semiconductor memory device |
US7768051B2 (en) | 2005-07-25 | 2010-08-03 | Micron Technology, Inc. | DRAM including a vertical surround gate transistor |
US7888721B2 (en) | 2005-07-06 | 2011-02-15 | Micron Technology, Inc. | Surround gate access transistors with grown ultra-thin bodies |
US7939409B2 (en) | 2005-09-01 | 2011-05-10 | Micron Technology, Inc. | Peripheral gate stacks and recessed array gates |
US20140299889A1 (en) * | 2013-04-08 | 2014-10-09 | Samsung Electronics Co., Ltd. | Semiconductor devices |
US10515801B2 (en) | 2007-06-04 | 2019-12-24 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7482270B2 (en) * | 2006-12-05 | 2009-01-27 | International Business Machines Corporation | Fully and uniformly silicided gate structure and method for forming same |
CN102779851B (en) * | 2012-07-06 | 2015-01-07 | 北京大学深圳研究生院 | Transistor free of junction field effect |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020019127A1 (en) * | 1997-02-14 | 2002-02-14 | Micron Technology, Inc. | Interconnect structure and method of making |
US6514859B1 (en) * | 2000-12-08 | 2003-02-04 | Advanced Micro Devices, Inc. | Method of salicide formation with a double gate silicide |
US6620718B1 (en) * | 2000-04-25 | 2003-09-16 | Advanced Micro Devices, Inc. | Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device |
US6767814B2 (en) * | 2001-03-19 | 2004-07-27 | Samsung Electronics Co., Ltd. | Semiconductor device having silicide thin film and method of forming the same |
US20050042831A1 (en) * | 2003-08-19 | 2005-02-24 | Manoj Mehrotra | Dual salicide process for optimum performance |
US20050070062A1 (en) * | 2003-09-30 | 2005-03-31 | Mark Visokay | MOS transistor gates with doped silicide and methods for making the same |
-
2005
- 2005-05-06 JP JP2005135188A patent/JP2006313784A/en active Pending
-
2006
- 2006-05-03 US US11/416,209 patent/US20060252264A1/en not_active Abandoned
- 2006-05-08 CN CNA2006100794660A patent/CN1858913A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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JP2006313784A (en) | 2006-11-16 |
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