US20060253808A1 - Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same - Google Patents
Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same Download PDFInfo
- Publication number
- US20060253808A1 US20060253808A1 US11/421,035 US42103506A US2006253808A1 US 20060253808 A1 US20060253808 A1 US 20060253808A1 US 42103506 A US42103506 A US 42103506A US 2006253808 A1 US2006253808 A1 US 2006253808A1
- Authority
- US
- United States
- Prior art keywords
- circuit
- logic
- library
- circuits
- domino
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Definitions
- This invention relates to improvements in circuit design methods, and more particularly to improvements in domino circuit design methods, and still more particularly to circuit libraries for use in performing such methods.
- domino logic circuits typically have an NMOS, or pull-down, logic portion, although PMOS pull-up logic circuits have been used in many applications.
- the logic portion serves to evaluate input logic signals to provide a conditional output signal to an output inverter.
- Domino logic circuits also have a precharge transistor, typically a PMOS device when the logic circuit is made up with NMOS transistors, which is switched by the clock signal to connect the “dynamic node” of the circuit to a precharge voltage during a “precharge phase” of the clock cycle.
- the “dynamic node” may be for example, the output node of the logic circuit or the input node of the associated output inverter.
- the output inverter transistors are precharged during the precharge phase, while the clock signal is in a first state, low, for example, in an NMOS logic circuit implementation, or high in a PMOS logic circuit implementation.
- an “evaluate” transistor whose gate is also connected to the clock signal, isolates the associated logic circuit from the precharge voltage.
- the output node of the logic circuit (the input of the inverter) is pulled down and the output of the inverter is pulled up. If the logic conditions of the logic circuit are not met, the output of the inverter remains low. Because the inverter is precharged when the clock signal transitions from low to high, the cell output can be developed very rapidly.
- layout templates have been proposed into which the various domino circuit components can be placed in order to facilitate interconnection of a number of gates in a particular circuit.
- the arrangement of the various circuit parts in fixed layout regions provides a “standard cell”, connectable to similar adjacent regions.
- a layout template is suggested for a domino logic circuit of the type having an n-FET logic tree.
- the n-FET logic tree is inserted into a first portion of the template.
- the output from the logic circuit is inverted in an output inverter, and latched by a p-FET device connected around the inverter.
- the p-FET portions of the inverter, a p-FET precharge transistor, and the p-FET latch transistor are inserted in predefined second template locations.
- the clock also includes an n-FET evaluate transistor, which is inserted into a third template area.
- the fixed layout template has not been concerned with the parametric characteristics of the ultimate cells, only the standardization of the layout template into which they are constructed to enable standardization of cell interconnections.
- An advantage of the invention is that sets of matchable circuits, namely, logic and drive circuits, can be selected to develop a library of circuits for a particular application.
- matchable By “matchable”, “match”, “matching”, or “matched” it is meant herein that the size, speed, capacitance, or other parametric characteristic of the circuits can be appropriately interconnected for a desired result. The term is not intended to imply that the parametric characteristics of the logic and drive circuits are necessarily the same, or even substantially the same.
- Another advantage of the invention is that a library of domino circuits can be quickly developed, constructed, and completed.
- layout templates may be used, they are not essential.
- the various sizes of the final circuits, which may constitute a library of “standard cells”, may be fixed or variable, depending upon the particular uses to which the library that is developed is to be used. In some cases, however, the boundary locations of the circuits may be established to readily accommodate interconnection of various circuits that may result from the use of the circuit libraries defined by the invention.
- a set, family, or library of logic circuits is provided from which a desired logic function can be constructed.
- the transistors in the set have different sizes, speeds, capacitances, loading characteristics, or other parametric characteristics.
- Each circuit has an associated evaluate or “footer” transistor that is selected with the selection of the circuit.
- a set, family, or library of driver circuits is provided so that a driver can be selected to match the characteristics of the selected n-logic circuit, for example, in respect to sizes, speeds, capacitances, loading characteristics, or other parametric characteristics.
- a standard PMOS precharge transistor may be constructed, depending upon the characteristics of the circuit components selected from the libraries.
- a cell library for use in designing integrated domino circuits.
- the cell library includes a first library portion including a plurality of FET logic circuits of first conductivity type to provide at least selectable transistor sizes.
- a second library portion includes a plurality of selectable prechargeable complementary FET driver circuits. Each of the driver circuits is configured to be connectable to an output of a selected one of the logic circuits, to provide selectable logic functions, transistor sizes, or other parametric characteristic.
- a cell library for use in designing integrated circuits.
- the cell library includes a first library portion containing a plurality of NMOS logic circuits to provide selectable logic functions and transistor sizes.
- a second library portion contains a plurality of selectable driver circuits, each configured to be connectable to an output of a selected one of the logic circuits.
- the driver circuits are selectable to match at least a size characteristic of the selected one of the logic circuits.
- a cell library includes a plurality of selectable inverting NMOS logic circuits and a plurality of selectable inverter circuits.
- the inverter circuits are connectable to receive at least one output from a selected NMOS logic circuit.
- a method for constructing an integrated circuit. The method includes selecting a logic circuit from a cell library containing a plurality of logic circuits and selecting a driver circuit from the cell library containing a plurality of driver circuits for connection to the selected logic circuit to match at least a size characteristic of the selected logic circuits.
- FIGS. 1 a - d are circuit and layout diagrams of an example of an abbreviated library set of logic circuits that may be used in the construction of a library of domino circuits, in accordance with a preferred embodiment of the invention.
- FIGS. 2 a - c are circuit and layout diagrams of a library set of driver circuits that may be used in conjunction with selected logic circuits of FIGS. 1 a - d in the construction of a library of domino circuits, in accordance with a preferred embodiment of the invention.
- FIG. 3 is a circuit and layout diagram of PMOS precharge transistor that may be used in conjunction with the logic and driver circuits of FIGS. 1 a - d and 2 a - c , in accordance with a preferred embodiment of the invention.
- FIG. 4 is a circuit and layout diagram of an example of a keeper circuit used in conjunction with the logic circuit of FIG. 1 c , in accordance with a preferred embodiment of the invention.
- FIG. 5 is a circuit and layout diagram of an example circuit constructed using the library circuits of FIGS. 4, 2 a , and 3 , in accordance with a preferred embodiment of the invention.
- a method and circuit library are provided.
- the library enables domino logic cell, gate, or circuit sets to be constructed for particular applications having varying drive power, speed, or other parametric characteristic requirements or having varying logic function requirements.
- FIGS. 1 a - d an exemplar of a logic circuit set that may be Is included in a logic circuit collection from which domino logic circuits can be constructed is shown. From the logic circuit library of FIGS. 1 a - d , a set or library of circuits can be designed that have desired logic functions and parametric characteristics. In the library of FIGS.
- the various transistors have different sizes, speeds, capacitances, loading characteristics, or other parametric characteristics, and, as mentioned above, may be of appropriate polarity, i.e., NMOS or PMOS.
- NMOS logic circuit functions are shown.
- the library example shown is abbreviated, showing only a few of the possible circuit configurations that can be presented for selection in the formation of a circuit library for a particular design application.
- FIGS. 1 a - c show various selectable two-input NAND logic gates, the electrical schematic of which being shown on the left of the drawing and a corresponding representation of the layout of each circuit being shown on the right of the drawing.
- the layout representations show features that are only of approximate relative size, and show the implant, poly-1, contact, and selected metal-1 layers. Those skilled in the art will recognize the existence of various oxide or isolation layers between the various features shown.
- the circuit 10 of FIG. 1 a of the abbreviated library has three transistors 12 , 14 , and 16 in series, which can be configured to receive respectively logic inputs A and B and the clock signal, CP, on their respective gates.
- the gate connections are labeled at respective contact features, and the corresponding metal-1 layers have been omitted for clarity.
- One end of the transistors 12 , 14 , and 16 is connected to a ground rail 18 , and the output, Z, is derived at the other end on line or node 20 .
- the node 20 is selectively connectable to a driver circuit, described below in detail, and constitutes the dynamic node that will be precharged in the operation of the domino circuit into which the circuit 10 may be incorporated.
- a typical metal-1 layer is shown connected to the contact 21 of transistor 12 to provide the output line, Z, 20 .
- the transistors 12 , 14 , and 16 have a width-to-length (W/L) ratio respectively of 1.6u/0.13u, 2u/0.13u, and 2u/0.13u. This results in known transistor characteristics, notably the speed, capacitance, and drive capabilities of the devices, as well as other characteristics.
- the circuit 22 of FIG. 1 b of the abbreviated library has three transistors 24 , 26 , and 28 in series, which can be configured to receive respectively logic inputs A and B and the clock signal, CP.
- One end of the transistors 24 , 26 , and 28 is connected to the ground rail 18 at one end, and the output, Z, is derived at the other end on line or node 20 .
- the transistors 24 , 26 , and 28 have a width-to-length (W/L) ratio respectively of 1.5u/0.13u, 1 .Su/0.13u, and 1.5u/0.13u. This results in known transistor characteristics different from those of the circuit of FIG. 1 a.
- the circuit 30 of FIG. 1 c of the abbreviated library has three transistors 32 , 34 , and 36 in series, which can be configured to receive respectively logic inputs A and B and the clock signal, CP.
- One end of the transistors 32 , 34 , and 36 is connected to the ground rail 18 at one end, and the output, Z, is derived at the other end on line or node 20 .
- the transistors 32 , 34 , and 36 have a width-to-length (W/L) ratio respectively of 1u/0.13u, 1u/0.13u, and 1u/0.13u. This results in known transistor characteristics different from those of the circuits of FIGS. 1 a and 1 b.
- the respective clock transistors 16 , 28 , and 36 will serve as the “evaluate” or “footer” transistor for the ultimate circuit to be constructed, in the selective matching combination of one of the circuits 10 , 22 , or 30 with a corresponding driver circuit described below in conjunction with FIGS. 2 a - c.
- circuits of FIGS. 1 a - c which are exemplary only, have a two input NAND logic function
- logic circuits of other logic functions, sizes, and parametric characteristics may also be included in the library, if desired.
- FIG. 1 d a three-input NAND gate embodiment 40 may be provided.
- Circuit embodiments having an OR functionality may also be provided, if desired.
- the library may contain circuits of particular custom physical architectures.
- the transistor 12 the circuit 10 of FIG. 1 a is shown as having a length of 1.6 microns, to provide a tapered structure to the output to reduce its loading. The remaining transistors are shown having a length of 2 microns, illustrating the flexibility of the system.
- the set of circuits that are collected in the library contain most, if not all, of the parametric characteristics that will be needed in constructing the final library set from which the application circuits will be made.
- the library should also contain circuits having sufficient logic functionality to enable the particular logic functions to be used to be constructed.
- a minimum library may contain a two-input NAND function and a two-input NOR function, since the logic circuits can be combined, as discussed below.
- a library portion having a set, family, or library of driver circuits.
- the driver circuit library is provided to enable a driver to be selected to match the characteristics of the selected logic circuit, for example, in respect to sizes, speeds, capacitances, loading characteristics, or other parametric characteristics.
- the driver circuits of FIGS. 2 a - c are provided as an exemplar of a driver library that may be included. As with the logic circuit example of FIGS. 1 a - d , various driver circuits are shown, the electrical schematic of which being shown on the left of the drawing and a corresponding representation of the layout of each circuit being shown on the right side of the drawing.
- the layout representations show features that are only of approximate relative size, and show the implant, poly-1, contact, and selected metal-1 layers. Those skilled in the art will recognize the existence of various oxide or isolation layers between the various features shown. Since a selected driver will be matched with a selected logic circuit, the driver circuits and logic circuits in each library should be designed with compatible manufacturing processes to enable them to be constructed as a part of the same integrated circuit.
- one circuit 45 that may be included in the library is an inverter having PMOS and NMOS transistors 46 and 48 , connected between the supply rail, Vcc, 50 , and the ground rail 18 .
- the PMOS device 46 is formed in an n-well 52 , and is of size, for example having a width-to-length (W/L) ratio of about 2u/0.13u. Only a single PMOS device structure is formed in the layout (as compared to the multiple device structures of the embodiments of FIGS. 2 b and 2 c ).
- the NMOS device 48 which is of much smaller size, for example, has a width-to-length (W/L) ratio of about 0.7u/0.13u.
- the input on input line 20 is connected to the corresponding output line 20 from a selected one of the logic circuits of FIGS. 1 a - d , and the inverted output is derived on output line 54 .
- the metal-1 layers have been omitted for clarity, except for the input line 20 and output line 54 .
- the node 20 will serve as the dynamic node that will be precharged in the operation of the domino circuit in which the circuit 55 may be incorporated.
- the inverter 55 has PMOS and NMOS transistors 56 and 58 , connected between the supply rail, Vcc, 50 , and the ground rail 18 .
- the PMOS device 56 is formed in an n-well 52 , and is of size, for example, having a width-to-length (W/L) ratio of about 3.6u/0.13u.
- the width of the PMOS device is doubled using the two poly gate lines formed in the layout.
- the NMOS device 58 is of much smaller size than the PMOS device, for example, having a width-to-length (W/L) ratio of about 0.7u/0.13u. This results in known transistor characteristics, notably the speed, capacitance, and drive capabilities of the devices, as well as other characteristics different from the circuit embodiment of FIG. 2 a.
- the input on input line 20 is connected to the corresponding output line 20 from a selected one of the logic circuits of FIGS. 1 ad , and the inverted output is derived on output line 54 .
- the metal-1 layers have been omitted for clarity, except for the input line 20 and output line 54 .
- the node 20 will serve as the dynamic node that will be precharged in the operation of the domino Is circuit in which the circuit 55 may be incorporated.
- the inverter 60 has PMOS and NMOS transistors 62 and 64 , connected between the supply rail, Vcc, 50 , and the ground rail 18 .
- the PMOS device 62 is formed in an n-well 52 , and is of size, for example, having a width-to-length (W/L) ratio of about 1.8u/0.26u.
- the NMOS device 64 is of much larger size than the NMOS device 58 of FIG. 2 b , for example, having a width-to-length (W/L) ratio of about 0.7u/0.26u. This results in known transistor characteristics, notably the speed, capacitance, and drive capabilities of the devices, as well as other characteristics different from the circuit embodiments of FIGS. 2 a and 2 b.
- the input on input line 20 is connected to the corresponding output line 20 from a selected one of the logic circuits of FIGS. 1 ad , and the inverted output is derived on output line 54 .
- the metal-1 layers have been omitted for clarity, except for the input line 20 and output line 54 .
- the node 20 will serve as the dynamic node that will be precharged in the operation of the domino circuit in which the circuit 55 may be incorporated.
- the PMOS device of the driver is made very large and the NMOS device is made very small.
- the PMOS device is large, a large load can be driven, but it may load down the associated logic circuitry. So by having a family of sized devices available, a trade-off can be made to decrease the loading on the logic circuitry, and reduce the drive capacity of the PMOS device to optimize the speed of the circuit. So, if a very large load is needed to be driven, the size of the PMOS device can be selected to accommodate that as well. In sum, different sized PMOS devices are available for different loading situations. On the other hand, a smaller driver slows down the n-logic less, so if a larger driver at the output is not necessary to drive the load, a smaller PMOS device may be chosen.
- a standard PMOS precharge transistor may be used.
- the parametric characteristics of the PMOS transistor may depend upon the characteristics of the circuit components selected from the libraries.
- a PMOS transistor 65 that can be used in conjunction with the circuit portions of FIGS. 1 a - d and 2 a - c is shown.
- the manufacturing processes by which the PMOS transistor is made should be compatible with the manufacturing processes of the circuits of the library portions with which it will be used to enable it to be constructed as a part of the same integrated circuit.
- the PMOS precharge transistor 65 has the clock input, CP, on its gate to conduct the supply voltage Vcc to the output line Z (the dynamic node), 20 when CP is low. In operation of the ultimate circuit, this will precharge the dynamic node 20 to enable domino operation.
- the PMOS transistor can be sized as needed, depending upon the particular circuit portions selected from the logic and driver circuit libraries. Various sized PMOS precharge transistors may be included as a part of the circuit libraries, if desired, or may be individually constructed for a particular circuit design as a standard transistor. Its size may be calculated, based upon known sizing parameters.
- a spot is left open during the initial design phases of the circuit, then a PMOS precharge transistor of predetermined size is inserted.
- the PMOS precharge transistor can also be made small, and vise versa.
- keeper circuits may also be provided, for example, conveniently as a part of the logic circuit portion of the library.
- a keeper circuit is desired in the design of a domino logic circuit; however, in some application, it may be desired to omit it. Consequently, the library may include some logic circuits having a keeper circuit, and some circuits in which the keeper is omitted.
- the example circuit of FIG. 4 shows a keeper circuit 70 associated with the logic circuit 30 of FIG. 1 c.
- the keeper circuit 70 includes an inverter having a PMOS transistor 72 in series with an NMOS transistor 74 between the Vcc rail 50 and the ground rail 18 .
- a weak PMOS transistor 76 is connected between the Vcc rail 50 and the dynamic node, Z, 20 .
- the weak PMOS transistor 76 may be sized with a width-to-length (W/L) ratio of about 0.16u/0.13u, for example.
- W/L width-to-length
- the weak PMOS transistor 76 serves to protect the dynamic node 20 from discharge that may be initiated by noise, current spikes, or the like.
- the location of the keeper circuit may need to be arranged to enable the insertion of the PMOS precharge transistor 65 .
- various circuit arrangements may be provided in the library.
- a circuit library can be constructed from the various circuit library portions of FIGS. 1 a - d , 2 a - c , 3 , and 4 .
- a circuit 90 shown in FIG. 5 , to which reference is now additionally made, may be constructed from the circuits of FIGS. 4, 2 a , and 3 .
- the circuit 90 includes the logic portion 30 , driver portion 45 , precharge PMOS device 65 , and keeper circuit 70 , as described above.
- the various circuits may be manually constructed to form a library of cells. Then a synthesis tool may be used to construct the final circuit.
- the sizes of the various cells available in the library may be insufficient for the particular application needed. For example, if a logic function requiring an eight input AND gate is specified, the loading may be too much to maintain the desired speed or other circuit characteristic.
- it may be possible to provide two or more logic cells from the library i.e., to split up the function among several logic cells.
- driver circuits in the library may perform a NAND or NOR function to achieve the ultimate desired logic result.
- two 4-input NOR gate logic circuits may be used to provide an input to a 2-input NAND driver circuit.
Abstract
A cell library for designing integrated domino circuits has a first library portion with a plurality of selectable logic circuits having different transistor sizes and/or logic functions for selection according to desired logic function and parametric characteristics. A second library portion includes a plurality of selectable prechargeable driver circuits. Each of the driver circuits is configured to be connectable to an output of a selected one of the logic circuits. The driver circuits also have at least different transistor sizes. Standard FET devices may be constructed to precharge the output node of the selected logic circuit in the design of a domino logic circuit.
Description
- The present application claims priority from, and is a divisional of, U.S. patent application Ser. No. 10/604,318 filed on Jul. 10, 2003. The disclosure of the foregoing United States Patent Application is specifically incorporated herein by this reference in its entirety and assigned to STMicroelectronics, Inc., Carrollton, Tex., assignee of the present invention.
- 1. Field of the Invention
- This invention relates to improvements in circuit design methods, and more particularly to improvements in domino circuit design methods, and still more particularly to circuit libraries for use in performing such methods.
- 2. Relevant Background
- Recently, circuit designers have been devoting increased interest to CMOS domino logic circuit designs, because of their reduced integrated circuit area, smaller parasitic capacitances, higher speed, and increased reliability.
- Typically, domino logic circuits have an NMOS, or pull-down, logic portion, although PMOS pull-up logic circuits have been used in many applications. The logic portion serves to evaluate input logic signals to provide a conditional output signal to an output inverter.
- Domino logic circuits also have a precharge transistor, typically a PMOS device when the logic circuit is made up with NMOS transistors, which is switched by the clock signal to connect the “dynamic node” of the circuit to a precharge voltage during a “precharge phase” of the clock cycle. The “dynamic node” may be for example, the output node of the logic circuit or the input node of the associated output inverter.
- Thus, typically, the output inverter transistors are precharged during the precharge phase, while the clock signal is in a first state, low, for example, in an NMOS logic circuit implementation, or high in a PMOS logic circuit implementation. During the precharge phase, an “evaluate” transistor, whose gate is also connected to the clock signal, isolates the associated logic circuit from the precharge voltage.
- When the particular logic conditions of the logic circuit are met during a subsequent “evaluate” phase when the clock signal transitions from low to high in the NMOS logic circuit implementation, the output node of the logic circuit (the input of the inverter) is pulled down and the output of the inverter is pulled up. If the logic conditions of the logic circuit are not met, the output of the inverter remains low. Because the inverter is precharged when the clock signal transitions from low to high, the cell output can be developed very rapidly.
- In the design of domino logic circuits, it will be appreciated that different applications require circuits of different speeds and driving abilities. However, usually a trade-off is involved, since in domino logic applications, usually faster circuits are larger in layout size, and consequently occupy more real estate of the substrate on which the circuit is constructed, and additionally consume more power. On the other hand, if the transistors of the logic circuit are made too large, they may unduly load the driver circuit. Consequently, in some applications, it may be that the driver circuit is large, while the associated logic circuitry is of relatively smaller devices, or vice versa. It can be seen that depending upon the particular application, large numbers of combinations of circuits may be required.
- As a result, domino logic circuits had to be individually designed to provide the necessary speed and drive power for a particular application. However, once the drive circuit has been designed, the associated logic circuit also had to be designed in accordance with the parameters of the drive circuit (or vice versa). As can be seen, this design process has been difficult and time consuming.
- In efforts to standardize the design process, layout templates have been proposed into which the various domino circuit components can be placed in order to facilitate interconnection of a number of gates in a particular circuit. The arrangement of the various circuit parts in fixed layout regions provides a “standard cell”, connectable to similar adjacent regions.
- In one proposal, for example, a layout template is suggested for a domino logic circuit of the type having an n-FET logic tree. The n-FET logic tree is inserted into a first portion of the template. The output from the logic circuit is inverted in an output inverter, and latched by a p-FET device connected around the inverter. The p-FET portions of the inverter, a p-FET precharge transistor, and the p-FET latch transistor are inserted in predefined second template locations. The clock also includes an n-FET evaluate transistor, which is inserted into a third template area.
- However, in this and other previous proposals, the fixed layout template has not been concerned with the parametric characteristics of the ultimate cells, only the standardization of the layout template into which they are constructed to enable standardization of cell interconnections.
- What is needed, therefore, is a method and circuit library for designing domino logic circuits to form a collection of domino logic cells that can be used for particular applications having varying drive power and speed requirements.
- In light of the above, therefore, it is an object of the invention to provide a method and circuit library from which domino logic cell or gate sets can be constructed for particular applications having varying drive power, speed, or other parametric characteristic requirements.
- An advantage of the invention is that sets of matchable circuits, namely, logic and drive circuits, can be selected to develop a library of circuits for a particular application. By “matchable”, “match”, “matching”, or “matched” it is meant herein that the size, speed, capacitance, or other parametric characteristic of the circuits can be appropriately interconnected for a desired result. The term is not intended to imply that the parametric characteristics of the logic and drive circuits are necessarily the same, or even substantially the same.
- Another advantage of the invention is that a library of domino circuits can be quickly developed, constructed, and completed.
- Although layout templates may be used, they are not essential. The various sizes of the final circuits, which may constitute a library of “standard cells”, may be fixed or variable, depending upon the particular uses to which the library that is developed is to be used. In some cases, however, the boundary locations of the circuits may be established to readily accommodate interconnection of various circuits that may result from the use of the circuit libraries defined by the invention.
- According to a broad aspect of the invention, a set, family, or library of logic circuits is provided from which a desired logic function can be constructed. The transistors in the set have different sizes, speeds, capacitances, loading characteristics, or other parametric characteristics. Each circuit has an associated evaluate or “footer” transistor that is selected with the selection of the circuit. Additionally, a set, family, or library of driver circuits is provided so that a driver can be selected to match the characteristics of the selected n-logic circuit, for example, in respect to sizes, speeds, capacitances, loading characteristics, or other parametric characteristics. A standard PMOS precharge transistor may be constructed, depending upon the characteristics of the circuit components selected from the libraries.
- According to another broad aspect of the invention, a cell library is provided for use in designing integrated domino circuits. The cell library includes a first library portion including a plurality of FET logic circuits of first conductivity type to provide at least selectable transistor sizes. A second library portion includes a plurality of selectable prechargeable complementary FET driver circuits. Each of the driver circuits is configured to be connectable to an output of a selected one of the logic circuits, to provide selectable logic functions, transistor sizes, or other parametric characteristic.
- According to yet another broad aspect of the invention, a cell library is provided for use in designing integrated circuits. The cell library includes a first library portion containing a plurality of NMOS logic circuits to provide selectable logic functions and transistor sizes. A second library portion contains a plurality of selectable driver circuits, each configured to be connectable to an output of a selected one of the logic circuits. The driver circuits are selectable to match at least a size characteristic of the selected one of the logic circuits.
- According to still another broad aspect of the invention, a cell library is provided. The cell library includes a plurality of selectable inverting NMOS logic circuits and a plurality of selectable inverter circuits. The inverter circuits are connectable to receive at least one output from a selected NMOS logic circuit.
- According to yet another broad aspect of the invention, a method is presented for constructing an integrated circuit. The method includes selecting a logic circuit from a cell library containing a plurality of logic circuits and selecting a driver circuit from the cell library containing a plurality of driver circuits for connection to the selected logic circuit to match at least a size characteristic of the selected logic circuits.
- The invention is illustrated in the accompanying drawing, in which:
-
FIGS. 1 a-d are circuit and layout diagrams of an example of an abbreviated library set of logic circuits that may be used in the construction of a library of domino circuits, in accordance with a preferred embodiment of the invention. -
FIGS. 2 a-c are circuit and layout diagrams of a library set of driver circuits that may be used in conjunction with selected logic circuits ofFIGS. 1 a-d in the construction of a library of domino circuits, in accordance with a preferred embodiment of the invention. -
FIG. 3 is a circuit and layout diagram of PMOS precharge transistor that may be used in conjunction with the logic and driver circuits ofFIGS. 1 a-d and 2 a-c, in accordance with a preferred embodiment of the invention. -
FIG. 4 is a circuit and layout diagram of an example of a keeper circuit used in conjunction with the logic circuit ofFIG. 1 c, in accordance with a preferred embodiment of the invention. - And
FIG. 5 is a circuit and layout diagram of an example circuit constructed using the library circuits ofFIGS. 4, 2 a, and 3, in accordance with a preferred embodiment of the invention. - In the various figures of the drawing, like reference numerals are used to denote like or similar parts.
- According to a preferred embodiment of the invention, a method and circuit library are provided. The library enables domino logic cell, gate, or circuit sets to be constructed for particular applications having varying drive power, speed, or other parametric characteristic requirements or having varying logic function requirements. Thus, with reference first to
FIGS. 1 a-d, an exemplar of a logic circuit set that may be Is included in a logic circuit collection from which domino logic circuits can be constructed is shown. From the logic circuit library ofFIGS. 1 a-d, a set or library of circuits can be designed that have desired logic functions and parametric characteristics. In the library ofFIGS. 1 a-d, the various transistors have different sizes, speeds, capacitances, loading characteristics, or other parametric characteristics, and, as mentioned above, may be of appropriate polarity, i.e., NMOS or PMOS. In the examples herein, NMOS logic circuit functions are shown. The library example shown is abbreviated, showing only a few of the possible circuit configurations that can be presented for selection in the formation of a circuit library for a particular design application. - More particularly, the circuits of
FIGS. 1 a-c show various selectable two-input NAND logic gates, the electrical schematic of which being shown on the left of the drawing and a corresponding representation of the layout of each circuit being shown on the right of the drawing. The layout representations show features that are only of approximate relative size, and show the implant, poly-1, contact, and selected metal-1 layers. Those skilled in the art will recognize the existence of various oxide or isolation layers between the various features shown. - Thus, as an example, the
circuit 10 ofFIG. 1 a of the abbreviated library has threetransistors transistors ground rail 18, and the output, Z, is derived at the other end on line ornode 20. - The
node 20 is selectively connectable to a driver circuit, described below in detail, and constitutes the dynamic node that will be precharged in the operation of the domino circuit into which thecircuit 10 may be incorporated. A typical metal-1 layer is shown connected to thecontact 21 oftransistor 12 to provide the output line, Z, 20. As can be seen, thetransistors - Similarly, the
circuit 22 ofFIG. 1 b of the abbreviated library has threetransistors transistors ground rail 18 at one end, and the output, Z, is derived at the other end on line ornode 20. As can be seen, thetransistors FIG. 1 a. - Moreover, the
circuit 30 ofFIG. 1 c of the abbreviated library has threetransistors transistors ground rail 18 at one end, and the output, Z, is derived at the other end on line ornode 20. As can be seen, thetransistors FIGS. 1 a and 1 b. - The
respective clock transistors circuits FIGS. 2 a-c. - Although the circuits of
FIGS. 1 a-c, which are exemplary only, have a two input NAND logic function, logic circuits of other logic functions, sizes, and parametric characteristics may also be included in the library, if desired. For example, as shown inFIG. 1 d, a three-inputNAND gate embodiment 40 may be provided. Circuit embodiments having an OR functionality may also be provided, if desired. Furthermore, the library may contain circuits of particular custom physical architectures. As an example, thetransistor 12 thecircuit 10 ofFIG. 1 a is shown as having a length of 1.6 microns, to provide a tapered structure to the output to reduce its loading. The remaining transistors are shown having a length of 2 microns, illustrating the flexibility of the system. - Desirably, the set of circuits that are collected in the library contain most, if not all, of the parametric characteristics that will be needed in constructing the final library set from which the application circuits will be made. The library should also contain circuits having sufficient logic functionality to enable the particular logic functions to be used to be constructed. Typically, for example, a minimum library may contain a two-input NAND function and a two-input NOR function, since the logic circuits can be combined, as discussed below.
- In addition to the library portion of logic circuits, according to a preferred embodiment of the invention, a library portion is provided having a set, family, or library of driver circuits. The driver circuit library is provided to enable a driver to be selected to match the characteristics of the selected logic circuit, for example, in respect to sizes, speeds, capacitances, loading characteristics, or other parametric characteristics. The driver circuits of
FIGS. 2 a-c are provided as an exemplar of a driver library that may be included. As with the logic circuit example ofFIGS. 1 a-d, various driver circuits are shown, the electrical schematic of which being shown on the left of the drawing and a corresponding representation of the layout of each circuit being shown on the right side of the drawing. The layout representations show features that are only of approximate relative size, and show the implant, poly-1, contact, and selected metal-1 layers. Those skilled in the art will recognize the existence of various oxide or isolation layers between the various features shown. Since a selected driver will be matched with a selected logic circuit, the driver circuits and logic circuits in each library should be designed with compatible manufacturing processes to enable them to be constructed as a part of the same integrated circuit. - Thus, with reference now additionally to
FIG. 2 a, as an example, onecircuit 45 that may be included in the library is an inverter having PMOS andNMOS transistors ground rail 18. ThePMOS device 46 is formed in an n-well 52, and is of size, for example having a width-to-length (W/L) ratio of about 2u/0.13u. Only a single PMOS device structure is formed in the layout (as compared to the multiple device structures of the embodiments ofFIGS. 2 b and 2 c). Similarly, theNMOS device 48, which is of much smaller size, for example, has a width-to-length (W/L) ratio of about 0.7u/0.13u. - The input on
input line 20 is connected to thecorresponding output line 20 from a selected one of the logic circuits ofFIGS. 1 a-d, and the inverted output is derived onoutput line 54. In the layout diagram, the metal-1 layers have been omitted for clarity, except for theinput line 20 andoutput line 54. As mentioned above, thenode 20 will serve as the dynamic node that will be precharged in the operation of the domino circuit in which thecircuit 55 may be incorporated. - With reference now additionally to
FIG. 2 b, another example of aninverter circuit 55 that may be included in the library is shown. Theinverter 55 has PMOS andNMOS transistors ground rail 18. ThePMOS device 56 is formed in an n-well 52, and is of size, for example, having a width-to-length (W/L) ratio of about 3.6u/0.13u. The width of the PMOS device is doubled using the two poly gate lines formed in the layout. Again, theNMOS device 58 is of much smaller size than the PMOS device, for example, having a width-to-length (W/L) ratio of about 0.7u/0.13u. This results in known transistor characteristics, notably the speed, capacitance, and drive capabilities of the devices, as well as other characteristics different from the circuit embodiment ofFIG. 2 a. - The input on
input line 20 is connected to thecorresponding output line 20 from a selected one of the logic circuits ofFIGS. 1 ad, and the inverted output is derived onoutput line 54. In the layout diagram, the metal-1 layers have been omitted for clarity, except for theinput line 20 andoutput line 54. As mentioned above, thenode 20 will serve as the dynamic node that will be precharged in the operation of the domino Is circuit in which thecircuit 55 may be incorporated. - With reference now additionally to
FIG. 2 c, still another example of aninverter circuit 60 that may be included in the library is shown. Theinverter 60 has PMOS andNMOS transistors ground rail 18. ThePMOS device 62 is formed in an n-well 52, and is of size, for example, having a width-to-length (W/L) ratio of about 1.8u/0.26u. TheNMOS device 64 is of much larger size than theNMOS device 58 ofFIG. 2 b, for example, having a width-to-length (W/L) ratio of about 0.7u/0.26u. This results in known transistor characteristics, notably the speed, capacitance, and drive capabilities of the devices, as well as other characteristics different from the circuit embodiments ofFIGS. 2 a and 2 b. - Again, the input on
input line 20 is connected to thecorresponding output line 20 from a selected one of the logic circuits ofFIGS. 1 ad, and the inverted output is derived onoutput line 54. In the layout diagram, the metal-1 layers have been omitted for clarity, except for theinput line 20 andoutput line 54. As mentioned above, thenode 20 will serve as the dynamic node that will be precharged in the operation of the domino circuit in which thecircuit 55 may be incorporated. - More particularly, in the design of typical domino circuits, the PMOS device of the driver is made very large and the NMOS device is made very small. However, because the PMOS device is large, a large load can be driven, but it may load down the associated logic circuitry. So by having a family of sized devices available, a trade-off can be made to decrease the loading on the logic circuitry, and reduce the drive capacity of the PMOS device to optimize the speed of the circuit. So, if a very large load is needed to be driven, the size of the PMOS device can be selected to accommodate that as well. In sum, different sized PMOS devices are available for different loading situations. On the other hand, a smaller driver slows down the n-logic less, so if a larger driver at the output is not necessary to drive the load, a smaller PMOS device may be chosen.
- In order to precharge the
dynamic node 20 of the circuit that is constructed using elements of the library exemplified byFIGS. 1 a-d and 2 a-c, a standard PMOS precharge transistor may be used. The parametric characteristics of the PMOS transistor may depend upon the characteristics of the circuit components selected from the libraries. Thus, with reference additionally now toFIG. 3 , aPMOS transistor 65 that can be used in conjunction with the circuit portions ofFIGS. 1 a-d and 2 a-c is shown. The manufacturing processes by which the PMOS transistor is made should be compatible with the manufacturing processes of the circuits of the library portions with which it will be used to enable it to be constructed as a part of the same integrated circuit. - The PMOS
precharge transistor 65 has the clock input, CP, on its gate to conduct the supply voltage Vcc to the output line Z (the dynamic node), 20 when CP is low. In operation of the ultimate circuit, this will precharge thedynamic node 20 to enable domino operation. The PMOS transistor can be sized as needed, depending upon the particular circuit portions selected from the logic and driver circuit libraries. Various sized PMOS precharge transistors may be included as a part of the circuit libraries, if desired, or may be individually constructed for a particular circuit design as a standard transistor. Its size may be calculated, based upon known sizing parameters. Typically, in the construction of the standard cell libraries, a spot is left open during the initial design phases of the circuit, then a PMOS precharge transistor of predetermined size is inserted. Thus, if the drive PMOS transistor is small, the PMOS precharge transistor can also be made small, and vise versa. - If desired, keeper circuits may also be provided, for example, conveniently as a part of the logic circuit portion of the library. Usually a keeper circuit is desired in the design of a domino logic circuit; however, in some application, it may be desired to omit it. Consequently, the library may include some logic circuits having a keeper circuit, and some circuits in which the keeper is omitted. The example circuit of
FIG. 4 , to which reference is now additionally made shows akeeper circuit 70 associated with thelogic circuit 30 ofFIG. 1 c. - The
keeper circuit 70 includes an inverter having aPMOS transistor 72 in series with anNMOS transistor 74 between theVcc rail 50 and theground rail 18. Aweak PMOS transistor 76 is connected between theVcc rail 50 and the dynamic node, Z, 20. Theweak PMOS transistor 76 may be sized with a width-to-length (W/L) ratio of about 0.16u/0.13u, for example. As known, theweak PMOS transistor 76 serves to protect thedynamic node 20 from discharge that may be initiated by noise, current spikes, or the like. - In the layout of the keeper circuit, depending upon the size of the logic circuit with which it is associated, the location of the keeper circuit may need to be arranged to enable the insertion of the PMOS
precharge transistor 65. As a result, various circuit arrangements may be provided in the library. - In performing the method according to a preferred embodiment of the invention, a circuit library can be constructed from the various circuit library portions of
FIGS. 1 a-d, 2 a-c, 3, and 4. For example, acircuit 90, shown in FIG. 5, to which reference is now additionally made, may be constructed from the circuits ofFIGS. 4, 2 a, and 3. Thecircuit 90 includes thelogic portion 30,driver portion 45,precharge PMOS device 65, andkeeper circuit 70, as described above. Through the selection of other combinations of the circuit library (only an exemplary portion of which being shown), other circuits can be designed having the logic function and parametric characteristics desired for a particular application. In the design of the final library, the various circuits may be manually constructed to form a library of cells. Then a synthesis tool may be used to construct the final circuit. - It should also be noted that in many circuit applications, the sizes of the various cells available in the library may be insufficient for the particular application needed. For example, if a logic function requiring an eight input AND gate is specified, the loading may be too much to maintain the desired speed or other circuit characteristic. Thus, it may be possible to provide two or more logic cells from the library, i.e., to split up the function among several logic cells. In that case, it may be necessary to provide driver circuits in the library that have multiple inputs, so that the driver circuit itself may perform a NAND or NOR function to achieve the ultimate desired logic result. For example, two 4-input NOR gate logic circuits may be used to provide an input to a 2-input NAND driver circuit.
- Although the invention has been described and illustrated with a certain degree of particularity, it should be understood that the description contained herein is made only by way of example, and that numerous changes in the arrangement and combination of parts may be made without departing from the spirit and scope of the invention, as hereinafter claimed.
Claims (4)
1. A method for constructing an integrated circuit, comprising:
selecting a logic circuit from a cell library containing a plurality of logic circuits; and
selecting a driver circuit from said cell library containing a plurality of driver circuits for connection to said selected logic circuit to match at least a size characteristic of said selected logic circuits.
2. The method of claim 1 wherein said selecting a logic circuit comprises selecting an NMOS logic circuit.
3. The method of claim 2 further comprising constructing a PMOS transistor for connection to said selected logic circuit to precharge same in a domino logic circuit.
4. The method of claim 1 further comprising selecting a keeper circuit that inverts an output from said selected NMOS circuit and latches a logic value therein.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/421,035 US20060253808A1 (en) | 2003-07-10 | 2006-05-30 | Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/604,318 US7084464B2 (en) | 2003-07-10 | 2003-07-10 | Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same |
US11/421,035 US20060253808A1 (en) | 2003-07-10 | 2006-05-30 | Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/604,318 Division US7084464B2 (en) | 2003-07-10 | 2003-07-10 | Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060253808A1 true US20060253808A1 (en) | 2006-11-09 |
Family
ID=33564167
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/604,318 Expired - Lifetime US7084464B2 (en) | 2003-07-10 | 2003-07-10 | Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same |
US11/421,035 Abandoned US20060253808A1 (en) | 2003-07-10 | 2006-05-30 | Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/604,318 Expired - Lifetime US7084464B2 (en) | 2003-07-10 | 2003-07-10 | Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same |
Country Status (1)
Country | Link |
---|---|
US (2) | US7084464B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060136852A1 (en) * | 2004-12-17 | 2006-06-22 | Bernard Bourgin | Method and apparatus for mixing static logic with domino logic |
US20060136859A1 (en) * | 2004-12-17 | 2006-06-22 | Bernard Bourgin | Method to unate a design for improved synthesizable domino logic flow |
WO2009033184A2 (en) * | 2007-09-06 | 2009-03-12 | Picogem Corp. | Clock guided logic with reduced switching |
US20120132963A1 (en) * | 2010-11-26 | 2012-05-31 | STMicroelectronics STM | Standard cell for integrated circuit |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7589990B2 (en) * | 2004-12-03 | 2009-09-15 | Taiwan Imagingtek Corporation | Semiconductor ROM device and manufacturing method thereof |
WO2007029051A1 (en) * | 2005-09-07 | 2007-03-15 | Freescale Semiconductor Inc. | Method and a computer readable medium for analyzing a design of an integrated circuit |
US20070164790A1 (en) * | 2006-01-16 | 2007-07-19 | Tzu-Pin Shen | Method for Forming a Domino Circuit |
US7926018B2 (en) * | 2007-09-25 | 2011-04-12 | Synopsys, Inc. | Method and apparatus for generating a layout for a transistor |
US9104435B2 (en) * | 2009-04-14 | 2015-08-11 | Empire Technology Development Llc | Program and data annotation for hardware customization and energy optimization |
US8543958B2 (en) * | 2009-12-11 | 2013-09-24 | Synopsys, Inc. | Optical proximity correction aware integrated circuit design optimization |
US9231594B2 (en) * | 2011-12-21 | 2016-01-05 | Ecole Polytechnique Federale De Lausanne (Epfl) | Non-LUT field-programmable gate arrays |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5633805A (en) * | 1994-09-30 | 1997-05-27 | Intel Corporation | Logic synthesis having two-dimensional sizing progression for selecting gates from cell libraries |
US5814846A (en) * | 1996-10-07 | 1998-09-29 | International Business Machines Corporation | Cell apparatus and method for use in building complex integrated circuit devices |
US6031982A (en) * | 1996-11-15 | 2000-02-29 | Samsung Electronics Co., Ltd. | Layout design of integrated circuit, especially datapath circuitry, using function cells formed with fixed basic cell and configurable interconnect networks |
US6643828B2 (en) * | 2001-12-14 | 2003-11-04 | Hewlett-Packard Development Company, L.P. | Method for controlling critical circuits in the design of integrated circuits |
US6721926B2 (en) * | 2002-01-25 | 2004-04-13 | Intel Corporation | Method and apparatus for improving digital circuit design |
US7034578B2 (en) * | 2003-04-28 | 2006-04-25 | Via Technologies, Inc. | N-domino output latch with accelerated evaluate path |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5150309A (en) * | 1987-08-04 | 1992-09-22 | Texas Instruments Incorporated | Comprehensive logic circuit layout system |
US5402012A (en) * | 1993-04-19 | 1995-03-28 | Vlsi Technology, Inc. | Sequentially clocked domino-logic cells |
JP2002215705A (en) * | 2001-01-23 | 2002-08-02 | Toshiba Corp | Automatic circuit generating device, automatic circuit generating method, and recording medium recorded with automatic circuit generating program |
JP2002299454A (en) * | 2001-04-02 | 2002-10-11 | Toshiba Corp | Method and apparatus for designing logic circuit, and method for mapping logic circuit |
US6711720B2 (en) * | 2002-03-14 | 2004-03-23 | Hewlett-Packard Development Company, L.P. | Method of optimizing high performance CMOS integrated circuit designs for power consumption and speed through genetic optimization |
US6785875B2 (en) * | 2002-08-15 | 2004-08-31 | Fulcrum Microsystems, Inc. | Methods and apparatus for facilitating physical synthesis of an integrated circuit design |
-
2003
- 2003-07-10 US US10/604,318 patent/US7084464B2/en not_active Expired - Lifetime
-
2006
- 2006-05-30 US US11/421,035 patent/US20060253808A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5633805A (en) * | 1994-09-30 | 1997-05-27 | Intel Corporation | Logic synthesis having two-dimensional sizing progression for selecting gates from cell libraries |
US5814846A (en) * | 1996-10-07 | 1998-09-29 | International Business Machines Corporation | Cell apparatus and method for use in building complex integrated circuit devices |
US6031982A (en) * | 1996-11-15 | 2000-02-29 | Samsung Electronics Co., Ltd. | Layout design of integrated circuit, especially datapath circuitry, using function cells formed with fixed basic cell and configurable interconnect networks |
US6643828B2 (en) * | 2001-12-14 | 2003-11-04 | Hewlett-Packard Development Company, L.P. | Method for controlling critical circuits in the design of integrated circuits |
US6721926B2 (en) * | 2002-01-25 | 2004-04-13 | Intel Corporation | Method and apparatus for improving digital circuit design |
US7034578B2 (en) * | 2003-04-28 | 2006-04-25 | Via Technologies, Inc. | N-domino output latch with accelerated evaluate path |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060136852A1 (en) * | 2004-12-17 | 2006-06-22 | Bernard Bourgin | Method and apparatus for mixing static logic with domino logic |
US20060136859A1 (en) * | 2004-12-17 | 2006-06-22 | Bernard Bourgin | Method to unate a design for improved synthesizable domino logic flow |
US7331030B2 (en) * | 2004-12-17 | 2008-02-12 | Stmicroelectronics, Inc. | Method to unate a design for improved synthesizable domino logic flow |
US7370301B2 (en) | 2004-12-17 | 2008-05-06 | Stmicroelectronics, Inc. | Method and apparatus for mixing static logic with domino logic |
WO2009033184A2 (en) * | 2007-09-06 | 2009-03-12 | Picogem Corp. | Clock guided logic with reduced switching |
WO2009033184A3 (en) * | 2007-09-06 | 2009-05-07 | Picogem Corp | Clock guided logic with reduced switching |
US20120132963A1 (en) * | 2010-11-26 | 2012-05-31 | STMicroelectronics STM | Standard cell for integrated circuit |
US8963210B2 (en) * | 2010-11-26 | 2015-02-24 | Stmicroelectronics Sa | Standard cell for integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
US7084464B2 (en) | 2006-08-01 |
US20050006670A1 (en) | 2005-01-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20060253808A1 (en) | Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same | |
US8161427B2 (en) | Logic circuit and method of logic circuit design | |
US8188767B2 (en) | Logic circuit and method of logic circuit design | |
US6972599B2 (en) | Pseudo CMOS dynamic logic with delayed clocks | |
US6952118B2 (en) | Gate-clocked domino circuits with reduced leakage current | |
JPH11511943A (en) | Compatible output driver for multiple logic families | |
US6949951B1 (en) | Integrated circuit multiplexer including transistors of more than one oxide thickness | |
JPH07106946A (en) | Level shifter | |
EP1236278B1 (en) | Method and apparatus for an n-nary logic circuit | |
KR930001749B1 (en) | Programmable logic circuit | |
US6288593B1 (en) | Digital electronic circuit for use in implementing digital logic functions | |
US20040104756A1 (en) | Voltage level shifter circuit having high speed and low switching power | |
US5663669A (en) | Circuitry and method for latching information | |
Ponnian et al. | A new systematic GDI circuit synthesis using MUX based decomposition algorithm and binary decision diagram for low power ASIC circuit design | |
US6363505B1 (en) | Programmable control circuit for grounding unused outputs | |
US11671101B2 (en) | Memory-type camouflaged logic gate using transistors with different threshold voltages | |
JP4565003B2 (en) | Logic basic cell, logic basic cell array, and logic circuit | |
US7463061B1 (en) | Apparatus and method for reducing leakage of unused buffers in an integrated circuit | |
JP2004336123A (en) | Semiconductor integrated circuit | |
US8885392B1 (en) | RAM/ROM memory circuit | |
US5694055A (en) | Zero static power programmable logic cell | |
JP2001274672A (en) | Try-state buffer circuit | |
US20020030513A1 (en) | Logic circuit cell constituting an integrated circuit and cell library having a collection of logic circuit cells | |
US8526218B2 (en) | Memory design | |
US7283068B2 (en) | Binary decoders in electronic integrated circuits |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |