US20060254810A1 - Technique for accommodating electronic components on a multilayer signal routing device - Google Patents
Technique for accommodating electronic components on a multilayer signal routing device Download PDFInfo
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- US20060254810A1 US20060254810A1 US11/488,799 US48879906A US2006254810A1 US 20060254810 A1 US20060254810 A1 US 20060254810A1 US 48879906 A US48879906 A US 48879906A US 2006254810 A1 US2006254810 A1 US 2006254810A1
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- signal routing
- routing device
- electrically conductive
- electronic components
- multilayer signal
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
- H05K1/0231—Capacitors or dielectric substances
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09236—Parallel layout
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09263—Meander
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09627—Special connections between adjacent vias, not for grounding vias
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10545—Related components mounted on both sides of the PCB
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
Definitions
- the present disclosure relates generally to multilayer signal routing devices and, more particularly, to a technique for accommodating electronic components on a multilayer signal routing device.
- PCBs printed circuit boards
- the first such circuit boards had only a single routing layer on a top surface thereof for routing electrical signals between electronic components mounted thereon.
- These single routing layer circuit boards have severe limitations with regard to the number of electrical signals that can be routed between electronic components mounted on the same circuit board. That is, the number of electrical signals that can be routed between electronic components mounted on a single routing layer circuit board is limited by the amount of area on the single routing layer.
- multilayer PCBs may be either single or double-sided and may have multiple routing layers on the surface of and buried within the multilayer PCBs.
- multilayer PCBs have allowed a large increase in the number of electrical signals that may be routed between electronic components mounted on the same circuit board.
- multilayer PCBs have been particularly beneficial when using electronic components having high-density packages. That is, electronic components having high-density packages generally require multiple layers of a multilayer PCB to make electrical connections with other electronic components mounted on the same circuit board. In fact, the density of electronic component packages typically dictates the number of layers that must be provided by the multilayer PCB upon which the electronic components are mounted. While the number of layers that may be provided by a multilayer PCB is theoretically unlimited, reliability and other problems occur when the number of layers in a multilayer PCB exceeds a reasonable number, particularly when trying to route high-speed electrical signals between electronic components.
- electrically conductive vias allow direct vertical electrical connections to be made between different layers within a multilayer PCB
- electrically conductive vias have intrinsic parasitic resistance, capacitance, and inductance, which can adversely affect signals propagating along each electrically conductive via.
- these intrinsic parasitics can also have an adverse effect on the manufacturability of a PCB and thus the cost thereof. Because of their adverse affect on signal performance, these intrinsic parasitics can also limit the bandwidth of signals propagating along each electrically conductive via. These adverse affects only increase as the number of layers in a multilayer PCB increase.
- resistive, capacitive, and/or inductive components electrically connected in series and/or parallel with an electrically conductive via, which is also electrically connected to a signal driver contact of an electronic component.
- the signal driver contact may be located within the interior of a contact array of the electronic component, and thus there is no place to mount the resistive, capacitive, and/or inductive components.
- a technique for accommodating electronic components on a multilayer signal routing device may be realized as a method for accommodating electronic components on a multilayer signal routing device.
- Such a method may comprise determining a component space that is required to accommodate a plurality of electronic components on a surface of a multilayer signal routing device, and then forming at least one signal routing channel on at least the surface of the multilayer signal routing device, wherein the at least one signal routing channel has a channel space that is equal to or greater than the component space.
- the at least one signal routing channel formed on the surface of the multilayer signal routing device may have a vertical, horizontal, and/or diagonal orientation portion along the surface of the multilayer signal routing device.
- determining a component space may beneficially comprise determining a number of the plurality of electronic components that are to be mounted on the surface of the multilayer signal routing device, and then determining a required space for each of the number of the plurality of electronic components that are to be mounted on the surface of the multilayer signal routing device.
- forming at least one signal routing channel may beneficially comprise forming at least two relatively aligned electrically conductive micro-vias in the multilayer signal routing device coinciding with the location of the at least one signal routing channel formed on the secondary surface of the multilayer signal routing device.
- a plurality of electrically conductive pads may beneficially be formed on a primary surface of the multilayer signal routing device opposite the secondary surface of the multilayer signal routing device. If such is the case, at least two relatively aligned electrically conductive micro-vias may beneficially be formed in the multilayer signal routing device in electrical connection with at least two respective ones of the electrically conductive pads and coinciding with the location of the at least one signal routing channel formed on the secondary surface of the multilayer signal routing device.
- At least a portion of the plurality of electronic components may beneficially be mounted on the secondary surface of the multilayer signal routing device within the at least one signal routing channel formed on the secondary surface of the multilayer signal routing device.
- an electrically conductive pad may beneficially be formed on the secondary surface of the multilayer signal routing device within the at least one signal routing channel formed on the secondary surface of the multilayer signal routing device. If such is the case, at least one of the plurality of electronic components may beneficially be mounted on the secondary surface of the multilayer signal routing device in electrical connection with the electrically conductive pad formed on the secondary surface of the multilayer signal routing device and coinciding with the position of the at least one signal routing channel formed on the secondary surface of the multilayer signal routing device.
- an electrically conductive trace may also beneficially be formed on the secondary surface of the multilayer signal routing device electrically connected to the electrically conductive pad formed on the secondary surface of the multilayer signal routing device.
- the technique may be realized as a novel multilayer signal routing device.
- a multilayer signal routing device may comprise a primary surface having a plurality of electrically conductive pads formed thereon, wherein a group of the plurality of electrically conductive pads is in respective electrical connection with a group of electrically conductive micro-vias formed in the multilayer signal routing device.
- Such a multilayer signal routing device may also comprise a secondary surface having a signal routing channel formed thereon coinciding with the location of the group of electrically conductive micro-vias, wherein the signal routing channel has a channel area on the secondary surface for accommodating an electronic component mounted on the secondary surface.
- the signal routing channel may have a vertical, horizontal, and/or diagonal orientation portion along the secondary surface of the multilayer signal routing device.
- the secondary surface may beneficially have an electrically conductive pad formed thereon within the signal routing channel. If such is the case, the electronic component may beneficially be mounted on the secondary surface within the signal routing channel in electrical connection with the electrically conductive pad formed on the secondary surface.
- the secondary surface may beneficially have an electrically conductive trace formed thereon, wherein the electrically conductive trace is in electrical connection with the electrically conductive pad formed on the secondary surface.
- FIG. 1 shows a portion of a secondary side of a multilayer signal routing device having signal routing channels.
- FIG. 2 shows the portion of the secondary side of the multilayer signal routing device of FIG. 1 having additional electronic components mounted in the signal routing channels in accordance with an embodiment of the present disclosure.
- FIG. 2A shows the portion of the secondary side of the multilayer signal routing device of FIG. 1 having additional electronic components, including logic devices, mounted in the signal routing channels in accordance with an embodiment of the present disclosure.
- FIG. 3 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having additional electronic components mounted in horizontal signal routing channels in accordance with an embodiment of the present disclosure.
- FIG. 4 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having additional electronic components mounted in vertical signal routing channels in accordance with an embodiment of the present disclosure.
- FIG. 5 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having additional electronic components mounted in proximate horizontal signal routing channels in accordance with an embodiment of the present disclosure.
- FIG. 6 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having additional electronic components mounted in proximate vertical signal routing channels in accordance with an embodiment of the present disclosure.
- FIG. 7 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having additional electronic components mounted in signal routing channels configured as a pair of rectangular-shaped pockets or cavities in accordance with an embodiment of the present disclosure.
- FIG. 8 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having additional electronic components mounted in a signal routing channel configured as a single rectangular-shaped pocket or cavity in accordance with an embodiment of the present disclosure.
- FIG. 9 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having signal routing channels configured in both horizontal and vertical directions for accommodating additional electronic components in both the horizontal and vertical directions in accordance with an embodiment of the present disclosure.
- FIG. 10 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having signal routing channels configured in both horizontal and diagonal directions for accommodating additional electronic components in both the horizontal and diagonal directions in accordance with an embodiment of the present disclosure.
- FIG. 11 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having signal routing channels configured in diagonal directions for accommodating additional electronic components in the diagonal directions in accordance with an embodiment of the present disclosure.
- FIG. 12 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having signal routing channels configured in vertical, horizontal, and diagonal directions for accommodating additional electronic components in the vertical, horizontal, and diagonal directions in accordance with an embodiment of the present disclosure.
- FIG. 13 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having signal routing channels configured in vertical, horizontal, and enclosed diagonal directions for accommodating additional electronic components in the vertical, horizontal, and enclosed diagonal directions in accordance with an embodiment of the present disclosure.
- the multilayer signal routing device portion 100 comprises a plurality of electrically conductive pads 102 formed thereon, each of which is preferably electrically connected to an electrically conductive via (not shown) formed in the multilayer signal routing device portion 100 .
- the plurality of electrically conductive pads 102 through respective ones of the electrically conductive vias, are electrically connected to electrically conductive pads (not shown) formed on a primary side (i.e., the opposite side) of the multilayer signal routing device portion 100 .
- These electrically conductive pads formed on the primary side of the multilayer signal routing device portion 100 are electrically connected to electrically conductive contacts of an electronic component (not shown) that is mounted on the primary side of the multilayer signal routing device portion 100 .
- the electronic component that is mounted on the primary side of the multilayer signal routing device portion 100 has a 20 ⁇ 20 array of electrically conductive contacts formed thereon. As shown in FIG. 1 , some of the electrically conductive contacts in the 20 ⁇ 20 array of electrically conductive contacts formed on the electronic component are not electrically connected to respective ones of the electrically conductive pads 102 formed on the secondary side of the multilayer signal routing device portion 100 . Those electrically conductive contacts of the electronic component that are not electrically connected to respective ones of the electrically conductive pads 102 formed on the secondary side of the multilayer signal routing device portion 100 may instead be electrically connected to additional electrically conductive pads formed on the primary side of the multilayer signal routing device portion 100 .
- These additional electrically conductive pads formed on the primary side of the multilayer signal routing device portion 100 may in turn be electrically connected to micro-vias (not shown) formed in the multilayer signal routing device portion 100 .
- These micro-vias may be arranged to form signal routing channels 104 on the secondary side of the multilayer signal routing device portion 100 , as well as within one or more internal layers of the multilayer signal routing device portion 100 , as described in the above-referenced techniques for reducing the number of layers in a multilayer signal routing device.
- some of those electrically conductive contacts of the electronic component that are not electrically connected to respective ones of the electrically conductive pads 102 formed on the secondary side of the multilayer signal routing device portion 100 may not be electrically connected to any electrically conductive pads formed on the primary side of the multilayer signal routing device portion 100 .
- some of those electrically conductive contacts of the electronic component that are not electrically connected to respective ones of the electrically conductive pads 102 formed on the secondary side of the multilayer signal routing device portion 100 may be used for testing the electronic component when the electronic component is not mounted on the multilayer signal routing device portion 100 .
- the signal routing channels 104 are very beneficial for reducing the number of layers in a multilayer signal routing device as described in the above-referenced techniques, the signal routing channels 104 may also be used to provide valuable space for mounting additional electronic components on the secondary side of the multilayer signal routing device portion 100 in accordance with an embodiment of the present disclosure.
- FIG. 2 there are shown multiple additional electronic components 106 mounted on the secondary side of the multilayer signal routing device portion 100 within the signal routing channels 104 .
- the multiple additional electronic components 106 are electrically connected to respective ones of the electrically conductive pads 102 formed on the secondary side of the multilayer signal routing device portion 100 by electrical connections 108 .
- the multiple additional electronic components 106 may be discrete resistive, capacitive, and/or inductive components.
- one or more of the multiple additional electronic components 106 A may be active electronic components such as, for example, logic circuitry.
- the electrical connections 108 may be electrically conductive traces formed on the secondary side of the multilayer signal routing device portion 100 .
- the multiple additional electronic components 106 may have electrically conductive contacts (e.g., surface mount pads) which may be mounted on respective mating electrically conductive pads (not shown) formed on the secondary side of the multilayer signal routing device portion 100 .
- electrically conductive contacts e.g., surface mount pads
- mating electrically conductive pads formed on the secondary side of the multilayer signal routing device portion 100 are electrically connected to respective electrically conductive traces.
- the electrical connections 108 may be electrically conductive leads associated with the multiple additional electronic components 106 .
- the multiple additional electronic components 106 may be mounted on the secondary side of the multilayer signal routing device portion 100 with a non-electrically conductive adhesive while the electrically conductive leads are separately electrically connected to respective ones of the electrically conductive pads 102 .
- the multiple additional electronic components 106 may even be mounted on top of surface mount components, which themselves are mounted on the secondary side of the multilayer signal routing device portion 100 within the signal routing channels 104 , thereby forming stacked component structures so as to further increase component density on the multilayer signal routing device portion 100 .
- the signal routing channels 104 may be used to provide valuable space for mounting the additional electronic components 106 on the secondary side of the multilayer signal routing device portion 100 in accordance with an embodiment of the present disclosure.
- An important benefit associated with the mounting of these additional electronic components 106 on the secondary side of the multilayer signal routing device portion 100 is that signal integrity may be improved when the additional electronic components 106 (e.g., resistive, capacitive, and/or inductive components) are mounted on the multilayer signal routing device 100 near a signal driver contact of the electronic component.
- An additional side benefit associated with the mounting of these additional electronic components 106 on the secondary side of the multilayer signal routing device portion 100 is that these additional electronic components 106 may be mounted in an orderly and logical fashion so as to facilitate troubleshooting in a laboratory environment.
- the total amount of space that is required to accommodate all of the additional electronic components 106 that are required for a particular design For example, assuming a worst case signal-to-ground ratio of 2:1, and that each signal must be attached to one of the additional electronic components 106 , the total number of additional electronic components 106 required for an electronic component having M ⁇ N array of electrically conductive contacts formed thereon is approximately (M ⁇ N)/3. Thus, the total amount of space that is required to accommodate all of the additional electronic components 106 that are required for a particular design is (M ⁇ N)/3*(space required for the additional electronic component 106 , including any required clearance surrounding the additional electronic component 106 ).
- the required number and size of signal routing channels 104 may be created using the above-referenced techniques for reducing the number of layers in a multilayer signal routing device.
- the signal routing channels 104 may be configured in a variety of ways to achieve the total amount of space that is required to accommodate all of the additional electronic components 106 .
- FIG. 3 there is shown an alternate embodiment of a portion of a secondary side of a multilayer signal routing device 300 .
- the signal routing channels 104 are all configured in a horizontal direction for accommodating all of the additional electronic components 106 in a similar horizontal direction.
- FIG. 4 there is shown another alternate embodiment of a portion of a secondary side of a multilayer signal routing device 400 .
- the signal routing channels 104 are all configured in a vertical direction for accommodating all of the additional electronic components 106 in a similar vertical direction.
- FIG. 5 there is shown another alternate embodiment of a portion of a secondary side of a multilayer signal routing device 500 .
- the signal routing channels 104 are all configured in a horizontal direction for accommodating all of the additional electronic components 106 in a similar horizontal direction. Also, pairs of the additional electronic components 106 are electrically connected together via electrical connections 108 .
- FIG. 6 there is shown another alternate embodiment of a portion of a secondary side of a multilayer signal routing device 600 .
- the signal routing channels 104 are all configured in a vertical direction for accommodating all of the additional electronic components 106 in a similar vertical direction. Also, pairs of the additional electronic components 106 are electrically connected together via electrical connections 108 .
- the signal routing channels 104 are configured as a pair of rectangular-shaped pockets or cavities surrounded by electrically conductive pads 102 for accommodating all of the additional electronic components 106 within the rectangular-shaped pockets or cavities. Also, pairs of the additional electronic components 106 are electrically connected together via electrical connections 108 .
- the signal routing channel 104 is configured as a single rectangular-shaped pocket or cavity (e.g., formed by combining multiple smaller-width signal routing channels) surrounded by electrically conductive pads 102 for accommodating all of the additional electronic components 106 within the single rectangular-shaped pocket or cavity. Also, pairs of the additional electronic components 106 are electrically connected together via electrical connections 108 .
- FIG. 9 there is shown another alternate embodiment of a portion of a secondary side of a multilayer signal routing device 900 (although without the additional electronic components 106 shown).
- the signal routing channels 104 are configured in both horizontal and vertical directions for accommodating all of the additional electronic components 106 in both the horizontal and vertical directions.
- FIG. 10 there is shown another alternate embodiment of a portion of a secondary side of a multilayer signal routing device 1000 (although without the additional electronic components 106 shown).
- the signal routing channels 104 are configured in both horizontal and diagonal directions for accommodating all of the additional electronic components 106 in both the horizontal and diagonal directions.
- FIG. 11 there is shown another alternate embodiment of a portion of a secondary side of a multilayer signal routing device 1100 (although without the additional electronic components 106 shown).
- the signal routing channels 104 are configured in diagonal directions for accommodating all of the additional electronic components 106 in the diagonal directions.
- FIG. 12 there is shown another alternate embodiment of a portion of a secondary side of a multilayer signal routing device 1200 (although without the additional electronic components 106 shown).
- the signal routing channels 104 are configured in vertical, horizontal, and diagonal directions for accommodating all of the additional electronic components 106 in the vertical, horizontal, and diagonal directions.
- FIG. 13 there is shown another alternate embodiment of a portion of a secondary side of a multilayer signal routing device 1300 (although without the additional electronic components 106 shown).
- the signal routing channels 104 are configured in vertical, horizontal, and enclosed diagonal directions for accommodating all of the additional electronic components 106 in the vertical, horizontal, and enclosed diagonal directions.
Abstract
Description
- This patent application is a divisional of U.S. patent application Ser. No. 10/716,599, filed Nov. 20, 2003, which claims priority to U.S. Provisional Patent Application No. 60/427,865, filed Nov. 20, 2002, each of which is hereby incorporated by reference herein in its entirety.
- The above-referenced U.S. patent application Ser. No. 10/716,599 is a continuation-in-part of U.S. patent application Ser. No. 10/101,211, filed Mar. 20, 2002, which is a continuation-in-part of U.S. patent application Ser. No. 09/651,188, filed Aug. 30, 2000, now U.S. Pat. No. 6,388,890, which claims priority to U.S. Provisional Patent Application No. 60/212,387, filed Jun. 19, 2000, each of which is hereby incorporated by reference herein in its entirety.
- The above-referenced U.S. patent application Ser. No. 10/716,599 is also a continuation-in-part of U.S. patent application Ser. No. 10/326,123, filed Dec. 23, 2002, now U.S. Pat. No. 7,069,650, which is a continuation-in-part of the above-referenced U.S. patent application Ser. No. 10/101,211, and a continuation-in-part of U.S. patent application Ser. No. 10/126,700, filed Apr. 22, 2002, now U.S. Pat. No. 6,545,876, which is a continuation of the above-referenced U.S. patent application Ser. No. 09/651,188, each of which is hereby incorporated by reference herein in its entirety.
- The above-referenced U.S. patent application Ser. No. 10/716,599 is also a continuation-in-part of U.S. patent application Ser. No. 10/326,079, filed Dec. 23, 2002, which is a continuation-in-part of the above-referenced U.S. patent application Ser. No. 10/126,700, and a continuation-in-part of the above-referenced U.S. patent application Ser. No. 10/101,211, each of which is hereby incorporated by reference herein in its entirety.
- The above-referenced U.S. patent application Ser. No. 10/716,599 is also a continuation-in-part of U.S. patent application Ser. No. 10/407,460, filed Apr. 7, 2003, now U.S. Pat. No. 7,069,646, which is a continuation-in-part of the above-referenced U.S. patent application Ser. No. 10/126,700, a continuation-in-part of the above-referenced U.S. patent application Ser. No. 10/101,211, a continuation-in-part of the above-referenced U.S. patent application Ser. No. 10/326,123, and a continuation-in-part of the above-referenced U.S. patent application Ser. No. 10/326,079, each of which is hereby incorporated by reference herein in its entirety.
- The present disclosure relates generally to multilayer signal routing devices and, more particularly, to a technique for accommodating electronic components on a multilayer signal routing device.
- The making of electrical connections between electronic components has long been accomplished using printed circuit boards (PCBs). The first such circuit boards had only a single routing layer on a top surface thereof for routing electrical signals between electronic components mounted thereon. These single routing layer circuit boards have severe limitations with regard to the number of electrical signals that can be routed between electronic components mounted on the same circuit board. That is, the number of electrical signals that can be routed between electronic components mounted on a single routing layer circuit board is limited by the amount of area on the single routing layer.
- The area limitations associated with single routing layer circuit boards led to the development of multilayer PCBs. Such multilayer PCBs may be either single or double-sided and may have multiple routing layers on the surface of and buried within the multilayer PCBs. Thus, such multilayer PCBs have allowed a large increase in the number of electrical signals that may be routed between electronic components mounted on the same circuit board.
- The use of multilayer PCBs has been particularly beneficial when using electronic components having high-density packages. That is, electronic components having high-density packages generally require multiple layers of a multilayer PCB to make electrical connections with other electronic components mounted on the same circuit board. In fact, the density of electronic component packages typically dictates the number of layers that must be provided by the multilayer PCB upon which the electronic components are mounted. While the number of layers that may be provided by a multilayer PCB is theoretically unlimited, reliability and other problems occur when the number of layers in a multilayer PCB exceeds a reasonable number, particularly when trying to route high-speed electrical signals between electronic components. For example, when making electrical connections between different layers in multilayer PCBs, a combination of electrically conductive traces and electrically conductive vias are generally used. While electrically conductive vias allow direct vertical electrical connections to be made between different layers within a multilayer PCB, there are intrinsic parasitics associated with these electrically conductive vias that can adversely affect the performance of signals propagating therethrough. That is, these electrically conductive vias have intrinsic parasitic resistance, capacitance, and inductance, which can adversely affect signals propagating along each electrically conductive via. In addition, these intrinsic parasitics can also have an adverse effect on the manufacturability of a PCB and thus the cost thereof. Because of their adverse affect on signal performance, these intrinsic parasitics can also limit the bandwidth of signals propagating along each electrically conductive via. These adverse affects only increase as the number of layers in a multilayer PCB increase.
- To alleviate at least some of the above-mentioned adverse effects, it is often helpful to have resistive, capacitive, and/or inductive components electrically connected in series and/or parallel with an electrically conductive via, which is also electrically connected to a signal driver contact of an electronic component. However, this if often difficult to achieve since the signal driver contact may be located within the interior of a contact array of the electronic component, and thus there is no place to mount the resistive, capacitive, and/or inductive components. Even if the signal driver contact is located along the periphery of a contact array of the electronic component, there may still be no place to mount the resistive, capacitive, and/or inductive components since electronic components are now being placed ever closer together on the surfaces of PCB's and other types of multilayer signal routing devices.
- One proposed solution to the problem of mounting resistive, capacitive, and/or inductive components since electronic components near a signal driver contact of an electronic component is to bury or embed the resistive, capacitive, and/or inductive components within a PCB or other type of multilayer signal routing device. However, the cost and maturity of suitable technologies for this proposed solution make it impractical.
- In view of the foregoing, it would be desirable to provide a technique for mounting resistive, capacitive, and/or inductive components on a multilayer signal routing device near a signal driver contact of an electronic component that overcomes the above-described inadequacies and shortcomings.
- According to the present disclosure, a technique for accommodating electronic components on a multilayer signal routing device is provided. In one particular exemplary embodiment, the technique may be realized as a method for accommodating electronic components on a multilayer signal routing device. Such a method may comprise determining a component space that is required to accommodate a plurality of electronic components on a surface of a multilayer signal routing device, and then forming at least one signal routing channel on at least the surface of the multilayer signal routing device, wherein the at least one signal routing channel has a channel space that is equal to or greater than the component space. The at least one signal routing channel formed on the surface of the multilayer signal routing device may have a vertical, horizontal, and/or diagonal orientation portion along the surface of the multilayer signal routing device.
- In accordance with other aspects of this particular exemplary embodiment of the present disclosure, determining a component space may beneficially comprise determining a number of the plurality of electronic components that are to be mounted on the surface of the multilayer signal routing device, and then determining a required space for each of the number of the plurality of electronic components that are to be mounted on the surface of the multilayer signal routing device.
- In accordance with further aspects of this particular exemplary embodiment of the present disclosure, forming at least one signal routing channel may beneficially comprise forming at least two relatively aligned electrically conductive micro-vias in the multilayer signal routing device coinciding with the location of the at least one signal routing channel formed on the secondary surface of the multilayer signal routing device.
- In accordance with additional aspects of this particular exemplary embodiment of the present disclosure, wherein the surface of the multilayer signal routing device is a secondary surface of the multilayer signal routing device, a plurality of electrically conductive pads may beneficially be formed on a primary surface of the multilayer signal routing device opposite the secondary surface of the multilayer signal routing device. If such is the case, at least two relatively aligned electrically conductive micro-vias may beneficially be formed in the multilayer signal routing device in electrical connection with at least two respective ones of the electrically conductive pads and coinciding with the location of the at least one signal routing channel formed on the secondary surface of the multilayer signal routing device. At least a portion of the plurality of electronic components may beneficially be mounted on the secondary surface of the multilayer signal routing device within the at least one signal routing channel formed on the secondary surface of the multilayer signal routing device. Also, an electrically conductive pad may beneficially be formed on the secondary surface of the multilayer signal routing device within the at least one signal routing channel formed on the secondary surface of the multilayer signal routing device. If such is the case, at least one of the plurality of electronic components may beneficially be mounted on the secondary surface of the multilayer signal routing device in electrical connection with the electrically conductive pad formed on the secondary surface of the multilayer signal routing device and coinciding with the position of the at least one signal routing channel formed on the secondary surface of the multilayer signal routing device. Of course, an electrically conductive trace may also beneficially be formed on the secondary surface of the multilayer signal routing device electrically connected to the electrically conductive pad formed on the secondary surface of the multilayer signal routing device.
- In another particular exemplary embodiment, the technique may be realized as a novel multilayer signal routing device. Such a multilayer signal routing device may comprise a primary surface having a plurality of electrically conductive pads formed thereon, wherein a group of the plurality of electrically conductive pads is in respective electrical connection with a group of electrically conductive micro-vias formed in the multilayer signal routing device. Such a multilayer signal routing device may also comprise a secondary surface having a signal routing channel formed thereon coinciding with the location of the group of electrically conductive micro-vias, wherein the signal routing channel has a channel area on the secondary surface for accommodating an electronic component mounted on the secondary surface. The signal routing channel may have a vertical, horizontal, and/or diagonal orientation portion along the secondary surface of the multilayer signal routing device.
- In accordance with other aspects of this particular exemplary embodiment of the present disclosure, the secondary surface may beneficially have an electrically conductive pad formed thereon within the signal routing channel. If such is the case, the electronic component may beneficially be mounted on the secondary surface within the signal routing channel in electrical connection with the electrically conductive pad formed on the secondary surface. Of course, the secondary surface may beneficially have an electrically conductive trace formed thereon, wherein the electrically conductive trace is in electrical connection with the electrically conductive pad formed on the secondary surface.
- The present disclosure will now be described in more detail with reference to exemplary embodiments thereof as shown in the accompanying drawings. While the present disclosure is described below with reference to exemplary embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present disclosure as described herein, and with respect to which the present disclosure may be of significant utility.
- In order to facilitate a fuller understanding of the present disclosure, reference is now made to the accompanying drawings, in which like elements are referenced with like numerals. These drawings should not be construed as limiting the present disclosure, but are intended to be exemplary only.
-
FIG. 1 shows a portion of a secondary side of a multilayer signal routing device having signal routing channels. -
FIG. 2 shows the portion of the secondary side of the multilayer signal routing device ofFIG. 1 having additional electronic components mounted in the signal routing channels in accordance with an embodiment of the present disclosure. -
FIG. 2A shows the portion of the secondary side of the multilayer signal routing device ofFIG. 1 having additional electronic components, including logic devices, mounted in the signal routing channels in accordance with an embodiment of the present disclosure. -
FIG. 3 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having additional electronic components mounted in horizontal signal routing channels in accordance with an embodiment of the present disclosure. -
FIG. 4 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having additional electronic components mounted in vertical signal routing channels in accordance with an embodiment of the present disclosure. -
FIG. 5 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having additional electronic components mounted in proximate horizontal signal routing channels in accordance with an embodiment of the present disclosure. -
FIG. 6 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having additional electronic components mounted in proximate vertical signal routing channels in accordance with an embodiment of the present disclosure. -
FIG. 7 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having additional electronic components mounted in signal routing channels configured as a pair of rectangular-shaped pockets or cavities in accordance with an embodiment of the present disclosure. -
FIG. 8 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having additional electronic components mounted in a signal routing channel configured as a single rectangular-shaped pocket or cavity in accordance with an embodiment of the present disclosure. -
FIG. 9 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having signal routing channels configured in both horizontal and vertical directions for accommodating additional electronic components in both the horizontal and vertical directions in accordance with an embodiment of the present disclosure. -
FIG. 10 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having signal routing channels configured in both horizontal and diagonal directions for accommodating additional electronic components in both the horizontal and diagonal directions in accordance with an embodiment of the present disclosure. -
FIG. 11 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having signal routing channels configured in diagonal directions for accommodating additional electronic components in the diagonal directions in accordance with an embodiment of the present disclosure. -
FIG. 12 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having signal routing channels configured in vertical, horizontal, and diagonal directions for accommodating additional electronic components in the vertical, horizontal, and diagonal directions in accordance with an embodiment of the present disclosure. -
FIG. 13 shows an alternate embodiment of a portion of a secondary side of a multilayer signal routing device having signal routing channels configured in vertical, horizontal, and enclosed diagonal directions for accommodating additional electronic components in the vertical, horizontal, and enclosed diagonal directions in accordance with an embodiment of the present disclosure. - At the outset, it is helpful to refer to the techniques for reducing the number of layers in a multilayer signal routing device as have been substantially described in the above-referenced U.S. Provisional Patent Application No. 60/212,387, the above-referenced U.S. patent application Ser. No. 09/651,188 (now U.S. Pat. No. 6,388,890), the above-referenced U.S. patent application Ser. No. 10/101,211, the above-referenced U.S. patent application Ser. No. 10/126,700 (now U.S. Pat. No. 6,545,876), the above-referenced U.S. patent application Ser. No. 10/326,123, the above-referenced U.S. patent application Ser. No. 10/326,079, and the above-referenced U.S. patent application Ser. No. 10/407,460, all of which have been incorporated by reference herein in their entirety.
- The above-referenced techniques are certainly beneficial for reducing the number of layers in a multilayer signal routing device. However, these techniques may be even more beneficial if used in conjunction with one or more of the several techniques described herein.
- Referring to
FIG. 1 , there is shown a portion of a secondary side of a multilayersignal routing device 100. The multilayer signalrouting device portion 100 comprises a plurality of electricallyconductive pads 102 formed thereon, each of which is preferably electrically connected to an electrically conductive via (not shown) formed in the multilayer signalrouting device portion 100. The plurality of electricallyconductive pads 102, through respective ones of the electrically conductive vias, are electrically connected to electrically conductive pads (not shown) formed on a primary side (i.e., the opposite side) of the multilayer signalrouting device portion 100. These electrically conductive pads formed on the primary side of the multilayer signalrouting device portion 100 are electrically connected to electrically conductive contacts of an electronic component (not shown) that is mounted on the primary side of the multilayer signalrouting device portion 100. - In the embodiment of
FIG. 1 , the electronic component that is mounted on the primary side of the multilayer signalrouting device portion 100 has a 20×20 array of electrically conductive contacts formed thereon. As shown inFIG. 1 , some of the electrically conductive contacts in the 20×20 array of electrically conductive contacts formed on the electronic component are not electrically connected to respective ones of the electricallyconductive pads 102 formed on the secondary side of the multilayer signalrouting device portion 100. Those electrically conductive contacts of the electronic component that are not electrically connected to respective ones of the electricallyconductive pads 102 formed on the secondary side of the multilayer signalrouting device portion 100 may instead be electrically connected to additional electrically conductive pads formed on the primary side of the multilayer signalrouting device portion 100. These additional electrically conductive pads formed on the primary side of the multilayer signalrouting device portion 100 may in turn be electrically connected to micro-vias (not shown) formed in the multilayer signalrouting device portion 100. These micro-vias may be arranged to formsignal routing channels 104 on the secondary side of the multilayer signalrouting device portion 100, as well as within one or more internal layers of the multilayer signalrouting device portion 100, as described in the above-referenced techniques for reducing the number of layers in a multilayer signal routing device. - At this point it should be noted that some of those electrically conductive contacts of the electronic component that are not electrically connected to respective ones of the electrically
conductive pads 102 formed on the secondary side of the multilayer signalrouting device portion 100 may not be electrically connected to any electrically conductive pads formed on the primary side of the multilayer signalrouting device portion 100. For example, some of those electrically conductive contacts of the electronic component that are not electrically connected to respective ones of the electricallyconductive pads 102 formed on the secondary side of the multilayer signalrouting device portion 100 may be used for testing the electronic component when the electronic component is not mounted on the multilayer signalrouting device portion 100. - While the
signal routing channels 104 are very beneficial for reducing the number of layers in a multilayer signal routing device as described in the above-referenced techniques, thesignal routing channels 104 may also be used to provide valuable space for mounting additional electronic components on the secondary side of the multilayer signalrouting device portion 100 in accordance with an embodiment of the present disclosure. For example, referring toFIG. 2 , there are shown multiple additionalelectronic components 106 mounted on the secondary side of the multilayer signalrouting device portion 100 within thesignal routing channels 104. As also shown inFIG. 2 , the multiple additionalelectronic components 106 are electrically connected to respective ones of the electricallyconductive pads 102 formed on the secondary side of the multilayer signalrouting device portion 100 byelectrical connections 108. - At this point it should be noted that, as shown in
FIG. 2 , the multiple additionalelectronic components 106 may be discrete resistive, capacitive, and/or inductive components. Alternatively, as shown inFIG. 2A , one or more of the multiple additionalelectronic components 106A may be active electronic components such as, for example, logic circuitry. - It should also be noted that the
electrical connections 108 may be electrically conductive traces formed on the secondary side of the multilayer signalrouting device portion 100. In such a case, the multiple additionalelectronic components 106 may have electrically conductive contacts (e.g., surface mount pads) which may be mounted on respective mating electrically conductive pads (not shown) formed on the secondary side of the multilayer signalrouting device portion 100. Of course, these mating electrically conductive pads formed on the secondary side of the multilayer signalrouting device portion 100 are electrically connected to respective electrically conductive traces. - Alternatively, the
electrical connections 108 may be electrically conductive leads associated with the multiple additionalelectronic components 106. In such a case, the multiple additionalelectronic components 106 may be mounted on the secondary side of the multilayer signalrouting device portion 100 with a non-electrically conductive adhesive while the electrically conductive leads are separately electrically connected to respective ones of the electricallyconductive pads 102. Indeed, the multiple additionalelectronic components 106 may even be mounted on top of surface mount components, which themselves are mounted on the secondary side of the multilayer signalrouting device portion 100 within thesignal routing channels 104, thereby forming stacked component structures so as to further increase component density on the multilayer signalrouting device portion 100. - As shown in
FIG. 2 , thesignal routing channels 104 may be used to provide valuable space for mounting the additionalelectronic components 106 on the secondary side of the multilayer signalrouting device portion 100 in accordance with an embodiment of the present disclosure. An important benefit associated with the mounting of these additionalelectronic components 106 on the secondary side of the multilayer signalrouting device portion 100 is that signal integrity may be improved when the additional electronic components 106 (e.g., resistive, capacitive, and/or inductive components) are mounted on the multilayersignal routing device 100 near a signal driver contact of the electronic component. An additional side benefit associated with the mounting of these additionalelectronic components 106 on the secondary side of the multilayer signalrouting device portion 100 is that these additionalelectronic components 106 may be mounted in an orderly and logical fashion so as to facilitate troubleshooting in a laboratory environment. - At this point it should be noted that an empirical prediction may be made regarding the total amount of space that is required to accommodate all of the additional
electronic components 106 that are required for a particular design. For example, assuming a worst case signal-to-ground ratio of 2:1, and that each signal must be attached to one of the additionalelectronic components 106, the total number of additionalelectronic components 106 required for an electronic component having M×N array of electrically conductive contacts formed thereon is approximately (M×N)/3. Thus, the total amount of space that is required to accommodate all of the additionalelectronic components 106 that are required for a particular design is (M×N)/3*(space required for the additionalelectronic component 106, including any required clearance surrounding the additional electronic component 106). Once the total amount of space is determined, the required number and size ofsignal routing channels 104 may be created using the above-referenced techniques for reducing the number of layers in a multilayer signal routing device. - At this point it should be noted that the
signal routing channels 104 may be configured in a variety of ways to achieve the total amount of space that is required to accommodate all of the additionalelectronic components 106. For example, referring toFIG. 3 , there is shown an alternate embodiment of a portion of a secondary side of a multilayersignal routing device 300. In the embodiment ofFIG. 3 , thesignal routing channels 104 are all configured in a horizontal direction for accommodating all of the additionalelectronic components 106 in a similar horizontal direction. - Referring to
FIG. 4 , there is shown another alternate embodiment of a portion of a secondary side of a multilayersignal routing device 400. In the embodiment ofFIG. 4 , thesignal routing channels 104 are all configured in a vertical direction for accommodating all of the additionalelectronic components 106 in a similar vertical direction. - Referring to
FIG. 5 , there is shown another alternate embodiment of a portion of a secondary side of a multilayersignal routing device 500. In the embodiment ofFIG. 5 , thesignal routing channels 104 are all configured in a horizontal direction for accommodating all of the additionalelectronic components 106 in a similar horizontal direction. Also, pairs of the additionalelectronic components 106 are electrically connected together viaelectrical connections 108. - Referring to
FIG. 6 , there is shown another alternate embodiment of a portion of a secondary side of a multilayersignal routing device 600. In the embodiment ofFIG. 6 , thesignal routing channels 104 are all configured in a vertical direction for accommodating all of the additionalelectronic components 106 in a similar vertical direction. Also, pairs of the additionalelectronic components 106 are electrically connected together viaelectrical connections 108. - Referring to
FIG. 7 , there is shown another alternate embodiment of a portion of a secondary side of a multilayersignal routing device 700. In the embodiment ofFIG. 7 , thesignal routing channels 104 are configured as a pair of rectangular-shaped pockets or cavities surrounded by electricallyconductive pads 102 for accommodating all of the additionalelectronic components 106 within the rectangular-shaped pockets or cavities. Also, pairs of the additionalelectronic components 106 are electrically connected together viaelectrical connections 108. - Referring to
FIG. 8 , there is shown another alternate embodiment of a portion of a secondary side of a multilayersignal routing device 800. In the embodiment ofFIG. 8 , thesignal routing channel 104 is configured as a single rectangular-shaped pocket or cavity (e.g., formed by combining multiple smaller-width signal routing channels) surrounded by electricallyconductive pads 102 for accommodating all of the additionalelectronic components 106 within the single rectangular-shaped pocket or cavity. Also, pairs of the additionalelectronic components 106 are electrically connected together viaelectrical connections 108. - Referring to
FIG. 9 , there is shown another alternate embodiment of a portion of a secondary side of a multilayer signal routing device 900 (although without the additionalelectronic components 106 shown). In the embodiment ofFIG. 9 , thesignal routing channels 104 are configured in both horizontal and vertical directions for accommodating all of the additionalelectronic components 106 in both the horizontal and vertical directions. - Referring to
FIG. 10 , there is shown another alternate embodiment of a portion of a secondary side of a multilayer signal routing device 1000 (although without the additionalelectronic components 106 shown). In the embodiment ofFIG. 10 , thesignal routing channels 104 are configured in both horizontal and diagonal directions for accommodating all of the additionalelectronic components 106 in both the horizontal and diagonal directions. - Referring to
FIG. 11 , there is shown another alternate embodiment of a portion of a secondary side of a multilayer signal routing device 1100 (although without the additionalelectronic components 106 shown). In the embodiment ofFIG. 11 , thesignal routing channels 104 are configured in diagonal directions for accommodating all of the additionalelectronic components 106 in the diagonal directions. - Referring to
FIG. 12 , there is shown another alternate embodiment of a portion of a secondary side of a multilayer signal routing device 1200 (although without the additionalelectronic components 106 shown). In the embodiment ofFIG. 12 , thesignal routing channels 104 are configured in vertical, horizontal, and diagonal directions for accommodating all of the additionalelectronic components 106 in the vertical, horizontal, and diagonal directions. - Referring to
FIG. 13 , there is shown another alternate embodiment of a portion of a secondary side of a multilayer signal routing device 1300 (although without the additionalelectronic components 106 shown). In the embodiment ofFIG. 13 , thesignal routing channels 104 are configured in vertical, horizontal, and enclosed diagonal directions for accommodating all of the additionalelectronic components 106 in the vertical, horizontal, and enclosed diagonal directions. - The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.
Claims (5)
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US11/488,799 US20060254810A1 (en) | 2000-06-19 | 2006-07-19 | Technique for accommodating electronic components on a multilayer signal routing device |
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US09/651,188 US6388890B1 (en) | 2000-06-19 | 2000-08-30 | Technique for reducing the number of layers in a multilayer circuit board |
US10/101,211 US7256354B2 (en) | 2000-06-19 | 2002-03-20 | Technique for reducing the number of layers in a multilayer circuit board |
US10/126,700 US6545876B1 (en) | 2000-06-19 | 2002-04-22 | Technique for reducing the number of layers in a multilayer circuit board |
US42786502P | 2002-11-20 | 2002-11-20 | |
US10/326,079 US20040003941A1 (en) | 2000-06-19 | 2002-12-23 | Technique for electrically interconnecting electrical signals between an electronic component and a multilayer signal routing device |
US10/326,123 US7069650B2 (en) | 2000-06-19 | 2002-12-23 | Method for reducing the number of layers in a multilayer signal routing device |
US10/407,460 US7069646B2 (en) | 2000-06-19 | 2003-04-07 | Techniques for reducing the number of layers in a multilayer signal routing device |
US10/716,599 US7107673B2 (en) | 2000-06-19 | 2003-11-20 | Technique for accommodating electronic components on a multiplayer signal routing device |
US11/488,799 US20060254810A1 (en) | 2000-06-19 | 2006-07-19 | Technique for accommodating electronic components on a multilayer signal routing device |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090174072A1 (en) * | 2008-01-04 | 2009-07-09 | Texas Instruments Incorporated | Semiconductor system having bga package with radially ball-depopulated substrate zones and board with radial via zones |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7107673B2 (en) * | 2000-06-19 | 2006-09-19 | Nortel Networks Limited | Technique for accommodating electronic components on a multiplayer signal routing device |
US7725860B1 (en) * | 2000-06-19 | 2010-05-25 | Herman Kwong | Contact mapping using channel routing |
US7738259B2 (en) * | 2004-01-22 | 2010-06-15 | Alcatel Lucent | Shared via decoupling for area arrays components |
US7365435B2 (en) * | 2005-08-10 | 2008-04-29 | Alcatel | Alternating micro-vias and throughboard vias to create PCB routing channels in BGA interconnect grid |
JP4844080B2 (en) * | 2005-10-18 | 2011-12-21 | 日本電気株式会社 | Printed wiring board and method for suppressing power supply noise thereof |
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US20080185181A1 (en) * | 2006-11-08 | 2008-08-07 | Pfeil Charles L | Alternating via fanout patterns |
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US9372205B2 (en) * | 2014-01-15 | 2016-06-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Universal probe card PCB design |
Citations (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5006820A (en) * | 1989-07-03 | 1991-04-09 | Motorola, Inc. | Low reflection input configuration for integrated circuit packages |
US5208604A (en) * | 1988-10-31 | 1993-05-04 | Canon Kabushiki Kaisha | Ink jet head and manufacturing method thereof, and ink jet apparatus with ink jet head |
US5249098A (en) * | 1991-08-22 | 1993-09-28 | Lsi Logic Corporation | Semiconductor device package with solder bump electrical connections on an external surface of the package |
US5281151A (en) * | 1991-07-05 | 1994-01-25 | Hitachi, Ltd. | Semiconductor chip carrier, module having same chip carrier mounted therein, and electronic device incorporating same module |
US5315069A (en) * | 1992-10-02 | 1994-05-24 | Compaq Computer Corp. | Electromagnetic radiation reduction technique using grounded conductive traces circumscribing internal planes of printed circuit boards |
US5357403A (en) * | 1990-06-29 | 1994-10-18 | General Electric Company | Adaptive lithography in a high density interconnect structure whose signal layers have fixed patterns |
US5384433A (en) * | 1991-10-29 | 1995-01-24 | Aptix Corporation | Printed circuit structure including power, decoupling and signal termination |
US5451721A (en) * | 1990-09-27 | 1995-09-19 | International Business Machines Corporation | Multilayer printed circuit board and method for fabricating same |
US5544018A (en) * | 1994-04-13 | 1996-08-06 | Microelectronics And Computer Technology Corporation | Electrical interconnect device with customizeable surface layer and interwoven signal lines |
US5686764A (en) * | 1996-03-20 | 1997-11-11 | Lsi Logic Corporation | Flip chip package with reduced number of package layers |
US6194668B1 (en) * | 1997-12-22 | 2001-02-27 | Shinko Electric Industries Co., Ltd. | Multi-layer circuit board |
US6198635B1 (en) * | 1999-05-18 | 2001-03-06 | Vsli Technology, Inc. | Interconnect layout pattern for integrated circuit packages and the like |
US6246112B1 (en) * | 1998-06-11 | 2001-06-12 | Intel Corporation | Interleaved signal trace routing |
US6271478B1 (en) * | 1997-11-19 | 2001-08-07 | Shinko Electric Industries Co., Ltd. | Multi-layer circuit board |
US6310398B1 (en) * | 1998-12-03 | 2001-10-30 | Walter M. Katz | Routable high-density interfaces for integrated circuit devices |
US6335493B1 (en) * | 1998-12-01 | 2002-01-01 | Shinko Electric Industries, Co., Ltd. | Multilayer wiring board |
US20020008314A1 (en) * | 1999-04-19 | 2002-01-24 | Yasushi Takeuchi | Semiconductor integrated circuit and printed wiring substrate provided with the same |
US6365975B1 (en) * | 1997-04-02 | 2002-04-02 | Tessera, Inc. | Chip with internal signal routing in external element |
US6384467B1 (en) * | 1997-06-06 | 2002-05-07 | Motorola, Inc. | Method for forming a cavity capable of accessing deep fuse structures and device containing the same |
US6388890B1 (en) * | 2000-06-19 | 2002-05-14 | Nortel Networks Limited | Technique for reducing the number of layers in a multilayer circuit board |
US6407343B1 (en) * | 1999-07-16 | 2002-06-18 | Nec Corporation | Multilayer wiring board |
US6452262B1 (en) * | 2001-02-12 | 2002-09-17 | Lsi Logic Corporation | Layout of Vdd and Vss balls in a four layer PBGA |
US6521846B1 (en) * | 2002-01-07 | 2003-02-18 | Sun Microsystems, Inc. | Method for assigning power and ground pins in array packages to enhance next level routing |
US20030043560A1 (en) * | 2001-06-15 | 2003-03-06 | Clarkson Robert Roy | Printed circuit board having a microelectronic semiconductor device mount area for trace routing therethrough |
US20030183419A1 (en) * | 2001-04-27 | 2003-10-02 | Lsi Logic Corporation | Ball assignment for ball grid array package |
US6690845B1 (en) * | 1998-10-09 | 2004-02-10 | Fujitsu Limited | Three-dimensional opto-electronic modules with electrical and optical interconnections and methods for making |
US7069650B2 (en) * | 2000-06-19 | 2006-07-04 | Nortel Networks Limited | Method for reducing the number of layers in a multilayer signal routing device |
US7107673B2 (en) * | 2000-06-19 | 2006-09-19 | Nortel Networks Limited | Technique for accommodating electronic components on a multiplayer signal routing device |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09223861A (en) | 1996-02-19 | 1997-08-26 | Canon Inc | Semiconductor integrated circuit and printed wiring board |
NL1014192C2 (en) | 2000-01-26 | 2001-08-08 | Industree B V | PCB. |
-
2003
- 2003-11-20 US US10/716,599 patent/US7107673B2/en not_active Expired - Fee Related
-
2006
- 2006-07-19 US US11/488,799 patent/US20060254810A1/en not_active Abandoned
Patent Citations (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5208604A (en) * | 1988-10-31 | 1993-05-04 | Canon Kabushiki Kaisha | Ink jet head and manufacturing method thereof, and ink jet apparatus with ink jet head |
US5006820A (en) * | 1989-07-03 | 1991-04-09 | Motorola, Inc. | Low reflection input configuration for integrated circuit packages |
US5357403A (en) * | 1990-06-29 | 1994-10-18 | General Electric Company | Adaptive lithography in a high density interconnect structure whose signal layers have fixed patterns |
US5451721A (en) * | 1990-09-27 | 1995-09-19 | International Business Machines Corporation | Multilayer printed circuit board and method for fabricating same |
US5281151A (en) * | 1991-07-05 | 1994-01-25 | Hitachi, Ltd. | Semiconductor chip carrier, module having same chip carrier mounted therein, and electronic device incorporating same module |
US5249098A (en) * | 1991-08-22 | 1993-09-28 | Lsi Logic Corporation | Semiconductor device package with solder bump electrical connections on an external surface of the package |
US5384433A (en) * | 1991-10-29 | 1995-01-24 | Aptix Corporation | Printed circuit structure including power, decoupling and signal termination |
US5315069A (en) * | 1992-10-02 | 1994-05-24 | Compaq Computer Corp. | Electromagnetic radiation reduction technique using grounded conductive traces circumscribing internal planes of printed circuit boards |
US5544018A (en) * | 1994-04-13 | 1996-08-06 | Microelectronics And Computer Technology Corporation | Electrical interconnect device with customizeable surface layer and interwoven signal lines |
US5686764A (en) * | 1996-03-20 | 1997-11-11 | Lsi Logic Corporation | Flip chip package with reduced number of package layers |
US6365975B1 (en) * | 1997-04-02 | 2002-04-02 | Tessera, Inc. | Chip with internal signal routing in external element |
US6384467B1 (en) * | 1997-06-06 | 2002-05-07 | Motorola, Inc. | Method for forming a cavity capable of accessing deep fuse structures and device containing the same |
US6271478B1 (en) * | 1997-11-19 | 2001-08-07 | Shinko Electric Industries Co., Ltd. | Multi-layer circuit board |
US6194668B1 (en) * | 1997-12-22 | 2001-02-27 | Shinko Electric Industries Co., Ltd. | Multi-layer circuit board |
US6246112B1 (en) * | 1998-06-11 | 2001-06-12 | Intel Corporation | Interleaved signal trace routing |
US6690845B1 (en) * | 1998-10-09 | 2004-02-10 | Fujitsu Limited | Three-dimensional opto-electronic modules with electrical and optical interconnections and methods for making |
US6335493B1 (en) * | 1998-12-01 | 2002-01-01 | Shinko Electric Industries, Co., Ltd. | Multilayer wiring board |
US6310398B1 (en) * | 1998-12-03 | 2001-10-30 | Walter M. Katz | Routable high-density interfaces for integrated circuit devices |
US20020008314A1 (en) * | 1999-04-19 | 2002-01-24 | Yasushi Takeuchi | Semiconductor integrated circuit and printed wiring substrate provided with the same |
US6198635B1 (en) * | 1999-05-18 | 2001-03-06 | Vsli Technology, Inc. | Interconnect layout pattern for integrated circuit packages and the like |
US6407343B1 (en) * | 1999-07-16 | 2002-06-18 | Nec Corporation | Multilayer wiring board |
US6388890B1 (en) * | 2000-06-19 | 2002-05-14 | Nortel Networks Limited | Technique for reducing the number of layers in a multilayer circuit board |
US6545876B1 (en) * | 2000-06-19 | 2003-04-08 | Nortel Networks Limited | Technique for reducing the number of layers in a multilayer circuit board |
US7069650B2 (en) * | 2000-06-19 | 2006-07-04 | Nortel Networks Limited | Method for reducing the number of layers in a multilayer signal routing device |
US7107673B2 (en) * | 2000-06-19 | 2006-09-19 | Nortel Networks Limited | Technique for accommodating electronic components on a multiplayer signal routing device |
US6452262B1 (en) * | 2001-02-12 | 2002-09-17 | Lsi Logic Corporation | Layout of Vdd and Vss balls in a four layer PBGA |
US20030183419A1 (en) * | 2001-04-27 | 2003-10-02 | Lsi Logic Corporation | Ball assignment for ball grid array package |
US20030043560A1 (en) * | 2001-06-15 | 2003-03-06 | Clarkson Robert Roy | Printed circuit board having a microelectronic semiconductor device mount area for trace routing therethrough |
US6521846B1 (en) * | 2002-01-07 | 2003-02-18 | Sun Microsystems, Inc. | Method for assigning power and ground pins in array packages to enhance next level routing |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090174072A1 (en) * | 2008-01-04 | 2009-07-09 | Texas Instruments Incorporated | Semiconductor system having bga package with radially ball-depopulated substrate zones and board with radial via zones |
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US20040099440A1 (en) | 2004-05-27 |
US7107673B2 (en) | 2006-09-19 |
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