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Número de publicaciónUS20060261435 A1
Tipo de publicaciónSolicitud
Número de solicitudUS 11/495,421
Fecha de publicación23 Nov 2006
Fecha de presentación28 Jul 2006
Fecha de prioridad7 Mar 2000
También publicado comoUS6627549, US7125800, US7235865, US20010053612, US20040061196, US20050023695, US20060001022, US20060246736, WO2001067500A2, WO2001067500A3
Número de publicación11495421, 495421, US 2006/0261435 A1, US 2006/261435 A1, US 20060261435 A1, US 20060261435A1, US 2006261435 A1, US 2006261435A1, US-A1-20060261435, US-A1-2006261435, US2006/0261435A1, US2006/261435A1, US20060261435 A1, US20060261435A1, US2006261435 A1, US2006261435A1
InventoresWerner Juengling
Cesionario originalMicron Technology, Inc.
Exportar citaBiBTeX, EndNote, RefMan
Enlaces externos: USPTO, Cesión de USPTO, Espacenet
Methods for making nearly planar dielectric films in integrated circuits
US 20060261435 A1
Resumen
In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers—the insulative layers sandwiched between layers of metal wiring—in integrated circuits. Accordingly, the inventor devised several methods for making nearly planar intermetal dielectric layers without the use of chemical-mechanical planarization and methods of modifying metal layout patterns to facilitate formation of dielectric layers with more uniform thickness. These methods of modifying metal layouts and making dielectric layers can be used in sequence to yield nearly planar intermetal dielectric layers with more uniform thickness.
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Reclamaciones(22)
1. An integrated circuit, comprising:
one or more conductors;
a first insulative layer which is substantially free of voids and which contacts the one or more conductors;
a second insulative layer which lies of the first insulative layer and which includes a substantial number of voids.
2. The integrated circuit of claim 1, wherein the first and second insulative layers consist essentially of silicon oxide and have substantially different dielectric constants.
3. An integrated circuit, comprising:
one or more memory cells;
one or more conductors coupled to the one or more memory cells;
a first insulative layer which is substantially free of voids and which contacts the one or more conductors; and
a second insulative layer which lies on the first insulative layer and which includes a substantial number of voids.
4. The integrated circuit of claim 3, wherein the first and second insulative layers consist essentially of silicon oxide and have substantially different dielectric constants.
5. A system, comprising:
at least one integrated circuit, including a processor;
at least one integrated memory circuit operable coupled to the processor, comprising;
one or more memory cells;
one or more conductors coupled to the one or more memory cells;
a first insulative layer which is substantially free of voids and which contacts the one or more conductors;
a second insulative layer which lies on the first insulative layer and which includes a substantial number of voids.
6. The system of claim 5, wherein the first and second insulative layers consist essentially of silicon oxide and have substantially different dielectric constants.
7. The system of claim 5, wherein the processor is a digital signal processor.
8. An integrated circuit, comprising:
one or more conductors including an oxide spacer on one or more lateral sides of each of the conductors;
a first insulative layer having a first thickness disposed upon the one or more
conductors and formed at a first deposition rate to form voids in the first insulative layer; and
a second insulative layer having a second thickness disposed upon the first insulative layer and formed at a second deposition rate to form a substantially void free layer.
9. The integrated circuit of claim 8, wherein the first and second insulative layers consist of silicon oxide and have different dielectric constants.
10. The integrated circuit of claim 8, wherein the second deposition rate is less than the first deposition rate.
11. The integrated circuit of claim 8, wherein the second insulative layer is facet etched to form sloping sides.
12. The integrated circuit of claim 8, wherein the insulative layers include at least one via hole formed in the first and second insulative layers, and at least the second insulative layer is at least one of facet etched and thermally reflowed to form sloping sides of the at least one via hole.
13. The integrated circuit of claim 8, wherein the one or more conductors further include a film resistant to lateral etching deposited upon the conductors.
14. The integrated circuit of claim 13, wherein the film resistant to lateral etching is a TEOS, oxide-nitride film.
15. An integrated circuit, comprising:
a first insulative layer having a first thickness and a first dielectric constant disposed upon one or more conductors and formed at a first deposition rate to form voids in the first insulative layer;
a second insulative layer having a second thickness and a second dielectric constant disposed upon the first insulative layer and formed at a second deposition rate that is less than the first deposition rate to form a substantially void free layer; and
the first and second insulative layers include at least one via hole formed in the first and second insulative layers, and at least the second insulative layer is at least one of facet etched and thermally reflowed to form sloping sides of the at least one via hole.
16. The integrated circuit of claim 15, wherein the first and second insulative layers include at least one of silicon dioxide, silicon oxide, silicon rich oxide, a silicon oxynitride and a silicon nitride; and
wherein the one or more conductors include a dielectric spacer on one or more lateral sides of each of the conductors film that is resistant to lateral etching and formed of at least one of an oxide, an oxynitride, a nitride, a TEOS oxide, a TEOS oxynitride, a TEOS nitride, a spin-on dielectric, and a plasma oxide.
17. An integrated circuit, comprising:
a plurality of conductors;
a first insulative layer having a first thickness disposed upon the plurality of conductors and formed at a first deposition rate to form voids in the first insulative layer;
a second insulative layer having a second thickness disposed upon the first insulative layer and formed at a second deposition rate to form a substantially void free layer;
wherein the plurality of conductors are disposed relative to one another to have a minimum separation and a maximum separation provided by individual ones of the plurality of conductors having a separation greater than the maximum separation, have at least one of a plurality of metal features inserted between the individual conductors, the feature selected from the list of pieces of metal including, a floating piece, a notch filling piece, a corner filling piece, and a between edges filling piece.
18. The integrated circuit of claim 17, wherein the plurality of metal features have a width determined by a difference between the separation greater than the maximum separation of the individual ones of the plurality of conductors disposed relative to one another, and the minimum separation value to provide a separation approximately equal to the minimum separation.
19. The integrated circuit of claim 18, wherein the plurality of metal features are selected by providing a first metal layout pattern having a first fill density;
generating a second metal layout pattern based upon the first metal layout pattern by identifying individual ones of the plurality of conductors having a separation greater than the maximum separation;
filling in one or more open areas of the first metal layout pattern having a separation greater than a predetermined value with floating metal;
filling in one or more notches in the first metal layout pattern having less than the predetermined value and more than the maximum value with added metal to at least one of the plurality of conductors;
filling in one or more corners of the first metal layout having less than the predetermined value and more than the maximum value with added metal to at least one of the plurality of conductors;
filling in one or more opposing edges of the first metal layout having less than the predetermined value and more than the maximum value with added metal to at least one of the plurality of conductors;
generating a second fill density for the second metal layout pattern and repeating the identifying the individual ones of the plurality of conductors having a separation greater than the maximum separation; and
continuing to generate metal layout patterns until at least one of a predetermined number of iterations occurs, and until none of the individual ones of the plurality of conductors has more than the maximum separation.
20. An integrated circuit, comprising:
a plurality of conductors including an oxide spacer on one or more lateral sides of at least one of the conductors;
a first insulative layer having a first thickness disposed upon the plurality of conductors and formed at a first deposition rate to form voids in the first insulative layer;
a second insulative layer having a second thickness disposed upon the first insulative layer and formed at a second deposition rate to form a substantially void free layer;
wherein the plurality of conductors are disposed relative to one another to have a minimum separation and a maximum separation;
wherein the separation is determined by providing a first metal layout pattern having a first fill density;
generating a second metal layout pattern based upon the first metal layout pattern by identifying individual ones of the plurality of conductors having a separation greater than the maximum separation;
filling in one or more open areas of the first metal layout pattern having a separation greater than a predetermined value with floating metal;
filling in one or more notches in the first metal layout pattern having less than the predetermined value and more than the maximum value with added metal to at least one of the plurality of conductors;
filling in one or more corners of the first metal layout having less than the predetermined value and more than the maximum value with added metal to at least one of the plurality of conductors;
filling in one or more opposing edges of the first metal layout having less than the predetermined value and more than the maximum value with added metal to at least one of the plurality of conductors;
generating a second fill density for the second metal layout pattern and repeating the identifying the individual ones of the plurality of conductors having a separation greater than the maximum separation; and
continuing to generate metal layout patterns until at least one of a predetermined number of iterations occurs, and until none of the individual ones of the plurality of conductors has more than the maximum separation.
21. The integrated circuit of claim 20, wherein the first and second insulative layers consist essentially of silicon oxide and have substantially different dielectric constants, and the second deposition rate is less than the first deposition rate.
22. The integrated circuit of claim 20, wherein the insulative layers include at least one via hole formed in the first and second insulative layers, and at least the second insulative layer is at least one of facet etched and thermally reflowed to form sloping sides of the at least one via hole.
Descripción
    RELATED APPLICATIONS
  • [0001]
    This application is a Divisional of U.S. application Ser. No. 10/926,471, filed Aug. 26, 2004, which is a Divisional of U.S. application Ser. No. 10/677,057, filed Sep. 30, 2003, which is a Divisional of U.S. application Ser. No. 09/801,265, filed Mar. 7, 2001, now U.S. Pat. No. 6,627,549, which claims priority to U.S. Provisional Application 60/187,658, filed on Mar. 7, 2000, all of which are incorporated herein by reference.
  • TECHNICAL FIELD
  • [0002]
    The present invention concerns methods of making integrated circuits, particularly methods of making metal masks and dielectric, or insulative, films.
  • BACKGROUND OF THE INVENTION
  • [0003]
    Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators typically build the circuits layer by layer, using techniques, such as doping, masking, and etching, to form thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon substrate, known as a wafer. The components are then wired, or interconnected, together to define a specific electric circuit, such as a computer memory.
  • [0004]
    One important concern during fabrication is flatness, or planarity, of various layers of the integrated circuit. For example, planarity significantly affects the accuracy of a photo-imaging process, known as photomasking or photolithography, which entails focusing light on light-sensitive materials to define specific patterns or structures in a layer of an integrated circuit. In this process, the presence of hills and valleys in a layer forces various regions of the layer out of focus, causing photo-imaged features to be smaller or larger than intended. Moreover, hills and valleys can reflect light undesirably onto other regions of a layer and add undesirable features, such as notches, to desired features. These problems can be largely avoided if the layer is sufficiently planar.
  • [0005]
    One process for making surfaces flat or planar is known as chemical-mechanical planarization or polishing. Chemical-mechanical planarization typically entails applying a fluid containing abrasive particles to a surface of an integrated circuit, and polishing the surface with a rotating polishing head. The process is used frequently to planarize the insulative, or dielectric, layers that lie between layers of metal wiring in integrated circuits. These insulative layers, which typically consist of silicon dioxide, are sometimes called intermetal dielectric layers. In conventional integrated-circuit fabrication, planarization of these layers is necessary because each insulative layer tends to follow the hills and valleys of the underlying metal wiring, similar to the way a bed sheet follows the contours of whatever it covers. Thus, fabricators generally deposit an insulative layer much thicker than necessary to cover the metal wiring and then planarize the insulative layer to remove the hills and valleys.
  • [0006]
    Unfortunately, conventional methods of forming these intermetal dielectric layers suffer from at least two problems. First, the process of chemical-mechanical planarization is not only relatively costly but also quite time consuming. And second, the thickness of these layers generally varies considerably from point to point because of underlying wiring. Occasionally, the thickness variation leaves metal wiring under a layer too close to metal wiring on the layer, encouraging shorting or crosstalking. Crosstalk, a phenomenon that also occurs in telephone systems, occurs when signals from one wire are undesirable transferred or communicated to another nearby wire.
  • [0007]
    Accordingly, the art needs fabrication methods that reduce the need to planarize internetal dielectric layers, that reduce thickness variation in these layers, and that improve their electrical properties generally.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0008]
    FIG. 1 is a cross-sectional view of a partial integrated-circuit assembly 10 including a substrate 12 and metal wires 14 a, 14 b, and 14 c;
  • [0009]
    FIG. 2 is a cross-sectional view of the FIG. 1 integrated-circuit assembly after formation of a substantially planar insulative layer 16, including a portion 16 a with voids and a portion 16 b without voids;
  • [0010]
    FIG. 3 is a cross-sectional view of the FIG. 2 assembly after a facet etch to improve the planarity of layer 16;
  • [0011]
    FIG. 4 is a cross-sectional view of the FIG. 3 assembly after formation of metal wires 18 a and 18 b, and substantially planar insulative layer 20, including a portion 20 a with voids and a portion 20 b without voids;
  • [0012]
    FIG. 5 is a cross-sectional view of a partial integrated-circuit assembly 21 including a substrate 22 and metal wires 24 a, 24 b, and 24 c;
  • [0013]
    FIG. 6 is a cross-sectional view of the FIG. 5 assembly after formation of an oxide spacer 26 and a substantially planar insulative layer 28, including a portion 28 a with voids and a portion 28 b without voids;
  • [0014]
    FIG. 7 is a cross-sectional view of the FIG. 6 assembly after a facet etch to improve the planarity of layer 28;
  • [0015]
    FIG. 8 is a cross-sectional view of the FIG. 7 assembly after formation of metal wires 30 a and 30 b, and substantially planar insulative layer 34, including a portion 34 a with voids and a portion 34 b without voids;
  • [0016]
    FIG. 9 is a cross-sectional view of a partial integrated-circuit assembly 35 including a substrate 36 and metal wires 36 a, 36 b, and 36 c;
  • [0017]
    FIG. 10 is a cross-sectional view of the FIG. 9 assembly after formation of an oxide spacer 40 and a substantially planar insulative layer 42;
  • [0018]
    FIG. 11 is a flow chart illustrating an exemplary method of modifying a metal layout to facilitate fabrication of intermetal dielectric layers with more uniform thickness;
  • [0019]
    FIG. 12 is a partial top view of a metal layout showing how the exemplary method of FIG. 11 adds metal to open areas in a metal layout;
  • [0020]
    FIG. 13 is a partial top view of a metal layout showing how the exemplary method of FIG. 11 fills notches in a metal layout;
  • [0021]
    FIG. 14 is a partial top view of a metal layout showing how the exemplary method of FIG. 11 fills corners in a metal layout;
  • [0022]
    FIG. 15 is a partial view of a metal layout showing how the exemplary method of FIG. 11 fills in between opposing edges of live metal regions in a metal layout;
  • [0023]
    FIG. 16 is a partial view of a metal layout showing how the exemplary method of FIG. 11 moves edges;
  • [0024]
    FIG. 17 is a block diagram of an exemplary computer system 42 for hosting and executing a software implementation of the exemplary pattern-filling method of FIG. 11; and
  • [0025]
    FIG. 18 is a simplified schematic diagram of an exemplary integrated memory circuit 50 that incorporates one or more nearly planar intermetal dielectric layers and/ or metal layers made in accord with exemplary methods of the invention.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0026]
    The following detailed description, which references and incorporates the above-identified Figures, describes and illustrates specific embodiments of the invention. These embodiments, offered not to limit but only to exemplify and teach the invention, are shown and described in sufficient detail to enable those skilled in the art to implement or practice the invention. Thus, where appropriate to avoid obscuring the invention, the description may omit certain information known to those of skill in the art.
  • First Exemplary Method of Forming Nearly Planar Dielectric Films
  • [0027]
    FIGS. 1-4 show a number of exemplary integrated-circuit assemblies, which taken collectively and sequentially, illustrate an exemplary method of making nearly planar or quasi planar dielectric films, or layers, within the scope of the present invention. As used herein, a quasi planar film is globally planar with local nonplanarities having slopes less than or equal to 45 degrees and depths less than the thickness of the next metal layer to be deposited. The local nonplanarities typically occur over the gaps between underlying metal features.
  • [0028]
    The method, as shown in FIG. 1, a cross-sectional view, begins with formation of an integrated-circuit assembly or structure 10, which can exist within any integrated circuit, for example, an integrated memory circuit. Assembly 10 includes a substrate 12. The term “substrate,” as used herein, encompasses a semiconductor wafer as well as structures having one or more insulative, semi-insulative, conductive, or semiconductive layers and materials. Thus, for example, the term embraces silicon-on-insulator, silicon-on-sapphire, and other advanced structures.
  • [0029]
    Substrate 12 includes three representative wires or conductive structures 14 a, 14 b, and 14 c, with a maximum (or average) feature spacing 14 s. In the exemplary embodiment, wires 14 a-14 c are approximately 3000-6000 angstroms thick and comprise metals, such as aluminum, gold, or silver, and nonmetals, such as heavily doped polysilicon. Spacing 14 s, in the exemplary embodiment, is 0.3 microns.
  • [0030]
    Wires 14 a-14 c can be formed using any number of methods, for example, photolithography and dry etching. To avoid increasing feature spacing during dry etching, the exemplary embodiment forms a lateral-etch-resistant layer, that is, a layer resistant to lateral etching, on a metal layer before etching. Examples of suitable layers include a TEOS, oxide-nitride layer. Alternatively, one can add extensive serif features to the metal mask layout to avoid large open areas, especially to reduce the diagonal distance between features.
  • [0031]
    FIG. 2 shows that the exemplary method next entails forming an insulative layer 16 over substrate 12 and wires 14 a-14 b. Layer 16 has a thickness 16 t of, for example, 6000 angstroms, and includes two layers or sublayers 16 a and 16 b. Sublayer 16 a includes a number of voids, particularly voids 17 between wires 14 a and 14 b, and between wires 14 b and 14 c, to increase its dielectric constant. Sublayer 16 b is either substantially voidless or includes a substantially fewer number of voids than sublayer 16 a. The presence of voids in sublayer 16 a reduces lateral electrical coupling between adjacent metal features, for example, between wires 14 a and 14 b and between wires 14 a-14 c and any overlying conductive structures.
  • [0032]
    The exemplary method forms layer 16 using a combination of a non-conformal and conformal oxide depositions. In particular, it uses a CVD TEOS (chemical vapor deposition tetraethyl-orthosilicate) or PECVD TEOS (plasma-enhanced CVD TEOS) oxide deposition process at a non-conformal deposition rate to form void-filled sublayer 16 a voids and then lowers the TEOS deposition rate to, a conformal rate to form substantially voidless sublayer 16 b.
  • [0033]
    FIG. 3 shows that after forming sublayer 16 b, which includes some level of nonplanarity, the exemplary method facet etches the sublayer at an angle of about 45 degrees to improve its global planarity. (That layer 16 b has undergone further processing is highlighted by its new reference numeral 16 b′.) The facet etch reduces or smooths any sharp trenches in regions overlying gaps between metal features, such as wires 14 a-14 c. As used herein, the term “facet etch” refers to any etch process that etches substantially faster in the horizontal direction than in the vertical direction. Thus, for example, the term includes an angled sputter etch or reactive-ion etch.
  • [0034]
    To optimize the slopes of any vias, one can perform the facet etch before via printing. More specifically, one can facet etch after etching any necessary vias and stripping photoresist to produce vias having greater slope and smoothness.
  • [0035]
    FIG. 4 shows the results of forming a second metallization level according to the procedure outlined in FIGS. 1-3. In brief, this entails forming conductive structures 18 a and 18 b on insulative sublayer 16 b′ and forming an insulative layer 20 on sublayer 16 b′ and conductive structures 18 a and 18 b. Insulative layer 20, like insulative layer 16, includes void-filled sublayer 20 a and substantially void-free sublayer 20 b′. Sublayer 20 a includes one or more voids 19 between conductive structures 18 a and 18 b. Sublayer 20 b′ was facet etch to improve its planarity. Layer 20 has a thickness 20 t, of for example 3000-6000 angstroms.
  • Second Exemplary Method of Forming Nearly Planar Dielectric Films
  • [0036]
    FIGS. 5-8 show a number of exemplary integrated-circuit assemblies, which taken collectively and sequentially, illustrate a second exemplary method of making nearly planar or quasi planar dielectric layers within the scope of the present invention. The second method is particularly applicable to maximum metal feature spacing greater than about 0.3 microns or oxide thickness less than 6000 angstroms to allow for shallow via formation, that is, via depths less than about 4000 angstroms.
  • [0037]
    More particularly, FIG. 5 shows that the method begins with formation of an integrated-circuit assembly or structure 21, which, like assembly 10 in FIG. 1, can exist within any integrated circuit. Assembly 10 includes a substrate 22 which supports three representative wires or conductive structures 24 a, 24 b, and 24 c, with a desired feature spacing 24 s. In the exemplary embodiment, spacing 24 s is greater than 0.3 microns. Some embodiments set a minimum spacing of 0.17 microns. However, the present invention is not limited to any particular spacing.
  • [0038]
    FIG. 6 shows that the exemplary method next entails forming an insulative spacer 26 and an insulative layer 28. Insulative spacers 26, which consists of silicon dioxide for example, lies over portions of substrate 22 adjacent wires 24 a-24 c to reduce the effective separation of wires 24 a-24 c. The exemplary method uses a TEOS oxide deposition and subsequent etching to form spacers 26. Insulative layer 28 has a thickness 28 t of, for example, 4000 angstroms, and includes two sublayers 28 a and 28 b, analogous to sublayers 16 a and 16 b in the first embodiment. Specifically, sublayer 28 a includes a number of voids 27 between the wires to increase its dielectric constant, and sublayer 28 b is either substantially voidless or includes a substantially fewer number of voids than sublayer 28 a. A two-stage TEOS oxide deposition process, similar to that used in the first embodiment, is used to form layer 28.
  • [0039]
    FIG. 7 shows that after forming sublayer 28 b, which includes some level of nonplanarity, the exemplary method facet etches the sublayer at an angle of about 45 degrees to improve its global planarity.
  • [0040]
    FIG. 8 shows the results of forming a second metallization level according to the procedure outlined in FIGS. 5-7. This entails forming conductive structures 30 a and 30 b on insulative sublayer 28 b′ and forming an insulative spacer 32 and an insulative layer 34, which, like insulative layer 28, includes void-filled sublayer 34 a and substantially void-free sublayer 34 b′. Sublayer 34 a includes voids 31 between conductive structures 30 a and 30 b, and sublayer 34 b′ is facet etched to improve its planarity.
  • Third Exemplary Method of Forming Nearly Planar Dielectric Films
  • [0041]
    FIGS. 9 and 10 show a number of exemplary integrated-circuit assemblies, which taken collectively and sequentially, illustrate a third exemplary method of making nearly planar or quasi planar dielectric layers within the scope of the present invention. In contrast to the first and second embodiment, the third exemplary embodiment is intended for forming insulative films on metal layers with maximum feature spacing up to about 0.5 microns.
  • [0042]
    FIG. 9 shows that the method begins with formation of an integrated-circuit assembly or structure 35, which like assembly 10 in FIG. 1 and assembly 21 in FIG. 5, can exist within any integrated circuit. Assembly 35 includes a substrate 36 which supports three representative wires or conductive structures 38 a, 38 b, and 38 c, with a desired feature spacing 38 s of about 0.5 microns.
  • [0043]
    FIG. 10 shows the results of forming an oxide spacers 40 and an insulative layer 42. The exemplary embodiment forms one or more oxide spacers 40 which is about 1000 angstroms wide, and thus reduces the effective spacing between conductors 38 a-38 c by 2000 angstroms. Forming insulative layer 42 entails executing a flow-fill procedure, such as TRIKON-200 by Trikon Technologies, Inc. To obtain global and local planarity, one can reduce the maximum feature space by using oxide/TEOS spacer as taught in the second exemplary method, or by enlarging the metal feature, or by adding floating metal between the metal features.
  • Exemplary Method of Promoting Uniform Thickness of Intermetal Dielectric Layers
  • [0044]
    To facilitate the formation of more uniformly thick inter-metal dielectric layers, such as those described above, the inventor developed specific methods of (and related computer software) for increasing the pattern density of metal layouts. The methods and associated software take a given metal layout and modify, or fill, open areas of the layout to increase pattern density and thus promote uniform thickness or reduce thickness variation across dielectric layers formed on metal layers based on the layouts. These methods and software can thus be used, for example, to facilitate formation of the conductive structures shown in FIGS. 1, 5, and 9.
  • [0045]
    The exemplary method generally entails iteratively measuring a given layout, adding floating metal to fill large open areas in the layout, and extending or filling out existing metal areas to meet maximum feature spacing, or gap, criteria. FIG. 11 shows a flow chart of the exemplary method, which is suitable for implementation as a computer-executable program.
  • [0046]
    Specifically, the flow chart includes a number of process or decision blocks 110, 120, 130, and 140. The exemplary method begins at process block 110 which entails measuring a given layout. This entails determining open (unmetallized or nonconductive) areas large enough to be filled with floating metal and identifying live metal areas that require additional metal to obtain desired spacing. Floating metal is metal that is not coupled to a signal path or component, whereas live metal is metal that is coupled to a signal path or component.
  • [0047]
    After executing block 110, the exemplary method proceeds to block 120 which entails adding floating metal to any large areas identified in block 110. To illustrate, FIG. 12 shows a hypothetical layout having a live metal region 200 with open area 210. In general, if dimension A is greater than the sum of dimension S1, dimension S2, and L (the maximum feature spacing criteria), the exemplary method adds floating metal, such as floating metal region 220.
  • [0048]
    After adding floating metal, the exemplary method adds live metal as indicated in block 120 of FIG. 11. FIG. 12 is again instructive of the exemplary method. If dimension B is less than the sum of dimension SI, dimension S2, and L, the exemplary method adds metal as indicated by added active metal region 230 process block 104 which entails filling in notches in the layout.
  • [0049]
    More particularly, the exemplary method follows an iterative process for adding live (or non-floating) metal, as indicated by blocks 130 a-130 g.
  • [0050]
    Block 130 a entails filling notches in the current live metal. FIG. 13 shows a live metal region 300 of a hypothetical metal layout having a notch 310. Included within notch 310 are a series of iteratively added live metal regions 320-325. The amount of metal added at each iteration can be selected using a minimum surface area criteria or computed dynamically each iteration. The exemplary embodiment repeatedly adds metal to the notch until it is filled, before advancing to block 310 b. However, other embodiments can advance to block 310 b before the notch is filled, relying on subsequent trips or iterations through the first loop in the flowchart to complete filling of the notch.
  • [0051]
    Block 130 b entails filling in corners in the current live metal, meaning the live metal after filling notches. FIG. 14 illustrates a live metal region 400 having a corner 410 and added L-shaped live metal regions 420-423 and a rectangular live metal region 424. (Other embodiments add other shapes of live metal regions.) The amount of metal added at each iteration can be selected using a minimum surface area or single-dimensional criteria or computed dynamically each iteration. The exemplary embodiment repeatedly adds metal to the corner until it is filled, before advancing to block 130 c. However, other embodiments can advance to block 310 b before the notch is filled, relying on subsequent trips through the inner loop to complete filling of the notch.
  • [0052]
    Block 130 c entails filling in between opposing edges of adjacent live metal regions to achieve a desired spacing, such as a maximum desired spacing L. FIG. 15 shows live metal regions 510 and 520, which have respective opposing edges 510 a and 520 a. The exemplary method entails adding live metal regions, such as live metal regions 521-523, one edge such as edge 520 a to achieved the maximum desired spacing L. However, other embodiments add live metal to both of the opposing edges to achieve the desired spacing. Still other embodiments look at the lengths of the opposing edges and use one or both of the lengths to determine one or more dimensions of the added live metal regions.
  • [0053]
    After filling in between opposing edges of existing live metal regions, the exemplary method advances to decision block 130 d in FIG. 11. This block entails determining whether more live metal can be added. More precisely, this entails measuring the layout as modified by the live metal already added and determining whether there are any adjacent regions that violate the desired maximum spacing criteria. (Note that some exemplary embodiments include more than one maximum spacing criteria to account for areas where capacitive effects or crosstalk issues are of greater importance than others.) If the determination indicates that more metal can be added execution proceeds back to block 130 a to fill in remaining notches, and so forth. If the determination indicates that no more live metal can be added to satisfy the maximum spacing criteria, execution to proceeds to block 130 e in FIG. 11.
  • [0054]
    Block 130 e entails moving (or redefining) one or more edges (or portions of edges) of live metal regions in the modified layout specification. To illustrate, FIG. 16 shows live metal regions 610 and 620, which have respective edges 610 a and 620 a. It also shows the addition of live metal region 630 to edge 620 a, which effectively extends the edge. Similarly, edge 620 a has been extended with the iterative addition of live metal regions 631 and 632. The additions can be made iteratively using a dynamic or static step size, or all it once by computing the size of an optimal addition to each edge. Exemplary execution then proceeds to decision block 130 f.
  • [0055]
    In decision block 130 f, the exemplary method decides again whether more metal can be added to the layout. If more metal can be added, the exemplary method repeats execution of process blocks 104-122. However, if no metal can be added, the method proceeds to process block 140 to output the modified layout for use in a fabrication process.
  • [0056]
    Although not show explicitly in the exemplary flow chart in FIG. 11, the exemplary method performs data compaction to minimize or reduce the amount of layout data carried forward from iteration to iteration. Data compaction reduces the number of cells which define the circuit associated with the metal layout and the computing power necessary to create the metal layout.
  • [0057]
    The exemplary compaction scheme flattens all array placement into single instance placements. For example, a single array placement of a cell incorporating a 3×4 matrix flattens to 12 instances of a single cell. It also flattens specific cells, such as array core cells, vias, or contacts, based on layout or user settings. Additionally, it flattens cells which contain less than a predetermined number of shapes regardless of any other effects. For example, one can flatten cells having less than 10, 20, or 40 shapes. Lastly, the exemplary compaction scheme attempts to merge shapes to minimize overlapping shapes and redundant data.
  • [0058]
    The appropriate or optimum degree of flattening depends largely on the processing power and memory capabilities of the computer executing the exemplary method. Faster computers with more core memory and swap space can handle larger number of shapes per cell and thus have less need for flattening than slower computers with less core memory and swap space. In the extreme, a complete circuit layout can be flattened into one cell.
  • [0059]
    If a given layout design is not a single flat list of shapes but includes two or more cells placed into each other as instances, additional precaution should be taken to reduce the risk of introducing unintended shorts into the layout during the pattern-fill process. In the exemplary embodiment, this entails managing the hierarchy of cells.
  • [0060]
    The exemplary embodiment implements a hierarchy management process which recognizes that each cell has an associated fill area that will not change throughout the metal-fill process. The exemplary management process entails executing the following steps from the bottom up until all cell dependencies are resolved. For each instance in each cell, the process creates a temporary unique copy of the cell associated with a given instance. After this, the process copies metal from other cells into the cell being examined if it falls into the fill area. The process then copies metal from other cell into the cell if the metal falls into a ring around the fill area. Next, the process identifies, extracts, and marks conflict areas.
  • [0061]
    This exemplary pattern-filling method and other simpler or more complex methods embodying one or more filling techniques of the exemplary embodiment can be used in combination with the methods of making nearly planar intermetal dielectric layers described using FIGS. 1-10. More precisely, one can use a pattern-filling method according to the invention to define a layout for a particular metal layer, form a metal layer based on the layout, and then form a nearly planar intermetal dielectric layer according to the invention on the metal layer. The combination of these methods promises to yield not only a nearly planar dielectric layer that reduces or avoids the need for chemical-mechanical planarization, but also a dielectric layer with less thickness deviation because of the adjusted pattern fill density of the underlying metal layer.
  • Exemplary Computer System Incorporating Pattern-Filling Method
  • [0062]
    FIG. 17 shows an exemplary computer system or workstation 42 for hosting and executing a software implementation of the exemplary pattern-filling method. The most pertinent features of system 42 include a processor 44, a local memory 45 and a data-storage device 46. Additionally, system 42 includes display devices 47 and user-interface devices 48. Some embodiments use distributed processors or parallel processors, and other embodiments use one or more of the following data-storage devices: a read-only memory (ROM), a random-access-memory (RAM), an electrically-erasable and programmable-read-only memory (EEPROM), an optical disk, or a floppy disk. Exemplary display devices include a color monitor, and exemplary user-interface devices include a keyboard, mouse, joystick, or microphone. Thus, the invention is not limited to any genus or species of computerized platforms.
  • [0063]
    Data-storage device 46 includes layout-development software 46 a, pattern-filling software 46 b, an exemplary input metal layout 46 c, and an exemplary output metal layout 46 d. (Software 46 a and 46 b can be installed on system 42 separately or in combination through a network-download or through a computer-readable medium, such as an optical or magnetic disc, or through other software transfer methods.) Exemplary storage devices include hard disk drives, optical disk drives, or floppy disk drives. In the exemplary embodiment, software 46 b is an add-on tool to layout-development software 46 a and layout 46 c was developed using software 46 a. However, in other embodiments, software 46 b operates as a separate application program and layout 46 c was developed by non-resident layout-development software. General examples of suitable layout-development software are available from Cadence and Mentor Graphics. Thus, the invention is not limited to any particular genus or species of layout-development software.
  • Exemplary Integrated Memory Circuit
  • [0064]
    FIG. 18 shows an exemplary integrated memory circuit 50 that incorporates one or more nearly planar intermetal dielectric layers and/or metal layers within the scope of the present invention. One more memory circuits resembling circuit 50 can be used in a variety of computer or computerized systems, such as system 42 of FIG. 17.
  • [0065]
    Memory circuit 50, which operates according to well-known and understood principles, is generally coupled to a processor (not shown) to form a computer system. More particularly, circuit 50 includes a memory array 52, which comprises a number of memory cells 53 a, 53 b, 53 c, and 53 d; a column address decoder 54, and a row address decoder 55; bit lines 56 a and 56 b; word lines 57 a and 57 b; and voltage-sense-amplifier circuit 58 coupled in conventional fashion to bit lines 56 a and 56 b. (For clarity, FIG. 18 omits many conventional elements of a memory circuit.)
  • Conclusion
  • [0066]
    In furtherance of the art, the inventor has presented several methods for making nearly planar intermetal dielectric layers without the use of chemical-mechanical planarization. Additionally, the inventor has presented a method of modifying metal layouts to facilitate formation of dielectric films with more uniform thickness. These methods of modifying metal layouts and making dielectric layers can be used in sequence to yield nearly planar intermetal dielectric layers with more uniform thickness.
  • [0067]
    Various methods are disclosed of making dielectric layers on metal layers, which reduce the need for chemical-mechanical planarization procedure. Specifically, a first exemplary method of the invention forms a metal layer with a predetermined maximum feature spacing and then uses a TEOS-based (tetraethyl-orthosilicate-based) oxide deposition procedure to form an oxide film having nearly planar or quasi-planar characteristics. The exemplary method executes a CVD (chemical vapor deposition) TEOS oxide procedure to form an oxide layer on a metal layer having a maximum feature spacing of 0.2-0.5 microns.
  • [0068]
    A second exemplary method includes voids within the oxide, or more generally insulative, film to improve its effective dielectric constant and thus improve its ability to prevent shorting and crosstalk between metal wiring. Specifically, the exemplary method uses a TEOS process at a non-conformal rate sufficient to encourage the formation of voids, and then uses the TEOS process at a conformal rate of deposition to seal the voids. More generally, however, the invention uses a non-conformal deposition procedure to encourage formation of voids and then a more conformal deposition to seal the voids.
  • [0069]
    A third exemplary method increases the metal-fill density of metal patterns to facilitate formation of intermetal dielectric layers having more uniform thicknesses. The third exemplary method adds floating metal to open areas in a metal layout and then extends non-floating metal dimensions according to an iterative procedure that entails filling in notches, and corners and moving selected edges of the layout.
  • [0070]
    The embodiments described above are intended only to illustrate and teach one or more ways of practicing or implementing the present invention, not to restrict its breadth or scope. The actual scope of the invention, which embraces all ways of practicing or implementing the invention, is defined only by the following claims and their equivalents.
Citas de patentes
Patente citada Fecha de presentación Fecha de publicación Solicitante Título
US5252520 *31 Oct 199112 Oct 1993At&T Bell LaboratoriesIntegrated circuit interlevel dielectric wherein the first and second dielectric layers are formed with different densities
US5304505 *23 Dic 199119 Abr 1994Emanuel HazaniProcess for EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells
US5461003 *27 May 199424 Oct 1995Texas Instruments IncorporatedMultilevel interconnect structure with air gaps formed between metal leads
US5503882 *18 Abr 19942 Abr 1996Advanced Micro Devices, Inc.Method for planarizing an integrated circuit topography
US5518959 *24 Ago 199521 May 1996Taiwan Semiconductor Manufacturing CompanyMethod for selectively depositing silicon oxide spacer layers
US5641712 *7 Ago 199524 Jun 1997Motorola, Inc.Method and structure for reducing capacitance between interconnect lines
US5776834 *7 Jun 19957 Jul 1998Advanced Micro Devices, Inc.Bias plasma deposition for selective low dielectric insulation
US5814555 *5 Jun 199629 Sep 1998Advanced Micro Devices, Inc.Interlevel dielectric with air gaps to lessen capacitive coupling
US5858876 *1 Abr 199612 Ene 1999Chartered Semiconductor Manufacturing, Ltd.Simultaneous deposit and etch method for forming a void-free and gap-filling insulator layer upon a patterned substrate layer
US5872058 *17 Jun 199716 Feb 1999Novellus Systems, Inc.High aspect ratio gapfill process by using HDP
US5949143 *22 Ene 19987 Sep 1999Advanced Micro Devices, Inc.Semiconductor interconnect structure with air gap for reducing intralayer capacitance in metal layers in damascene metalization process
US5968610 *28 Oct 199719 Oct 1999United Microelectronics Corp.Multi-step high density plasma chemical vapor deposition process
US6030881 *5 May 199829 Feb 2000Novellus Systems, Inc.High throughput chemical vapor deposition process capable of filling high aspect ratio structures
US6087724 *27 May 199811 Jul 2000Advanced Micro Devices, Inc.HSQ with high plasma etching resistance surface for borderless vias
US6100205 *28 Oct 19978 Ago 2000United Microelectronics Corp.Intermetal dielectric layer formation with low dielectric constant using high density plasma chemical vapor deposition process
US6136687 *26 Nov 199724 Oct 2000Integrated Device Technology, Inc.Method of forming air gaps for reducing interconnect capacitance
US6174808 *4 Ago 199916 Ene 2001Taiwan Semiconductor Manufacturing CompanyIntermetal dielectric using HDP-CVD oxide and SACVD O3-TEOS
US6207571 *29 Feb 200027 Mar 2001Micron Technology, Inc.Self-aligned contact formation for semiconductor devices
US6223331 *30 Jul 199824 Abr 2001Micron Technology, Inc.Semiconductor circuit design method for employing spacing constraints and circuits thereof
US6251470 *9 Oct 199726 Jun 2001Micron Technology, Inc.Methods of forming insulating materials, and methods of forming insulating materials around a conductive component
US6255162 *16 Mar 19993 Jul 2001United Microelectronics Corp.Method of gap filling
US6274479 *21 Ago 199814 Ago 2001Micron Technology, IncFlowable germanium doped silicate glass for use as a spacer oxide
US6531412 *10 Ago 200111 Mar 2003International Business Machines CorporationMethod for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications
US6599847 *27 Ago 199629 Jul 2003Taiwan Semiconductor Manufacturing CompanySandwich composite dielectric layer yielding improved integrated circuit device reliability
US7125800 *30 Sep 200324 Oct 2006Micron Technology, Inc.Methods for making nearly planar dielectric films in integrated circuits
US20050023695 *26 Ago 20043 Feb 2005Micron Technology, Inc.Methods for making nearly planar dielectric films in integrated circuits
US20060001022 *29 Ago 20055 Ene 2006Micron Technology, Inc.Methods for making nearly planar dielectric films in integrated circuits
US20060246736 *17 Jul 20062 Nov 2006Micron Technology, Inc.Methods for making nearly planar dielectric films in integrated circuits
Clasificaciones
Clasificación de EE.UU.257/501, 257/E21.583, 257/E21.58
Clasificación internacionalH01L21/316, H01L21/768, H01L21/3205, H01L21/3105, H01L29/00
Clasificación cooperativaH01L21/7684, H01L21/02126, H01L21/7682, H01L21/31051, H01L21/022, H01L21/31612, H01L21/02271, H01L21/02203, H01L21/76819, H01L21/31695
Clasificación europeaH01L21/3105B, H01L21/02K2C3, H01L21/316P, H01L21/02K2C5, H01L21/02K2E3B6, H01L21/768B6, H01L21/02K2C1L1, H01L21/768C2, H01L21/768B4