US20060264007A1 - High quality oxide on an epitaxial layer - Google Patents

High quality oxide on an epitaxial layer Download PDF

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US20060264007A1
US20060264007A1 US11/493,114 US49311406A US2006264007A1 US 20060264007 A1 US20060264007 A1 US 20060264007A1 US 49311406 A US49311406 A US 49311406A US 2006264007 A1 US2006264007 A1 US 2006264007A1
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environment
layer
oxygen
oxide layer
state
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US11/493,114
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Ruojia Lee
Randhir Thakur
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Micron Technology Inc
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Micron Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer

Definitions

  • the embodiments of the invention relate to integrated circuit manufacture and, more particularly, to the formation of ultra-thin high quality gate oxides that are useable in flash and dynamic random access memories.
  • thermal oxides are used routinely as gate dielectric layers for field-effect transistors.
  • DRAMs 4-megabit dynamic random access memories
  • the current of 4-megabit dynamic random access memories (DRAMs) typically uses gate oxide layers having a thickness within a range of 200 to 250 ⁇ for both memory array and peripheral transistors. For 16-megabit DRAMs, this figure is expected to fall to 150 to 200 ⁇ ; for 64-megabit and 256-megabit DRAMs, the thickness is expected to fall still further.
  • EEPROMs electrically-erasable programmable read-only memories
  • flash memories even thinner gate oxide layers are required to facilitate Fowler-Nordheim tunneling (universally used as the erase mechanism and often as the write mechanism).
  • EEPROMs electrically-erasable programmable read-only memories
  • flash memories even thinner gate oxide layers are required to facilitate Fowler-Nordheim tunneling (universally used as the erase mechanism and often as the write mechanism).
  • 110 ⁇ -thick gate oxide layers are the norm.
  • gate oxide layers are expected to drop to the 80 to 90 ⁇ range.
  • defects in the gate oxide layer have several sources.
  • One major source of defects is the imperfections in the single-crystal bulk silicon from which starting wafers are manufactured. Such imperfections in the 10 single-crystal silicon lattice generally result from impurities, which may include metal atoms. Thermal growth of an oxide layer on top of bulk silicon will result in “pin holes” in the dielectric at the defect sites.
  • Another major source of defects is the low quality of the native silicon dioxide which forms at room temperature on exposure to the atmosphere.
  • Prior processes for forming a gate dielectric layer typically begin with a cleaning step which normally consists of a short-time dip in a hydrofluoric acid bath.
  • the wafers are generally exposed to the atmosphere, at which time a 3 to 7 ⁇ -thick layer of native oxide forms on the surface of exposed bare silicon.
  • the defects in native silicon dioxide are the result of the low temperature of formation (which results in oxides of uneven stoichiometry) and the uncontrolled content of the atmosphere (which results in trace amounts of compounds other than silicon dioxide).
  • U.S. Pat. No. 4,656,054 to Inoue describes a method of manufacturing a semiconductor device involving a capacitor, the primary object being to improve the method of mass-manufacturing chips containing a larger-capacitance capacitor. It does teach selectively growing a silicon layer on the substrate surface by an epitaxial growth method and then forming a gate oxide film by thermal oxidation.
  • the objective of Inoue is to create a capacitor, the capacitance being controlled by the pattern and depth of etching into the insulation layer.
  • Inoue's focus is on the ability to repeatably produce the same pattern of depressions and does not include any mention of a controlled manufacturing environment or an attempt to maximize the quality of the gate oxide layer. Inoue teaches improving capacitor performance and Inoue does not consider the quality of the substrate surface prior to the epitaxial growth step.
  • U.S. Pat. No. 5,304,221 to Atherton teaches a process for modelling and controlling production integrated processing equipment (PIPE), although in the Background section it makes passing reference to PIPEs being able to minimize human involvement and operate in a controlled environment, although “controlled environment” is not defined in Atherton.
  • PIPE production integrated processing equipment
  • FIG. 1 is a cross-sectional view of a portion of an in-process semiconductor wafer immediately following field oxidation
  • FIG. 2 is a cross-sectional view of the portion of an in-process semiconductor wafer depicted in FIG. 1 following removal of the silicon nitride masking layer and the pad oxide layer;
  • FIG. 3 is a cross-sectional view of the portion of an in-process semiconductor wafer depicted in FIG. 2 following selective epitaxial growth of a silicon layer on top of the active areas;
  • FIG. 4 is a cross-sectional view of the portion of an in-process semiconductor wafer depicted in FIG. 3 following a thermal oxidation step.
  • FIG. 5 is a flowchart showing a method for forming an oxide layer on a bulk silicon active area of a silicon wafer according to an embodiment of the invention.
  • a semiconductor wafer has been subjected to a conventional field oxidation process known as LOCOS.
  • LOCOS conventional field oxidation process
  • the process involved forming a pad oxide layer 11 on top of the entire wafer, depositing an oxygen-impermeable silicon nitride layer on top of the pad oxide layer, patterning and etching the silicon nitride layer to form silicon nitride islands 12 which masked the active areas 13 , and subjecting the wafer to an oxidation step which has formed field oxide regions 14 .
  • the silicon nitride islands 12 have been stripped, following which the pad oxide layer 11 that was beneath the islands is stripped in an oxygen-free environment to prevent a native oxide layer from forming on the exposed substrate once the pad oxide layer 11 is stripped.
  • an epitaxial silicon layer 31 is selectively grown on top of the active areas 13 .
  • no silicon is deposited on the field oxide regions 14 .
  • silicon atoms possessing high surface mobility are deposited on the bare single-crystal silicon substrate in the active areas. The atoms migrate to sites on the single crystal substrate where nucleation is favored, thus forming a virtually defect-free layer of epitaxial silicon on top of the silicon substrate in the active areas 13 .
  • the in-process wafer is subjected to a thermal oxidation step, which oxidizes an upper portion 33 of the epitaxial layer 31 ( FIG. 3 ) to form a gate oxide layer 41 .
  • the oxidation step is allowed to proceed until the appropriate thickness of gate oxide is achieved. It is essential that between the epitaxial growth step depicted in FIG. 3 and the oxidation step depicted in FIG. 4 , the wafer be protected from the atmosphere to prevent the formation of a native oxide layer on the active areas. Thus, the wafer must either be maintained in an inert atmosphere or in a vacuum chamber in which the partial pressure of oxygen is very nearly zero.
  • Processing of the wafer following the formation of the high-quality gate oxide layer 41 may be entirely conventional, with a polysilicon layer or a layer of other material suitable for gate electrodes being deposited on top of the gate oxide layer 41 .
  • the polysilicon layer is doped, then patterned and etched to form gate electrodes.
  • the quality of gate oxide dielectric layers is thus improved by using the two-pronged approach described above.
  • an in-situ grown epitaxial layer is formed on active areas following a strip of the pad oxide layer used beneath the silicon nitride pattern used for masking during the field oxidation process.
  • the wafers are maintained in a controlled, oxygen-free environment until the epitaxial growth step is accomplished.
  • the controlled environment is a low-pressure, virtually oxygen-free environment.
  • the wafers are maintained in a controlled, oxygen-free environment until being subjected to elevated temperature in a controlled, oxidizing environment.
  • the oxidizing environment comprises diatomic oxygen, while in another embodiment, the oxidizing environment comprises diatomic oxygen and ozone.

Abstract

Some embodiments of the invention improve the quality of gate oxide dielectric layers using a two-pronged approach, thus permitting the use of much thinner silicon dioxide gate dielectric layers required for lower-voltage, ultra-dense integrated circuits. In order to eliminate defects caused by imperfections in bulk silicon, an in-situ grown epitaxial layer is formed on active areas following a strip of the pad oxide layer used beneath the silicon nitride islands used for masking during the field oxidation process. By growing an epitaxial silicon layer prior to gate dielectric layer formation, defects in the bulk silicon substrate are covered over and, hence, isolated from the oxide growth step. In order to maintain the integrity of the selective epitaxial growth step, the wafers are maintained in a controlled, oxygen-free environment until the epitaxial growth step is accomplished. In order to eliminate defects caused by a native oxide layer, the wafers are maintained in a controlled, oxygen-free environment until being subjected to elevated temperature in a controlled, oxidizing environment. In one embodiment, the oxidizing environment comprises diatomic oxygen, while in another embodiment, the oxidizing environment comprises diatomic oxygen and ozone. Other embodiments of the invention are described and claimed.

Description

    RELATED APPLICATIONS
  • This application is a Divisional of U.S. Ser. No. 08/593,949 filed Jan. 30, 1996, which is incorporated herein by reference.
    • FIELD
  • The embodiments of the invention relate to integrated circuit manufacture and, more particularly, to the formation of ultra-thin high quality gate oxides that are useable in flash and dynamic random access memories.
    • BACKGROUND
  • The thermal oxidation of silicon in a dry, oxygen ambient is a vital element in the manufacture of integrated circuits. Thermal oxides are used routinely as gate dielectric layers for field-effect transistors. As device dimensions are scaled down to increase circuit density, increasingly lower voltages are necessary to prevent channel punch-through and reduce the parasitic transistor effect between adjacent devices. With lower voltages, thinner gate dielectric layers are required. For example, the current of 4-megabit dynamic random access memories (DRAMs) typically uses gate oxide layers having a thickness within a range of 200 to 250 Å for both memory array and peripheral transistors. For 16-megabit DRAMs, this figure is expected to fall to 150 to 200 Å; for 64-megabit and 256-megabit DRAMs, the thickness is expected to fall still further. For electrically-programmable memories such as electrically-erasable programmable read-only memories (EEPROMs) and flash memories, even thinner gate oxide layers are required to facilitate Fowler-Nordheim tunneling (universally used as the erase mechanism and often as the write mechanism). For the current generation of 4-megabit flash memories, 110 Å-thick gate oxide layers are the norm. For future generations of more dense flash memories, gate oxide layers are expected to drop to the 80 to 90 Å range.
  • As gate oxide layers become thinner, it becomes increasingly important that such layers be defect free in order to eliminate leakage. Defects in the gate oxide layer have several sources. One major source of defects is the imperfections in the single-crystal bulk silicon from which starting wafers are manufactured. Such imperfections in the 10 single-crystal silicon lattice generally result from impurities, which may include metal atoms. Thermal growth of an oxide layer on top of bulk silicon will result in “pin holes” in the dielectric at the defect sites. Another major source of defects is the low quality of the native silicon dioxide which forms at room temperature on exposure to the atmosphere. Prior processes for forming a gate dielectric layer typically begin with a cleaning step which normally consists of a short-time dip in a hydrofluoric acid bath. Following the cleaning step, the wafers are generally exposed to the atmosphere, at which time a 3 to 7 Å-thick layer of native oxide forms on the surface of exposed bare silicon. The defects in native silicon dioxide are the result of the low temperature of formation (which results in oxides of uneven stoichiometry) and the uncontrolled content of the atmosphere (which results in trace amounts of compounds other than silicon dioxide).
  • U.S. Pat. No. 4,656,054 to Inoue describes a method of manufacturing a semiconductor device involving a capacitor, the primary object being to improve the method of mass-manufacturing chips containing a larger-capacitance capacitor. It does teach selectively growing a silicon layer on the substrate surface by an epitaxial growth method and then forming a gate oxide film by thermal oxidation. However, the objective of Inoue is to create a capacitor, the capacitance being controlled by the pattern and depth of etching into the insulation layer. Inoue's focus is on the ability to repeatably produce the same pattern of depressions and does not include any mention of a controlled manufacturing environment or an attempt to maximize the quality of the gate oxide layer. Inoue teaches improving capacitor performance and Inoue does not consider the quality of the substrate surface prior to the epitaxial growth step.
  • U.S. Pat. No. 5,013,681 to Godbey teaches removal of silicon oxide present on the active area after the wafer is placed in the growth chamber.
  • U.S. Pat. No. 4,870,245 to Price teaches an apparatus for plasma enhanced thermal treating of silicon-bearing materials. Price does not describe increasing the effectiveness of fabrication steps through plasma enhancement.
  • U.S. Pat. No. 5,304,221 to Atherton teaches a process for modelling and controlling production integrated processing equipment (PIPE), although in the Background section it makes passing reference to PIPEs being able to minimize human involvement and operate in a controlled environment, although “controlled environment” is not defined in Atherton.
  • What is lacking in the art is an improved method of forming silicon dioxide for use as gate dielectric layers which are less prone to leakage than those which are conventionally grown.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view of a portion of an in-process semiconductor wafer immediately following field oxidation;
  • FIG. 2 is a cross-sectional view of the portion of an in-process semiconductor wafer depicted in FIG. 1 following removal of the silicon nitride masking layer and the pad oxide layer;
  • FIG. 3 is a cross-sectional view of the portion of an in-process semiconductor wafer depicted in FIG. 2 following selective epitaxial growth of a silicon layer on top of the active areas; and
  • FIG. 4 is a cross-sectional view of the portion of an in-process semiconductor wafer depicted in FIG. 3 following a thermal oxidation step.
  • FIG. 5 is a flowchart showing a method for forming an oxide layer on a bulk silicon active area of a silicon wafer according to an embodiment of the invention.
    • DETAILED DESCRIPTION OF THE DRAWINGS
  • The method for forming a high quality gate oxide layer on a bulk silicon active area will be explained in the context of a conventional integrated circuit process flow. Referring now to FIG. 1, a semiconductor wafer has been subjected to a conventional field oxidation process known as LOCOS. The process involved forming a pad oxide layer 11 on top of the entire wafer, depositing an oxygen-impermeable silicon nitride layer on top of the pad oxide layer, patterning and etching the silicon nitride layer to form silicon nitride islands 12 which masked the active areas 13, and subjecting the wafer to an oxidation step which has formed field oxide regions 14.
  • Referring now to FIG. 2, the silicon nitride islands 12 have been stripped, following which the pad oxide layer 11 that was beneath the islands is stripped in an oxygen-free environment to prevent a native oxide layer from forming on the exposed substrate once the pad oxide layer 11 is stripped.
  • Referring now to FIG. 3, with the in-process wafer of FIG. 2 still being maintained in an oxygen-free environment, an epitaxial silicon layer 31 is selectively grown on top of the active areas 13. With selective epitaxial growth, no silicon is deposited on the field oxide regions 14. At an atomic level during the epitaxial growth step, silicon atoms possessing high surface mobility are deposited on the bare single-crystal silicon substrate in the active areas. The atoms migrate to sites on the single crystal substrate where nucleation is favored, thus forming a virtually defect-free layer of epitaxial silicon on top of the silicon substrate in the active areas 13.
  • Referring now to FIG. 4, the in-process wafer is subjected to a thermal oxidation step, which oxidizes an upper portion 33 of the epitaxial layer 31 (FIG. 3) to form a gate oxide layer 41. The oxidation step is allowed to proceed until the appropriate thickness of gate oxide is achieved. It is essential that between the epitaxial growth step depicted in FIG. 3 and the oxidation step depicted in FIG. 4, the wafer be protected from the atmosphere to prevent the formation of a native oxide layer on the active areas. Thus, the wafer must either be maintained in an inert atmosphere or in a vacuum chamber in which the partial pressure of oxygen is very nearly zero. Processing of the wafer following the formation of the high-quality gate oxide layer 41 may be entirely conventional, with a polysilicon layer or a layer of other material suitable for gate electrodes being deposited on top of the gate oxide layer 41. The polysilicon layer is doped, then patterned and etched to form gate electrodes.
  • Through the process of the embodiments of the present invention, the quality of gate oxide dielectric layers is thus improved by using the two-pronged approach described above. In order to eliminate defects caused by imperfections in the bulk silicon, an in-situ grown epitaxial layer is formed on active areas following a strip of the pad oxide layer used beneath the silicon nitride pattern used for masking during the field oxidation process. By growing an epitaxial silicon layer prior to gate dielectric layer formation, defects in the bulk silicon substrate are covered over and, hence, isolated from the oxide growth step.
  • In order to maintain the integrity of the selective epitaxial growth step, the wafers are maintained in a controlled, oxygen-free environment until the epitaxial growth step is accomplished. In the alternative, the controlled environment is a low-pressure, virtually oxygen-free environment. In order to eliminate defects caused by a native oxide layer, the wafers are maintained in a controlled, oxygen-free environment until being subjected to elevated temperature in a controlled, oxidizing environment. In one embodiment, the oxidizing environment comprises diatomic oxygen, while in another embodiment, the oxidizing environment comprises diatomic oxygen and ozone.
  • Although some embodiments of the invention have been disclosed herein, it will be obvious to those having ordinary skill in the art of integrated circuit manufacture that certain changes and modifications may be made thereto without departing from the scope of the invention as hereinafter claimed.

Claims (20)

1. A method comprising:
forming a pad oxide layer on a silicon wafer;
forming a nitride island on the pad oxide layer and over a first area of the silicon wafer;
forming field oxide regions in a second area and a third area of the silicon wafer;
stripping the nitride island;
stripping the pad oxide layer in an oxygen-free environment, wherein the pad oxide layer being stripped in the oxygen-free environment is the pad oxide layer formed beneath the nitride island before the nitride island was stripped;
maintaining the silicon wafer in a controlled environment;
exposing the first area while the controlled environment is in a first state, wherein the first state is the oxygen-free environment;
growing an epitaxial silicon layer only on the surface of the first area while depositing substantially no silicon on the field oxide regions, and while the controlled environment is in the first state;
oxidizing at least a portion of the epitaxial silicon layer while the controlled environment is in a second state, wherein the second state is an oxidizing environment; and
maintaining the controlled environment in the first state continuously between growing the epitaxial silicon layer and oxidizing at least the portion of the epitaxial silicon layer.
2. The method of claim 1, further comprising:
preventing a formation of a native oxide layer on the surface of the first area before growing the epitaxial silicon layer.
3. The method of claim 1, wherein the oxidizing environment comprising diatomic oxygen.
4. The method of claim 1, wherein the oxidizing environment comprising ozone and diatomic oxygen.
5. The method of claim 1, wherein the oxygen free environment is a low pressure environment.
6. A method comprising:
forming a pad oxide layer on a silicon wafer;
forming a nitride island on the pad oxide layer and over an active area of the silicon wafer;
forming field oxide regions in a first non-active area and a second non-active area of the silicon wafer;
stripping the nitride island;
stripping the pad oxide layer in an oxygen-free environment, wherein the pad oxide layer being stripped in the oxygen-free environment is the pad oxide layer formed beneath the nitride island before the nitride island was stripped;
maintaining the silicon wafer in a controlled environment;
exposing the first area while the controlled environment is in an active state, wherein the first state is the oxygen-free environment;
growing an epitaxial silicon layer only on the surface of the first area while depositing substantially no silicon on the field oxide regions, and while the controlled environment is in the first state;
forming a non-sacrificial oxide layer from at least a portion of the epitaxial silicon layer while the controlled environment is in a non-active state, wherein the second state is an oxidizing environment; and
maintaining the controlled environment in the first state continuously between growing the epitaxial silicon layer and oxidizing at least the portion of the epitaxial silicon layer.
7. The method of claim 6, wherein forming the non-sacrificial oxide layer includes thermally oxidizing at least a portion of the epitaxial silicon layer.
8. The method of claim 7, wherein the oxidizing environment comprising diatomic oxygen.
9. The method of claim 7, wherein the oxidizing environment comprising ozone and diatomic oxygen.
10. The method of claim 7, further comprising:
preventing a formation of a native oxide layer on the surface of the first area before growing the epitaxial silicon layer.
11. A method comprising:
forming a pad oxide layer on a silicon wafer;
forming a mask on the pad oxide layer and over a first area of the silicon wafer;
forming field oxide regions in a second area and a third area of the silicon wafer;
removing the mask;
stripping the pad oxide layer in an oxygen-free environment, wherein the pad oxide layer being stripped in the oxygen-free environment is the pad oxide layer formed beneath the mask before the mask was removed;
maintaining the silicon wafer in a controlled environment;
exposing the first area while the controlled environment is in a first state, wherein the first state is the oxygen-free environment;
growing an epitaxial silicon layer only on the surface of the first area while depositing substantially no silicon on the field oxide regions, and while the controlled environment is in the first state;
forming a gate oxide dielectric layer from the epitaxial silicon layer while the controlled environment is in a second state, wherein the second state is an oxidizing environment; and
maintaining the controlled environment in the first state continuously between growing the epitaxial silicon layer and forming the non-sacrificial oxide layer.
12. The method of claim 11, wherein the oxygen free environment is a low pressure environment.
13. The method of claim 12, further comprising:
preventing a formation of a native oxide layer on the surface of the active area before growing the epitaxial silicon layer.
14. The method of claim 13, wherein the oxidizing environment comprising diatomic oxygen.
15. The method of claim 13, wherein the oxidizing environment comprising ozone and diatomic oxygen.
16. A method comprising:
forming a pad oxide layer on a silicon wafer;
forming a nitride island on the pad oxide layer and over a first area of the silicon wafer;
forming field oxide regions in a second area and a third area of the silicon wafer;
stripping the nitride island;
stripping the pad oxide layer in an oxygen-free environment, wherein the pad oxide layer being stripped in the oxygen-free environment is the pad oxide layer formed beneath the nitride island before the nitride island was stripped;
maintaining the silicon wafer in a controlled environment;
exposing the first area while the controlled environment is in a first state, wherein the first state is the oxygen-free environment;
growing an epitaxial silicon layer only on the surface of the first area while depositing substantially no silicon on the field oxide regions, and while the controlled environment is in the first state;
thermally oxidizing at least a portion of the epitaxial silicon layer while the controlled environment is in a second state to form a gate oxide dielectric layer, wherein the second state is an oxidizing environment;
maintaining the controlled environment in the first state continuously between growing the epitaxial silicon layer and forming the non-sacrificial oxide layer;
forming a gate electrode layer over the gate oxide dielectric layer.
17. The method of claim 16, wherein the oxygen free environment is a low pressure environment.
18. The method of claim 16, further comprising:
preventing a formation of a native oxide layer on the surface of the active area before growing the epitaxial silicon layer.
19. The method of claim 16, wherein the oxidizing environment comprising diatomic oxygen, and ozone and diatomic oxygen.
20. The method of claim 16, wherein the oxidizing environment comprising ozone and diatomic oxygen.
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US20080149988A1 (en) * 2006-12-22 2008-06-26 Hiroyuki Kinoshita Semiconductor memory devices and methods for fabricating the same
US20100163997A1 (en) * 2008-12-29 2010-07-01 Texas Instruments Incorporated Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated circuits therefrom

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