US20060267078A1 - Charge-trapping memory device - Google Patents
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- US20060267078A1 US20060267078A1 US11/141,254 US14125405A US2006267078A1 US 20060267078 A1 US20060267078 A1 US 20060267078A1 US 14125405 A US14125405 A US 14125405A US 2006267078 A1 US2006267078 A1 US 2006267078A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- This invention concerns memory devices comprising arrays of charge-trapping memory cells.
- Nonvolatile memory cells that are electrically programmable and erasable can be realized as charge-trapping memory cells, which comprise a memory layer sequence of dielectric materials with a memory layer between confinement layers of dielectric material having a larger energy band gap than the memory layer.
- the memory layer sequence is arranged between a channel region within a semiconductor body and a gate electrode provided to control the channel by means of an applied electric voltage.
- Examples of charge-trapping memory cells are the SONOS memory cells, in which each confinement layer is an oxide and the memory layer is a nitride of the semiconductor material, usually silicon (U.S. Pat. Nos. 5,768,192, and 6,011,725, which are incorporated herein by reference).
- Charge carriers are accelerated from source to drain through the channel region and gain enough energy to be able to penetrate the lower confinement layer and to be trapped within the memory layer.
- the trapped charge carriers change the threshold voltage of the cell transistor structure. Different programming states can be read by applying the appropriate reading voltages.
- the oxide-nitride-oxide layer sequence is especially designed to avoid the direct tunneling regime and to guarantee the vertical retention of the trapped charge carriers.
- the oxide layers are specified to have a thickness of more than 5 nm.
- the memory layer can be substituted with another dielectric material, provided the energy band gap is smaller than the energy band gap of the confinement layers.
- the difference in the energy band gaps should be as great as possible to secure a good charge carrier confinement and thus a good data retention.
- the memory layer may be tantalum oxide, cadmium silicate, titanium oxide, zirconium oxide or aluminum oxide. Also intrinsically conducting (non-doped) silicon may be used as the material of the memory layer.
- a semiconductor memory device comprises an array of memory cells provided for the storage of information and an addressing circuitry that is located in a peripheral area.
- CMOS field-effect transistors are important logic components of the addressing circuits. Source and drain regions of these field-effect transistors are arranged at a certain distance from the gate electrodes. In the production process, therefore, sidewall spacers at flanks of the gate electrode stacks are used to implant the source/drain regions so that the pn junctions between the doped regions and the basic semiconductor material are located at a distance from the gate electrode. To this end, a nitride liner is deposited on the surfaces of the substrate or semiconductor body and the gate electrode stacks.
- This liner protects the areas of shallow trench isolations between the devices and serves as an etching stop layer for the RIE (reactive iron etching) of the oxide spacers.
- the oxide spacers are removed, usually by means of wet chemical etching.
- the oxide spacers are preferably formed as TEOS (tetraethylorthosilicate) spacers, and the oxide is applied directly onto the nitride liner. The oxide can be removed selectively to the nitride of the liner. Therefore, the nitride liner is suitable as an etching stop layer in this production step.
- a nitride liner which is applied all over the surface of the device and thus covers also the area of the memory cell array, shows negative effects on the performance of the memory cell transistors.
- the nitride liner is directly adjacent to the wordline stack of the memory cells and is in contact with the memory layer sequence, which is usually oxide/nitride/oxide. This is supposed to cause poor values of retention after cycling (RAC), which is one of the key parameters to be optimized in a charge-trapping memory device.
- RAC retention after cycling
- Insufficient RAC values are probably related to a high trapping density of charge carriers in the nitride liner and/or to high mechanical stress caused by the nitride liner being deposited directly on the memory layer sequence so that a formation of leakage paths in the memory layer sequence may result.
- the present invention provides a charge-trapping memory device with improved retention after cycling values, especially an NROM cell comprising an oxide-nitride-oxide memory layer sequence.
- this invention removes the difficulties deriving from the application of a nitride liner adjacent to the memory layer sequence.
- a solution to achieve advantages is the formation of an oxidized region underneath the nitride liner and especially the formation of lateral oxidized regions between the memory layer sequence and the nitride liner.
- the oxide serves to cause a stress relaxation at the location between the nitride liner and the semiconductor body or substrate and bars the loss of charge carriers out of the memory layer into the liner nitride.
- the oxidized region can be produced by the growth of a thermal oxide using rapid thermal oxidation (RTO) or radical-based oxidation. Both these methods can replace a standard anneal to activate the implanted dopant under nitrogen atmosphere, which provides the additional advantage that no further production step is necessary.
- RTO rapid thermal oxidation
- the process option of radical-based oxidation oxidizes besides the bulk semiconductor material, preferably silicon, also the nitride of an oxide-nitride-oxide memory layer sequence and thus enables a spatial separation of the memory layer from the nitride liner.
- the loss of charge carriers moving into the nitride liner can thus effectively be inhibited.
- Other process steps, especially the formation of the TEOS spacers, are not affected unfavorably.
- FIG. 1 shows a cross-section of a section of the memory cell array before theapplication of the nitride liner
- FIG. 2 shows the cross-section according to FIG. 1 after the formation of theoxidized regions
- FIG. 3 shows the cross-section according to FIG. 2 of another embodiment
- FIG. 4 shows the cross-section according to FIG. 2 after the application of the nitride liner and the spacer layer;
- FIG. 5 shows the cross-section according to FIG. 3 after the application of the nitride liner and the spacer layer
- FIG. 6 shows a cross-section of a section of the addressing periphery after the formation of the oxide spacers.
- FIG. 1 shows a cross-section of the memory cell array transverse to the longitudinal direction of the wordlines.
- the semiconductor body e.g., a substrate 1 , source/drain regions 2 , a memory layer sequence 3 comprising a lower boundary layer 31 , a memory layer 32 , and an upper boundary layer 33 , the wordline stacks 4 including the gate electrodes of the cell transistors with sidewall insulations 7 in spacer form and top insulations 8 and an oxide layer 9 covering the sidewalls of the wordline stacks and forming a part of the upper boundary layer 33 are shown for an intermediate product of a typical preferred embodiment.
- the wordline stacks 4 are shown as double-layer strips extending perpendicularly to the drawing plane and typically comprising a lower layer of preferably polysilicon, encompassing the gate electrodes of the transistor structures of the memory cells, and an upper electrically conductive wordline layer, which is provided to reduce the track resistance.
- the upper portion can be a silicide such as tungsten silicide, cobalt silicide or nickel silicide, as examples.
- the structure shown in the cross-section of FIG. 1 is the intermediate product of the manufacturing process on which the nitride liner is to be applied.
- the surface of the semiconductor body or substrate 1 in the areas above the source/drain regions 2 is oxidized to form the oxidized regions 10 , which are shown in FIG. 2 .
- FIG. 2 shows the cross-section according to FIG. 1 after the formation of the oxidized regions 10 and an annealing step to activate the implanted dopant, which results in an extension of the dimensions of the source/drain regions 2 .
- the remaining partial layer of the lower boundary layer 31 which may be an oxide, is indicated by the broken line in the oxidized region 10 . This remaining partial lower boundary layer 31 is lifted when the semiconductor material of the semiconductor body or substrate 1 is oxidized and the volume of the oxidized material is considerably increased.
- FIG. 3 shows the cross-section according to FIG. 2 for another embodiment, which comprises lateral oxidized regions 101 located between the memory layer sequence and the nitride liner.
- These lateral oxidized regions 101 can preferably be produced by means of a radical-based oxidation process instead of an annealing procedure under nitrogen atmosphere.
- the sidewall insulations 7 and the top insulations 8 can preferably be nitride.
- the radical-based oxidation produces thin oxidized layers 14 that cover the surfaces of the nitride material, as shown in FIG. 3 .
- FIGS. 4 and 5 show cross-sections according to the cross-sections of FIGS. 2 and 3 , respectively, after the application of the nitride liner 11 and the spacer layer 12 .
- the nitride liner is applied all over the surface, including the wordline stacks.
- the spacer layer 12 is first conformally deposited and subsequently anisotropically etched back to form the sidewall spacers in the addressing periphery and the remaining parts shown in FIGS. 4 and 5 within the small spaces between neighboring wordline stacks.
- FIG. 4 shows that the nitride liner 11 is spaced apart from the semiconductor material underneath by the oxidized region 10 .
- the alternative embodiment according to FIG. 5 also comprises lateral oxidized regions, which here separate the nitride liner 11 also from the memory layer sequence 3 , especially from the memory layer itself, which may be nitride in preferred embodiments.
- the oxidized region 10 thus hinders or inhibits a leakage of charge carriers from the memory layer into the nitride liner 11 .
- FIG. 5 therefore shows the preferred embodiment, although also the embodiment according to FIG. 4 provides an inventive improvement leading to better RAC values.
- FIG. 6 shows a cross-section of the peripheral area of the device with the semiconductor body or substrate 1 , the source/drain region 2 , the gate dielectric 5 , and the gate electrodes 6 .
- the gate electrodes 6 are here represented as parts of layer stacks, with a lower layer forming the gate electrode 6 , which may be doped polysilicon, and an upper layer, which can be a metal or a metal silicide.
- the sidewall spacers 13 are arranged above the nitride liner 11 .
- the spacers 13 are provided for the implantation step as a mask to reduce the lateral dimension of the source/drain regions 2 .
- the gate dielectric 5 comprises a partial layer that is formed of oxidized semiconductor material so that the lower boundary of the gate dielectric layer is slightly lower in the area between the gate electrode stacks than in the area beneath the stacks.
- the nitride liner 11 here serves as the etching stop layer when the sidewall spacers 13 are anisotropically etched, starting from a conformally deposited layer of the spacer material.
- both the stress release and the spatial separation between the memory layer sequence and the nitride liner have a positive impact on the RAC performance of the device, while the formation of the spacers in the peripheral area is not adversely affected and can be effected in the established manner.
Abstract
Description
- This invention concerns memory devices comprising arrays of charge-trapping memory cells.
- Nonvolatile memory cells that are electrically programmable and erasable can be realized as charge-trapping memory cells, which comprise a memory layer sequence of dielectric materials with a memory layer between confinement layers of dielectric material having a larger energy band gap than the memory layer. The memory layer sequence is arranged between a channel region within a semiconductor body and a gate electrode provided to control the channel by means of an applied electric voltage. Examples of charge-trapping memory cells are the SONOS memory cells, in which each confinement layer is an oxide and the memory layer is a nitride of the semiconductor material, usually silicon (U.S. Pat. Nos. 5,768,192, and 6,011,725, which are incorporated herein by reference).
- Charge carriers are accelerated from source to drain through the channel region and gain enough energy to be able to penetrate the lower confinement layer and to be trapped within the memory layer. The trapped charge carriers change the threshold voltage of the cell transistor structure. Different programming states can be read by applying the appropriate reading voltages.
- A publication by B. Eitan et al., “NROM: a Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell” in IEEE Electron Device Letters, volume 21, pages 543 to 545 (2000), describes a charge-trapping memory cell with a memory layer sequence of oxide, nitride and oxide, which is especially adapted to be operated with a reading voltage that is reverse to the programming voltage (reverse read). The oxide-nitride-oxide layer sequence is especially designed to avoid the direct tunneling regime and to guarantee the vertical retention of the trapped charge carriers. The oxide layers are specified to have a thickness of more than 5 nm.
- The memory layer can be substituted with another dielectric material, provided the energy band gap is smaller than the energy band gap of the confinement layers. The difference in the energy band gaps should be as great as possible to secure a good charge carrier confinement and thus a good data retention. When using silicon dioxide as confinement layers, the memory layer may be tantalum oxide, cadmium silicate, titanium oxide, zirconium oxide or aluminum oxide. Also intrinsically conducting (non-doped) silicon may be used as the material of the memory layer.
- A semiconductor memory device comprises an array of memory cells provided for the storage of information and an addressing circuitry that is located in a peripheral area. CMOS field-effect transistors are important logic components of the addressing circuits. Source and drain regions of these field-effect transistors are arranged at a certain distance from the gate electrodes. In the production process, therefore, sidewall spacers at flanks of the gate electrode stacks are used to implant the source/drain regions so that the pn junctions between the doped regions and the basic semiconductor material are located at a distance from the gate electrode. To this end, a nitride liner is deposited on the surfaces of the substrate or semiconductor body and the gate electrode stacks. This liner protects the areas of shallow trench isolations between the devices and serves as an etching stop layer for the RIE (reactive iron etching) of the oxide spacers. After the implantations of the source/drain regions have taken place, the oxide spacers are removed, usually by means of wet chemical etching. The oxide spacers are preferably formed as TEOS (tetraethylorthosilicate) spacers, and the oxide is applied directly onto the nitride liner. The oxide can be removed selectively to the nitride of the liner. Therefore, the nitride liner is suitable as an etching stop layer in this production step.
- However, a nitride liner, which is applied all over the surface of the device and thus covers also the area of the memory cell array, shows negative effects on the performance of the memory cell transistors. The nitride liner is directly adjacent to the wordline stack of the memory cells and is in contact with the memory layer sequence, which is usually oxide/nitride/oxide. This is supposed to cause poor values of retention after cycling (RAC), which is one of the key parameters to be optimized in a charge-trapping memory device. Insufficient RAC values are probably related to a high trapping density of charge carriers in the nitride liner and/or to high mechanical stress caused by the nitride liner being deposited directly on the memory layer sequence so that a formation of leakage paths in the memory layer sequence may result.
- In one aspect, the present invention provides a charge-trapping memory device with improved retention after cycling values, especially an NROM cell comprising an oxide-nitride-oxide memory layer sequence.
- In a further aspect, this invention removes the difficulties deriving from the application of a nitride liner adjacent to the memory layer sequence.
- A solution to achieve advantages is the formation of an oxidized region underneath the nitride liner and especially the formation of lateral oxidized regions between the memory layer sequence and the nitride liner. The oxide serves to cause a stress relaxation at the location between the nitride liner and the semiconductor body or substrate and bars the loss of charge carriers out of the memory layer into the liner nitride. The oxidized region can be produced by the growth of a thermal oxide using rapid thermal oxidation (RTO) or radical-based oxidation. Both these methods can replace a standard anneal to activate the implanted dopant under nitrogen atmosphere, which provides the additional advantage that no further production step is necessary. The process option of radical-based oxidation oxidizes besides the bulk semiconductor material, preferably silicon, also the nitride of an oxide-nitride-oxide memory layer sequence and thus enables a spatial separation of the memory layer from the nitride liner. The loss of charge carriers moving into the nitride liner can thus effectively be inhibited. Other process steps, especially the formation of the TEOS spacers, are not affected unfavorably.
- These and other features and advantages of the invention will become apparent from the following brief description of the drawings, detailed description and appended claims and drawings.
- For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:
-
FIG. 1 shows a cross-section of a section of the memory cell array before theapplication of the nitride liner; -
FIG. 2 shows the cross-section according toFIG. 1 after the formation of theoxidized regions; -
FIG. 3 shows the cross-section according toFIG. 2 of another embodiment; -
FIG. 4 shows the cross-section according toFIG. 2 after the application of the nitride liner and the spacer layer; -
FIG. 5 shows the cross-section according toFIG. 3 after the application of the nitride liner and the spacer layer; and -
FIG. 6 shows a cross-section of a section of the addressing periphery after the formation of the oxide spacers. - The following list of reference symbols can be used in conjunction with the figures:
1 substrate 7 sidewall insulation 2 source/ drain region 8 top insulation 3 memory layer sequence 9 oxide layer 31 lower boundary layer 10 oxidized region 32 memory layer 101 lateral oxidized region 33 upper boundary layer 11 nitride liner 4 wordline stack 12 spacer layer 5 gate dielectric 13 sidewall spacer 6 gate electrode 14 oxidized layer - The features of an embodiment of the device according to embodiments of this invention are further described following a preferred production process.
FIG. 1 shows a cross-section of the memory cell array transverse to the longitudinal direction of the wordlines. The semiconductor body, e.g., a substrate 1, source/drain regions 2, amemory layer sequence 3 comprising alower boundary layer 31, amemory layer 32, and anupper boundary layer 33, thewordline stacks 4 including the gate electrodes of the cell transistors with sidewall insulations 7 in spacer form andtop insulations 8 and anoxide layer 9 covering the sidewalls of the wordline stacks and forming a part of theupper boundary layer 33 are shown for an intermediate product of a typical preferred embodiment. - Between the spacers of the sidewall insulations 7, the memory layer sequence has been removed to leave only a thin residual layer of the
lower boundary layer 31. Instead, the wholememory layer sequence 3 can be left also in the areas above the source/drain regions 2. Thewordline stacks 4 are shown as double-layer strips extending perpendicularly to the drawing plane and typically comprising a lower layer of preferably polysilicon, encompassing the gate electrodes of the transistor structures of the memory cells, and an upper electrically conductive wordline layer, which is provided to reduce the track resistance. The upper portion can be a silicide such as tungsten silicide, cobalt silicide or nickel silicide, as examples. - The structure shown in the cross-section of
FIG. 1 is the intermediate product of the manufacturing process on which the nitride liner is to be applied. In order to produce the structure of the inventive device, the surface of the semiconductor body or substrate 1 in the areas above the source/drain regions 2 is oxidized to form the oxidizedregions 10, which are shown inFIG. 2 . -
FIG. 2 shows the cross-section according toFIG. 1 after the formation of the oxidizedregions 10 and an annealing step to activate the implanted dopant, which results in an extension of the dimensions of the source/drain regions 2. The remaining partial layer of thelower boundary layer 31, which may be an oxide, is indicated by the broken line in the oxidizedregion 10. This remaining partiallower boundary layer 31 is lifted when the semiconductor material of the semiconductor body or substrate 1 is oxidized and the volume of the oxidized material is considerably increased. -
FIG. 3 shows the cross-section according toFIG. 2 for another embodiment, which comprises lateral oxidizedregions 101 located between the memory layer sequence and the nitride liner. These lateral oxidizedregions 101 can preferably be produced by means of a radical-based oxidation process instead of an annealing procedure under nitrogen atmosphere. The sidewall insulations 7 and thetop insulations 8 can preferably be nitride. In this case, the radical-based oxidation produces thinoxidized layers 14 that cover the surfaces of the nitride material, as shown inFIG. 3 . -
FIGS. 4 and 5 show cross-sections according to the cross-sections ofFIGS. 2 and 3 , respectively, after the application of thenitride liner 11 and thespacer layer 12. As can be seen fromFIGS. 4 and 5 , the nitride liner is applied all over the surface, including the wordline stacks. Thespacer layer 12 is first conformally deposited and subsequently anisotropically etched back to form the sidewall spacers in the addressing periphery and the remaining parts shown inFIGS. 4 and 5 within the small spaces between neighboring wordline stacks. -
FIG. 4 shows that thenitride liner 11 is spaced apart from the semiconductor material underneath by the oxidizedregion 10. - The alternative embodiment according to
FIG. 5 also comprises lateral oxidized regions, which here separate thenitride liner 11 also from thememory layer sequence 3, especially from the memory layer itself, which may be nitride in preferred embodiments. The oxidizedregion 10 thus hinders or inhibits a leakage of charge carriers from the memory layer into thenitride liner 11.FIG. 5 therefore shows the preferred embodiment, although also the embodiment according toFIG. 4 provides an inventive improvement leading to better RAC values. -
FIG. 6 shows a cross-section of the peripheral area of the device with the semiconductor body or substrate 1, the source/drain region 2, thegate dielectric 5, and thegate electrodes 6. Thegate electrodes 6 are here represented as parts of layer stacks, with a lower layer forming thegate electrode 6, which may be doped polysilicon, and an upper layer, which can be a metal or a metal silicide. The sidewall spacers 13 are arranged above thenitride liner 11. Thespacers 13 are provided for the implantation step as a mask to reduce the lateral dimension of the source/drain regions 2.FIG. 6 shows that thegate dielectric 5 comprises a partial layer that is formed of oxidized semiconductor material so that the lower boundary of the gate dielectric layer is slightly lower in the area between the gate electrode stacks than in the area beneath the stacks. Thenitride liner 11 here serves as the etching stop layer when thesidewall spacers 13 are anisotropically etched, starting from a conformally deposited layer of the spacer material. - It is an advantage of the memory device according to embodiments of this invention that both the stress release and the spatial separation between the memory layer sequence and the nitride liner have a positive impact on the RAC performance of the device, while the formation of the spacers in the peripheral area is not adversely affected and can be effected in the established manner.
- Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (18)
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US11/141,254 US7144776B1 (en) | 2005-05-31 | 2005-05-31 | Charge-trapping memory device |
DE102005027714A DE102005027714A1 (en) | 2005-05-31 | 2005-06-15 | Charge-trapping memory device |
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US11/141,254 US7144776B1 (en) | 2005-05-31 | 2005-05-31 | Charge-trapping memory device |
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US20060267078A1 true US20060267078A1 (en) | 2006-11-30 |
US7144776B1 US7144776B1 (en) | 2006-12-05 |
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US11/141,254 Expired - Fee Related US7144776B1 (en) | 2005-05-31 | 2005-05-31 | Charge-trapping memory device |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060281255A1 (en) * | 2005-06-14 | 2006-12-14 | Chun-Jen Chiu | Method for forming a sealed storage non-volative multiple-bit memory cell |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5768192A (en) * | 1996-07-23 | 1998-06-16 | Saifun Semiconductors, Ltd. | Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping |
US5830784A (en) * | 1993-05-26 | 1998-11-03 | Semiconductor Energy Laboratory Company, Ltd. | Method for producing a semiconductor device including doping with a group IV element |
US5966603A (en) * | 1997-06-11 | 1999-10-12 | Saifun Semiconductors Ltd. | NROM fabrication method with a periphery portion |
US6011725A (en) * | 1997-08-01 | 2000-01-04 | Saifun Semiconductors, Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US6426247B1 (en) * | 2001-01-17 | 2002-07-30 | International Business Machines Corporation | Low bitline capacitance structure and method of making same |
US20030205727A1 (en) * | 2001-03-17 | 2003-11-06 | Samsung Electronics Co., Ltd | Flash memory device and a method for fabricating the same |
US6869843B2 (en) * | 2003-06-27 | 2005-03-22 | Macronix International Co., Ltd. | Non-volatile memory cell with dielectric spacers along sidewalls of a component stack, and method for forming same |
US6913987B2 (en) * | 2002-12-05 | 2005-07-05 | Infineon Technologies Ag | Method for fabricating self-aligned contact connections on buried bit lines |
US7041545B2 (en) * | 2004-03-08 | 2006-05-09 | Infineon Technologies Ag | Method for producing semiconductor memory devices and integrated memory device |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5830794A (en) | 1996-03-11 | 1998-11-03 | Ricoh Company, Ltd. | Method of fabricating semiconductor memory |
-
2005
- 2005-05-31 US US11/141,254 patent/US7144776B1/en not_active Expired - Fee Related
- 2005-06-15 DE DE102005027714A patent/DE102005027714A1/en not_active Withdrawn
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5830784A (en) * | 1993-05-26 | 1998-11-03 | Semiconductor Energy Laboratory Company, Ltd. | Method for producing a semiconductor device including doping with a group IV element |
US5768192A (en) * | 1996-07-23 | 1998-06-16 | Saifun Semiconductors, Ltd. | Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping |
US5966603A (en) * | 1997-06-11 | 1999-10-12 | Saifun Semiconductors Ltd. | NROM fabrication method with a periphery portion |
US6011725A (en) * | 1997-08-01 | 2000-01-04 | Saifun Semiconductors, Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US6426247B1 (en) * | 2001-01-17 | 2002-07-30 | International Business Machines Corporation | Low bitline capacitance structure and method of making same |
US20030205727A1 (en) * | 2001-03-17 | 2003-11-06 | Samsung Electronics Co., Ltd | Flash memory device and a method for fabricating the same |
US6913987B2 (en) * | 2002-12-05 | 2005-07-05 | Infineon Technologies Ag | Method for fabricating self-aligned contact connections on buried bit lines |
US6869843B2 (en) * | 2003-06-27 | 2005-03-22 | Macronix International Co., Ltd. | Non-volatile memory cell with dielectric spacers along sidewalls of a component stack, and method for forming same |
US7041545B2 (en) * | 2004-03-08 | 2006-05-09 | Infineon Technologies Ag | Method for producing semiconductor memory devices and integrated memory device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060281255A1 (en) * | 2005-06-14 | 2006-12-14 | Chun-Jen Chiu | Method for forming a sealed storage non-volative multiple-bit memory cell |
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DE102005027714A1 (en) | 2006-12-07 |
US7144776B1 (en) | 2006-12-05 |
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