US20060273408A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- US20060273408A1 US20060273408A1 US11/476,867 US47686706A US2006273408A1 US 20060273408 A1 US20060273408 A1 US 20060273408A1 US 47686706 A US47686706 A US 47686706A US 2006273408 A1 US2006273408 A1 US 2006273408A1
- Authority
- US
- United States
- Prior art keywords
- film
- metal
- nitrogen
- gas
- silicate film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 229910052914 metal silicate Inorganic materials 0.000 claims abstract description 58
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 48
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 42
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 37
- 239000010703 silicon Substances 0.000 claims abstract description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 239000010408 film Substances 0.000 description 280
- 239000007789 gas Substances 0.000 description 97
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 53
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 46
- 239000000463 material Substances 0.000 description 44
- 238000000034 method Methods 0.000 description 44
- 239000010410 layer Substances 0.000 description 40
- 229910052814 silicon oxide Inorganic materials 0.000 description 40
- 239000012535 impurity Substances 0.000 description 30
- 229910000449 hafnium oxide Inorganic materials 0.000 description 29
- 238000010438 heat treatment Methods 0.000 description 22
- 230000015572 biosynthetic process Effects 0.000 description 21
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 20
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 20
- 229960005419 nitrogen Drugs 0.000 description 19
- 239000010409 thin film Substances 0.000 description 18
- UKLSEQWAHKCNJT-UHFFFAOYSA-N CC(C)C(C)(C)[NH-].CC(C)C(C)(C)[NH-].CC(C)C(C)(C)[NH-].CC(C)C(C)(C)[NH-].[Hf+4] Chemical compound CC(C)C(C)(C)[NH-].CC(C)C(C)(C)[NH-].CC(C)C(C)(C)[NH-].CC(C)C(C)(C)[NH-].[Hf+4] UKLSEQWAHKCNJT-UHFFFAOYSA-N 0.000 description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 15
- 229920005591 polysilicon Polymers 0.000 description 15
- 238000010926 purge Methods 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 14
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 12
- 238000000231 atomic layer deposition Methods 0.000 description 11
- 229910052786 argon Inorganic materials 0.000 description 10
- 229910052735 hafnium Inorganic materials 0.000 description 10
- GIRKRMUMWJFNRI-UHFFFAOYSA-N tris(dimethylamino)silicon Chemical compound CN(C)[Si](N(C)C)N(C)C GIRKRMUMWJFNRI-UHFFFAOYSA-N 0.000 description 9
- 238000000280 densification Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 229910052726 zirconium Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 150000004645 aluminates Chemical class 0.000 description 4
- 229910001873 dinitrogen Inorganic materials 0.000 description 4
- 230000001965 increasing effect Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000001590 oxidative effect Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000010453 quartz Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- YQNVPNRHJFZONU-UHFFFAOYSA-N 2,3-dimethylbutan-2-amine Chemical compound CC(C)C(C)(C)N YQNVPNRHJFZONU-UHFFFAOYSA-N 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 3
- XMIJDTGORVPYLW-UHFFFAOYSA-N [SiH2] Chemical compound [SiH2] XMIJDTGORVPYLW-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000035484 reaction time Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- RYXIJJYQTUUPEV-UHFFFAOYSA-N CC(C([NH-])(C)C)C.[Zr+4].CC(C(C)(C)[NH-])C.CC(C(C)(C)[NH-])C.CC(C(C)(C)[NH-])C Chemical compound CC(C([NH-])(C)C)C.[Zr+4].CC(C(C)(C)[NH-])C.CC(C(C)(C)[NH-])C.CC(C(C)(C)[NH-])C RYXIJJYQTUUPEV-UHFFFAOYSA-N 0.000 description 1
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 108091006146 Channels Proteins 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910052692 Dysprosium Inorganic materials 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910052693 Europium Inorganic materials 0.000 description 1
- 229910052688 Gadolinium Inorganic materials 0.000 description 1
- 229910052689 Holmium Inorganic materials 0.000 description 1
- 229910052765 Lutetium Inorganic materials 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910052777 Praseodymium Inorganic materials 0.000 description 1
- 229910052772 Samarium Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910020750 SixGey Inorganic materials 0.000 description 1
- 229910052771 Terbium Inorganic materials 0.000 description 1
- 229910052769 Ytterbium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-OUBTZVSYSA-N boron-12 Chemical compound [12B] ZOXJGFHDIHLPTG-OUBTZVSYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- VBCSQFQVDXIOJL-UHFFFAOYSA-N diethylazanide;hafnium(4+) Chemical compound [Hf+4].CC[N-]CC.CC[N-]CC.CC[N-]CC.CC[N-]CC VBCSQFQVDXIOJL-UHFFFAOYSA-N 0.000 description 1
- GOVWJRDDHRBJRW-UHFFFAOYSA-N diethylazanide;zirconium(4+) Chemical compound [Zr+4].CC[N-]CC.CC[N-]CC.CC[N-]CC.CC[N-]CC GOVWJRDDHRBJRW-UHFFFAOYSA-N 0.000 description 1
- UCXUKTLCVSGCNR-UHFFFAOYSA-N diethylsilane Chemical compound CC[SiH2]CC UCXUKTLCVSGCNR-UHFFFAOYSA-N 0.000 description 1
- ZYLGGWPMIDHSEZ-UHFFFAOYSA-N dimethylazanide;hafnium(4+) Chemical compound [Hf+4].C[N-]C.C[N-]C.C[N-]C.C[N-]C ZYLGGWPMIDHSEZ-UHFFFAOYSA-N 0.000 description 1
- DWCMDRNGBIZOQL-UHFFFAOYSA-N dimethylazanide;zirconium(4+) Chemical compound [Zr+4].C[N-]C.C[N-]C.C[N-]C.C[N-]C DWCMDRNGBIZOQL-UHFFFAOYSA-N 0.000 description 1
- UBHZUDXTHNMNLD-UHFFFAOYSA-N dimethylsilane Chemical compound C[SiH2]C UBHZUDXTHNMNLD-UHFFFAOYSA-N 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- KBQHZAAAGSGFKK-UHFFFAOYSA-N dysprosium atom Chemical compound [Dy] KBQHZAAAGSGFKK-UHFFFAOYSA-N 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- OGPBJKLSAFTDLK-UHFFFAOYSA-N europium atom Chemical compound [Eu] OGPBJKLSAFTDLK-UHFFFAOYSA-N 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- UIWYJDYFSGRHKR-UHFFFAOYSA-N gadolinium atom Chemical compound [Gd] UIWYJDYFSGRHKR-UHFFFAOYSA-N 0.000 description 1
- KJZYNXUDTRRSPN-UHFFFAOYSA-N holmium atom Chemical compound [Ho] KJZYNXUDTRRSPN-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 150000002500 ions Chemical group 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- OHSVLFRHMCKCQY-UHFFFAOYSA-N lutetium atom Chemical compound [Lu] OHSVLFRHMCKCQY-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- VYIRVGYSUZPNLF-UHFFFAOYSA-N n-(tert-butylamino)silyl-2-methylpropan-2-amine Chemical compound CC(C)(C)N[SiH2]NC(C)(C)C VYIRVGYSUZPNLF-UHFFFAOYSA-N 0.000 description 1
- GURMJCMOXLWZHZ-UHFFFAOYSA-N n-ethyl-n-[tris(diethylamino)silyl]ethanamine Chemical compound CCN(CC)[Si](N(CC)CC)(N(CC)CC)N(CC)CC GURMJCMOXLWZHZ-UHFFFAOYSA-N 0.000 description 1
- SSCVMVQLICADPI-UHFFFAOYSA-N n-methyl-n-[tris(dimethylamino)silyl]methanamine Chemical compound CN(C)[Si](N(C)C)(N(C)C)N(C)C SSCVMVQLICADPI-UHFFFAOYSA-N 0.000 description 1
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- PUDIUYLPXJFUGB-UHFFFAOYSA-N praseodymium atom Chemical compound [Pr] PUDIUYLPXJFUGB-UHFFFAOYSA-N 0.000 description 1
- 230000000754 repressing effect Effects 0.000 description 1
- KZUNJOHGWZRPMI-UHFFFAOYSA-N samarium atom Chemical compound [Sm] KZUNJOHGWZRPMI-UHFFFAOYSA-N 0.000 description 1
- 229910052706 scandium Inorganic materials 0.000 description 1
- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium atom Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- GZCRRIHWUXGPOV-UHFFFAOYSA-N terbium atom Chemical compound [Tb] GZCRRIHWUXGPOV-UHFFFAOYSA-N 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
- H01L21/02148—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing hafnium, e.g. HfSiOx or HfSiON
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3141—Deposition using atomic layer deposition techniques [ALD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
- H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31608—Deposition of SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31645—Deposition of Hafnium oxides, e.g. HfO2
Definitions
- the present invention relates to a semiconductor device using a metal silicate film as a gate insulating film, to a method for manufacturing such a semiconductor device, to an apparatus being available for forming film in such a semiconductor device, and to method being available for forming high-dielectric-constant film in such a semiconductor device.
- silicon oxide film and the like silicon oxynitride films
- a method for inhibiting leak current by using a high-dielectric-constant film such as a metal oxide film, a metal silicate film and a metal aluminate film, which has a higher specific inductive capacity higher than that of silicon oxide film and the like as the gate insulating film; and by increasing the physical film thickness of the gate insulating film.
- a method for forming a high-dielectric-constant film composed of a zirconium oxynitride layer or a hafnium oxynitride layer by forming a metal layer composed of zirconium or hafnium on a substrate, and oxynitriding the metal layer (refer to e.g., Japanese Patent Laid-Open No. 2000-58832).
- the ALD (atomic layer deposition) method is generally used.
- material gasses are alternately supplied while resetting the chamber to the original state to form each atomic layer.
- hafnium oxide (HfO 2 ) film as a high-dielectric-constant film.
- the chamber is evacuated, argon gas is flowed in the chamber, and the pressure in the chamber is maintained to 0.2 Torr.
- hafnium tetramethylethylamide [Hf(N(CH 3 )(C 2 H 5 ) 2 ) 4 ] is flowed into the chamber while controlling the flow rate, and the Hf material is vaporized and adsorbed on the surface of the substrate.
- the chamber is purged, and an oxidizing gas such as ozone gas is introduced. Thereafter, the chamber is purged.
- a hafnium oxide (HfO 2 ) film of a thickness of several nanometers can be formed on the surface of the substrate.
- Vfb shift flat-band-voltage shift
- a high-dielectric-constant thin film formed using the ALD method generally contains several percent impurities. This is considered because carbon (C), hydrogen (H) or chlorine (Cl) included in material gas using the ALD method remains and is incorporated in the formed film. The impurities remaining in the high-dielectric-constant film may cause fixed charge and trap, and the characteristics of the film is damaged.
- the one object of the present invention is to restrict initial Vfb shift, to form a gate insulating film having high film quantity, and to achieve satisfactory transistor characteristics.
- Another object of the present invention is to lower the impurity content in the high-dielectric-constant film of the gate insulating film.
- a semiconductor device comprises a substrate, a gate insulating film and a gate electrode.
- the gate insulating film is formed on the substrate, and has a nitrogen-containing metal silicate film or a nitrogen-containing metal aluminate film that contains a metal in a peak concentration of 1 atomic % or more and 30 atomic % or less on the uppermost layer.
- the gate electrode is formed on the gate insulating film.
- a semiconductor device comprises a substrate, a gate insulating film, and a gate electrode.
- the gate insulating film is formed on the substrate and has a base interface layer, a metal silicate film and a nitrogen-containing metal silicate film.
- the base interface layer is formed on the substrate.
- the metal silicate film is formed on the base interface layer, and contains a metal, oxygen and silicon.
- the nitrogen-containing metal silicate film contains a metal in a peak concentration of 1 atomic % or more and 30 atomic % or less, oxygen, silicon, and nitrogen.
- the gate electrode formed on the gate insulating film.
- a base interface layer is formed on a substrate.
- a metal silicate film containing a metal in a peak concentration of 1 atomic % or more and 30 atomic % or less is formed on the base interface layer.
- a nitrogen-containing metal silicate film containing nitrogen in a peak concentration of 10 atomic % or more and 30 atomic % or less is formed on the upper layer of the metal silicate film.
- a gate electrode is formed on the nitrogen-containing metal silicate film.
- a base interface layer is formed on a substrate.
- a metal silicate film containing a metal in a peak concentration of 5 atomic % or more and 40 atomic % or less is formed on the base interface layer.
- a nitrogen-containing metal silicate film containing a metal in a peak concentration of 1 atomic % or more and 30 atomic % or less and nitrogen in a peak concentration of 10 atomic % or more and 30 atomic % or less is formed on the metal silicate film.
- a gate electrode is formed on the nitrogen-containing metal silicate film.
- a apparatus for forming a film comprises a housing, a table installed in the housing, for placing a substrate, a gas supply port for supplying a gas into the housing, a gas discharge port for discharging the gas in the housing out of the housing, and a heater.
- the heater is for heating the surface of the substrate by radiating light on the surface of the substrate placed on the table for a time up to several milliseconds.
- a first material gas that contains at least one element in elements constituting the high-dielectric-constant film is supplied into a housing wherein the substrate is placed.
- a second material gas that reacts with the first material gas and forms the high-dielectric-constant film is supplied into the housing.
- the surface of the substrate is heated by radiating light onto the surface of the substrate for a time up to several milliseconds.
- FIG. 1 is a sectional view for illustrating a semiconductor device in the first embodiment of the present invention
- FIG. 2 is a flow diagram for illustrating a method for forming a metal silicate film in the first embodiment of the present invention
- FIG. 3 is a graph showing the relationship between the number of cycles and the thickness of the hafnium oxide film when the hafnium oxide film is formed using tetramethylethylamide as an Hf material;
- FIGS. 4A and 4B are graphs showing the relationship between the number of cycles and the thickness of the silicon oxide film when the silicon oxide film is formed using tris(dimethylamino)silane [SiH(N(CH 3 ) 2 ) 3 ] as an Si material;
- FIG. 5 is a graph showing the relationship between the number of cycles and the thickness of the Hf silicate film when a hafnium oxide film is formed using hafnium tetramethylethylamide [Hf(N(CH 3 )(C 2 H 5 ) 2 ) 4 ] as a Hf material, and a silicon oxide film is formed using tris(dimethylamino)silane [SiH(N(CH 3 ) 2 ) 3 ] as a Si material;
- FIG. 6 is a graph showing the relationship between the Hf/Si ratio and the Hf content in the Hf silicate film [Hf/(Hf+Si)] in the case wherein a hafnium oxide film is formed using hafnium tetramethylethylamide [Hf(N(CH 3 )(C 2 H 5 ) 2 ) 4 ] as a Hf material and a silicon oxide film is formed using tris(dimethylamino)silane [SiH(N(CH 3 ) 2 ) 3 ] as a Si material;
- FIG. 7 is a flow diagram for illustrating the method for manufacturing a semiconductor device in the first embodiment of the present invention.
- FIGS. 8A to 10 C are sectional views for illustrating the process for manufacturing a semiconductor device in the first embodiment of the present invention.
- FIGS. 11A and 11B are a graphs showing the C-V characteristics of a semiconductor device in the first embodiment of the present invention.
- FIG. 12 is a schematic diagram for illustrating a thin film forming apparatus in the second embodiment of the present invention.
- FIG. 13 is a flow diagram for illustrating the method for forming a metal silicate film in the second embodiment of the present invention.
- FIG. 14 is a graph for illustrating the sequence in the method for forming a metal silicate film in the second embodiment.
- FIG. 1 is a sectional view for illustrating a semiconductor device according to the first embodiment of the present invention. Specifically, FIG. 1 is a sectional view for illustrating a P-channel MOS transistor (hereafter referred to as “PMOS transistor”).
- PMOS transistor P-channel MOS transistor
- a substrate 1 is a p-type silicon substrate.
- an n-type well 2 to which an n-type impurity is introduced is formed in the substrate 1 .
- An element-isolating structure 3 is formed on the element-isolating region of the substrate 1 .
- the element-isolating structure 3 is an STI (shallow trench isolation) formed by filling a shallow trench formed from the surface side of the substrate 1 with a silicon oxide film.
- gate insulating films 4 a , 5 a and 6 a are laminated and a gate electrode 7 b is formed through the gate insulating films 4 a , 5 a and 6 a.
- the gate insulating film has a base interface layer 4 a formed on the substrate 1 , a high-dielectric-constant film 5 a formed on the base interface layer 4 a , and an upper layer insulating film 6 a formed on the high-dielectric-constant film 5 a .
- the base interface layer 4 a is silicon oxide film for repressing the reaction at the interface.
- the thickness of the base interface layer 4 a is preferably 1 nm or below, for example, about 0.5 nm.
- the high-dielectric-constant film 5 a is a metal silicate film that contains a metal, oxygen and silicon, and for example, an Hf (hafnium) silicate film or a Zr (zirconium) silicate film can be used.
- the thickness of the high-dielectric-constant film 5 a is, for example, about 3 nm.
- the upper layer insulating film 6 a is a nitrogen-containing metal silicate film that contains a metal, oxygen, silicon and nitrogen, and for example, a nitrogen-containing Hf silicate film or a nitrogen-containing Zr silicate film can be used.
- the upper layer insulating film 6 a is a film containing a metal such as Hf and Zr in a peak concentration of 1 atomic % or more and 30 atomic % or less. That is, the nitrogen-containing metal silicate film 6 a is a silicon-rich film. This is because if the peak concentration of the metal exceeds 30 atomic %, satisfactory electrical properties cannot be obtained as described later.
- the upper layer insulating film 6 a also contains nitrogen in a peak concentration of 10 atomic % or more and 30 atomic % or less. This is because if the peak concentration of nitrogen is less than 10 atomic %, the densification of the upper layer insulating film 6 a becomes insufficient, and in the activating heat treatment, the inhibition of the diffusion of impurities such as phosphorus and boron introduced into polysilicon, which is the gate electrode, becomes difficult to control. It is practically impossible to make the peak concentration of nitrogen exceed 30 atomic %, and even if it is possible, excellent electrical properties cannot be obtained.
- the thickness of the upper layer insulating film 6 a is preferably about 1/20 to 2 ⁇ 3 the thickness of the high-dielectric-constant film 5 a.
- the gate electrode 7 b is a polysilicon electrode consisting of a doped silicon film formed by introducing an impurity into a polysilicon film.
- the polysilicon electrode can be substituted by a silicon-germanium (Si x Ge y ) can be used as the gate electrode 7 b.
- a sidewall 11 is formed as a spacer for forming LDD.
- the sidewall 11 consists of a silicon oxide film or a silicon nitride film.
- an extension region 14 of lower concentration is formed by introducing a p-type impurity.
- a source-drain region 15 of higher concentration is formed by introducing a p-type impurity on the n-type well 2 so as to connect to the extension region 14 .
- An interlayer insulating film 16 such as BPSG, BSG and PSG, is formed so as to coat the gate electrode 7 b .
- interlayer insulating film 16 contact hole connected to the source-drain region 15 are formed, and in the contact holes, contacts 17 , in which conductive films such as a laminated films of barrier metal films and tungsten films are buried, are formed.
- Metal wirings 18 are formed on the contacts 17 .
- the present invention can be applied not only to the above-described PMOS transistor, but also to an N-type channel MOS transistor (hereafter referred to as “NMOS transistor”) having the same cross-sectional structure.
- NMOS transistor N-type channel MOS transistor
- a p-type well is formed in a p-type substrate 1 , and an NMOS transistor-forming region is partitioned by an element isolating structure 3 . Furthermore, in the p-type well, an extension region of a lower concentration formed by introducing an n-type impurity, and a source-drain region of a higher concentration formed by introducing an n-type impurity and connected to the extension are formed.
- FIG. 2 is a flow diagram for illustrating a method for forming a metal silicate film in the second embodiment of the present invention.
- the method for forming a metal silicate film as the above-described high-dielectric-constant film 5 will be described below referring to FIG. 2 . Specifically, a method for forming an Hf silicate film will be described.
- the Hf silicate film is formed by the combination of a step for forming a hafnium oxide film (HfO 2 film) using the ALD (atomic layer deposition) method, and a step for forming a silicon oxide film (SiO 2 film) using the ALD method, and by controlling the number of each step.
- a step for forming a hafnium oxide film (HfO 2 film) using the ALD (atomic layer deposition) method atomic layer deposition) method
- SiO 2 film silicon oxide film
- the hafnium oxide film is formed by controlling the flow rate of hafnium tetramethylethylamide [Hf(N(CH 3 )(C 2 H 5 ) 2 ) 4 ] as an Hf material using a mass flow controller, gasifying the flow-rate-controlled Hf material, adsorbing the gasified Hf material on the surface of a silicon substrate held in a film-forming chamber (Step S 102 ), and then introducing an oxidizing gas such as ozone gas into the chamber (Step S 104 ).
- the above steps for forming the hafnium oxide film are made one cycle.
- FIG. 3 is a graph showing the relationship between the number of cycles and the thickness of the hafnium oxide film when the hafnium oxide film is formed using tetramethylethylamide [Hf(N(CH 3 )(C 2 H 5 ) 2 ) 4 ] as an Hf material.
- FIG. 3 shows change in film thickness when the substrate temperature is 200° C., 275° C., 300° C. and 325° C.
- the thickness of the hafnium oxide film increases linearly with increase in the number of cycles at each temperature of the silicon wafer. Furthermore, with the rise of substrate temperature, the gradient of the straight line increases, and the film-forming speed per cycle increases.
- the speed of HfO 2 film formation per cycle at each substrate temperature was 0.090 nm/cycle at 200° C., 0.093 nm/cycle at 250° C., 0.117 nm/cycle at 275° C., 0.227 nm/cycle at 300° C., and 0.458 nm/cycle at 325° C.
- hafnium tetradimethylamide Hf(N(CH 3 ) 2 ) 4
- hafnium tetradiethylamide Hf(N(C 2 H 5 ) 2 ) 4
- a Zr silicate film can be formed.
- a Zr material zirconium tetramethylethylamide [Zr(N(CH 3 )(C 2 H 5 ) 2 ) 4 ], zirconium tetradimethylamide [Zr(N(CH 3 ) 2 ) 4 ] or zirconium tetradiethylamide [Zr(N(C 2 H 5 ) 2 ) 4 ] can be used.
- materials wherein the hafnium in the above Hf materials is substituted by each metal element can be used.
- the silicon oxide film is formed by controlling the flow rate of tris(dimethylamino)silane [SiH(N(CH 3 ) 2 ) 3 ] as an Si material using a mass flow controller, gasifying the flow-rate-controlled Si material, adsorbing the gasified Si material on the surface of a silicon substrate held in a film-forming chamber (Step S 106 ), and then introducing an oxidizing gas such as ozone gas into the chamber (Step S 108 ).
- the above steps for forming the silicon oxide film are made one cycle.
- FIG. 4 is a graph showing the relationship between the number of cycles and the thickness of the silicon oxide film when the silicon oxide film is formed using tris(dimethylamino)silane [SiH(N(CH 3 ) 2 ) 3 ] as an Si material.
- FIG. 4A shows the results when the pressure in the film-forming chamber is 0.5 Torr; and
- FIG. 4B shows the results when the pressure in the film-forming chamber is 5.0 Torr.
- FIG. 4A shows, although the thickness of a silicon oxide film linearly increased with increase in the number of cycles, the film-forming speed was low.
- FIG. 4B shows, the film-forming speed increased largely.
- FIG. 4B shows, when the film was formed under a low pressure of 0.5 Torr, the speed of forming the SiO 2 film per cycle at each substrate temperature was 0.058 nm/cycle at 225° C., 0.070 nm/cycle at 250° C., and 0.080 nm/cycle at 275° C.
- FIG. 5 is a graph showing the relationship between the number of cycles and the thickness of the Hf silicate film when a hafnium oxide (HfO 2 ) film is formed using hafnium tetramethylethylamide [Hf(N(CH 3 )(C 2 H 5 ) 2 ) 4 ] as a Hf material, and a silicon oxide (SiO 2 ) film is formed using tris(dimethylamino)silane [SiH(N(CH 3 ) 2 ) 3 ] as a Si material.
- the formation of the hafnium oxide film and the silicon oxide film is as described above.
- the pressure in the film-forming chamber in HfO 2 film formation was 0.5 Torr
- the pressure in the film-forming chamber in SiO 2 film formation was 5.0 Torr.
- the substrate temperature was 275° C.
- the thickness of the Hf silicate film was linearly increased with increase in the number of cycles. This means that the thickness of the Hf silicate film can be controlled very accurately by controlling the number of cycles.
- Hf materials and Si materials can be duly changed to the above-described other materials.
- FIG. 6 is a graph showing the relationship between the Hf/Si ratio and the Hf content in the Hf silicate film [Hf/(Hf+Si)] in the case wherein a hafnium oxide film is formed using hafnium tetramethylethylamide [Hf(N(CH 3 )(C 2 H 5 ) 2 ) 4 ] as a Hf material and a silicon oxide film is formed using tris(dimethylamino)silane [SiH(N(CH 3 ) 2 ) 3 ] as a Si material.
- the HfO 2 film and the SiO 2 film were formed under different pressures in the film-forming chamber, and the pressure in HfO 2 film formation was 0.5 Torr and that in SiO 2 film formation was 5.0 Torr.
- the substrate temperature was 275° C.
- FIG. 6 shows, by controlling the Hf/Si ratio, that is the ratio of the number of steps for forming the HfO 2 film to the number of steps for forming the SiO 2 film in a cycle of the formation of the Hf silicate film, the Hf concentration in the Hf silicate film can be accurately controlled within a wide range, of 1/30 to about 1. Therefore, by using the above-described method, the peak concentration of the metal in the metal silicate film can be accurately controlled.
- FIG. 7 is a flow diagram for illustrating the method for manufacturing a semiconductor device according to the first embodiment.
- FIGS. 8A to 1 C are sectional views for illustrating the process for manufacturing a semiconductor device according to the first embodiment.
- FIGS. 8A to 10 C are sectional views for illustrating the process for manufacturing a PMOS transistor. Since an NMOS transistor has the similar cross-sectional structure to a PMOS transistor, the drawings illustrating the method for manufacturing an NMOS transistor will be omitted, and the process will be described when required.
- FIG. 8A shows, in the PMOS transistor-forming region, an n-type impurity is introduced into a P-type silicon substrate 1 , and heat treatment is carried out to form an n-type well 2 .
- a p-type impurity is introduced into the silicon substrate 1 , and heat treatment is carried out to form a p-type well (Step S 202 ).
- the PMOS and NMOS transistor-forming regions are partitioned (Step S 204 ).
- the element-isolating region 3 is formed by forming a shallow trench in the element-isolating region of the silicon substrate 1 , and burying a silicon oxide film in the trench.
- the silicon oxide film formed out of the trench can be removed using the CMP method or the etch-back method.
- Step S 206 the surface of the silicon substrate is cleaned using diluted hydrofluoric acid (DHF) (Step S 206 ). Thereafter, as FIG. 8B shows, a silicon oxide film 4 of a thickness of, for example, about 0.5 nm is formed on the surface of the silicon substrate 1 by a rapid heat treatment using a halogen lamp or a flash lamp (Step S 208 ).
- DHF diluted hydrofluoric acid
- an Hf silicate film 5 of a thickness of, for example, about 3 nm is formed using the above-described method (Step S 210 ).
- a treatment for the densification of the Hf silicate film 5 may be carried out (Step S 212 ).
- the densification treatment can be carried out, for example, by performing rapid heat treatment using a halogen lamp in a nitrogen-gas atmosphere wherein a trace of oxygen gas is added, or in a nitrogen-gas atmosphere for 1 to 600 sec.
- the densification treatment can be carried out by performing rapid heat treatment using a flash lamp in the same atmosphere for 0.8 to 20 msec.
- a nitrogen-containing Hf silicate film 6 containing Hf of a peak concentration of 1 atomic % or more and 30 atomic % or less, and nitrogen of a peak concentration of 10 atomic % or more and 30 atomic % or less is formed on the upper layer of the Hf silicate film 5 (Step S 214 ).
- the nitrogen-containing Hf silicate film 6 can be formed by the plasma treatment using a nitrogen-based gas.
- the nitrogen-containing Hf silicate film 6 may be formed on the Hf silicate film 5 using a material that contains hafnium, oxygen, silicon and nitrogen.
- densification treatment is carried out (Step S 216 ).
- the densification treatment can be carried out, for example, by rapid heat treatment using a lamp in a nitrogen-gas atmosphere wherein a trace of oxygen gas is added, or in a nitrogen-gas atmosphere.
- a polysilicon film 7 that will finally become a gate electrode is formed on the nitrogen-containing Hf silicate film 6 (Step S 218 ).
- an impurity 8 such as boron is ion-implanted into the polysilicon film 7 (Step S 220 ). Thereby, a doped polysilicon film 7 a is formed on the nitrogen-containing Hf silicate film 6 .
- an impurity such as phosphorus is ion-implanted into a polysilicon film formed on the NMOS transistor-forming region.
- a resist pattern (not shown) is formed on the doped polysilicon film 7 a (Step S 222 ), and using the resist pattern as a mask, the doped polysilicon film 7 a , the nitrogen-containing Hf silicate film 6 , the Hf silicate film 5 , and the silicon oxide film 4 are sequentially etched (Step S 224 ).
- a polysilicon gate electrode 7 b is formed on the n-type well 2 of the silicon substrate 1 , through the gate insulating film formed by laminating the silicon oxide film 4 a , the Hf silicate film 5 a , and the nitrogen-containing Hf silicate film 6 a.
- a low concentration of boron difluoride (BF 2 ) is ion-implanted into the n-type well 2 using the gate electrode 7 b as a mask.
- boron difluoride boron difluoride
- a p-type low-concentration ion-implanted layer 10 that will finally become an extension region is formed on the upper layer of the silicon substrate 1 on the both sides of the gate electrode 7 b .
- arsenic is ion-implanted into the p-type well to form an n-type low-concentration ion-implanted layer (Step S 226 ).
- a silicon nitride film having a thickness of, for example, about 100 nm is formed on the entire surface of the silicon substrate 1 so as to coat the gate electrode 7 b , and the silicon nitride film is subjected to anisotropic etching.
- a sidewall 11 consisting of the silicon nitride film is formed in a self-aligning manner (Step S 228 ).
- boron 12 is ion-implanted into the n-type well 2 as a high-concentration P-type impurity 12 using the gate electrode 7 b and the sidewall 11 as masks.
- a p-type high-concentration ion-implanted layer 13 that will finally become the source/drain region is formed in the n-type well 2 .
- phosphorus is ion-implanted into the p-type well to form an n-type high-concentration ion-implanted layer (Step S 230 ).
- Step S 232 rapid heat treatment using a lamp is performed.
- the p-type low-concentration ion-implanted layer 10 and the p-type high-concentration ion-implanted layer 13 in the n-type well 2 are activated, and the p-type extension region 14 wherein an impurity is introduced in a low concentration, and the p-type source/drain region 15 wherein an impurity is introduced in a high concentration are formed.
- the n-type low-concentration ion-implanted layer and the n-type high-concentration ion-implanted layer in the p-type well are activated, and the n-type extension region wherein an impurity is introduced in a low concentration, and the n-type source/drain region wherein an impurity is introduced in a high concentration are formed.
- the temperature of heat treatment for activation is preferably at least 10 degrees lower than the temperature of heat treatment for densification.
- heat treatment for activation can be performed at 980° C.
- heat treatment for densification can be performed at 1000° C.
- an interlayer insulating film 16 is formed on the entire surface of the substrate using the CVD method. Thereafter, a resist pattern (not shown) is formed on the insulating film 16 using a lithography techniques, contact holes connected to the source/drain region 15 are formed in the interlayer insulating film 16 by dry etching using the resist pattern as masks, and then a barrier metal film and a tungsten film are buried in the contact holes to form contacts 17 . The unnecessary barrier metal film and tungsten film are removed using the CMP method. Thereafter, metal wirings 18 are formed on the contacts 17 to manufacture the semiconductor device shown in FIG. 1 .
- C-V characteristics the gate capacity-gate voltage characteristics of the MOS transistor manufactured in this embodiment.
- FIG. 11 is a graph showing the C-V characteristics of a semiconductor device according to the first embodiment. Specifically, FIG. 1A is a graph showing the C-V characteristics of an NMOS transistor; and FIG. 11B is a graph showing the C-V characteristics of a PMOS transistor.
- FIGS. 11A and 11B show, it is known that the C/Cmax value varies depending on the Hf/Si ratio in the reverse side, and with increase in the concentration of silicon, the C/Cmax value increases. This is considered because as the concentration of silicon in the Hf silicate film increases, the diffusion of impurities from the upper electrode polysilicon decreases, and depletion is minimized.
- the peak concentration of the metal in the nitrogen-containing Hf silicate film 6 a positioned on the uppermost layer of the gate insulating film was controlled to 1 atomic % or more and 30 atomic % or less.
- the peak concentration of nitrogen in the nitrogen-containing Hf silicate film 6 a was controlled to 10 atomic % or more and 30 atomic % or less. Thereby, the diffusion of impurities introduced into the gate electrode in the activating heat treatment could be inhibited, and the Vfb shift due to the diffusion of impurities could be inhibited.
- the present invention can be applied to the case of using a metal aluminate film as the high-dielectric-constant film, and using a nitrogen-containing metal aluminate film as the upper layer insulating film, and the similar results can also be obtained from this case.
- the peak concentration of the metal was equivalent in the metal silicate film 5 a and in the nitrogen-containing metal silicate film 6 a .
- the peak concentration of the metal in the metal silicate film 5 a was higher than that in the nitrogen-containing metal silicate film 6 a .
- the metal silicate film 5 a was made to be a metal-rich film; and the nitrogen-containing metal silicate film 6 a was made to be a silicon-rich film. Since other constitution is the same as in the above-described embodiment, the description thereof will be omitted.
- a metal silicate film e.g., Hf silicate film or Zr silicate film
- a metal silicate film as the high-dielectric-constant film 5 a was made to be a metal-rich film that contains a metal in the peak concentration of 5 atomic % or more and 40 atomic % or less.
- the silicon-rich Hf silicate film is nitrided to form a silicon-rich nitrogen-containing Hf silicate film as the upper layer insulating film.
- a polysilicon film 7 is formed on the nitrogen-containing Hf silicate film.
- this modification by making the film on the uppermost layer of the gate insulating film a nitrogen-containing metal silicate film that contains the metal in the peak concentration of 1 atomic % or more and 30 atomic % or less, the similar effect as in the above-described embodiment can also be obtained. Furthermore, this modification can improve the total effective specific dielectric constant of the gate insulating film by the use of a metal-rich metal silicate film as the high-dielectric-constant film 5 a.
- the semiconductor device and the method for the manufacture thereof according to the second embodiment is the same as those described in the first embodiment. In the second embodiment, however, a different method is used to form a metal silicate such as an Hf silicate.
- FIG. 12 is a schematic diagram for illustrating a thin film forming apparatus in the second embodiment of the present invention.
- the thin film forming apparatus 100 is equipped with a vacuum chamber 20 .
- a table 21 is disposed on the central portion in the chamber 20 .
- a heater 22 is installed to heat the table from the bottom thereof to a predetermined temperature.
- a gas supply pipe 23 is installed so as to pass through a portion of the outer wall of the chamber 20 .
- the gas supply pipe 23 passes from the outside of the chamber 20 to the inside of the chamber 20 , and thereby supplies the gas into the chamber 20 .
- the gas supply pipe 23 is also disposed so as to surround upside of the table 21 .
- the gas supply pipe 23 has a plurality of ejection nozzles 24 . The gas supplied from the gas supply pipe 23 is ejected through these ejection nozzles 24 into the chamber 20 .
- a total of two gas discharge ports 25 are installed so as to pass through the underside of the outer wall of the chamber 20 .
- the gas discharge ports 25 run from the inside to the outside of the chamber 20 , and are connected to a vacuum pump through a valve 26 . Thereby the gas in the chamber 20 can be discharged to the exterior.
- the ceiling portion of the chamber 20 facing the table 21 , is formed of a quartz window 27 .
- a total of 50 flash lamps 28 are disposed, and the flash lamps 28 are covered with a reflective plate 29 .
- the flash lamps 28 are connected to a capacitor 30 , and the capacitor 30 is connected to a power source 31 .
- the ceiling portion of the chamber 20 is formed of a quartz window 27 that permeates light so as to introduce light emitted from the flash lamps 28 .
- the reflective plate 29 is installed so as to reflect the light emitted from the flash lamps 28 toward the opposite side to the chamber 20 (upward in FIG. 12 ) to the chamber 20 , and to introduce the light into the chamber 20 .
- the current from the power source 31 is charged into the capacitor 30 , and instant discharge of the electric charge makes the flash lamp 28 emit light.
- a metal silicate is formed using the thin film forming apparatus 100 constituted as described above, in place of the steps S 102 to S 110 (S 210 ) in the manufacturing process of the semiconductor device described in the first embodiment.
- a substrate 32 is placed on the table 21 .
- FIG. 13 is a flow diagram for illustrating the method for forming a metal silicate film in the second embodiment of the present invention.
- FIG. 14 is a graph for illustrating the sequence in the method for forming a metal silicate film in the second embodiment.
- the metal silicate film is also formed by individually forming a hafnium oxide film and a silicon oxide film. This will be specifically described referring to FIGS. 12 to 14 .
- a hafnium oxide film is formed.
- the table 21 is heated in the state where a substrate 32 is placed on the table 21 (Step S 302 ).
- the table 21 is heated using the heater 22 to a temperature of 300° C.
- the temperature of the substrate 32 is maintained at 300° C.
- the gas in the chamber 20 is discharged (Step S 304 ). Gas discharge is performed by opening the valve 26 and sucking the gas through the gas discharge ports 25 using the vacuum pump until the pressure in the chamber 20 becomes 10 ⁇ 7 Torr.
- argon gas is supplied into the chamber 20 (Step S 306 ).
- the argon gas is supplied through the gas supply pipe 23 , and is ejected through the ejection nozzles 24 into the chamber 20 .
- the pressure in the chamber 20 is fixed to 0.5 Torr.
- the supply of hafnium tetramethylethylamide is started at the point A 1 (Step S 310 ).
- Hafnium tetramethylethylamide is supplied through the gas supply pipe 23 , and is ejected through the ejection nozzles 24 into the chamber 20 .
- the supply of hafnium tetramethylethylamide is performed at 2 sccm for 1.5 seconds, and the supply is stopped at the point B 1 1.5 seconds later (Step S 312 ).
- Step S 314 the purge of the gas in the chamber 20 is started.
- argon gas is supplied through the gas supply pipe 23 for about 5 seconds.
- the valve 26 is opened and the gas in the chamber 20 is discharged through the gas discharge ports 25 with the vacuum pump.
- the supply of argon gas and gas discharge are stopped at the point C 1 5 seconds later (Step S 316 ). At this time, the valve 26 is closed.
- Step S 318 the supply of ozone gas is started.
- ozone gas is also supplied through the gas supply pipe 23 , and is ejected through the ejection nozzles 24 into the chamber 20 .
- the supply of ozone gas is performed at 5 sccm for 2 seconds, and the supply is stopped at the point D 1 2 seconds later (Step S 320 ).
- Step S 322 the discharge of the gas from the chamber 20 is started.
- the gas is purged by supplying argon gas through the gas supply pipe 23 , and simultaneously the valve 26 is opened to discharge the gas through the gas discharge ports 25 using the vacuum pump.
- the light emitting of the flash lamps 28 is performed (Step S 324 ).
- the energy of the light-emitting flash lamps 28 is 15 J/cm 2 .
- the light-emitting time of the flash lamps 28 is as an extremely short time such as about 5.0 to 20 msec, and thereby only the surface of the substrate 32 is heated instantly.
- Step S 326 the supply of argon gas and the discharge of the gas from the chamber 20 are stopped. Thereafter, the introduction of hafnium tetramethylethylamide is started again (Step S 310 ), and steps S 310 to S 326 are repeated.
- Step S 310 and S 312 the introduction of hafnium tetramethylethylamide (Steps S 310 and S 312 ), the purge of the gas (Steps S 314 and S 316 ), the introduction of ozone gas (Steps S 318 and S 320 ), the purge of the (Steps S 322 and S 326 ), and the light emitting of the flash lamps during the purge of the gas (Step S 324 ) are repeated for 20 times, and the formation of the thin film is completed.
- a hafnium oxide film of a thickness of about 2.5 nm can be formed on the substrate 32 .
- the table 21 is maintained at about 300° C. in the same manner as in the formation of the hafnium oxide film.
- the chamber 20 is purged with argon gas, and the pressure in the chamber 20 is fixed to 5.0 Torr.
- Step S 330 the supply of trisdimethylaminosilane as the Si material is started at the point A 1 (Step S 330 ).
- Trisdimethylaminosilane is supplied through the gas supply pipe 23 , and is ejected through the ejection nozzles 24 into the chamber 20 .
- the supply of trisdimethylaminosilane is performed at 2 sccm for 1.5 seconds, and the supply is stopped at the point B 1 1.5 seconds later (Step S 332 ).
- Step S 334 the purge of the gas in the chamber 20 is started.
- argon gas is supplied through the gas supply pipe 23 for about 5 seconds, and on the other hand, the valve 26 is opened.
- the gas in the chamber 20 is discharged through the gas discharge ports 25 with the vacuum pump, and the purge of the gas is stopped at the point C 1 5 seconds later (Step S 336 ).
- Step S 338 the supply of ozone gas is started.
- ozone gas is also supplied through the gas supply pipe 23 , and is ejected through the ejection nozzles 24 into the chamber 20 .
- the supply of ozone gas is performed at 5 sccm for 2 seconds, and the supply is stopped at the point D 1 2 seconds later (Step S 340 ).
- Step S 342 the discharge of the gas from the chamber 20 is started.
- the gas is purged by supplying argon gas through the gas supply pipe 23 , and simultaneously the valve 26 is opened to discharge the gas through the gas discharge ports 25 using the vacuum pump.
- the light emitting of the flash lamps 28 is performed (Step S 344 ).
- the energy of the light-emitting flash lamps 28 is 15 J/cm 2 .
- the light-emitting time of the flash lamps 28 is as an extremely short time such as about 5.0 to 20 msec, and thereby only the surface of the substrate 32 is heated instantly.
- Step S 346 the purge of the gas in the chamber 20 is stopped. Thereafter, the introduction of trisdimethylaminosilane is started again (Step S 330 ), and steps S 330 to S 346 are repeated.
- Step S 330 and S 332 the introduction of trisdimethylaminosilane (Steps S 330 and S 332 ), the purge of the gas (Steps S 334 and S 336 ), the introduction of ozone gas (Steps S 338 and S 340 ), the purge of the gas (Steps S 342 and S 346 ), and the light emitting of the flash lamps 28 during the purge of the gas (Step S 344 ) are repeated for 5 times, and the formation of the thin film is completed.
- a silicon oxide film of a thickness of about 0.4 nm can be formed on the substrate 32 .
- the formed hafnium oxide film in the second embodiment was compared with an aluminum oxide film formed according to a conventional method, wherein the sequence of the supply of the material gas and the purge of the gas is performed in the same manner, but without heating with the flash lamps 28 , using a secondary ion mass spectrometer, and it was found that the quantity of residual carbon in the thin film was lowered to about 1/10.
- heating of the millisecond order can be performed by heating by flash lamps, the temperature of the surface of the substrate 32 can be raised instantly to accelerate the reaction, and the temperature of the substrate 32 can be immediately lowered to the original temperature.
- an oxidizing gas such as ozone gas is supplied to start oxidation reaction.
- the temperature of the wafer is low, and the reaction time is not sufficiently long, the oxidation reaction is not completed. This is considered to be the cause of residual impurities in the film.
- the flash lamps 28 can heat the surface of a wafer for the millisecond order and can raise the surface temperature of the wafer instantly to accelerate the rate of reaction. Also since only the surface of the substrate 32 is heated for an extremely short time, the wafer temperature can be immediately returned to the original temperature. Therefore, the next cycle (Steps S 310 to S 324 ) can be performed at the original wafer temperature. Thereby, a high-dielectric-constant thin film having a low impurity concentration and good characteristics can be formed.
- the present invention is not limited thereto, but the thin film forming apparatus 100 can be applied to the formation of other thin films.
- the thin film forming apparatus of the present invention is not limited to the apparatus using 50 flash lamps.
- flash lamps 28 are used as the heating means.
- the heating means in the present invention is not limited to the flash lamps, but other means can be used as long as the surface of the substrate can be adequately heated.
- the heating time by the flash lamps is 5.0 to 20 milliseconds.
- the heating time in the present invention is not limited to this range.
- the heating time is preferably 0.8 milliseconds or longer.
- the upper portion of the chamber 20 was made to be a quartz window 27 , through which light from the flash lamps 28 was transmitted to irradiate the substrate in the chamber 20 . Furthermore, the case wherein a reflective plate 29 is installed above the flash lamps 28 so as to reflect light emitted upward and irradiate the chamber 20 was described.
- the constitution of the thin film forming apparatus according to the present invention is not limited thereto, but other constitution, for example, the constitution wherein the flash lamps 28 are directly installed in the chamber 20 , can be used.
- the thin film forming apparatus of the present invention is not limited to the apparatus having such a constitution, but other constitutions can be used as long as the gas can be supplied into the chamber 20 , and the gas can be adequately discharged from the chamber 20 .
- the other constitutions of the thin film forming apparatus of the present invention are not limited to the constitution described in this embodiment, but other constitutions can be used as long as the surface of the substrate can be adequately heated, and the reaction can be accelerated.
- the metal content in the metal silicate film formed on the uppermost layer of a high-dielectric-constant film is controlled. Accordingly, the semiconductor device having C-V characteristics equivalent to ideal C-V characteristics can be realized.
Abstract
A semiconductor device includes a substrate, and a gate electrode on the substrate via a gate insulating film. The gate insulating film includes a base interface layer on the substrate, metal silicate film on the base interface layer and containing a metal, oxygen, and silicon, and a nitrogen-containing metal silicate film on the metal silicate film, and containing the metal, oxygen, silicon, and nitrogen and including nitrogen in a range from ten atomic % to thirty atomic %, and the metal silicate film contains the metal in a concentration higher than metal concentration of said nitrogen-containing metal silicate film.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device using a metal silicate film as a gate insulating film, to a method for manufacturing such a semiconductor device, to an apparatus being available for forming film in such a semiconductor device, and to method being available for forming high-dielectric-constant film in such a semiconductor device.
- 2. Background Art
- Accompanying the miniaturization of semiconductor devices, the reduction of thickness of gate insulating films has been demanded. The reduction of thickness of silicon oxide films and silicon oxynitride films (hereafter referred to as “silicon oxide film and the like”), which are used as conventional gate insulating films, is limited due to increase in leak current, and it is difficult to reduce the SiO2-converted film thickness to 1.5 nm or less. Therefore, there has been proposed a method for inhibiting leak current by using a high-dielectric-constant film, such as a metal oxide film, a metal silicate film and a metal aluminate film, which has a higher specific inductive capacity higher than that of silicon oxide film and the like as the gate insulating film; and by increasing the physical film thickness of the gate insulating film.
- However, when the high-dielectric-constant film is used as the gate insulating film, and a polysilicon electrode is used as the gate electrode, there has been a problem that impurities doped in the polysilicon electrode diffuse into the substrate through the gate insulating film when the impurities are activated, and the transistor properties are deteriorated.
- In order to solve this problem, a method for introducing nitrogen into the high-dielectric-constant film has been proposed.
- Specifically, there has been proposed a method for forming a high-dielectric-constant film composed of a zirconium oxynitride layer or a hafnium oxynitride layer, by forming a metal layer composed of zirconium or hafnium on a substrate, and oxynitriding the metal layer (refer to e.g., Japanese Patent Laid-Open No. 2000-58832).
- Furthermore, there has also been proposed a method for laminating a lower barrier film consisting of a hafnium-containing silicon oxynitride film, a high-dielectric-constant film consisting of a silicon-containing hafnium oxide film, and an upper barrier film consisting of a silicon-containing hafnium oxide film that contains nitrogen to form a gate insulating film and for controlling the composition of a metal (M), oxygen (O), nitrogen (N) and silicon (Si) in the high-dielectric-constant film and the lower barrier film (refer to e.g., Japanese Patent Laid-Open No. 2003-8011).
- In a thin-film formation using a high-dielectric-constant material, the ALD (atomic layer deposition) method is generally used. In this method, material gasses are alternately supplied while resetting the chamber to the original state to form each atomic layer.
- For example, the formation of a hafnium oxide (HfO2) film as a high-dielectric-constant film will be specifically described. First, the chamber is evacuated, argon gas is flowed in the chamber, and the pressure in the chamber is maintained to 0.2 Torr. In this state, hafnium tetramethylethylamide [Hf(N(CH3)(C2H5)2)4] is flowed into the chamber while controlling the flow rate, and the Hf material is vaporized and adsorbed on the surface of the substrate. Then, the chamber is purged, and an oxidizing gas such as ozone gas is introduced. Thereafter, the chamber is purged. By repeating such steps for several tens of times, a hafnium oxide (HfO2) film of a thickness of several nanometers can be formed on the surface of the substrate.
- The introduction of nitrogen into a high-dielectric-constant film reduces flat-band-voltage shift (hereafter referred to as “Vfb shift”) due to the diffusion of impurities. This is estimated because the high-dielectric-constant gate insulating film is densified by nitriding treatment, and the diffusion of impurities is restricted.
- However, in the above-described conventional method, initial Vfb shift due to the effect of fixed charge or the like is large, and there has been a problem that satisfactory transistor characteristics cannot obtained particularly in P-channel MIS transistors.
- In addition, a high-dielectric-constant thin film formed using the ALD method generally contains several percent impurities. This is considered because carbon (C), hydrogen (H) or chlorine (Cl) included in material gas using the ALD method remains and is incorporated in the formed film. The impurities remaining in the high-dielectric-constant film may cause fixed charge and trap, and the characteristics of the film is damaged.
- The one object of the present invention is to restrict initial Vfb shift, to form a gate insulating film having high film quantity, and to achieve satisfactory transistor characteristics.
- Another object of the present invention is to lower the impurity content in the high-dielectric-constant film of the gate insulating film.
- According to one aspect of the present invention, a semiconductor device comprises a substrate, a gate insulating film and a gate electrode. The gate insulating film is formed on the substrate, and has a nitrogen-containing metal silicate film or a nitrogen-containing metal aluminate film that contains a metal in a peak concentration of 1 atomic % or more and 30 atomic % or less on the uppermost layer. The gate electrode is formed on the gate insulating film.
- Another aspect of the present invention, a semiconductor device comprises a substrate, a gate insulating film, and a gate electrode. The gate insulating film is formed on the substrate and has a base interface layer, a metal silicate film and a nitrogen-containing metal silicate film. The base interface layer is formed on the substrate. The metal silicate film is formed on the base interface layer, and contains a metal, oxygen and silicon. The nitrogen-containing metal silicate film contains a metal in a peak concentration of 1 atomic % or more and 30 atomic % or less, oxygen, silicon, and nitrogen. The gate electrode formed on the gate insulating film.
- Another aspect of the present invention, in method for manufacturing a semiconductor device, a base interface layer is formed on a substrate. A metal silicate film containing a metal in a peak concentration of 1 atomic % or more and 30 atomic % or less is formed on the base interface layer. A nitrogen-containing metal silicate film containing nitrogen in a peak concentration of 10 atomic % or more and 30 atomic % or less is formed on the upper layer of the metal silicate film. A gate electrode is formed on the nitrogen-containing metal silicate film.
- Another aspect of the present invention, in method for manufacturing a semiconductor device, a base interface layer is formed on a substrate. A metal silicate film containing a metal in a peak concentration of 5 atomic % or more and 40 atomic % or less is formed on the base interface layer. A nitrogen-containing metal silicate film containing a metal in a peak concentration of 1 atomic % or more and 30 atomic % or less and nitrogen in a peak concentration of 10 atomic % or more and 30 atomic % or less is formed on the metal silicate film. A gate electrode is formed on the nitrogen-containing metal silicate film.
- Another aspect of the present invention, a apparatus for forming a film comprises a housing, a table installed in the housing, for placing a substrate, a gas supply port for supplying a gas into the housing, a gas discharge port for discharging the gas in the housing out of the housing, and a heater. The heater is for heating the surface of the substrate by radiating light on the surface of the substrate placed on the table for a time up to several milliseconds.
- Another aspect of the present invention, in a method for forming a high-dielectric-constant film on a substrate, a first material gas that contains at least one element in elements constituting the high-dielectric-constant film is supplied into a housing wherein the substrate is placed. A second material gas that reacts with the first material gas and forms the high-dielectric-constant film is supplied into the housing. The surface of the substrate is heated by radiating light onto the surface of the substrate for a time up to several milliseconds.
- Other and further objects, features and advantages of the invention will appear more fully from the following description.
-
FIG. 1 is a sectional view for illustrating a semiconductor device in the first embodiment of the present invention; -
FIG. 2 is a flow diagram for illustrating a method for forming a metal silicate film in the first embodiment of the present invention; -
FIG. 3 is a graph showing the relationship between the number of cycles and the thickness of the hafnium oxide film when the hafnium oxide film is formed using tetramethylethylamide as an Hf material; -
FIGS. 4A and 4B are graphs showing the relationship between the number of cycles and the thickness of the silicon oxide film when the silicon oxide film is formed using tris(dimethylamino)silane [SiH(N(CH3)2)3] as an Si material; -
FIG. 5 is a graph showing the relationship between the number of cycles and the thickness of the Hf silicate film when a hafnium oxide film is formed using hafnium tetramethylethylamide [Hf(N(CH3)(C2H5)2)4] as a Hf material, and a silicon oxide film is formed using tris(dimethylamino)silane [SiH(N(CH3)2)3] as a Si material; -
FIG. 6 is a graph showing the relationship between the Hf/Si ratio and the Hf content in the Hf silicate film [Hf/(Hf+Si)] in the case wherein a hafnium oxide film is formed using hafnium tetramethylethylamide [Hf(N(CH3)(C2H5)2)4] as a Hf material and a silicon oxide film is formed using tris(dimethylamino)silane [SiH(N(CH3)2)3] as a Si material; -
FIG. 7 is a flow diagram for illustrating the method for manufacturing a semiconductor device in the first embodiment of the present invention; -
FIGS. 8A to 10C are sectional views for illustrating the process for manufacturing a semiconductor device in the first embodiment of the present invention; -
FIGS. 11A and 11B are a graphs showing the C-V characteristics of a semiconductor device in the first embodiment of the present invention; -
FIG. 12 is a schematic diagram for illustrating a thin film forming apparatus in the second embodiment of the present invention; -
FIG. 13 is a flow diagram for illustrating the method for forming a metal silicate film in the second embodiment of the present invention; and -
FIG. 14 is a graph for illustrating the sequence in the method for forming a metal silicate film in the second embodiment. - The embodiment of the present invention will be described referring to the drawings. In each of the drawings, the same or like parts will be denoted with the same reference numerals, and the description thereof will be simplified or omitted.
-
FIG. 1 is a sectional view for illustrating a semiconductor device according to the first embodiment of the present invention. Specifically,FIG. 1 is a sectional view for illustrating a P-channel MOS transistor (hereafter referred to as “PMOS transistor”). - In the PMOS, a
substrate 1 is a p-type silicon substrate. AsFIG. 1 shows, an n-type well 2 to which an n-type impurity is introduced is formed in thesubstrate 1. An element-isolatingstructure 3 is formed on the element-isolating region of thesubstrate 1. By the element-isolatingstructure 3, a PMOS transistor-forming region, which is an active region, is partitioned. The element-isolatingstructure 3 is an STI (shallow trench isolation) formed by filling a shallow trench formed from the surface side of thesubstrate 1 with a silicon oxide film. On thesubstrate 1 of the MOS transistor-forming region,gate insulating films gate electrode 7 b is formed through thegate insulating films - The gate insulating film has a
base interface layer 4 a formed on thesubstrate 1, a high-dielectric-constant film 5 a formed on thebase interface layer 4 a, and an upperlayer insulating film 6 a formed on the high-dielectric-constant film 5 a. Thebase interface layer 4 a is silicon oxide film for repressing the reaction at the interface. The thickness of thebase interface layer 4 a is preferably 1 nm or below, for example, about 0.5 nm. - The high-dielectric-
constant film 5 a is a metal silicate film that contains a metal, oxygen and silicon, and for example, an Hf (hafnium) silicate film or a Zr (zirconium) silicate film can be used. The thickness of the high-dielectric-constant film 5 a is, for example, about 3 nm. - The upper
layer insulating film 6 a is a nitrogen-containing metal silicate film that contains a metal, oxygen, silicon and nitrogen, and for example, a nitrogen-containing Hf silicate film or a nitrogen-containing Zr silicate film can be used. - The upper
layer insulating film 6 a is a film containing a metal such as Hf and Zr in a peak concentration of 1 atomic % or more and 30 atomic % or less. That is, the nitrogen-containingmetal silicate film 6 a is a silicon-rich film. This is because if the peak concentration of the metal exceeds 30 atomic %, satisfactory electrical properties cannot be obtained as described later. - The upper
layer insulating film 6 a also contains nitrogen in a peak concentration of 10 atomic % or more and 30 atomic % or less. This is because if the peak concentration of nitrogen is less than 10 atomic %, the densification of the upperlayer insulating film 6 a becomes insufficient, and in the activating heat treatment, the inhibition of the diffusion of impurities such as phosphorus and boron introduced into polysilicon, which is the gate electrode, becomes difficult to control. It is practically impossible to make the peak concentration of nitrogen exceed 30 atomic %, and even if it is possible, excellent electrical properties cannot be obtained. - The thickness of the upper
layer insulating film 6 a is preferably about 1/20 to ⅔ the thickness of the high-dielectric-constant film 5 a. - The
gate electrode 7 b is a polysilicon electrode consisting of a doped silicon film formed by introducing an impurity into a polysilicon film. The polysilicon electrode can be substituted by a silicon-germanium (SixGey) can be used as thegate electrode 7 b. - On the sides of the
gate electrode 7 b, andgate insulating films sidewall 11 is formed as a spacer for forming LDD. Thesidewall 11 consists of a silicon oxide film or a silicon nitride film. - Across the channel region on the surface of the
substrate 1 below thegate electrode 7 b, anextension region 14 of lower concentration is formed by introducing a p-type impurity. A source-drain region 15 of higher concentration is formed by introducing a p-type impurity on the n-type well 2 so as to connect to theextension region 14. - An interlayer insulating
film 16, such as BPSG, BSG and PSG, is formed so as to coat thegate electrode 7 b. In theinterlayer insulating film 16, contact hole connected to the source-drain region 15 are formed, and in the contact holes,contacts 17, in which conductive films such as a laminated films of barrier metal films and tungsten films are buried, are formed.Metal wirings 18 are formed on thecontacts 17. - The present invention can be applied not only to the above-described PMOS transistor, but also to an N-type channel MOS transistor (hereafter referred to as “NMOS transistor”) having the same cross-sectional structure.
- In the case of an NMOS transistor, a p-type well is formed in a p-
type substrate 1, and an NMOS transistor-forming region is partitioned by anelement isolating structure 3. Furthermore, in the p-type well, an extension region of a lower concentration formed by introducing an n-type impurity, and a source-drain region of a higher concentration formed by introducing an n-type impurity and connected to the extension are formed. -
FIG. 2 is a flow diagram for illustrating a method for forming a metal silicate film in the second embodiment of the present invention. - The method for forming a metal silicate film as the above-described high-dielectric-
constant film 5 will be described below referring toFIG. 2 . Specifically, a method for forming an Hf silicate film will be described. - The Hf silicate film is formed by the combination of a step for forming a hafnium oxide film (HfO2 film) using the ALD (atomic layer deposition) method, and a step for forming a silicon oxide film (SiO2 film) using the ALD method, and by controlling the number of each step.
- The details of each step will be described below.
- First, the step for forming a hafnium oxide film will be described.
- The hafnium oxide film is formed by controlling the flow rate of hafnium tetramethylethylamide [Hf(N(CH3)(C2H5)2)4] as an Hf material using a mass flow controller, gasifying the flow-rate-controlled Hf material, adsorbing the gasified Hf material on the surface of a silicon substrate held in a film-forming chamber (Step S102), and then introducing an oxidizing gas such as ozone gas into the chamber (Step S104). The above steps for forming the hafnium oxide film are made one cycle.
-
FIG. 3 is a graph showing the relationship between the number of cycles and the thickness of the hafnium oxide film when the hafnium oxide film is formed using tetramethylethylamide [Hf(N(CH3)(C2H5)2)4] as an Hf material.FIG. 3 shows change in film thickness when the substrate temperature is 200° C., 275° C., 300° C. and 325° C. - As
FIG. 3 shows, the thickness of the hafnium oxide film increases linearly with increase in the number of cycles at each temperature of the silicon wafer. Furthermore, with the rise of substrate temperature, the gradient of the straight line increases, and the film-forming speed per cycle increases. - This is considered because the quantity of tetramethylethylamide [Hf(N(CH3)(C2H5)2)4] adsorbed on the surface of the substrate increases with the rise of substrate temperature.
- As
FIG. 3 shows, the speed of HfO2 film formation per cycle at each substrate temperature was 0.090 nm/cycle at 200° C., 0.093 nm/cycle at 250° C., 0.117 nm/cycle at 275° C., 0.227 nm/cycle at 300° C., and 0.458 nm/cycle at 325° C. - As an Hf material, hafnium tetradimethylamide [Hf(N(CH3)2)4] or hafnium tetradiethylamide [Hf(N(C2H5)2)4] can be used.
- In place of an Hf silicate film, a Zr silicate film can be formed. In this case, as a Zr material, zirconium tetramethylethylamide [Zr(N(CH3)(C2H5)2)4], zirconium tetradimethylamide [Zr(N(CH3)2)4] or zirconium tetradiethylamide [Zr(N(C2H5)2)4] can be used.
- As a metal, tantalum (Ta), scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), ytterbium (Yb), and lutetium (Lu) other than Hf or Zr can be used. In these cases, materials wherein the hafnium in the above Hf materials is substituted by each metal element can be used.
- Next, the step for forming a silicon oxide film will be described.
- The silicon oxide film is formed by controlling the flow rate of tris(dimethylamino)silane [SiH(N(CH3)2)3] as an Si material using a mass flow controller, gasifying the flow-rate-controlled Si material, adsorbing the gasified Si material on the surface of a silicon substrate held in a film-forming chamber (Step S106), and then introducing an oxidizing gas such as ozone gas into the chamber (Step S108). The above steps for forming the silicon oxide film are made one cycle.
-
FIG. 4 is a graph showing the relationship between the number of cycles and the thickness of the silicon oxide film when the silicon oxide film is formed using tris(dimethylamino)silane [SiH(N(CH3)2)3] as an Si material.FIG. 4A shows the results when the pressure in the film-forming chamber is 0.5 Torr; andFIG. 4B shows the results when the pressure in the film-forming chamber is 5.0 Torr. - When the pressure in the film-forming chamber is 0.5 Torr, as
FIG. 4A shows, although the thickness of a silicon oxide film linearly increased with increase in the number of cycles, the film-forming speed was low. On the other hand, when the pressure in the film-forming chamber is raised to 5.0 Torr, asFIG. 4B shows, the film-forming speed increased largely. - This is considered because tris(dimethylamino)silane [SiH(N(CH3)2)3], which is an Si material, is difficult to adsorb on the surface of the substrate at a pressure as low as 0.5 Torr, and the quantity of adsorption increases by raising the pressure to 5.0 Torr.
- As
FIG. 4B shows, when the film was formed under a low pressure of 0.5 Torr, the speed of forming the SiO2 film per cycle at each substrate temperature was 0.058 nm/cycle at 225° C., 0.070 nm/cycle at 250° C., and 0.080 nm/cycle at 275° C. - As an Si material, tris(dimethylamino)silane [SiH(N(CH3)2)3], tetrakis(dimethylamino)silane [SiH(N(CH3)2)4], tetrakis(diethylamino)silane [SiH(N(C2H5)2)4], dimethylsilane [SiH2(CH3)2], diethylsilane [SiH2(C2H5)2], or bis-tert-butylaminosilane [SiH2(NH(C4H9)2] can be used.
-
FIG. 5 is a graph showing the relationship between the number of cycles and the thickness of the Hf silicate film when a hafnium oxide (HfO2) film is formed using hafnium tetramethylethylamide [Hf(N(CH3)(C2H5)2)4] as a Hf material, and a silicon oxide (SiO2) film is formed using tris(dimethylamino)silane [SiH(N(CH3)2)3] as a Si material. The formation of the hafnium oxide film and the silicon oxide film is as described above. - In
FIG. 5 , Hf/Si=1/1 means that HfO2 film formation and SiO2 film formation are performed in every other cycle in a cycle of the step for forming the Hf silicate film. Hf/Si=1/2 means that after HfO2 film formation has been performed once, SiO2 film formation is performed twice; and Hf/Si=1/4 means that after HfO2 film formation has been performed once, SiO2 film formation is performed four times. In either cycle ratio, the pressure in the film-forming chamber in HfO2 film formation was 0.5 Torr, and the pressure in the film-forming chamber in SiO2 film formation was 5.0 Torr. The substrate temperature was 275° C. - As
FIG. 5 shows, in either Hf/Si=1/1, Hf/Si=1/2 or Hf/Si=1/4, the thickness of the Hf silicate film was linearly increased with increase in the number of cycles. This means that the thickness of the Hf silicate film can be controlled very accurately by controlling the number of cycles. The speed of forming the Hf silicate film per cycle was 0.155 nm/cycle when Hf/Si=1/1, 0.222 nm/cycle when Hf/Si=1/2, and 0.373 nm/cycle when Hf/Si=1/4 as shown inFIG. 5 . - Hf materials and Si materials can be duly changed to the above-described other materials.
-
FIG. 6 is a graph showing the relationship between the Hf/Si ratio and the Hf content in the Hf silicate film [Hf/(Hf+Si)] in the case wherein a hafnium oxide film is formed using hafnium tetramethylethylamide [Hf(N(CH3)(C2H5)2)4] as a Hf material and a silicon oxide film is formed using tris(dimethylamino)silane [SiH(N(CH3)2)3] as a Si material. Here, the HfO2 film and the SiO2 film were formed under different pressures in the film-forming chamber, and the pressure in HfO2 film formation was 0.5 Torr and that in SiO2 film formation was 5.0 Torr. The substrate temperature was 275° C. - As
FIG. 6 shows, by controlling the Hf/Si ratio, that is the ratio of the number of steps for forming the HfO2 film to the number of steps for forming the SiO2 film in a cycle of the formation of the Hf silicate film, the Hf concentration in the Hf silicate film can be accurately controlled within a wide range, of 1/30 to about 1. Therefore, by using the above-described method, the peak concentration of the metal in the metal silicate film can be accurately controlled. - The method for manufacturing the semiconductor device in the first embodiment will be described.
-
FIG. 7 is a flow diagram for illustrating the method for manufacturing a semiconductor device according to the first embodiment.FIGS. 8A to 1C are sectional views for illustrating the process for manufacturing a semiconductor device according to the first embodiment. Specifically,FIGS. 8A to 10C are sectional views for illustrating the process for manufacturing a PMOS transistor. Since an NMOS transistor has the similar cross-sectional structure to a PMOS transistor, the drawings illustrating the method for manufacturing an NMOS transistor will be omitted, and the process will be described when required. - First, as
FIG. 8A shows, in the PMOS transistor-forming region, an n-type impurity is introduced into a P-type silicon substrate 1, and heat treatment is carried out to form an n-type well 2. On the other hand, in the NMOS transistor-forming region, a p-type impurity is introduced into thesilicon substrate 1, and heat treatment is carried out to form a p-type well (Step S202). Then, by forming an element-isolatingregion 3 using the STI method, the PMOS and NMOS transistor-forming regions are partitioned (Step S204). Specifically, the element-isolatingregion 3 is formed by forming a shallow trench in the element-isolating region of thesilicon substrate 1, and burying a silicon oxide film in the trench. The silicon oxide film formed out of the trench can be removed using the CMP method or the etch-back method. - Next, the surface of the silicon substrate is cleaned using diluted hydrofluoric acid (DHF) (Step S206). Thereafter, as
FIG. 8B shows, asilicon oxide film 4 of a thickness of, for example, about 0.5 nm is formed on the surface of thesilicon substrate 1 by a rapid heat treatment using a halogen lamp or a flash lamp (Step S208). - After the extremely thin
silicon oxide film 4 has been formed, anHf silicate film 5 of a thickness of, for example, about 3 nm is formed using the above-described method (Step S210). - After the
Hf silicate film 5 has been formed, and before a nitrogen-containingHf silicate film 6 is formed, a treatment for the densification of theHf silicate film 5 may be carried out (Step S212). The densification treatment can be carried out, for example, by performing rapid heat treatment using a halogen lamp in a nitrogen-gas atmosphere wherein a trace of oxygen gas is added, or in a nitrogen-gas atmosphere for 1 to 600 sec. Alternatively, the densification treatment can be carried out by performing rapid heat treatment using a flash lamp in the same atmosphere for 0.8 to 20 msec. - Next, as
FIG. 8C shows, a nitrogen-containingHf silicate film 6 containing Hf of a peak concentration of 1 atomic % or more and 30 atomic % or less, and nitrogen of a peak concentration of 10 atomic % or more and 30 atomic % or less is formed on the upper layer of the Hf silicate film 5 (Step S214). The nitrogen-containingHf silicate film 6 can be formed by the plasma treatment using a nitrogen-based gas. - In place of forming the nitrogen-containing
Hf silicate film 6 by nitriding theHf silicate film 5, the nitrogen-containingHf silicate film 6 may be formed on theHf silicate film 5 using a material that contains hafnium, oxygen, silicon and nitrogen. - After the nitrogen-containing
Hf silicate film 6 has been formed, densification treatment is carried out (Step S216). The densification treatment can be carried out, for example, by rapid heat treatment using a lamp in a nitrogen-gas atmosphere wherein a trace of oxygen gas is added, or in a nitrogen-gas atmosphere. - Next, as
FIG. 8D shows, a polysilicon film 7 that will finally become a gate electrode is formed on the nitrogen-containing Hf silicate film 6 (Step S218). - Then, as
FIG. 9A shows, an impurity 8 such as boron is ion-implanted into the polysilicon film 7 (Step S220). Thereby, a dopedpolysilicon film 7 a is formed on the nitrogen-containingHf silicate film 6. On the other hand, although not shown in the drawings, an impurity such as phosphorus is ion-implanted into a polysilicon film formed on the NMOS transistor-forming region. - Next, a resist pattern (not shown) is formed on the doped
polysilicon film 7 a (Step S222), and using the resist pattern as a mask, the dopedpolysilicon film 7 a, the nitrogen-containingHf silicate film 6, theHf silicate film 5, and thesilicon oxide film 4 are sequentially etched (Step S224). Thereby, asFIG. 9B shows, apolysilicon gate electrode 7 b is formed on the n-type well 2 of thesilicon substrate 1, through the gate insulating film formed by laminating thesilicon oxide film 4 a, theHf silicate film 5 a, and the nitrogen-containingHf silicate film 6 a. - Then, a low concentration of boron difluoride (BF2) is ion-implanted into the n-type well 2 using the
gate electrode 7 b as a mask. Thereby, in the n-type well 2, a p-type low-concentration ion-implantedlayer 10 that will finally become an extension region is formed on the upper layer of thesilicon substrate 1 on the both sides of thegate electrode 7 b. On the other hand, although not shown in the drawings, in the NMOS transistor-forming region, arsenic is ion-implanted into the p-type well to form an n-type low-concentration ion-implanted layer (Step S226). - Next, a silicon nitride film having a thickness of, for example, about 100 nm is formed on the entire surface of the
silicon substrate 1 so as to coat thegate electrode 7 b, and the silicon nitride film is subjected to anisotropic etching. Thereby, asFIG. 9C shows, asidewall 11 consisting of the silicon nitride film is formed in a self-aligning manner (Step S228). - Next, as
FIG. 10A shows,boron 12 is ion-implanted into the n-type well 2 as a high-concentration P-type impurity 12 using thegate electrode 7 b and thesidewall 11 as masks. Thereby, a p-type high-concentration ion-implantedlayer 13 that will finally become the source/drain region is formed in the n-type well 2. On the other hand, although not shown in the drawings, in the NMOS transistor-forming region, phosphorus is ion-implanted into the p-type well to form an n-type high-concentration ion-implanted layer (Step S230). - Next, rapid heat treatment using a lamp is performed (Step S232). Thereby, as
FIG. 10B shows, the p-type low-concentration ion-implantedlayer 10 and the p-type high-concentration ion-implantedlayer 13 in the n-type well 2 are activated, and the p-type extension region 14 wherein an impurity is introduced in a low concentration, and the p-type source/drain region 15 wherein an impurity is introduced in a high concentration are formed. On the other hand, although not shown in the drawings, in the NMOS transistor-forming region, the n-type low-concentration ion-implanted layer and the n-type high-concentration ion-implanted layer in the p-type well are activated, and the n-type extension region wherein an impurity is introduced in a low concentration, and the n-type source/drain region wherein an impurity is introduced in a high concentration are formed. - Here, the temperature of heat treatment for activation is preferably at least 10 degrees lower than the temperature of heat treatment for densification. For example, heat treatment for activation can be performed at 980° C., and heat treatment for densification can be performed at 1000° C. Thereby, the interaction between the gate insulating film and the gate electrode is inhibited, and the thermally stable gate insulating film wherein the diffusion of the impurity introduced into the gate electrode is inhibited can be obtained.
- Next, as
FIG. 10C shows, aninterlayer insulating film 16 is formed on the entire surface of the substrate using the CVD method. Thereafter, a resist pattern (not shown) is formed on the insulatingfilm 16 using a lithography techniques, contact holes connected to the source/drain region 15 are formed in theinterlayer insulating film 16 by dry etching using the resist pattern as masks, and then a barrier metal film and a tungsten film are buried in the contact holes to formcontacts 17. The unnecessary barrier metal film and tungsten film are removed using the CMP method. Thereafter, metal wirings 18 are formed on thecontacts 17 to manufacture the semiconductor device shown inFIG. 1 . - Next, the gate capacity-gate voltage characteristics (hereafter referred to as “C-V characteristics”) of the MOS transistor manufactured in this embodiment will be described.
-
FIG. 11 is a graph showing the C-V characteristics of a semiconductor device according to the first embodiment. Specifically,FIG. 1A is a graph showing the C-V characteristics of an NMOS transistor; andFIG. 11B is a graph showing the C-V characteristics of a PMOS transistor. - As
FIGS. 11A and 11B show, when an Hf silicate film is formed in Hf/Si=1/1 (above described), the C-V characteristics of an actually obtained MOS transistor are deviated from ideal C-V characteristics. This is because the initial Vfb shift is not inhibited. - On the other hand, when an Hf silicate film is formed in Hf/Si=1/2, the C-V characteristics are close to ideal C-V characteristics.
- Furthermore, when an Hf silicate film is formed in Hf/Si=1/4, that is, when the metal concentration [hf/(Hf+Si)] is about 30% or less, substantially ideal C-V characteristics can be obtained. Therefore, it is understood that the initial Vfb is sufficiently inhibited.
- Thus, better C-V characteristics could be obtained by forming a silicon-rich Hf silicate film, and a substantially ideal C-V curve was obtained when the metal concentration was about 30% or less. Especially, as
FIG. 11B shows, marked improvement of C-V characteristics was achieved in the PMOS transistor. - In addition, as
FIGS. 11A and 11B show, it is known that the C/Cmax value varies depending on the Hf/Si ratio in the reverse side, and with increase in the concentration of silicon, the C/Cmax value increases. This is considered because as the concentration of silicon in the Hf silicate film increases, the diffusion of impurities from the upper electrode polysilicon decreases, and depletion is minimized. - The same results can also be obtained in the case of the Hf silicate formation using the above-described other Hf materials or Si materials.
- According to this embodiment, as described above, the peak concentration of the metal in the nitrogen-containing
Hf silicate film 6 a positioned on the uppermost layer of the gate insulating film was controlled to 1 atomic % or more and 30 atomic % or less. Thereby, the initial Vfb shift could be sufficiently inhibited, and C-V characteristics equivalent to ideal C-V characteristics could be obtained. - Further, the peak concentration of nitrogen in the nitrogen-containing
Hf silicate film 6 a was controlled to 10 atomic % or more and 30 atomic % or less. Thereby, the diffusion of impurities introduced into the gate electrode in the activating heat treatment could be inhibited, and the Vfb shift due to the diffusion of impurities could be inhibited. - In the first embodiment, the case of using a metal silicate film as the high-dielectric-
constant film 5, and using a nitrogen-containing metal silicate film as the upperlayer insulating film 6 was described. However, for example, the present invention can be applied to the case of using a metal aluminate film as the high-dielectric-constant film, and using a nitrogen-containing metal aluminate film as the upper layer insulating film, and the similar results can also be obtained from this case. - Next, the modification on the first embodiment will be described.
- In the above-described embodiment, the peak concentration of the metal was equivalent in the
metal silicate film 5 a and in the nitrogen-containingmetal silicate film 6 a. In this modification, however, the peak concentration of the metal in themetal silicate film 5 a was higher than that in the nitrogen-containingmetal silicate film 6 a. In other words, themetal silicate film 5 a was made to be a metal-rich film; and the nitrogen-containingmetal silicate film 6 a was made to be a silicon-rich film. Since other constitution is the same as in the above-described embodiment, the description thereof will be omitted. - In this modification, a metal silicate film (e.g., Hf silicate film or Zr silicate film) as the high-dielectric-
constant film 5 a was made to be a metal-rich film that contains a metal in the peak concentration of 5 atomic % or more and 40 atomic % or less. - In the method for manufacturing a semiconductor device according to the above-described embodiment, after a
silicon oxide film 4 has been formed, for example, a hafnium-rich Hf silicate film is formed in the ratio of Hf/Si=1/2. On the Hf silicate film, a silicon-rich Hf silicate film is formed in the ratio of Hf/Si=1/4. Thereafter, the silicon-rich Hf silicate film is nitrided to form a silicon-rich nitrogen-containing Hf silicate film as the upper layer insulating film. Thereafter, in the same manner as in the above-described embodiment, a polysilicon film 7 is formed on the nitrogen-containing Hf silicate film. - In this modification, by making the film on the uppermost layer of the gate insulating film a nitrogen-containing metal silicate film that contains the metal in the peak concentration of 1 atomic % or more and 30 atomic % or less, the similar effect as in the above-described embodiment can also be obtained. Furthermore, this modification can improve the total effective specific dielectric constant of the gate insulating film by the use of a metal-rich metal silicate film as the high-dielectric-
constant film 5 a. - The semiconductor device and the method for the manufacture thereof according to the second embodiment is the same as those described in the first embodiment. In the second embodiment, however, a different method is used to form a metal silicate such as an Hf silicate.
- This will be described below in detail.
-
FIG. 12 is a schematic diagram for illustrating a thin film forming apparatus in the second embodiment of the present invention. - As
FIG. 12 shows, the thinfilm forming apparatus 100 is equipped with avacuum chamber 20. - On the central portion in the
chamber 20, a table 21 is disposed. In the table 21, aheater 22 is installed to heat the table from the bottom thereof to a predetermined temperature. - Above the table 21, a
gas supply pipe 23 is installed so as to pass through a portion of the outer wall of thechamber 20. In other words, thegas supply pipe 23 passes from the outside of thechamber 20 to the inside of thechamber 20, and thereby supplies the gas into thechamber 20. Thegas supply pipe 23 is also disposed so as to surround upside of the table 21. Thegas supply pipe 23 has a plurality ofejection nozzles 24. The gas supplied from thegas supply pipe 23 is ejected through theseejection nozzles 24 into thechamber 20. - A total of two
gas discharge ports 25 are installed so as to pass through the underside of the outer wall of thechamber 20. Thegas discharge ports 25 run from the inside to the outside of thechamber 20, and are connected to a vacuum pump through avalve 26. Thereby the gas in thechamber 20 can be discharged to the exterior. - The ceiling portion of the
chamber 20, facing the table 21, is formed of aquartz window 27. In the upper portion of thequartz window 27, a total of 50flash lamps 28 are disposed, and theflash lamps 28 are covered with areflective plate 29. Theflash lamps 28 are connected to acapacitor 30, and thecapacitor 30 is connected to apower source 31. - In the thin
film forming apparatus 100, the ceiling portion of thechamber 20 is formed of aquartz window 27 that permeates light so as to introduce light emitted from theflash lamps 28. Thereflective plate 29 is installed so as to reflect the light emitted from theflash lamps 28 toward the opposite side to the chamber 20 (upward inFIG. 12 ) to thechamber 20, and to introduce the light into thechamber 20. The current from thepower source 31 is charged into thecapacitor 30, and instant discharge of the electric charge makes theflash lamp 28 emit light. - In the second embodiment, a metal silicate is formed using the thin
film forming apparatus 100 constituted as described above, in place of the steps S102 to S110 (S210) in the manufacturing process of the semiconductor device described in the first embodiment. In this case asubstrate 32 is placed on the table 21. -
FIG. 13 is a flow diagram for illustrating the method for forming a metal silicate film in the second embodiment of the present invention; andFIG. 14 is a graph for illustrating the sequence in the method for forming a metal silicate film in the second embodiment. - In the second embodiment, the metal silicate film is also formed by individually forming a hafnium oxide film and a silicon oxide film. This will be specifically described referring to FIGS. 12 to 14.
- First, a hafnium oxide film is formed.
- Here, first, the table 21 is heated in the state where a
substrate 32 is placed on the table 21 (Step S302). Here, the table 21 is heated using theheater 22 to a temperature of 300° C. Thereby, the temperature of thesubstrate 32 is maintained at 300° C. Next, the gas in thechamber 20 is discharged (Step S304). Gas discharge is performed by opening thevalve 26 and sucking the gas through thegas discharge ports 25 using the vacuum pump until the pressure in thechamber 20 becomes 10−7 Torr. Thereafter, argon gas is supplied into the chamber 20 (Step S306). The argon gas is supplied through thegas supply pipe 23, and is ejected through the ejection nozzles 24 into thechamber 20. The pressure in thechamber 20 is fixed to 0.5 Torr. - After the
chamber 20 has been maintained in this state, the introduction of the material gas is started. - Referring to
FIG. 14 , the supply of hafnium tetramethylethylamide is started at the point A1 (Step S310). Hafnium tetramethylethylamide is supplied through thegas supply pipe 23, and is ejected through the ejection nozzles 24 into thechamber 20. The supply of hafnium tetramethylethylamide is performed at 2 sccm for 1.5 seconds, and the supply is stopped at the point B1 1.5 seconds later (Step S312). - Thereafter, the purge of the gas in the
chamber 20 is started (Step S314). Here, argon gas is supplied through thegas supply pipe 23 for about 5 seconds. On the other hand, thevalve 26 is opened and the gas in thechamber 20 is discharged through thegas discharge ports 25 with the vacuum pump. The supply of argon gas and gas discharge are stopped at thepoint C 1 5 seconds later (Step S316). At this time, thevalve 26 is closed. - Thereafter, the supply of ozone gas is started (Step S318). In the same manner as hafnium tetramethylethylamide, ozone gas is also supplied through the
gas supply pipe 23, and is ejected through the ejection nozzles 24 into thechamber 20. The supply of ozone gas is performed at 5 sccm for 2 seconds, and the supply is stopped at thepoint D 1 2 seconds later (Step S320). - Thereafter, the discharge of the gas from the
chamber 20 is started (Step S322). In the same manner as the discharge performed after the supply of hafnium tetramethylethylamide, the gas is purged by supplying argon gas through thegas supply pipe 23, and simultaneously thevalve 26 is opened to discharge the gas through thegas discharge ports 25 using the vacuum pump. - At the point E1, 6 seconds after gas purge was started, the light emitting of the
flash lamps 28 is performed (Step S324). The energy of the light-emittingflash lamps 28 is 15 J/cm2. The light-emitting time of theflash lamps 28 is as an extremely short time such as about 5.0 to 20 msec, and thereby only the surface of thesubstrate 32 is heated instantly. - At the point A2, 8 seconds after gas purge was started, the supply of argon gas and the discharge of the gas from the
chamber 20 are stopped (Step S326). Thereafter, the introduction of hafnium tetramethylethylamide is started again (Step S310), and steps S310 to S326 are repeated. - Thus, the introduction of hafnium tetramethylethylamide (Steps S310 and S312), the purge of the gas (Steps S314 and S316), the introduction of ozone gas (Steps S318 and S320), the purge of the (Steps S322 and S326), and the light emitting of the flash lamps during the purge of the gas (Step S324) are repeated for 20 times, and the formation of the thin film is completed. Thereby, a hafnium oxide film of a thickness of about 2.5 nm can be formed on the
substrate 32. - Next, in the same manner, a silicon oxide film is formed.
- First, the table 21 is maintained at about 300° C. in the same manner as in the formation of the hafnium oxide film. The
chamber 20 is purged with argon gas, and the pressure in thechamber 20 is fixed to 5.0 Torr. - After the
chamber 20 is maintained in this state, the introduction of the material gas is started. - Referring again to
FIG. 14 , the supply of trisdimethylaminosilane as the Si material is started at the point A1 (Step S330). Trisdimethylaminosilane is supplied through thegas supply pipe 23, and is ejected through the ejection nozzles 24 into thechamber 20. The supply of trisdimethylaminosilane is performed at 2 sccm for 1.5 seconds, and the supply is stopped at the point B1 1.5 seconds later (Step S332). - Thereafter, the purge of the gas in the
chamber 20 is started (Step S334). Here, argon gas is supplied through thegas supply pipe 23 for about 5 seconds, and on the other hand, thevalve 26 is opened. The gas in thechamber 20 is discharged through thegas discharge ports 25 with the vacuum pump, and the purge of the gas is stopped at thepoint C 1 5 seconds later (Step S336). - Thereafter, the supply of ozone gas is started (Step S338). In the same manner as trisdimethylaminosilane, ozone gas is also supplied through the
gas supply pipe 23, and is ejected through the ejection nozzles 24 into thechamber 20. The supply of ozone gas is performed at 5 sccm for 2 seconds, and the supply is stopped at thepoint D 1 2 seconds later (Step S340). - Thereafter, the discharge of the gas from the
chamber 20 is started (Step S342). In the same manner as the discharge performed after the supply of trisdimethylaminosilane, the gas is purged by supplying argon gas through thegas supply pipe 23, and simultaneously thevalve 26 is opened to discharge the gas through thegas discharge ports 25 using the vacuum pump. - At the point E1, 6 seconds after the purge of the gas was started, the light emitting of the
flash lamps 28 is performed (Step S344). The energy of the light-emittingflash lamps 28 is 15 J/cm2. The light-emitting time of theflash lamps 28 is as an extremely short time such as about 5.0 to 20 msec, and thereby only the surface of thesubstrate 32 is heated instantly. - At the point A2, 8 seconds after the purge of the gas was started, the purge of the gas in the
chamber 20 is stopped (Step S346). Thereafter, the introduction of trisdimethylaminosilane is started again (Step S330), and steps S330 to S346 are repeated. - Thus, the introduction of trisdimethylaminosilane (Steps S330 and S332), the purge of the gas (Steps S334 and S336), the introduction of ozone gas (Steps S338 and S340), the purge of the gas (Steps S342 and S346), and the light emitting of the
flash lamps 28 during the purge of the gas (Step S344) are repeated for 5 times, and the formation of the thin film is completed. Thereby, a silicon oxide film of a thickness of about 0.4 nm can be formed on thesubstrate 32. - Thereafter, the steps S212 to S232 described in the first embodiment is carried out to form a semiconductor device according to the second embodiment.
- Here, the formed hafnium oxide film in the second embodiment was compared with an aluminum oxide film formed according to a conventional method, wherein the sequence of the supply of the material gas and the purge of the gas is performed in the same manner, but without heating with the
flash lamps 28, using a secondary ion mass spectrometer, and it was found that the quantity of residual carbon in the thin film was lowered to about 1/10. - This is considered that since heating of the millisecond order can be performed by heating by flash lamps, the temperature of the surface of the
substrate 32 can be raised instantly to accelerate the reaction, and the temperature of thesubstrate 32 can be immediately lowered to the original temperature. - Whereas, in the case of using the conventional ALD method, after supplying the material gas, an oxidizing gas such as ozone gas is supplied to start oxidation reaction. However, at this time, since the temperature of the wafer is low, and the reaction time is not sufficiently long, the oxidation reaction is not completed. This is considered to be the cause of residual impurities in the film.
- In the ALD method, however, since the reaction rate of the film is low, the reaction time cannot be made sufficiently long when productivity is considered.
- Since chemical kinetics teaches that the reaction rate is the exponential function of temperature, it is considered to raise temperature to increase the reaction rate. However, in an apparatus used for the conventional ALD method, it is considered that if the temperature of a wafer is simply raised, decomposition begins only by supplying the material gas. For example, if hafnium tetramethylethylamide is supplied at a high substrate temperature, the hafnium tetramethylethylamide is decomposed by itself, and a carbon-containing hafnium film is formed. Therefore, temperature cannot be raised in the conventional ALD.
- On the other hand, according to the formation of a metal silicate film in the above-described embodiment, the
flash lamps 28 can heat the surface of a wafer for the millisecond order and can raise the surface temperature of the wafer instantly to accelerate the rate of reaction. Also since only the surface of thesubstrate 32 is heated for an extremely short time, the wafer temperature can be immediately returned to the original temperature. Therefore, the next cycle (Steps S310 to S324) can be performed at the original wafer temperature. Thereby, a high-dielectric-constant thin film having a low impurity concentration and good characteristics can be formed. - In the second embodiment, the case wherein a thin
film forming apparatus 100 is used for forming the metal silicate film of a semiconductor device was described. However, the present invention is not limited thereto, but the thinfilm forming apparatus 100 can be applied to the formation of other thin films. - In the second embodiment, the case wherein 50
flash lamps 28 are used was described; however, the thin film forming apparatus of the present invention is not limited to the apparatus using 50 flash lamps. Further in this embodiment,flash lamps 28 are used as the heating means. However, the heating means in the present invention is not limited to the flash lamps, but other means can be used as long as the surface of the substrate can be adequately heated. - Also in the second embodiment, the case wherein the heating time by the flash lamps is 5.0 to 20 milliseconds was described. However, the heating time in the present invention is not limited to this range. However, when the lowering of the impurity concentration contained in the high-dielectric-constant film is considered, it is considered that the heating time is preferably 0.8 milliseconds or longer.
- In this embodiment, the upper portion of the
chamber 20 was made to be aquartz window 27, through which light from theflash lamps 28 was transmitted to irradiate the substrate in thechamber 20. Furthermore, the case wherein areflective plate 29 is installed above theflash lamps 28 so as to reflect light emitted upward and irradiate thechamber 20 was described. However, the constitution of the thin film forming apparatus according to the present invention is not limited thereto, but other constitution, for example, the constitution wherein theflash lamps 28 are directly installed in thechamber 20, can be used. - Further in this embodiment, the case wherein ejecting
nozzles 24 are installed in thegas supply pipe 23, and a vacuum pump is installed in thegas discharge ports 25 through avalve 26 to discharge the gas was described. However, the thin film forming apparatus of the present invention is not limited to the apparatus having such a constitution, but other constitutions can be used as long as the gas can be supplied into thechamber 20, and the gas can be adequately discharged from thechamber 20. - The other constitutions of the thin film forming apparatus of the present invention are not limited to the constitution described in this embodiment, but other constitutions can be used as long as the surface of the substrate can be adequately heated, and the reaction can be accelerated.
- Furthermore, since the description of the material gas and the like to be used in the second embodiment is the same as those described in the first embodiment, the description thereof was omitted.
- The features and the advantages of the present invention as described above may be summarized as follows.
- According to one aspect of the present invention, in a semiconductor device, the metal content in the metal silicate film formed on the uppermost layer of a high-dielectric-constant film is controlled. Accordingly, the semiconductor device having C-V characteristics equivalent to ideal C-V characteristics can be realized.
- Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may by practiced otherwise than as specifically described.
- The entire disclosure of a Japanese Patent Application No. 2003-434367, filed on Dec. 26, 2003 including specification, claims, drawings and summary, on which the Convention priority of the present application is based, are incorporated herein by reference in its entirety.
Claims (7)
1. (canceled)
2. A semiconductor device comprising:
a substrate;
a gate insulating film on said substrate, and including:
a base interface layer on said substrate,
a metal silicate film on said base interface layer, and containing a metal, oxygen, and silicon, and
a nitrogen-containing metal silicate film that contains said metal, oxygen, silicon, and nitrogen, and including ten to thirty atomic percent nitrogen; and
a gate electrode on said gate insulating film, wherein said metal silicate film has a metal concentration higher than metal concentration of said nitrogen-containing metal silicate film.
3. The semiconductor device according to claim 2 , wherein said nitrogen-containing metal silicate film contains said metal in a concentration in a range from one to thirty atomic percent.
4. The semiconductor device according to claim 3 , wherein said metal silicate film contains said metal in a concentration in a range from five to forty atomic percent.
5-20. (canceled)
21. The semiconductor device as claimed in claim 2 , wherein metal concentration of said metal silicate film is two times silicon concentration of said metal silicate film.
22. The semiconductor device according to claim 2 , wherein metal concentration of said nitrogen-containing metal silicate film is four times silicon concentration of said nitrogen-containing metal silicate film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/476,867 US20060273408A1 (en) | 2003-12-26 | 2006-06-29 | Semiconductor device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003-434367 | 2003-12-26 | ||
JP2003434367A JP2005191482A (en) | 2003-12-26 | 2003-12-26 | Semiconductor device and its manufacturing method |
US10/811,979 US7101753B2 (en) | 2003-12-26 | 2004-03-30 | Method for manufacturing a semiconductor device and method for forming high-dielectric-constant film |
US11/476,867 US20060273408A1 (en) | 2003-12-26 | 2006-06-29 | Semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/811,979 Division US7101753B2 (en) | 2003-12-26 | 2004-03-30 | Method for manufacturing a semiconductor device and method for forming high-dielectric-constant film |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060273408A1 true US20060273408A1 (en) | 2006-12-07 |
Family
ID=34545101
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/811,979 Expired - Fee Related US7101753B2 (en) | 2003-12-26 | 2004-03-30 | Method for manufacturing a semiconductor device and method for forming high-dielectric-constant film |
US11/476,867 Abandoned US20060273408A1 (en) | 2003-12-26 | 2006-06-29 | Semiconductor device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/811,979 Expired - Fee Related US7101753B2 (en) | 2003-12-26 | 2004-03-30 | Method for manufacturing a semiconductor device and method for forming high-dielectric-constant film |
Country Status (4)
Country | Link |
---|---|
US (2) | US7101753B2 (en) |
EP (1) | EP1548839A1 (en) |
JP (1) | JP2005191482A (en) |
KR (1) | KR20050066936A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070281475A1 (en) * | 2006-05-30 | 2007-12-06 | Robert Daniel Clark | Diethylsilane As A Silicon Source In The Deposition Of Metal Silicate Films |
US20110201169A1 (en) * | 2001-06-01 | 2011-08-18 | Semiconductor Energy Laboratory Co., Ltd. | Thermal Treatment Equipment and Method for Heat-Treating |
US8323754B2 (en) * | 2004-05-21 | 2012-12-04 | Applied Materials, Inc. | Stabilization of high-k dielectric materials |
US20130337661A1 (en) * | 2012-06-15 | 2013-12-19 | Dainippon Screen Mfg. Co., Ltd. | Heat treatment method and heat treatment apparatus for heating substrate by irradiating substrate with light |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100689824B1 (en) * | 2004-05-14 | 2007-03-08 | 삼성전자주식회사 | Method of manufacturing a metal silicate layer using atomic layer deposition technique |
US7564108B2 (en) * | 2004-12-20 | 2009-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitrogen treatment to improve high-k gate dielectrics |
KR100688521B1 (en) * | 2005-01-18 | 2007-03-02 | 삼성전자주식회사 | Semiconductor Device comprising High-k insulating layer and Manufacturing Method for the Same |
JP2006261434A (en) | 2005-03-17 | 2006-09-28 | L'air Liquide Sa Pour L'etude & L'exploitation Des Procede S Georges Claude | Method for forming silicon oxide film |
JP4671729B2 (en) * | 2005-03-28 | 2011-04-20 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
JP4554446B2 (en) * | 2005-06-21 | 2010-09-29 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US7655994B2 (en) * | 2005-10-26 | 2010-02-02 | International Business Machines Corporation | Low threshold voltage semiconductor device with dual threshold voltage control means |
JP2007235093A (en) * | 2006-01-31 | 2007-09-13 | Toshiba Corp | Method for manufacturing semiconductor device |
US8012442B2 (en) | 2006-03-31 | 2011-09-06 | Tokyo Electron Limited | Method of forming mixed rare earth nitride and aluminum nitride films by atomic layer deposition |
US7816737B2 (en) | 2006-03-31 | 2010-10-19 | Tokyo Electron Limited | Semiconductor device with gate dielectric containing mixed rare earth elements |
US7601651B2 (en) * | 2006-03-31 | 2009-10-13 | Applied Materials, Inc. | Method to improve the step coverage and pattern loading for dielectric films |
US8097300B2 (en) | 2006-03-31 | 2012-01-17 | Tokyo Electron Limited | Method of forming mixed rare earth oxynitride and aluminum oxynitride films by atomic layer deposition |
US7759746B2 (en) | 2006-03-31 | 2010-07-20 | Tokyo Electron Limited | Semiconductor device with gate dielectric containing aluminum and mixed rare earth elements |
US20080001237A1 (en) * | 2006-06-29 | 2008-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having nitrided high-k gate dielectric and metal gate electrode and methods of forming same |
KR100744423B1 (en) | 2006-08-28 | 2007-07-30 | 동부일렉트로닉스 주식회사 | Method of forming hafnium-silicate-oxide layer and method of manufactruing the same method |
US7767262B2 (en) | 2006-09-29 | 2010-08-03 | Tokyo Electron Limited | Nitrogen profile engineering in nitrided high dielectric constant films |
WO2008042695A2 (en) * | 2006-09-29 | 2008-04-10 | Tokyo Electron Limited | Semiconductor devices containing nitrided high dielectric constant films and method of forming |
EP1916705A3 (en) * | 2006-10-23 | 2009-01-14 | Interuniversitair Microelektronica Centrum (IMEC) | Semiconductor device comprising a doped metal comprising main electrode |
US7678422B2 (en) | 2006-12-13 | 2010-03-16 | Air Products And Chemicals, Inc. | Cyclic chemical vapor deposition of metal-silicon containing films |
KR100864871B1 (en) * | 2007-05-29 | 2008-10-22 | 한국전자통신연구원 | The manufacturing method of semiconductor device |
US8159035B2 (en) * | 2007-07-09 | 2012-04-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gates of PMOS devices having high work functions |
US7998820B2 (en) * | 2007-08-07 | 2011-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | High-k gate dielectric and method of manufacture |
US7858535B2 (en) * | 2008-05-02 | 2010-12-28 | Micron Technology, Inc. | Methods of reducing defect formation on silicon dioxide formed by atomic layer deposition (ALD) processes and methods of fabricating semiconductor structures |
KR101451716B1 (en) * | 2008-08-11 | 2014-10-16 | 도쿄엘렉트론가부시키가이샤 | Film forming method and film forming apparatus |
US8129284B2 (en) * | 2009-04-28 | 2012-03-06 | Dainippon Screen Mfg. Co., Ltd. | Heat treatment method and heat treatment apparatus for heating substrate by light irradiation |
JP5247619B2 (en) * | 2009-07-28 | 2013-07-24 | キヤノンアネルバ株式会社 | Dielectric film, semiconductor device manufacturing method using the dielectric film, and semiconductor manufacturing apparatus |
US8076241B2 (en) | 2009-09-30 | 2011-12-13 | Tokyo Electron Limited | Methods for multi-step copper plating on a continuous ruthenium film in recessed features |
JP6092902B2 (en) * | 2012-03-09 | 2017-03-08 | エア プロダクツ アンド ケミカルズ インコーポレイテッドAir Products And Chemicals Incorporated | Method for producing a silicon-containing film on a thin film transistor device |
US10769826B2 (en) | 2014-12-31 | 2020-09-08 | Servicenow, Inc. | Visual task board visualization |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5705224A (en) * | 1991-03-20 | 1998-01-06 | Kokusai Electric Co., Ltd. | Vapor depositing method |
US6013553A (en) * | 1997-07-24 | 2000-01-11 | Texas Instruments Incorporated | Zirconium and/or hafnium oxynitride gate dielectric |
US6544906B2 (en) * | 2000-12-21 | 2003-04-08 | Texas Instruments Incorporated | Annealing of high-k dielectric materials |
US6548424B2 (en) * | 2000-04-14 | 2003-04-15 | Asm Microchemistry Oy | Process for producing oxide thin films |
US6642131B2 (en) * | 2001-06-21 | 2003-11-04 | Matsushita Electric Industrial Co., Ltd. | Method of forming a silicon-containing metal-oxide gate dielectric by depositing a high dielectric constant film on a silicon substrate and diffusing silicon from the substrate into the high dielectric constant film |
US20030218223A1 (en) * | 2002-02-26 | 2003-11-27 | Kabushiki Kaisha Toshiba | Semiconductor device and its manufacturing method |
US20040171276A1 (en) * | 2001-08-23 | 2004-09-02 | Heiji Watanabe | Semiconductor device having high-piemittivity insulation film and production method therefor |
US20040169240A1 (en) * | 2002-12-05 | 2004-09-02 | Masato Koyama | Semiconductor device and method of manufacturing semiconductor device |
US20050110091A1 (en) * | 1992-08-27 | 2005-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
US20050167768A1 (en) * | 2003-03-17 | 2005-08-04 | Fujitsu Limited | Manufacture of semiconductor device having insulation film of high dielectric constant |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002299607A (en) * | 2001-03-28 | 2002-10-11 | Toshiba Corp | Misfet and method of manufacturing the same |
JP2002343790A (en) | 2001-05-21 | 2002-11-29 | Nec Corp | Vapor-phase deposition method of metallic compound thin film and method for manufacturing semiconductor device |
JP3773448B2 (en) * | 2001-06-21 | 2006-05-10 | 松下電器産業株式会社 | Semiconductor device |
WO2003001605A1 (en) * | 2001-06-21 | 2003-01-03 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and its manufacturing method |
JP4102072B2 (en) * | 2002-01-08 | 2008-06-18 | 株式会社東芝 | Semiconductor device |
JP4095326B2 (en) * | 2002-03-29 | 2008-06-04 | 株式会社東芝 | Semiconductor device manufacturing method and semiconductor device |
JP3627106B2 (en) * | 2002-05-27 | 2005-03-09 | 株式会社高純度化学研究所 | Method for producing hafnium silicate thin film by atomic layer adsorption deposition |
JP4059183B2 (en) * | 2003-10-07 | 2008-03-12 | ソニー株式会社 | Insulator thin film manufacturing method |
-
2003
- 2003-12-26 JP JP2003434367A patent/JP2005191482A/en active Pending
-
2004
- 2004-03-17 EP EP04006409A patent/EP1548839A1/en not_active Withdrawn
- 2004-03-30 KR KR1020040021385A patent/KR20050066936A/en not_active Application Discontinuation
- 2004-03-30 US US10/811,979 patent/US7101753B2/en not_active Expired - Fee Related
-
2006
- 2006-06-29 US US11/476,867 patent/US20060273408A1/en not_active Abandoned
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5705224A (en) * | 1991-03-20 | 1998-01-06 | Kokusai Electric Co., Ltd. | Vapor depositing method |
US20050110091A1 (en) * | 1992-08-27 | 2005-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
US6013553A (en) * | 1997-07-24 | 2000-01-11 | Texas Instruments Incorporated | Zirconium and/or hafnium oxynitride gate dielectric |
US6020243A (en) * | 1997-07-24 | 2000-02-01 | Texas Instruments Incorporated | Zirconium and/or hafnium silicon-oxynitride gate dielectric |
US6548424B2 (en) * | 2000-04-14 | 2003-04-15 | Asm Microchemistry Oy | Process for producing oxide thin films |
US6544906B2 (en) * | 2000-12-21 | 2003-04-08 | Texas Instruments Incorporated | Annealing of high-k dielectric materials |
US6642131B2 (en) * | 2001-06-21 | 2003-11-04 | Matsushita Electric Industrial Co., Ltd. | Method of forming a silicon-containing metal-oxide gate dielectric by depositing a high dielectric constant film on a silicon substrate and diffusing silicon from the substrate into the high dielectric constant film |
US20040171276A1 (en) * | 2001-08-23 | 2004-09-02 | Heiji Watanabe | Semiconductor device having high-piemittivity insulation film and production method therefor |
US20030218223A1 (en) * | 2002-02-26 | 2003-11-27 | Kabushiki Kaisha Toshiba | Semiconductor device and its manufacturing method |
US20040169240A1 (en) * | 2002-12-05 | 2004-09-02 | Masato Koyama | Semiconductor device and method of manufacturing semiconductor device |
US20050167768A1 (en) * | 2003-03-17 | 2005-08-04 | Fujitsu Limited | Manufacture of semiconductor device having insulation film of high dielectric constant |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110201169A1 (en) * | 2001-06-01 | 2011-08-18 | Semiconductor Energy Laboratory Co., Ltd. | Thermal Treatment Equipment and Method for Heat-Treating |
US8318567B2 (en) * | 2001-06-01 | 2012-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Thermal treatment equipment and method for heat-treating |
US8323754B2 (en) * | 2004-05-21 | 2012-12-04 | Applied Materials, Inc. | Stabilization of high-k dielectric materials |
US20070281475A1 (en) * | 2006-05-30 | 2007-12-06 | Robert Daniel Clark | Diethylsilane As A Silicon Source In The Deposition Of Metal Silicate Films |
US7582574B2 (en) * | 2006-05-30 | 2009-09-01 | Air Products And Chemicals, Inc. | Diethylsilane as a silicon source in the deposition of metal silicate films |
US20130337661A1 (en) * | 2012-06-15 | 2013-12-19 | Dainippon Screen Mfg. Co., Ltd. | Heat treatment method and heat treatment apparatus for heating substrate by irradiating substrate with light |
US9023740B2 (en) * | 2012-06-15 | 2015-05-05 | SCREEN Holdings Co., Ltd. | Heat treatment method and heat treatment apparatus for heating substrate by irradiating substrate with light |
Also Published As
Publication number | Publication date |
---|---|
US7101753B2 (en) | 2006-09-05 |
KR20050066936A (en) | 2005-06-30 |
EP1548839A1 (en) | 2005-06-29 |
JP2005191482A (en) | 2005-07-14 |
US20050139937A1 (en) | 2005-06-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7101753B2 (en) | Method for manufacturing a semiconductor device and method for forming high-dielectric-constant film | |
JP4554446B2 (en) | Manufacturing method of semiconductor device | |
US7473994B2 (en) | Method of producing insulator thin film, insulator thin film, method of manufacturing semiconductor device, and semiconductor device | |
US8334198B2 (en) | Method of fabricating a plurality of gate structures | |
US7153786B2 (en) | Method of fabricating lanthanum oxide layer and method of fabricating MOSFET and capacitor using the same | |
JP4863296B2 (en) | Manufacturing method of semiconductor device | |
US8350335B2 (en) | Semiconductor device including off-set spacers formed as a portion of the sidewall | |
US20150140838A1 (en) | Two Step Deposition of High-k Gate Dielectric Materials | |
US8987095B2 (en) | Method of fabricating a carbon-free dielectric layer over a carbon-doped dielectric layer | |
US20050051857A1 (en) | Semiconductor device | |
US20060273320A1 (en) | Method of manufacturing semiconductor device | |
US8163626B2 (en) | Enhancing NAND flash floating gate performance | |
JP2005032908A (en) | Method for forming thin film | |
EP1796174A1 (en) | Highly dielectric film, and utilizing the same, field-effect transistor and semiconductor integrated circuit apparatus, and process for producing the highly dielectric film | |
KR100647484B1 (en) | method of forming a thin film layer, and method of forming a gate structure, capacitor and flash memory device using the same | |
JP2004247474A (en) | Semiconductor device and its manufacturing method, and deposition method | |
KR20120089147A (en) | Manufacturing method of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |