US20060273459A1 - Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry - Google Patents
Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry Download PDFInfo
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- US20060273459A1 US20060273459A1 US11/496,843 US49684306A US2006273459A1 US 20060273459 A1 US20060273459 A1 US 20060273459A1 US 49684306 A US49684306 A US 49684306A US 2006273459 A1 US2006273459 A1 US 2006273459A1
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- integrated circuitry
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- 238000000034 method Methods 0.000 title abstract description 9
- 239000004065 semiconductor Substances 0.000 title description 7
- 238000003672 processing method Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 238000004891 communication Methods 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 abstract description 11
- 239000012634 fragment Substances 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention relates to semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry comprising such contact openings and electrical connections and interconnections.
- a semiconductor wafer fragment is indicated generally at 10 and comprises a semiconductive substrate 12 .
- semiconductive substrate is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials).
- substrate refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
- Substrate 12 comprises a field oxide region 13 having an outer surface 14 ( FIG. 2 ) over which a plurality of conductive runners or conductive lines 16 , 18 , and 20 are formed.
- the illustrated conductive lines or runners include conductive portions and insulative portions.
- Exemplary conductive portions are constituted, in this example, by a respective polysilicon layer 22 and an overlying silicide layer 24 .
- the insulative portions of the runners or lines are constituted by respective overlying caps 26 and associated sidewall spacers 28 .
- Exemplary materials for the insulative portions include oxides and nitrides.
- An insulative layer 30 such as borophosphosilicate glass is formed over runners 16 , 18 , and 20 and a contact opening 32 is formed through a masked etch of layer 30 to outwardly expose a portion of silicide layer 24 . Thereafter, conductive material such as conductively doped polysilicon is formed within contact opening 32 to provide a conductive contact 34 to conductive line 18 . A metal layer 36 is provided thereover to form an electrical connection with conductive line 18 .
- a typical practice within the semiconductor industry is to provide a conductive line or runner with a widened landing pad in order to accommodate mask misalignments when contact openings are formed.
- An exemplary widened landing pad is shown in FIGS. 1 and 2 at 38 .
- contact opening 32 can shift left or right some distance relative to the position shown in FIGS. 1 and 2 without making undesirable contact with the substrate.
- landing pad 38 includes the conductive and insulative portions of conductive line 18 ; and the conductive portions of conductive line 18 define a contact pad with which electrical communication is desired. Accordingly, in the illustrated example a contact pad is defined by polysilicon layer 22 and silicide layer 24 of conductive line 18 .
- the contact pad defines a target area A inside of which it is desirable to form a contact opening.
- An electrical connection through contact opening 32 can be formed anywhere within target area A and still effectively make a desirable connection with the conductive contact pad.
- the target area tolerates a contact opening mask misalignment on either side of the illustrated and desired contact opening 32 .
- a tradeoff for improved mask misalignment tolerance is a reduction in wafer real estate available for supporting conductive lines and other integrated circuitry components. This is due largely in part to the increased area which is occupied by the widened landing pad 38 . This also adversely impacts the conductive line spacing such that desired minimum spacing adjacent conductive lines is not achieved. Hence, integrated circuitry cannot be packed as densely upon a wafer as is desirable when the widened landing pads are used.
- This invention grew out of concerns associated with enhancing the efficiency with which wafer real estate is used to support integrated circuitry. This invention also grew out of concerns associated with improving the methods and structures through which contact is made relative to conductive lines.
- a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface.
- a conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad.
- Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad.
- a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof.
- the conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed.
- such plug(s) can include a portion which overlaps with the contact pad of the associated conductive line.
- FIG. 1 is a top plan view of a prior art semiconductor wafer fragment and a plurality of conductive lines supported thereon.
- FIG. 2 is a view which is taken along line 2 - 2 in FIG. 1 at a subsequent processing step.
- FIG. 3 is a diagrammatic sectional view of a semiconductor wafer fragment at one processing step in accordance with one implementation of the invention.
- FIG. 4 is a view of the FIG. 3 wafer fragment at another processing step.
- FIG. 5 is a view of the FIG. 3 wafer fragment at another processing step.
- FIG. 6 is a view of the FIG. 3 wafer fragment at another processing step.
- FIG. 7 is a view which is similar to the FIG. 6 view, but which shows an alternate embodiment in accordance with another implementation of the invention.
- FIG. 8 is a view of the FIG. 3 wafer fragment at another processing step.
- FIGS. 9 and 10 are top plan views of semiconductor wafer fragments which have been processed in accordance with the inventive methodologies.
- a plurality of conductive runners or lines 16 a , 18 a , and 20 a are formed over outer surface 14 , and can be formed over oxide isolation regions 40 .
- Exemplary isolation regions include shallow trench isolation regions or field oxide regions formed through LOCOS techniques.
- the conductive lines comprise respective outermost surfaces 44 portions of which define respective conductive line heights h outwardly of outer surface 14 .
- Diffusion regions 42 can be provided between the conductive lines, and preferably comprise n-regions having doping concentrations of 1 ⁇ 10 18 cm ⁇ 3 .
- the diffusion regions can be provided in a separate doping step, or through outdiffusion of dopant from conductive material which will become more apparent below.
- An outer contact opening target area B is defined by conductive line 18 a.
- an insulating material layer 46 is formed over substrate 12 .
- An exemplary material is borophosphosilicate glass.
- At least one, and preferably a pair of contact openings 48 , 50 are formed through layer 46 and preferably outwardly expose respective portions of outer surface 14 .
- the contact openings can be formed through a suitable masked etch of layer 46 .
- the individual contact openings are essentially self-aligned at and to the substrate at two locations 48 a , 48 b , and 50 a , 50 b respectively, along a line extending laterally from conductive runner or line 18 a .
- one of the two locations for the individual contact openings is defined by conductive runner 18 a .
- the other of the two respective locations are defined by respective next adjacent conductive lines 16 a , 20 a.
- first conductive material 52 , 54 is formed within contact openings 48 , 50 , between the illustrated conductive lines and laterally proximate or adjacent the contact pad defined by conductive line 18 a .
- An exemplary and preferred first conductive material is conductively doped polysilicon, which can serve as a source of outdiffused dopant for regions 42 .
- the polysilicon can be chemical vapor deposited over the substrate and subsequently removed through conventional processing to provide conductive plugs 56 , 58 .
- Such conventional processing can include planarization processing to isolate conductive material within the respective contact openings, followed by a suitable timed etch to recess the conductive material within the contact openings.
- conductive plugs are formed on both sides of conductive line 18 a . It is possible, however, for only one conductive plug to be formed on either side of conductive line 18 a .
- the individual conductive plugs are essentially self-aligned at and to the substrate at the same locations as are the contact openings in which each is formed.
- the illustrated conductive plugs are formed to preferably extend outwardly from outer surface 14 a distance which is greater than conductive runner height h. Because the plugs in this example are formed atop the same surface (outer surface 14 ) atop which the conductive lines are formed, each extends elevationally beyond the respective conductive line heights. Such plugs could, however, be formed to extend from outer surface 14 a distance which is less than or no further than the conductive runner height. This could, for example, be done by conducting a timed etch for a longer period of time than is suitable for forming the illustrated FIG. 6 plugs. An exemplary construction is shown in FIG. 7 .
- individual conductive plugs include portions which overlap with portions of conductive line 18 a and the respective next adjacent conductive lines 16 a , 20 a .
- the respective plugs overlap with the outermost surfaces of the conductive lines adjacent which each is formed. Accordingly, portions of at least one, and preferably both conductive plugs can overlap target area B.
- the conductive material of conductive plugs 56 , 58 , and the conductive material of conductive line 18 a define an effective contact pad having an outermost surface 60 , which defines an effectively widened target area A′. The widened target area reduces the wafer area which was formerly required by the prior art widened landing pad ( FIGS. 1 and 2 ) described above.
- effective contact pad outermost surface 60 defines a generally non-planar surface.
- at least one of the conductive plugs, and preferably both, define a region of outermost surface 60 having a higher topographical elevation than the region defined by the contact pad of line 18 a.
- a layer 62 of insulative material is formed over the substrate and the effective contact pad.
- a contact opening 64 is etched or otherwise formed through layer 62 to outwardly expose portions of the effective contact pad.
- the contact pad of line 18 a is exposed, with any mask misalignment resulting in exposure of conductive material of either or both of conductive plugs 56 , 58 .
- a second conductive material 66 is formed within contact opening 64 and in electrical communication with at least portions of the contact pad and, if exposed, an associated portion of a conductive plug.
- a bit line 68 can then be formed over the substrate and in electrical communication with material 66 .
- conductive lines 16 a , 18 a and 20 a have first respective line widths w 1 at respective first locations and second line widths w 2 at respective second locations, an exemplary second line width and location being shown for line 18 a .
- the second line width corresponds to a line location where at least a portion of contact opening 64 is formed.
- the first and second line widths are essentially the same or equivalent. This is made possible because the above-described conductive plugs 56 , 58 (shown in dashed lines in FIGS. 9 and 10 ) reduce, if not eliminate, the requirement of the FIG. 1 widened landing pad.
- the illustrated conductive plugs provide an effective contact pad width which is greater than second line width w 2 , and include respective portions proximate the first line width w 1 which overlap with or extend elevationally over the conductive portions, e.g. the contact pad, of line 18 a .
- the plugs can also include portions which overlap with corresponding portions of conductive lines 16 a , 20 a . This compensates for a contact opening mask misalignment by enabling desired contact to be made through a respective one of the conductive plugs as discussed above.
- first and second line widths w 1 , w 2 respectively are different with second line width w 2 being greater than first line width w 1 .
- the second line width defines a portion of a landing pad which is smaller in dimension than the FIG. 1 landing pad.
- Portions of conductive lines 16 b and 20 b laterally proximate respective conductive plugs 56 , 58 can be tapered or otherwise configured to accommodate the somewhat wider landing pad.
Abstract
Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed. In the former instance and in accordance with one aspect, such plug(s) can include a portion which overlaps with the contact pad of the associated conductive line.
Description
- This invention relates to semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry comprising such contact openings and electrical connections and interconnections.
- Referring to
FIGS. 1 and 2 , a semiconductor wafer fragment is indicated generally at 10 and comprises asemiconductive substrate 12. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.Substrate 12 comprises afield oxide region 13 having an outer surface 14 (FIG. 2 ) over which a plurality of conductive runners orconductive lines respective polysilicon layer 22 and anoverlying silicide layer 24. The insulative portions of the runners or lines are constituted by respectiveoverlying caps 26 and associatedsidewall spacers 28. Exemplary materials for the insulative portions include oxides and nitrides. - An
insulative layer 30 such as borophosphosilicate glass is formed overrunners contact opening 32 is formed through a masked etch oflayer 30 to outwardly expose a portion ofsilicide layer 24. Thereafter, conductive material such as conductively doped polysilicon is formed withincontact opening 32 to provide aconductive contact 34 toconductive line 18. Ametal layer 36 is provided thereover to form an electrical connection withconductive line 18. - A typical practice within the semiconductor industry is to provide a conductive line or runner with a widened landing pad in order to accommodate mask misalignments when contact openings are formed. An exemplary widened landing pad is shown in
FIGS. 1 and 2 at 38. By having a widened landing pad, contact opening 32 can shift left or right some distance relative to the position shown inFIGS. 1 and 2 without making undesirable contact with the substrate. For purposes of the ongoing discussion,landing pad 38 includes the conductive and insulative portions ofconductive line 18; and the conductive portions ofconductive line 18 define a contact pad with which electrical communication is desired. Accordingly, in the illustrated example a contact pad is defined bypolysilicon layer 22 andsilicide layer 24 ofconductive line 18. The contact pad defines a target area A inside of which it is desirable to form a contact opening. An electrical connection throughcontact opening 32 can be formed anywhere within target area A and still effectively make a desirable connection with the conductive contact pad. Hence, the target area tolerates a contact opening mask misalignment on either side of the illustrated and desiredcontact opening 32. A tradeoff for improved mask misalignment tolerance is a reduction in wafer real estate available for supporting conductive lines and other integrated circuitry components. This is due largely in part to the increased area which is occupied by the widenedlanding pad 38. This also adversely impacts the conductive line spacing such that desired minimum spacing adjacent conductive lines is not achieved. Hence, integrated circuitry cannot be packed as densely upon a wafer as is desirable when the widened landing pads are used. - This invention grew out of concerns associated with enhancing the efficiency with which wafer real estate is used to support integrated circuitry. This invention also grew out of concerns associated with improving the methods and structures through which contact is made relative to conductive lines.
- Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed. In the former instance and in accordance with one aspect, such plug(s) can include a portion which overlaps with the contact pad of the associated conductive line.
- Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
-
FIG. 1 is a top plan view of a prior art semiconductor wafer fragment and a plurality of conductive lines supported thereon. -
FIG. 2 is a view which is taken along line 2-2 inFIG. 1 at a subsequent processing step. -
FIG. 3 is a diagrammatic sectional view of a semiconductor wafer fragment at one processing step in accordance with one implementation of the invention. -
FIG. 4 is a view of theFIG. 3 wafer fragment at another processing step. -
FIG. 5 is a view of theFIG. 3 wafer fragment at another processing step. -
FIG. 6 is a view of theFIG. 3 wafer fragment at another processing step. -
FIG. 7 is a view which is similar to theFIG. 6 view, but which shows an alternate embodiment in accordance with another implementation of the invention. -
FIG. 8 is a view of theFIG. 3 wafer fragment at another processing step. -
FIGS. 9 and 10 are top plan views of semiconductor wafer fragments which have been processed in accordance with the inventive methodologies. - This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (
Article 1, Section 8). - Referring to
FIG. 3 , like numerals from the above-described embodiment are utilized where appropriate, with differences being indicated by the suffix “a” or with different numerals. Accordingly, a plurality of conductive runners orlines outer surface 14, and can be formed overoxide isolation regions 40. Exemplary isolation regions include shallow trench isolation regions or field oxide regions formed through LOCOS techniques. The conductive lines comprise respectiveoutermost surfaces 44 portions of which define respective conductive line heights h outwardly ofouter surface 14.Diffusion regions 42 can be provided between the conductive lines, and preferably comprise n-regions having doping concentrations of 1×1018 cm−3. The diffusion regions can be provided in a separate doping step, or through outdiffusion of dopant from conductive material which will become more apparent below. An outer contact opening target area B is defined byconductive line 18 a. - Referring to
FIG. 4 , aninsulating material layer 46 is formed oversubstrate 12. An exemplary material is borophosphosilicate glass. - Referring to
FIG. 5 , at least one, and preferably a pair ofcontact openings layer 46 and preferably outwardly expose respective portions ofouter surface 14. The contact openings can be formed through a suitable masked etch oflayer 46. Preferably, the individual contact openings are essentially self-aligned at and to the substrate at twolocations line 18 a. In a preferred implementation, one of the two locations for the individual contact openings is defined byconductive runner 18 a. Even more preferably, the other of the two respective locations are defined by respective next adjacentconductive lines - Referring to
FIG. 6 , and in accordance with a first implementation, firstconductive material contact openings conductive line 18 a. An exemplary and preferred first conductive material is conductively doped polysilicon, which can serve as a source of outdiffused dopant forregions 42. The polysilicon can be chemical vapor deposited over the substrate and subsequently removed through conventional processing to provideconductive plugs conductive line 18 a. It is possible, however, for only one conductive plug to be formed on either side ofconductive line 18 a. The individual conductive plugs are essentially self-aligned at and to the substrate at the same locations as are the contact openings in which each is formed. - Referring still to
FIG. 6 , the illustrated conductive plugs are formed to preferably extend outwardly from outer surface 14 a distance which is greater than conductive runner height h. Because the plugs in this example are formed atop the same surface (outer surface 14) atop which the conductive lines are formed, each extends elevationally beyond the respective conductive line heights. Such plugs could, however, be formed to extend from outer surface 14 a distance which is less than or no further than the conductive runner height. This could, for example, be done by conducting a timed etch for a longer period of time than is suitable for forming the illustratedFIG. 6 plugs. An exemplary construction is shown inFIG. 7 . - In one implementation, individual conductive plugs include portions which overlap with portions of
conductive line 18 a and the respective next adjacentconductive lines conductive plugs conductive line 18 a define an effective contact pad having anoutermost surface 60, which defines an effectively widened target area A′. The widened target area reduces the wafer area which was formerly required by the prior art widened landing pad (FIGS. 1 and 2 ) described above. - Alternately considered, effective contact pad
outermost surface 60 defines a generally non-planar surface. In a preferred implementation, at least one of the conductive plugs, and preferably both, define a region ofoutermost surface 60 having a higher topographical elevation than the region defined by the contact pad ofline 18 a. - Referring to
FIG. 8 , alayer 62 of insulative material is formed over the substrate and the effective contact pad. Acontact opening 64 is etched or otherwise formed throughlayer 62 to outwardly expose portions of the effective contact pad. Preferably, the contact pad ofline 18 a is exposed, with any mask misalignment resulting in exposure of conductive material of either or both ofconductive plugs conductive material 66 is formed withincontact opening 64 and in electrical communication with at least portions of the contact pad and, if exposed, an associated portion of a conductive plug. Abit line 68 can then be formed over the substrate and in electrical communication withmaterial 66. - Referring to
FIG. 9 ,conductive lines line 18 a. The second line width corresponds to a line location where at least a portion ofcontact opening 64 is formed. In one implementation, the first and second line widths are essentially the same or equivalent. This is made possible because the above-describedconductive plugs 56, 58 (shown in dashed lines inFIGS. 9 and 10 ) reduce, if not eliminate, the requirement of theFIG. 1 widened landing pad. The illustrated conductive plugs provide an effective contact pad width which is greater than second line width w2, and include respective portions proximate the first line width w1 which overlap with or extend elevationally over the conductive portions, e.g. the contact pad, ofline 18 a. The plugs can also include portions which overlap with corresponding portions ofconductive lines - Referring to
FIG. 10 and in accordance with another implementation, localized first and second line widths w1, w2 respectively, are different with second line width w2 being greater than first line width w1. In this example, the second line width defines a portion of a landing pad which is smaller in dimension than theFIG. 1 landing pad. Portions ofconductive lines conductive plugs - In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.
Claims (4)
1-51. (canceled)
52. Integrated circuitry comprising:
a semiconductive substrate having an outer surface;
a conductive line disposed over the outer surface and having a conductive portion which defines a contact pad with which electrical connection is desired;
at least one conductive plug disposed laterally proximate the contact pad and having a plug portion disposed elevationally over a portion of the contact pad; and
conductive material disposed over the contact pad and in electrical communication with at least a portion of the conductive plug.
53. Integrated circuitry comprising:
a semiconductive substrate having an outer surface;
a conductive line disposed over the outer surface and having a first line width at one location and a second line width which is different from the first line width at another location; at least a portion of the second line width defining a contact pad with which electrical connection is desired;
a conductive plug disposed laterally proximate the contact pad and defining therewith an effective contact pad having an effective contact pad width which is greater than the second line width; and
conductive material disposed over the effective contact pad and making electrical connection with at least a portion of the conductive plug.
54. Integrated circuitry comprising:
a semiconductive substrate having an outer surface;
a conductive line disposed over the outer surface and having a conductive line width and a target area with which electrical communication is desired;
a pair of conductive plugs disposed over the outer surface on either side of the conductive line laterally proximate the target area and self-aligned to the substrate adjacent the conductive line, the plugs and target area defining an effectively widened target area; and
conductive material disposed over and in electrical communication with at least a portion of the effectively widened target area which includes the conductive line target area.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/496,843 US20060273459A1 (en) | 1998-09-03 | 2006-07-31 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/146,840 US6242302B1 (en) | 1998-09-03 | 1998-09-03 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
US09/565,197 US6476490B1 (en) | 1998-09-03 | 2000-05-04 | Contact openings, electrical connections and interconnections for integrated circuitry |
US10/268,737 US7291917B2 (en) | 1998-09-03 | 2002-10-09 | Integrated circuitry |
US11/218,004 US20060014379A1 (en) | 1998-09-03 | 2005-09-01 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
US11/496,843 US20060273459A1 (en) | 1998-09-03 | 2006-07-31 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
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US11/218,004 Division US20060014379A1 (en) | 1998-09-03 | 2005-09-01 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
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US09/565,197 Expired - Lifetime US6476490B1 (en) | 1998-09-03 | 2000-05-04 | Contact openings, electrical connections and interconnections for integrated circuitry |
US09/565,196 Expired - Fee Related US6323087B1 (en) | 1998-09-03 | 2000-05-04 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
US09/808,886 Expired - Lifetime US6468883B2 (en) | 1998-09-03 | 2001-03-14 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections |
US09/956,274 Expired - Fee Related US6753241B2 (en) | 1998-09-03 | 2001-09-18 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
US10/244,122 Expired - Lifetime US6855628B2 (en) | 1998-09-03 | 2002-09-12 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
US10/268,737 Expired - Fee Related US7291917B2 (en) | 1998-09-03 | 2002-10-09 | Integrated circuitry |
US11/218,004 Abandoned US20060014379A1 (en) | 1998-09-03 | 2005-09-01 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
US11/496,843 Abandoned US20060273459A1 (en) | 1998-09-03 | 2006-07-31 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
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US09/146,840 Expired - Lifetime US6242302B1 (en) | 1998-09-03 | 1998-09-03 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
US09/565,197 Expired - Lifetime US6476490B1 (en) | 1998-09-03 | 2000-05-04 | Contact openings, electrical connections and interconnections for integrated circuitry |
US09/565,196 Expired - Fee Related US6323087B1 (en) | 1998-09-03 | 2000-05-04 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
US09/808,886 Expired - Lifetime US6468883B2 (en) | 1998-09-03 | 2001-03-14 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections |
US09/956,274 Expired - Fee Related US6753241B2 (en) | 1998-09-03 | 2001-09-18 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
US10/244,122 Expired - Lifetime US6855628B2 (en) | 1998-09-03 | 2002-09-12 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
US10/268,737 Expired - Fee Related US7291917B2 (en) | 1998-09-03 | 2002-10-09 | Integrated circuitry |
US11/218,004 Abandoned US20060014379A1 (en) | 1998-09-03 | 2005-09-01 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
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US (9) | US6242302B1 (en) |
JP (1) | JP3703081B2 (en) |
KR (1) | KR100417891B1 (en) |
AU (1) | AU5682499A (en) |
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WO (1) | WO2000014792A1 (en) |
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US7271489B2 (en) * | 2003-10-15 | 2007-09-18 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
KR100408414B1 (en) * | 2001-06-20 | 2003-12-06 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
US6784076B2 (en) * | 2002-04-08 | 2004-08-31 | Micron Technology, Inc. | Process for making a silicon-on-insulator ledge by implanting ions from silicon source |
KR100445638B1 (en) * | 2002-07-26 | 2004-08-25 | 삼성전자주식회사 | Interconnection structure connecting electrically isolated regions and method of fabricatinging the same |
US6831006B2 (en) * | 2003-01-15 | 2004-12-14 | International Business Machines Corporation | Structure and method for eliminating metal contact to P-well or N-well shorts or high leakage paths using polysilicon liner |
US7126200B2 (en) * | 2003-02-18 | 2006-10-24 | Micron Technology, Inc. | Integrated circuits with contemporaneously formed array electrodes and logic interconnects |
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US20060228862A1 (en) * | 2005-04-06 | 2006-10-12 | International Business Machines Corporation | Fet design with long gate and dense pitch |
US7528065B2 (en) * | 2006-01-17 | 2009-05-05 | International Business Machines Corporation | Structure and method for MOSFET gate electrode landing pad |
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US20010010969A1 (en) | 2001-08-02 |
US20030054621A1 (en) | 2003-03-20 |
US6753241B2 (en) | 2004-06-22 |
JP3703081B2 (en) | 2005-10-05 |
US6476490B1 (en) | 2002-11-05 |
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US20020013047A1 (en) | 2002-01-31 |
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AU5682499A (en) | 2000-03-27 |
US6855628B2 (en) | 2005-02-15 |
US6323087B1 (en) | 2001-11-27 |
US20030089989A1 (en) | 2003-05-15 |
US7291917B2 (en) | 2007-11-06 |
TW429580B (en) | 2001-04-11 |
JP2002524875A (en) | 2002-08-06 |
KR100417891B1 (en) | 2004-02-11 |
WO2000014792A1 (en) | 2000-03-16 |
KR20010073109A (en) | 2001-07-31 |
US6242302B1 (en) | 2001-06-05 |
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