US20070013065A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US20070013065A1
US20070013065A1 US11/449,796 US44979606A US2007013065A1 US 20070013065 A1 US20070013065 A1 US 20070013065A1 US 44979606 A US44979606 A US 44979606A US 2007013065 A1 US2007013065 A1 US 2007013065A1
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Prior art keywords
conductive layer
semiconductor device
layer
electrode pad
width
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US11/449,796
Inventor
Takeshi Yuzawa
Masatoshi Tagaki
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Seiko Epson Corp
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Seiko Epson Corp
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Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Assigned to SEIKO EPSON CORPORATION reassignment SEIKO EPSON CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TAGAKI, MASATOSHI, YUZAWA, TAKESHI
Publication of US20070013065A1 publication Critical patent/US20070013065A1/en
Priority to US13/273,613 priority Critical patent/US8878365B2/en
Priority to US14/467,548 priority patent/US20140361433A1/en
Abandoned legal-status Critical Current

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Definitions

  • the present invention relates to a semiconductor device.
  • the characteristics of a semiconductor element e.g. MIS transistor
  • a conductive layer e.g. interconnect
  • a semiconductor device comprising:
  • a first conductive layer formed above the semiconductor layer and having a first width
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width
  • connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad;
  • connection section a reinforcing section being provided at the connection section.
  • a semiconductor device comprising:
  • a first conductive layer formed above the semiconductor layer and having a first width
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width
  • connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned outward from a line extending vertically downward from an edge of at least part of the electrode pad;
  • connection section a reinforcing section being provided at the connection section.
  • a semiconductor device comprising:
  • a first conductive layer formed above the semiconductor layer and having a first width
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width
  • connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned inward from a line extending vertically downward from an edge of the bump;
  • connection section a reinforcing section being provided at the connection section.
  • a semiconductor device comprising:
  • a first conductive layer formed above the semiconductor layer and having a first width
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width
  • a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad;
  • connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned inward and outward from a line extending vertically downward from an edge of at least part of the bump;
  • connection section a reinforcing section being provided at the connection section.
  • FIG. 1 is a view illustrative of a semiconductor device according to a first embodiment.
  • FIG. 2 is a view illustrative of a semiconductor device according to the first embodiment.
  • FIG. 3 is a view illustrative of a semiconductor device according to a second embodiment.
  • FIG. 4 is a view illustrative of a semiconductor device according to the second embodiment.
  • FIG. 5 is a view illustrative of a semiconductor device according to a third embodiment.
  • FIG. 6 is a view illustrative of a semiconductor device according to the third embodiment.
  • FIG. 7 is a view illustrative of a semiconductor device according to a fourth embodiment.
  • FIG. 8 is a view illustrative of a semiconductor device according to the fourth embodiment.
  • FIGS. 9A and 9B are views showing examples of a bent conductive layer in the shape of the letter “T” or “L”.
  • FIGS. 10A and 10B are views showing other examples of a bent conductive layer in the shape of the letter “T” or “L”.
  • FIGS. 11A and 11B are views illustrative of a semiconductor device according to a modification of the second and fourth embodiments.
  • FIG. 12 is a view illustrative of a semiconductor device according to a modification.
  • the invention may provide a highly reliable semiconductor device in which a conductive layer can be formed under an electrode pad or a bump.
  • a semiconductor device comprising:
  • a first conductive layer formed above the semiconductor layer and having a first width
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width
  • connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad;
  • connection section a reinforcing section being provided at the connection section.
  • a specific layer B (hereinafter called “layer B”) formed above a specific layer A (hereinafter called “layer A”)” includes the case where the layer B is directly formed on the layer A and the case where the layer B is formed on the layer A through another layer.
  • a semiconductor device comprising:
  • a first conductive layer formed above the semiconductor layer and having a first width
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width
  • connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned outward from a line extending vertically downward from an edge of at least part of the electrode pad;
  • connection section a reinforcing section being provided at the connection section.
  • the electrode pad may have a rectangular shape having a short side and a long side
  • the reinforcing section may be provided at the connection section provided in a specific region positioned outward from a line extending vertically downward from an edge of the short side of the electrode pad.
  • the semiconductor device may comprise:
  • a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad
  • the specific region is a region having a width corresponding to a thickness of the passivation layer outward from a line extending vertically downward from the edge.
  • the semiconductor device may comprise:
  • a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad
  • the specific region is a region having a width of 1.0 to 2.5 micrometers outward from a line extending vertically downward from the edge.
  • the semiconductor device may comprise a bump formed in the opening.
  • a semiconductor device comprising:
  • a first conductive layer formed above the semiconductor layer and having a first width
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width
  • a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad;
  • connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned inward from a line extending vertically downward from an edge of the bump;
  • connection section a reinforcing section being provided at the connection section.
  • a semiconductor device comprising:
  • a first conductive layer formed above the semiconductor layer and having a first width
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width
  • a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad;
  • connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned inward and outward from a line extending vertically downward from an edge of at least part of the bump;
  • connection section a reinforcing section being provided at the connection section.
  • the bump may have a rectangular shape having a short side and a long side;
  • the reinforcing section may be provided at the connection section provided in a specific region positioned inward and outward from a line extending vertically downward from an edge of the short side of the bump.
  • the specific region may be a region having a width of 2.0 to 3.0 micrometers outward from a line extending vertically downward from the edge and having a width of 2.0 to 3.0 micrometers inward from a line extending vertically downward from the edge.
  • the first conductive layer and the second conductive layer may be connected in a shape of the letter “T” or “L”.
  • the reinforcing section may be formed by a third conductive layer protruding from the first conductive layer and the second conductive layer.
  • the first conductive layer, the second conductive layer, and the third conductive layer may be polysilicon layers.
  • FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment of the invention
  • FIG. 2 is a plan view schematically showing the relationship between an electrode pad and a conductive layer in the semiconductor device according to the first embodiment.
  • FIG. 1 is a cross-sectional view along the line X-X shown in FIG. 2 .
  • the semiconductor device includes a semiconductor layer 10 .
  • a semiconductor layer 10 a single crystal silicon substrate, a silicon on insulator (SOI) substrate in which a semiconductor layer is formed on an insulating layer, the semiconductor layer being a silicon layer, a germanium layer, or a silicon germanium layer, or the like may be used.
  • SOI silicon on insulator
  • a conductive layer 14 is formed on the semiconductor layer 10 .
  • the conductive layer 14 is an interconnect in the shape of the letter “T”.
  • the conductive layer 14 includes a first conductive layer 14 a having a first width, and a second conductive layer 14 b connected with the first conductive layer 14 a and having a second width smaller than the first width.
  • a reinforcing section 14 c is provided at a boundary 30 (hereinafter also called “connection section”) at which the first conductive layer 14 a and the second conductive layer 14 b are connected.
  • connection section As the material for the conductive layer 14 , polysilicon, aluminum, an aluminum alloy, or the like may be used.
  • a metal insulator semiconductor (MIS) transistor (not shown) is formed on the semiconductor layer 10 .
  • the conductive layer 14 may be electrically connected with the MIS transistor.
  • An interlayer dielectric 50 provided to cover the conductive layer 14 and an interlayer dielectric 60 are formed over the conductive layer 14 in that order.
  • the interlayer dielectric 50 and the interlayer dielectric 60 may be formed using a known material.
  • An interconnect layer 52 having a specific pattern is formed on the interlayer dielectric 50 .
  • An electrode pad 62 is formed on the interlayer dielectric 60 .
  • the electrode pad 62 may be electrically connected with the interconnect layer 52 through a contact layer 64 .
  • the electrode pad 62 may be formed of a metal such as aluminum or copper.
  • the semiconductor device according to the first embodiment further includes a passivation layer 70 .
  • An opening 72 which exposes at least part of the electrode pad 62 is formed in the passivation layer 70 .
  • the opening 72 may be formed to expose only the center region of the electrode pad 62 .
  • the passivation layer 70 may be formed to cover the edge portion of the electrode pad 62 .
  • the passivation layer may be formed of SiO 2 , SiN, a polyimide resin, or the like.
  • the term “electrode pad” refers to a region which includes the region in which the opening 72 is formed and has a width greater than that of the interconnect section.
  • a bump 80 is formed at least in the opening 72 .
  • the bump 80 is formed on the exposed surface of the electrode pad 62 .
  • the bump 80 is also formed on the passivation layer 70 .
  • the bump 80 may include one or more layers and may be formed of a metal such as gold, nickel, or copper.
  • the external shape of the bump 80 is not particularly limited.
  • the external shape of the bump 80 may be a quadrilateral (including square and rectangle) or a circle.
  • the external shape of the bump 80 may cover less area than that of the electrode pad 62 . In this case, the bump 80 may be formed only in the area in which the bump 80 overlaps the electrode pad 62 .
  • a barrier layer (not shown) may be formed in the lowermost layer of the bump 80 .
  • the barrier layer prevents diffusion between the electrode pad 62 and the bump 80 .
  • the barrier layer may include one or more layers.
  • the barrier layer may be formed by sputtering.
  • the barrier layer may have a function of increasing the adhesion between the electrode pad 62 and the bump 80 .
  • the barrier layer may include a titanium tungsten (TiW) layer.
  • the outermost surface of the barrier layer may be an electroplating feed metal layer (e.g. Au layer) for depositing the bump 80 .
  • a region 12 is described below.
  • the region 12 is a region within a specific range positioned inward from a line extending vertically downward from the edge of the electrode pad 62 .
  • the T-shaped conductive layer 14 includes the first conductive layer 14 a extending in a direction X, the second conductive layer 14 b which branches in a direction Y from the first conductive layer 14 a , and the reinforcing section 14 c formed in the base section of the second conductive layer 14 b , for example.
  • the reinforcing section 14 c is formed by a conductive layer protruding from the first conductive layer 14 a and the second conductive layer 14 b .
  • the T-shaped bent conductive layer 14 may include the reinforcing section 14 c having a stepwise planar shape. Note that the shape of the reinforcing section 14 c is not limited to the above examples. The reinforcing section 14 c may have an arbitrary shape insofar as the reinforcement effect for the conductive layer can be achieved.
  • the conductive layer 14 when the conductive layer 14 is in the shape of the letter “L”, the conductive layer 14 includes the first conductive layer 14 a extending in the direction X, the second conductive layer 14 b extending in the direction Y from the end of the first conductive layer 14 a , and the reinforcing section 14 c formed in the base section of the second conductive layer 14 b .
  • the reinforcing section 14 c is formed by a conductive layer protruding from the first conductive layer 14 a and the second conductive layer 14 b .
  • the L-shaped bent conductive layer 14 when the second conductive layer 14 b has a width smaller than the first conductive layer 14 a , defects such as cracks tend to occur near the boundary between the first conductive layer 14 a and the second conductive layer 14 b due to mechanical and thermal stress during mounting. However, such defects are prevented from occurring by providing the reinforcing section 14 c .
  • the L-shaped bent conductive layer 14 may include the reinforcing section 14 c having a stepwise shape. Note that the shape of the reinforcing section 14 c is not limited to the above examples.
  • the reinforcing section 14 c may have an arbitrary shape insofar as the reinforcement effect can be achieved.
  • the region 12 may be the region inward from a line extending vertically downward from the edge of the electrode pad 62 .
  • the range of the region 12 is specified as described above for the following reasons.
  • the electrode pad 62 When the electrode pad 62 is formed, stress occurs in the interlayer dielectric 60 at a position in which the edge of the electrode pad 62 is positioned.
  • the bump 80 When the bump 80 is formed on the electrode pad 62 , a continuous stress additionally occurs due to the internal stress of the bump 80 .
  • the stress may cause cracks to occur in the interlayer dielectrics 50 and 60 from the position (edge of the electrode pad 62 ) at which the stress occurs. Such cracks may reach the lowermost interlayer dielectric. For example, when a conductive layer is formed in such a region, defects such as cracks may occur in the conductive layer.
  • the range of the region 12 is not limited to the first layer, but may be applied to a conductive layer formed in the second or higher layer, for example.
  • the semiconductor device allows the T-shaped or L-shaped bent conductive layer exhibiting mechanical strength to be formed as the conductive layer in the region 12 , whereby the degrees of freedom of the wiring pattern design can be increased.
  • FIG. 3 is a cross-sectional view schematically showing a semiconductor device according to a second embodiment of the invention
  • FIG. 4 is a plan view schematically showing the relationship between an electrode pad and a conductive layer in the semiconductor device according to the second embodiment.
  • FIG. 3 is a cross-sectional view along the line X-X shown in FIG. 4 .
  • the second embodiment differs from the first embodiment as to the position of the region 12 .
  • members substantially the same as the members of the semiconductor device according to the first embodiment are assigned the same symbols. Detailed description of these members is omitted.
  • the semiconductor device includes the semiconductor layer 10 .
  • the conductive layer 14 is formed on the semiconductor layer 10 .
  • the conductive layer 14 is an interconnect in the shape of the letter “T”.
  • the conductive layer 14 includes the first conductive layer 14 a having the first width, and the second conductive layer 14 b connected with the first conductive layer 14 a and having the second width smaller than the first width.
  • the reinforcing section 14 c is provided at the boundary 30 (hereinafter also called “connection section”) at which the first conductive layer 14 a and the second conductive layer 14 b are connected.
  • As the material for the conductive layer 14 polysilicon, aluminum, an aluminum alloy, or the like may be used.
  • a metal insulator semiconductor (MIS) transistor (not shown) is formed on the semiconductor layer 10 .
  • the conductive layer 14 may be electrically connected with the MIS transistor.
  • the interlayer dielectric 50 provided to cover the conductive layer 14 and the interlayer dielectric 60 are formed over the conductive layer 14 in that order.
  • the interlayer dielectric 50 and the interlayer dielectric 60 may be formed using a known material.
  • the interconnect layer 52 having a specific pattern is formed on the interlayer dielectric 50 .
  • the electrode pad 62 is formed on the interlayer dielectric 60 .
  • the electrode pad 62 may be electrically connected with the interconnect layer 52 through the contact layer 64 .
  • the semiconductor device according to the first embodiment further includes the passivation layer 70 .
  • the opening 72 which exposes at least part of the electrode pad 62 is formed in the passivation layer 70 .
  • the bump 80 is formed at least in the opening 72 . Specifically, the bump 80 is formed on the exposed surface of the electrode pad 62 . The bump 80 is formed to reach the portion on the passivation layer 70 .
  • the region 12 is described below.
  • the region 12 is a region within a specific range positioned outward from a line extending vertically downward from the edge of the electrode pad 62 .
  • connection section 30 of the T-shaped conductive layer 14 When the connection section 30 of the T-shaped conductive layer 14 is disposed in the region 12 , the reinforcing section 14 c is provided at the connection section 30 .
  • the conductive layer 14 may be in the shape of the letter “T” or “L” similar to that described in the first embodiment. Since the conductive layer 14 includes the reinforcing section 14 c , defects such as cracks due to mechanical and thermal stress during mounting rarely occur near the boundary between the first conductive layer 14 a and the second conductive layer 14 b.
  • the region 12 may be the range having a width corresponding to the thickness of the passivation layer 70 outward (in the direction away from the opening 72 ) from a line extending vertically downward from the edge of the electrode pad 62 .
  • the region 12 may be the range having a width of 1.0 to 2.5 micrometers outward from the edge of the electrode pad 62 .
  • the range of the region 12 is specified as described above for the following reasons.
  • the electrode pad 62 When the electrode pad 62 is formed, stress occurs in the interlayer dielectric 60 at a position in which the edge of the electrode pad 62 is positioned.
  • the bump 80 When the bump 80 is formed on the electrode pad 62 , a continuous stress additionally occurs due to the internal stress of the bump 80 .
  • the stress may cause cracks to occur in the interlayer dielectrics 50 and 60 from the position (edge of the electrode pad 62 ) at which the stress occurs. Such cracks may reach the lowermost interlayer dielectric. For example, when a conductive layer is formed in such a region, defects such as cracks may occur in the conductive layer.
  • the passivation layer 70 is not formed on a surface having a uniform height. That is, the passivation layer 70 may have a surface having a level difference corresponding to the shape of the electrode pad 62 .
  • the passivation layer 70 may have a surface having a level difference corresponding to the shape of the electrode pad 62 .
  • COF chip-on-film
  • stress due to contact and bonding tends to be concentrated in the region in which the level difference is formed when connecting the bump 80 through a connection line (lead wire) formed on a film. This may also cause cracks to occur in the interlayer dielectrics 50 and 60 .
  • the level difference is generally formed in the area having a width approximately corresponding to the thickness of the passivation layer 70 outward from the edge of the electrode pad 62 .
  • the range of the region 12 may be specified taking these problems into consideration.
  • the range of the region 12 is not limited to the first layer, but may be applied to a conductive layer formed in the second or higher layer, for example.
  • the region 12 may be the region within a specific range positioned outward from a line extending vertically downward from the edge of at least part of the electrode pad 62 .
  • the semiconductor device allows the T-shaped or L-shaped bent conductive layer exhibiting mechanical strength to be formed as the conductive layer in the region 12 , whereby the degrees of freedom of the wiring pattern design can be increased.
  • FIG. 5 is a cross-sectional view schematically showing a semiconductor device according to a third embodiment of the invention
  • FIG. 6 is a plan view schematically showing the relationship between a bump and a conductive layer in the semiconductor device according to the third embodiment.
  • FIG. 5 is a cross-sectional view along the line X-X shown in FIG. 6 .
  • the third embodiment differs from the first and second embodiments as to the position of the region 12 .
  • members substantially the same as the members of the semiconductor device according to the first embodiment are assigned the same symbols. Detailed description of these members is omitted.
  • the semiconductor device includes the semiconductor layer 10 .
  • the conductive layer 14 is formed on the semiconductor layer 10 .
  • the conductive layer 14 is an interconnect in the shape of the letter “T”.
  • the conductive layer 14 includes the first conductive layer 14 a having the first width, and the second conductive layer 14 b connected with the first conductive layer 14 a and having the second width smaller than the first width.
  • the reinforcing section 14 c is provided at the boundary 30 (hereinafter also called “connection section”) at which the first conductive layer 14 a and the second conductive layer 14 b are connected.
  • As the material for the conductive layer 14 polysilicon, aluminum, an aluminum alloy, or the like may be used.
  • a metal insulator semiconductor (MIS) transistor (not shown) is formed on the semiconductor layer 10 .
  • the conductive layer 14 may be electrically connected with the MIS transistor.
  • the interlayer dielectric 50 provided to cover the conductive layer 14 and the interlayer dielectric 60 are formed over the conductive layer 14 in that order.
  • the interlayer dielectric 50 and the interlayer dielectric 60 may be formed using a known material.
  • the interconnect layer 52 having a specific pattern is formed on the interlayer dielectric 50 .
  • the electrode pad 62 is formed on the interlayer dielectric 60 .
  • the electrode pad 62 may be electrically connected with the interconnect layer 52 through the contact layer 64 .
  • the semiconductor device according to the first embodiment further includes the passivation layer 70 .
  • the opening 72 which exposes at least part of the electrode pad 62 is formed in the passivation layer 70 .
  • the bump 80 is formed at least in the opening 72 . Specifically, the bump 80 is formed on the exposed surface of the electrode pad 62 . In the semiconductor device according to the first embodiment shown in FIG. 1 , the bump 80 is also formed on the passivation layer 70 .
  • the region 12 is described below.
  • the region 12 is a region within a specific range positioned inward from a line extending vertically downward from the edge of the bump 80 .
  • connection section 30 of the T-shaped conductive layer 14 When the connection section 30 of the T-shaped conductive layer 14 is disposed in the region 12 , the reinforcing section 14 c is provided at the connection section 30 .
  • the conductive layer 14 may be in the shape of the letter “T” or “L” similar to that described in the first embodiment. Since the conductive layer 14 includes the reinforcing section 14 c , defects such as cracks due to mechanical and thermal stress during mounting rarely occur near the boundary between the first conductive layer 14 a and the second conductive layer 14 b.
  • the region 12 may be the region inward from a line extending vertically downward from the edge of the bump 80 .
  • the range of the region 12 is specified as described above for the following reasons.
  • the electrode pad 62 When the electrode pad 62 is formed, stress occurs in the interlayer dielectric 60 at a position at which the edge of the electrode pad 62 is positioned.
  • the bump 80 When the bump 80 is formed on the electrode pad 62 , as shown in FIG. 5 , a continuous stress additionally occurs due to the internal stress of the bump 80 .
  • the stress may cause cracks to occur in the interlayer dielectrics 50 and 60 from the position (edge of the electrode pad 62 ) at which the stress occurs. Such cracks may reach the lowermost interlayer dielectric. For example, when a conductive layer is formed in such a region, defects such as cracks may occur in the conductive layer.
  • the range of the region 12 is not limited to the first layer, but may be applied to a conductive layer formed in the second or higher layer, for example.
  • the region 12 may be the region within a specific range positioned outward from a line extending vertically downward from the edge of at least part of the electrode pad 62 .
  • the semiconductor device allows the T-shaped or L-shaped bent conductive layer exhibiting mechanical strength to be formed as the conductive layer in the region 12 , whereby the degrees of freedom of the wiring pattern design can be increased.
  • FIG. 7 is a cross-sectional view schematically showing a semiconductor device according to a fourth embodiment of the invention
  • FIG. 8 is a plan view schematically showing the relationship between a bump and a conductive layer in the semiconductor device according to the fourth embodiment.
  • FIG. 7 is a cross-sectional view along the line X-X shown in FIG. 8 .
  • the fourth embodiment differs from the first to third embodiments as to the position of the region 12 .
  • members substantially the same as the members of the semiconductor device according to the first embodiment are assigned the same symbols. Detailed description of these members is omitted.
  • the semiconductor device includes the semiconductor layer 10 .
  • the conductive layer 14 is formed on the semiconductor layer 10 .
  • the conductive layer 14 is an interconnect in the shape of the letter “T”.
  • the conductive layer 14 includes the first conductive layer 14 a having the first width, and the second conductive layer 14 b connected with the first conductive layer 14 a and having the second width smaller than the first width.
  • the reinforcing section 14 c is provided at the boundary 30 (hereinafter also called “connection section”) at which the first conductive layer 14 a and the second conductive layer 14 b are connected.
  • As the material for the conductive layer 14 polysilicon, aluminum, an aluminum alloy, or the like may be used.
  • a metal insulator semiconductor (MIS) transistor (not shown) is formed on the semiconductor layer 10 .
  • the conductive layer 14 may be electrically connected with the MIS transistor.
  • the interlayer dielectric 50 provided to cover the conductive layer 14 and the interlayer dielectric 60 are formed over the conductive layer 14 in that order.
  • the interlayer dielectric 50 and the interlayer dielectric 60 may be formed using a known material.
  • the interconnect layer 52 having a specific pattern is formed on the interlayer dielectric 50 .
  • the electrode pad 62 is formed on the interlayer dielectric 60 .
  • the electrode pad 62 may be electrically connected with the interconnect layer 52 through the contact layer 64 .
  • the semiconductor device according to the fourth embodiment further includes the passivation layer 70 .
  • the opening 72 which exposes at least part of the electrode pad 62 is formed in the passivation layer 70 .
  • the bump 80 is formed at least in the opening 72 . Specifically, the bump 80 is formed on the exposed surface of the electrode pad 62 . In the semiconductor device according to the first embodiment shown in FIG. 1 , the bump 80 is also formed on the passivation layer 70 .
  • the region 12 is described below.
  • the region 12 is a region within a specific range positioned inward and outward from a line extending vertically downward from the edge of the bump 80 .
  • connection section 30 of the T-shaped conductive layer 14 When the connection section 30 of the T-shaped conductive layer 14 is disposed in the region 12 , the reinforcing section 14 c is provided at the connection section 30 .
  • the conductive layer 14 may be in the shape of the letter “T” or “L” similar to that described in the first embodiment. Since the conductive layer 14 includes the reinforcing section 14 c , defects such as cracks due to mechanical and thermal stress during mounting rarely occur near the boundary between the first conductive layer 14 a and the second conductive layer 14 b.
  • the region 12 may be the range having a width of 2.0 to 3.0 micrometers outward (in the direction away from the opening 72 ) from a line extending vertically downward from the edge of the bump 80 and having a width of 2.0 to 3.0 micrometers inward (in the direction toward the opening 72 ) from the a line extending vertically downward from the edge of the bump 80 .
  • the range of the region 12 is specified as described above for the following reasons.
  • Stress occurs near the edge of the bump 80 during the formation process of the bump 80 . After the bump 80 has been formed, stress continuously occurs near the edge of the bump 80 due to the internal stress of the bump 80 .
  • the stress may cause cracks to occur in the interlayer dielectrics 50 and 60 from the position at which the stress occurs. Such cracks may reach the lowermost interlayer dielectric, whereby defects such as cracks may occur in the conductive layer formed in such a region.
  • the range of the region 12 is not limited to the first layer, but may be applied to a conductive layer formed in the second or higher layer, for example.
  • the region 12 may be the region within a specific range positioned outward from a line extending vertically downward from the edge of at least part of the electrode pad 62 .
  • the semiconductor device allows the T-shaped or L-shaped bent conductive layer exhibiting mechanical strength to be formed as the conductive layer in the region 12 , whereby the degrees of freedom of the wiring pattern design can be increased.
  • FIGS. 11A and 11B are plan views schematically showing the positional relationship among the bump 80 , the electrode pad 62 , and the region 12 .
  • the following description merely illustrates the difference from the semiconductor devices according to the second embodiment and the fourth embodiment.
  • the bump 80 is formed in the opening 72 on the electrode pad 62 , as shown in FIGS. 3 and 7 .
  • the electrode pad 62 has a rectangular shape.
  • the opening 72 is formed on part of the upper surface of the electrode pad 62
  • the bump 80 is formed in the opening 72 .
  • the bump 80 has a planar shape smaller in area than that of the electrode pad 62 . As shown in FIGS. 11A and 11B , it is preferable that the bump 80 be provided inside the electrode pad 62 when viewed from the top side.
  • a first modification is a modification relating to the second embodiment.
  • the region 12 is provided in the region positioned outward from a line extending vertically downward from the edge of the short side of the electrode pad 62 , as shown in FIG. 11A .
  • This configuration has the following advantage when mounting the semiconductor device by tape automated bonding (TAB) technology provided that the extension direction of a connection line (lead wire) formed on a film made of a polyimide resin or the like is the direction along the long side of the electrode pad 62 . In this case, the electrode pad 62 is pulled in the extension direction of the connection line, whereby stress occurs on the short side of the electrode pad 62 .
  • TAB tape automated bonding
  • a second modification is a modification relating to the fourth embodiment.
  • the region 12 is provided in the region positioned inward and outward from a line extending vertically downward from the edge of the short side of the bump 80 , as shown in FIG. 11B .
  • a structure may be required in which the opening 72 and the bump 80 are formed in a rectangular planar shape to provide a number of openings 72 .
  • a semiconductor device which is scaled down and provided with improved reliability can be provided by providing the region 12 in an appropriate region of the semiconductor device having such rectangular electrode pads 62 (bumps 80 ).
  • the above embodiments illustrate the case where two interlayer dielectrics 50 and 60 are provided and one interconnect layer 52 is provided between the interlayer dielectrics 50 and 60 . Note that the above embodiments are not limited thereto. A structure may also be employed in which three or more interlayer dielectrics are stacked and interconnect layers in a number corresponding to the number of interlayer dielectrics are provided.
  • the invention includes various other configurations substantially the same as the configurations described in the embodiments (in function, method and result, or in objective and result, for example).
  • the invention also includes a configuration in which an unsubstantial portion in the described embodiments is replaced.
  • the invention also includes a configuration having the same effects as the configurations described in the embodiments, or a configuration able to achieve the same objective.
  • the invention includes a configuration in which a publicly known technique is added to the configurations in the embodiments.

Abstract

A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; and an electrode pad formed above the interlayer dielectric. A connection section at which the first conductive layer and the second conductive layer are connected is disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and a reinforcing section is provided at the connection section.

Description

  • Japanese Patent Application No. 2005-204521, filed on Jul. 13, 2005, is hereby incorporated by reference in its entirety.
    • BACKGROUND OF THE INVENTION
  • The present invention relates to a semiconductor device.
  • In general, the characteristics of a semiconductor element (e.g. MIS transistor) and a conductive layer (e.g. interconnect) under a pad or a bump may be impaired due to stress during bonding or residual stress of the bump.
    • SUMMARY
  • According to a first aspect of the invention, there is provided a semiconductor device, comprising:
  • a semiconductor layer;
  • a first conductive layer formed above the semiconductor layer and having a first width;
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width;
  • an interlayer dielectric formed above the first conductive layer and the second conductive layer; and
  • an electrode pad formed above the interlayer dielectric,
  • a connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and
  • a reinforcing section being provided at the connection section.
  • According to a second aspect of the invention, there is provided a semiconductor device, comprising:
  • a semiconductor layer;
  • a first conductive layer formed above the semiconductor layer and having a first width;
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width;
  • an interlayer dielectric formed above the first conductive layer and the second conductive layer; and
  • an electrode pad formed above the interlayer dielectric,
  • a connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned outward from a line extending vertically downward from an edge of at least part of the electrode pad; and
  • a reinforcing section being provided at the connection section.
  • According to a third aspect of the invention, there is provided a semiconductor device, comprising:
  • a semiconductor layer;
  • a first conductive layer formed above the semiconductor layer and having a first width;
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width;
  • an interlayer dielectric formed above the first conductive layer and the second conductive layer;
  • an electrode pad formed above the interlayer dielectric, a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad; and
  • a bump formed in the opening,
  • a connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned inward from a line extending vertically downward from an edge of the bump; and
  • a reinforcing section being provided at the connection section.
  • According to a fourth aspect of the invention, there is provided a semiconductor device, comprising:
  • a semiconductor layer;
  • a first conductive layer formed above the semiconductor layer and having a first width;
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width;
  • an interlayer dielectric formed above the first conductive layer and the second conductive layer;
  • an electrode pad formed above the interlayer dielectric,
  • a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad; and
  • a bump formed in the opening,
  • a connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned inward and outward from a line extending vertically downward from an edge of at least part of the bump; and
  • a reinforcing section being provided at the connection section.
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
  • FIG. 1 is a view illustrative of a semiconductor device according to a first embodiment.
  • FIG. 2 is a view illustrative of a semiconductor device according to the first embodiment.
  • FIG. 3 is a view illustrative of a semiconductor device according to a second embodiment.
  • FIG. 4 is a view illustrative of a semiconductor device according to the second embodiment.
  • FIG. 5 is a view illustrative of a semiconductor device according to a third embodiment.
  • FIG. 6 is a view illustrative of a semiconductor device according to the third embodiment.
  • FIG. 7 is a view illustrative of a semiconductor device according to a fourth embodiment.
  • FIG. 8 is a view illustrative of a semiconductor device according to the fourth embodiment.
  • FIGS. 9A and 9B are views showing examples of a bent conductive layer in the shape of the letter “T” or “L”.
  • FIGS. 10A and 10B are views showing other examples of a bent conductive layer in the shape of the letter “T” or “L”.
  • FIGS. 11A and 11B are views illustrative of a semiconductor device according to a modification of the second and fourth embodiments.
  • FIG. 12 is a view illustrative of a semiconductor device according to a modification.
    • DETAILED DESCRIPTION OF THE EMBODIMENT
  • The invention may provide a highly reliable semiconductor device in which a conductive layer can be formed under an electrode pad or a bump.
  • (1) According to one embodiment of the invention, there is provided a semiconductor device, comprising:
  • a semiconductor layer;
  • a first conductive layer formed above the semiconductor layer and having a first width;
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width;
  • an interlayer dielectric formed above the first conductive layer and the second conductive layer; and
  • an electrode pad formed above the interlayer dielectric,
  • a connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and
  • a reinforcing section being provided at the connection section.
  • In the semiconductor device according to this embodiment, stress tends to occur after formation of the electrode pad in the region under the electrode pad. Therefore, cracks tend to occur in the conductive layer having a connection section disposed in this region. In the semiconductor device according to this embodiment, this problem is eliminated by providing the reinforcing section to the conductive layer formed in this region.
  • In this embodiment, the statement “a specific layer B (hereinafter called “layer B”) formed above a specific layer A (hereinafter called “layer A”)” includes the case where the layer B is directly formed on the layer A and the case where the layer B is formed on the layer A through another layer.
  • (2) According to one embodiment of the invention, there is provided a semiconductor device, comprising:
  • a semiconductor layer;
  • a first conductive layer formed above the semiconductor layer and having a first width;
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width;
  • an interlayer dielectric formed above the first conductive layer and the second conductive layer; and
  • an electrode pad formed above the interlayer dielectric,
  • a connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned outward from a line extending vertically downward from an edge of at least part of the electrode pad; and
  • a reinforcing section being provided at the connection section.
  • In the semiconductor device according to this embodiment, stress tends to occur after formation of the electrode pad in a specific region positioned outward from a line extending vertically downward from the edge of at least part of the electrode pad. Therefore, cracks tend to occur in the conductive layer having a connection section disposed in this region. In the semiconductor device according to this embodiment, this problem is eliminated by providing the reinforcing section to the conductive layer formed in this region.
  • (3) In this semiconductor device,
  • the electrode pad may have a rectangular shape having a short side and a long side; and
  • the reinforcing section may be provided at the connection section provided in a specific region positioned outward from a line extending vertically downward from an edge of the short side of the electrode pad.
  • (4) The semiconductor device may comprise:
  • a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad,
  • wherein the specific region is a region having a width corresponding to a thickness of the passivation layer outward from a line extending vertically downward from the edge.
  • (5) The semiconductor device may comprise:
  • a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad,
  • wherein the specific region is a region having a width of 1.0 to 2.5 micrometers outward from a line extending vertically downward from the edge.
  • (6) The semiconductor device may comprise a bump formed in the opening.
  • (7) According to one embodiment of the invention, there is provided a semiconductor device, comprising:
  • a semiconductor layer;
  • a first conductive layer formed above the semiconductor layer and having a first width;
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width;
  • an interlayer dielectric formed above the first conductive layer and the second conductive layer;
  • an electrode pad formed above the interlayer dielectric,
  • a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad; and
  • a bump formed in the opening,
  • a connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned inward from a line extending vertically downward from an edge of the bump; and
  • a reinforcing section being provided at the connection section.
  • In the semiconductor device according to this embodiment, stress tends to occur after formation of the bump in the region under the bump. Therefore, cracks tend to occur in the conductive layer having a connection section disposed in this region. In the semiconductor device according to this embodiment, this problem is eliminated by providing the reinforcing section to the conductive layer formed in this region.
  • (8) According to one embodiment of the invention, there is provided a semiconductor device, comprising:
  • a semiconductor layer;
  • a first conductive layer formed above the semiconductor layer and having a first width;
  • a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width;
  • an interlayer dielectric formed above the first conductive layer and the second conductive layer;
  • an electrode pad formed above the interlayer dielectric,
  • a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad; and
  • a bump formed in the opening,
  • a connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned inward and outward from a line extending vertically downward from an edge of at least part of the bump; and
  • a reinforcing section being provided at the connection section.
  • In the semiconductor device according to this embodiment, stress tends to occur after formation of the bump in a specific region positioned inward and outward from a line extending vertically downward from the edge of at least part of the bump. Therefore, cracks tend to occur in the conductive layer disposed in this region. In the semiconductor device according to this embodiment, this problem is eliminated by providing the reinforcing section to the conductive layer formed in this region.
  • (9) In this semiconductor device,
  • the bump may have a rectangular shape having a short side and a long side; and
  • the reinforcing section may be provided at the connection section provided in a specific region positioned inward and outward from a line extending vertically downward from an edge of the short side of the bump.
  • (10) In this semiconductor device,
  • the specific region may be a region having a width of 2.0 to 3.0 micrometers outward from a line extending vertically downward from the edge and having a width of 2.0 to 3.0 micrometers inward from a line extending vertically downward from the edge.
  • (11) In this semiconductor device, the first conductive layer and the second conductive layer may be connected in a shape of the letter “T” or “L”.
  • (12) In this semiconductor device, the reinforcing section may be formed by a third conductive layer protruding from the first conductive layer and the second conductive layer.
  • (13) In this semiconductor device, the first conductive layer, the second conductive layer, and the third conductive layer may be polysilicon layers.
  • Some embodiments of the invention will be described in detail below, with reference to the drawings.
    • 1. First Embodiment
  • FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment of the invention, and FIG. 2 is a plan view schematically showing the relationship between an electrode pad and a conductive layer in the semiconductor device according to the first embodiment. FIG. 1 is a cross-sectional view along the line X-X shown in FIG. 2.
  • As shown in FIG. 1, the semiconductor device according to the first embodiment includes a semiconductor layer 10. As the semiconductor layer 10, a single crystal silicon substrate, a silicon on insulator (SOI) substrate in which a semiconductor layer is formed on an insulating layer, the semiconductor layer being a silicon layer, a germanium layer, or a silicon germanium layer, or the like may be used.
  • A conductive layer 14 is formed on the semiconductor layer 10. As shown in FIG. 2, the conductive layer 14 is an interconnect in the shape of the letter “T”. In more detail, the conductive layer 14 includes a first conductive layer 14 a having a first width, and a second conductive layer 14 b connected with the first conductive layer 14 a and having a second width smaller than the first width. A reinforcing section 14 c is provided at a boundary 30 (hereinafter also called “connection section”) at which the first conductive layer 14 a and the second conductive layer 14 b are connected. As the material for the conductive layer 14, polysilicon, aluminum, an aluminum alloy, or the like may be used. A metal insulator semiconductor (MIS) transistor (not shown) is formed on the semiconductor layer 10. The conductive layer 14 may be electrically connected with the MIS transistor.
  • An interlayer dielectric 50 provided to cover the conductive layer 14 and an interlayer dielectric 60 are formed over the conductive layer 14 in that order. The interlayer dielectric 50 and the interlayer dielectric 60 may be formed using a known material. An interconnect layer 52 having a specific pattern is formed on the interlayer dielectric 50.
  • An electrode pad 62 is formed on the interlayer dielectric 60. The electrode pad 62 may be electrically connected with the interconnect layer 52 through a contact layer 64. The electrode pad 62 may be formed of a metal such as aluminum or copper.
  • As shown in FIG. 1, the semiconductor device according to the first embodiment further includes a passivation layer 70. An opening 72 which exposes at least part of the electrode pad 62 is formed in the passivation layer 70. As shown in FIGS. 1 and 2, the opening 72 may be formed to expose only the center region of the electrode pad 62. Specifically, the passivation layer 70 may be formed to cover the edge portion of the electrode pad 62. The passivation layer may be formed of SiO2, SiN, a polyimide resin, or the like. In the semiconductor device according to the first embodiment, the term “electrode pad” refers to a region which includes the region in which the opening 72 is formed and has a width greater than that of the interconnect section.
  • In the semiconductor device according to the first embodiment, a bump 80 is formed at least in the opening 72. Specifically, the bump 80 is formed on the exposed surface of the electrode pad 62. In the semiconductor device according to the first embodiment shown in FIG. 1, the bump 80 is also formed on the passivation layer 70. The bump 80 may include one or more layers and may be formed of a metal such as gold, nickel, or copper. The external shape of the bump 80 is not particularly limited. The external shape of the bump 80 may be a quadrilateral (including square and rectangle) or a circle. The external shape of the bump 80 may cover less area than that of the electrode pad 62. In this case, the bump 80 may be formed only in the area in which the bump 80 overlaps the electrode pad 62.
  • A barrier layer (not shown) may be formed in the lowermost layer of the bump 80. The barrier layer prevents diffusion between the electrode pad 62 and the bump 80. The barrier layer may include one or more layers. The barrier layer may be formed by sputtering. The barrier layer may have a function of increasing the adhesion between the electrode pad 62 and the bump 80. The barrier layer may include a titanium tungsten (TiW) layer. When the barrier layer includes two or more layers, the outermost surface of the barrier layer may be an electroplating feed metal layer (e.g. Au layer) for depositing the bump 80.
  • A region 12 is described below.
  • The region 12 is a region within a specific range positioned inward from a line extending vertically downward from the edge of the electrode pad 62. When the connection section 30 of the T-shaped conductive layer 14 is disposed in the region 12, the reinforcing section 14 c is provided at the connection section 30.
  • As shown in FIG. 9A, the T-shaped conductive layer 14 includes the first conductive layer 14 a extending in a direction X, the second conductive layer 14 b which branches in a direction Y from the first conductive layer 14 a, and the reinforcing section 14 c formed in the base section of the second conductive layer 14 b, for example. The reinforcing section 14 c is formed by a conductive layer protruding from the first conductive layer 14 a and the second conductive layer 14 b. In the T-shaped conductive layer 14, when the second conductive layer 14 b which branches from the first conductive layer 14 a has a width smaller than the first conductive layer 14 a, defects such as cracks tend to occur near the boundary between the first conductive layer 14 a and the second conductive layer 14 b due to mechanical and thermal stress during mounting. However, such defects are prevented from occurring by providing the reinforcing section 14 c. As shown in FIG. 10A, the T-shaped bent conductive layer 14 may include the reinforcing section 14 c having a stepwise planar shape. Note that the shape of the reinforcing section 14 c is not limited to the above examples. The reinforcing section 14 c may have an arbitrary shape insofar as the reinforcement effect for the conductive layer can be achieved.
  • As shown in FIG. 9B, when the conductive layer 14 is in the shape of the letter “L”, the conductive layer 14 includes the first conductive layer 14 a extending in the direction X, the second conductive layer 14 b extending in the direction Y from the end of the first conductive layer 14 a, and the reinforcing section 14 c formed in the base section of the second conductive layer 14 b. The reinforcing section 14 c is formed by a conductive layer protruding from the first conductive layer 14 a and the second conductive layer 14 b. In the L-shaped bent conductive layer 14, when the second conductive layer 14 b has a width smaller than the first conductive layer 14 a, defects such as cracks tend to occur near the boundary between the first conductive layer 14 a and the second conductive layer 14 b due to mechanical and thermal stress during mounting. However, such defects are prevented from occurring by providing the reinforcing section 14 c. As shown in FIG. 10B, the L-shaped bent conductive layer 14 may include the reinforcing section 14 c having a stepwise shape. Note that the shape of the reinforcing section 14 c is not limited to the above examples. The reinforcing section 14 c may have an arbitrary shape insofar as the reinforcement effect can be achieved.
  • The region 12 may be the region inward from a line extending vertically downward from the edge of the electrode pad 62. The range of the region 12 is specified as described above for the following reasons.
  • When the electrode pad 62 is formed, stress occurs in the interlayer dielectric 60 at a position in which the edge of the electrode pad 62 is positioned. When the bump 80 is formed on the electrode pad 62, a continuous stress additionally occurs due to the internal stress of the bump 80. The stress may cause cracks to occur in the interlayer dielectrics 50 and 60 from the position (edge of the electrode pad 62) at which the stress occurs. Such cracks may reach the lowermost interlayer dielectric. For example, when a conductive layer is formed in such a region, defects such as cracks may occur in the conductive layer.
  • The range of the region 12 is not limited to the first layer, but may be applied to a conductive layer formed in the second or higher layer, for example.
  • As described above, the semiconductor device according to the first embodiment allows the T-shaped or L-shaped bent conductive layer exhibiting mechanical strength to be formed as the conductive layer in the region 12, whereby the degrees of freedom of the wiring pattern design can be increased.
    • 2. Second Embodiment
  • FIG. 3 is a cross-sectional view schematically showing a semiconductor device according to a second embodiment of the invention, and FIG. 4 is a plan view schematically showing the relationship between an electrode pad and a conductive layer in the semiconductor device according to the second embodiment. FIG. 3 is a cross-sectional view along the line X-X shown in FIG. 4.
  • The second embodiment differs from the first embodiment as to the position of the region 12. Note that members substantially the same as the members of the semiconductor device according to the first embodiment are assigned the same symbols. Detailed description of these members is omitted.
  • As shown in FIG. 3, the semiconductor device according to the second embodiment includes the semiconductor layer 10. The conductive layer 14 is formed on the semiconductor layer 10. As shown in FIG. 4, the conductive layer 14 is an interconnect in the shape of the letter “T”. In more detail, the conductive layer 14 includes the first conductive layer 14 a having the first width, and the second conductive layer 14 b connected with the first conductive layer 14 a and having the second width smaller than the first width. The reinforcing section 14 c is provided at the boundary 30 (hereinafter also called “connection section”) at which the first conductive layer 14 a and the second conductive layer 14 b are connected. As the material for the conductive layer 14, polysilicon, aluminum, an aluminum alloy, or the like may be used. A metal insulator semiconductor (MIS) transistor (not shown) is formed on the semiconductor layer 10. The conductive layer 14 may be electrically connected with the MIS transistor.
  • The interlayer dielectric 50 provided to cover the conductive layer 14 and the interlayer dielectric 60 are formed over the conductive layer 14 in that order. The interlayer dielectric 50 and the interlayer dielectric 60 may be formed using a known material. The interconnect layer 52 having a specific pattern is formed on the interlayer dielectric 50. The electrode pad 62 is formed on the interlayer dielectric 60. The electrode pad 62 may be electrically connected with the interconnect layer 52 through the contact layer 64.
  • As shown in FIG. 3, the semiconductor device according to the first embodiment further includes the passivation layer 70. The opening 72 which exposes at least part of the electrode pad 62 is formed in the passivation layer 70.
  • In the semiconductor device according to the first embodiment, the bump 80 is formed at least in the opening 72. Specifically, the bump 80 is formed on the exposed surface of the electrode pad 62. The bump 80 is formed to reach the portion on the passivation layer 70.
  • The region 12 is described below.
  • The region 12 is a region within a specific range positioned outward from a line extending vertically downward from the edge of the electrode pad 62.
  • When the connection section 30 of the T-shaped conductive layer 14 is disposed in the region 12, the reinforcing section 14 c is provided at the connection section 30.
  • The conductive layer 14 may be in the shape of the letter “T” or “L” similar to that described in the first embodiment. Since the conductive layer 14 includes the reinforcing section 14 c, defects such as cracks due to mechanical and thermal stress during mounting rarely occur near the boundary between the first conductive layer 14 a and the second conductive layer 14 b.
  • The region 12 may be the range having a width corresponding to the thickness of the passivation layer 70 outward (in the direction away from the opening 72) from a line extending vertically downward from the edge of the electrode pad 62. For example, the region 12 may be the range having a width of 1.0 to 2.5 micrometers outward from the edge of the electrode pad 62. The range of the region 12 is specified as described above for the following reasons.
  • When the electrode pad 62 is formed, stress occurs in the interlayer dielectric 60 at a position in which the edge of the electrode pad 62 is positioned. When the bump 80 is formed on the electrode pad 62, a continuous stress additionally occurs due to the internal stress of the bump 80. The stress may cause cracks to occur in the interlayer dielectrics 50 and 60 from the position (edge of the electrode pad 62) at which the stress occurs. Such cracks may reach the lowermost interlayer dielectric. For example, when a conductive layer is formed in such a region, defects such as cracks may occur in the conductive layer.
  • The passivation layer 70 is not formed on a surface having a uniform height. That is, the passivation layer 70 may have a surface having a level difference corresponding to the shape of the electrode pad 62. For example, when mounting the semiconductor device by a chip-on-film (COF) method, stress due to contact and bonding tends to be concentrated in the region in which the level difference is formed when connecting the bump 80 through a connection line (lead wire) formed on a film. This may also cause cracks to occur in the interlayer dielectrics 50 and 60. The level difference is generally formed in the area having a width approximately corresponding to the thickness of the passivation layer 70 outward from the edge of the electrode pad 62. The range of the region 12 may be specified taking these problems into consideration.
  • The range of the region 12 is not limited to the first layer, but may be applied to a conductive layer formed in the second or higher layer, for example. The region 12 may be the region within a specific range positioned outward from a line extending vertically downward from the edge of at least part of the electrode pad 62.
  • As described above, the semiconductor device according to the second embodiment allows the T-shaped or L-shaped bent conductive layer exhibiting mechanical strength to be formed as the conductive layer in the region 12, whereby the degrees of freedom of the wiring pattern design can be increased.
    • 3. Third Embodiment
  • FIG. 5 is a cross-sectional view schematically showing a semiconductor device according to a third embodiment of the invention, and FIG. 6 is a plan view schematically showing the relationship between a bump and a conductive layer in the semiconductor device according to the third embodiment. FIG. 5 is a cross-sectional view along the line X-X shown in FIG. 6.
  • The third embodiment differs from the first and second embodiments as to the position of the region 12. Note that members substantially the same as the members of the semiconductor device according to the first embodiment are assigned the same symbols. Detailed description of these members is omitted.
  • As shown in FIG. 5, the semiconductor device according to the third embodiment includes the semiconductor layer 10. The conductive layer 14 is formed on the semiconductor layer 10. As shown in FIG. 6, the conductive layer 14 is an interconnect in the shape of the letter “T”. In more detail, the conductive layer 14 includes the first conductive layer 14 a having the first width, and the second conductive layer 14 b connected with the first conductive layer 14 a and having the second width smaller than the first width. The reinforcing section 14 c is provided at the boundary 30 (hereinafter also called “connection section”) at which the first conductive layer 14 a and the second conductive layer 14 b are connected. As the material for the conductive layer 14, polysilicon, aluminum, an aluminum alloy, or the like may be used. A metal insulator semiconductor (MIS) transistor (not shown) is formed on the semiconductor layer 10. The conductive layer 14 may be electrically connected with the MIS transistor.
  • The interlayer dielectric 50 provided to cover the conductive layer 14 and the interlayer dielectric 60 are formed over the conductive layer 14 in that order. The interlayer dielectric 50 and the interlayer dielectric 60 may be formed using a known material. The interconnect layer 52 having a specific pattern is formed on the interlayer dielectric 50. The electrode pad 62 is formed on the interlayer dielectric 60. The electrode pad 62 may be electrically connected with the interconnect layer 52 through the contact layer 64.
  • As shown in FIG. 5, the semiconductor device according to the first embodiment further includes the passivation layer 70. The opening 72 which exposes at least part of the electrode pad 62 is formed in the passivation layer 70.
  • In the semiconductor device according to the first embodiment, the bump 80 is formed at least in the opening 72. Specifically, the bump 80 is formed on the exposed surface of the electrode pad 62. In the semiconductor device according to the first embodiment shown in FIG. 1, the bump 80 is also formed on the passivation layer 70.
  • The region 12 is described below.
  • The region 12 is a region within a specific range positioned inward from a line extending vertically downward from the edge of the bump 80.
  • When the connection section 30 of the T-shaped conductive layer 14 is disposed in the region 12, the reinforcing section 14 c is provided at the connection section 30.
  • The conductive layer 14 may be in the shape of the letter “T” or “L” similar to that described in the first embodiment. Since the conductive layer 14 includes the reinforcing section 14 c, defects such as cracks due to mechanical and thermal stress during mounting rarely occur near the boundary between the first conductive layer 14 a and the second conductive layer 14 b.
  • The region 12 may be the region inward from a line extending vertically downward from the edge of the bump 80. The range of the region 12 is specified as described above for the following reasons.
  • When the electrode pad 62 is formed, stress occurs in the interlayer dielectric 60 at a position at which the edge of the electrode pad 62 is positioned. When the bump 80 is formed on the electrode pad 62, as shown in FIG. 5, a continuous stress additionally occurs due to the internal stress of the bump 80. The stress may cause cracks to occur in the interlayer dielectrics 50 and 60 from the position (edge of the electrode pad 62) at which the stress occurs. Such cracks may reach the lowermost interlayer dielectric. For example, when a conductive layer is formed in such a region, defects such as cracks may occur in the conductive layer.
  • The range of the region 12 is not limited to the first layer, but may be applied to a conductive layer formed in the second or higher layer, for example. The region 12 may be the region within a specific range positioned outward from a line extending vertically downward from the edge of at least part of the electrode pad 62.
  • As described above, the semiconductor device according to the third embodiment allows the T-shaped or L-shaped bent conductive layer exhibiting mechanical strength to be formed as the conductive layer in the region 12, whereby the degrees of freedom of the wiring pattern design can be increased.
    • 4. Fourth Embodiment
  • FIG. 7 is a cross-sectional view schematically showing a semiconductor device according to a fourth embodiment of the invention, and FIG. 8 is a plan view schematically showing the relationship between a bump and a conductive layer in the semiconductor device according to the fourth embodiment. FIG. 7 is a cross-sectional view along the line X-X shown in FIG. 8.
  • The fourth embodiment differs from the first to third embodiments as to the position of the region 12. Note that members substantially the same as the members of the semiconductor device according to the first embodiment are assigned the same symbols. Detailed description of these members is omitted.
  • As shown in FIG. 7, the semiconductor device according to the fourth embodiment includes the semiconductor layer 10. The conductive layer 14 is formed on the semiconductor layer 10. As shown in FIG. 8, the conductive layer 14 is an interconnect in the shape of the letter “T”. In more detail, the conductive layer 14 includes the first conductive layer 14 a having the first width, and the second conductive layer 14 b connected with the first conductive layer 14 a and having the second width smaller than the first width. The reinforcing section 14 c is provided at the boundary 30 (hereinafter also called “connection section”) at which the first conductive layer 14 a and the second conductive layer 14 b are connected. As the material for the conductive layer 14, polysilicon, aluminum, an aluminum alloy, or the like may be used. A metal insulator semiconductor (MIS) transistor (not shown) is formed on the semiconductor layer 10. The conductive layer 14 may be electrically connected with the MIS transistor.
  • The interlayer dielectric 50 provided to cover the conductive layer 14 and the interlayer dielectric 60 are formed over the conductive layer 14 in that order. The interlayer dielectric 50 and the interlayer dielectric 60 may be formed using a known material. The interconnect layer 52 having a specific pattern is formed on the interlayer dielectric 50. The electrode pad 62 is formed on the interlayer dielectric 60. The electrode pad 62 may be electrically connected with the interconnect layer 52 through the contact layer 64.
  • As shown in FIG. 7, the semiconductor device according to the fourth embodiment further includes the passivation layer 70. The opening 72 which exposes at least part of the electrode pad 62 is formed in the passivation layer 70.
  • In the semiconductor device according to the first embodiment, the bump 80 is formed at least in the opening 72. Specifically, the bump 80 is formed on the exposed surface of the electrode pad 62. In the semiconductor device according to the first embodiment shown in FIG. 1, the bump 80 is also formed on the passivation layer 70.
  • The region 12 is described below.
  • The region 12 is a region within a specific range positioned inward and outward from a line extending vertically downward from the edge of the bump 80.
  • When the connection section 30 of the T-shaped conductive layer 14 is disposed in the region 12, the reinforcing section 14 c is provided at the connection section 30.
  • The conductive layer 14 may be in the shape of the letter “T” or “L” similar to that described in the first embodiment. Since the conductive layer 14 includes the reinforcing section 14 c, defects such as cracks due to mechanical and thermal stress during mounting rarely occur near the boundary between the first conductive layer 14 a and the second conductive layer 14 b.
  • The region 12 may be the range having a width of 2.0 to 3.0 micrometers outward (in the direction away from the opening 72) from a line extending vertically downward from the edge of the bump 80 and having a width of 2.0 to 3.0 micrometers inward (in the direction toward the opening 72) from the a line extending vertically downward from the edge of the bump 80. The range of the region 12 is specified as described above for the following reasons.
  • Stress occurs near the edge of the bump 80 during the formation process of the bump 80. After the bump 80 has been formed, stress continuously occurs near the edge of the bump 80 due to the internal stress of the bump 80. The stress may cause cracks to occur in the interlayer dielectrics 50 and 60 from the position at which the stress occurs. Such cracks may reach the lowermost interlayer dielectric, whereby defects such as cracks may occur in the conductive layer formed in such a region.
  • The range of the region 12 is not limited to the first layer, but may be applied to a conductive layer formed in the second or higher layer, for example. The region 12 may be the region within a specific range positioned outward from a line extending vertically downward from the edge of at least part of the electrode pad 62.
  • As described above, the semiconductor device according to the fourth embodiment allows the T-shaped or L-shaped bent conductive layer exhibiting mechanical strength to be formed as the conductive layer in the region 12, whereby the degrees of freedom of the wiring pattern design can be increased.
    • 5. Modification
  • A modification of the semiconductor devices according to the second embodiment and the fourth embodiment is described below with reference to FIGS. 11A and 11B. This modification is characterized in that the electrode pad 62 and the bump 80 have a rectangular shape. FIGS. 11A and 11B are plan views schematically showing the positional relationship among the bump 80, the electrode pad 62, and the region 12. The following description merely illustrates the difference from the semiconductor devices according to the second embodiment and the fourth embodiment.
  • In the semiconductor device according to this modification, the bump 80 is formed in the opening 72 on the electrode pad 62, as shown in FIGS. 3 and 7. In this modification, the electrode pad 62 has a rectangular shape. The opening 72 is formed on part of the upper surface of the electrode pad 62, and the bump 80 is formed in the opening 72. The bump 80 has a planar shape smaller in area than that of the electrode pad 62. As shown in FIGS. 11A and 11B, it is preferable that the bump 80 be provided inside the electrode pad 62 when viewed from the top side.
  • A first modification is a modification relating to the second embodiment. In this modification, the region 12 is provided in the region positioned outward from a line extending vertically downward from the edge of the short side of the electrode pad 62, as shown in FIG. 11A. This configuration has the following advantage when mounting the semiconductor device by tape automated bonding (TAB) technology provided that the extension direction of a connection line (lead wire) formed on a film made of a polyimide resin or the like is the direction along the long side of the electrode pad 62. In this case, the electrode pad 62 is pulled in the extension direction of the connection line, whereby stress occurs on the short side of the electrode pad 62. Therefore, cracks tend to occur in the interlayer dielectrics 50 and 60 on the edge on the short side of the electrode pad 62. This modification reliably prevents the semiconductor element from being formed at a position in which the reliability is decreased by providing the region 12 on the short side of the electrode pad 62.
  • A second modification is a modification relating to the fourth embodiment. In this modification, the region 12 is provided in the region positioned inward and outward from a line extending vertically downward from the edge of the short side of the bump 80, as shown in FIG. 11B.
  • In particular, in a semiconductor chip 200 which is scaled down as shown in FIG. 12, a structure may be required in which the opening 72 and the bump 80 are formed in a rectangular planar shape to provide a number of openings 72. According to this modification, a semiconductor device which is scaled down and provided with improved reliability can be provided by providing the region 12 in an appropriate region of the semiconductor device having such rectangular electrode pads 62 (bumps 80).
  • The above embodiments illustrate the case where two interlayer dielectrics 50 and 60 are provided and one interconnect layer 52 is provided between the interlayer dielectrics 50 and 60. Note that the above embodiments are not limited thereto. A structure may also be employed in which three or more interlayer dielectrics are stacked and interconnect layers in a number corresponding to the number of interlayer dielectrics are provided.
  • The invention is not limited to the above-described embodiments, and various modifications can be made. For example, the invention includes various other configurations substantially the same as the configurations described in the embodiments (in function, method and result, or in objective and result, for example). The invention also includes a configuration in which an unsubstantial portion in the described embodiments is replaced. The invention also includes a configuration having the same effects as the configurations described in the embodiments, or a configuration able to achieve the same objective. Further, the invention includes a configuration in which a publicly known technique is added to the configurations in the embodiments.
  • Although only some embodiments of the invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention.

Claims (22)

1. A semiconductor device, comprising:
a semiconductor layer;
a first conductive layer formed above the semiconductor layer and having a first width;
a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width;
an interlayer dielectric formed above the first conductive layer and the second conductive layer; and
an electrode pad formed above the interlayer dielectric,
a connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and
a reinforcing section being provided at the connection section.
2. The semiconductor device as defined in claim 1,
wherein the first conductive layer and the second conductive layer are connected in a shape of the letter “T” or “L”.
3. The semiconductor device as defined in claim 1,
wherein the reinforcing section is formed by a third conductive layer protruding from the first conductive layer and the second conductive layer.
4. The semiconductor device as defined in claim 3,
wherein the first conductive layer, the second conductive layer, and the third conductive layer are polysilicon layers.
5. A semiconductor device, comprising:
a semiconductor layer;
a first conductive layer formed above the semiconductor layer and having a first width;
a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width;
an interlayer dielectric formed above the first conductive layer and the second conductive layer; and
an electrode pad formed above the interlayer dielectric,
a connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned outward from a line extending vertically downward from an edge of at least part of the electrode pad; and
a reinforcing section being provided at the connection section.
6. The semiconductor device as defined in claim 5,
wherein the electrode pad has a rectangular shape having a short side and a long side; and
wherein the reinforcing section is provided at the connection section provided in a specific region positioned outward from a line extending vertically downward from an edge of the short side of the electrode pad.
7. The semiconductor device as defined in claim 5, comprising:
a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad,
wherein the specific region is a region having a width corresponding to a thickness of the passivation layer outward from a line extending vertically downward from the edge.
8. The semiconductor device as defined in claim 5, comprising:
a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad,
wherein the specific region is a region having a width of 1.0 to 2.5 micrometers outward from a line extending vertically downward from the edge.
9. The semiconductor device as defined in claim 7, comprising a bump formed in the opening.
10. The semiconductor device as defined in claim 5,
wherein the first conductive layer and the second conductive layer are connected in a shape of the letter “T” or “L”.
11. The semiconductor device as defined in claim 5,
wherein the reinforcing section is formed by a third conductive layer protruding from the first conductive layer and the second conductive layer.
12. The semiconductor device as defined in claim 11,
wherein the first conductive layer, the second conductive layer, and the third conductive layer are polysilicon layers.
13. A semiconductor device, comprising:
a semiconductor layer;
a first conductive layer formed above the semiconductor layer and having a first width;
a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width;
an interlayer dielectric formed above the first conductive layer and the second conductive layer;
an electrode pad formed above the interlayer dielectric,
a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad; and
a bump formed in the opening,
a connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned inward from a line extending vertically downward from an edge of the bump; and
a reinforcing section being provided at the connection section.
14. The semiconductor device as defined in claim 13,
wherein the first conductive layer and the second conductive layer are connected in a shape of the letter “T” or “L”.
15. The semiconductor device as defined in claim 13,
wherein the reinforcing section is formed by a third conductive layer protruding from the first conductive layer and the second conductive layer.
16. The semiconductor device as defined in claim 15,
wherein the first conductive layer, the second conductive layer, and the third conductive layer are polysilicon layers.
17. A semiconductor device, comprising:
a semiconductor layer;
a first conductive layer formed above the semiconductor layer and having a first width;
a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width;
an interlayer dielectric formed above the first conductive layer and the second conductive layer;
an electrode pad formed above the interlayer dielectric,
a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad; and
a bump formed in the opening,
a connection section at which the first conductive layer and the second conductive layer are connected being disposed in a specific region positioned inward and outward from a line extending vertically downward from an edge of at least part of the bump; and
a reinforcing section being provided at the connection section.
18. The semiconductor device as defined in claim 17,
wherein the bump has a rectangular shape having a short side and a long side; and
wherein the reinforcing section is provided at the connection section provided in a specific region positioned inward and outward from a line extending vertically downward from an edge of the short side of the bump.
19. The semiconductor device as defined in claim 17,
wherein the specific region is a region having a width of 2.0 to 3.0 micrometers outward from a line extending vertically downward from the edge and having a width of 2.0 to 3.0 micrometers inward from a line extending vertically downward from the edge.
20. The semiconductor device as defined in claim 17,
wherein the first conductive layer and the second conductive layer are connected in a shape of the letter “T” or “L”.
21. The semiconductor device as defined in claim 17,
wherein the reinforcing section is formed by a third conductive layer protruding from the first conductive layer and the second conductive layer.
22. The semiconductor device as defined in claim 21,
wherein the first conductive layer, the second conductive layer, and the third conductive layer are polysilicon layers.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140264828A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method and Apparatus for a Conductive Pillar Structure
US20180214956A1 (en) * 2015-07-17 2018-08-02 Ap&C Advanced Powders & Coatings Inc. Plasma atomization metal powder manufacturing processes and system therefor
US20180337143A1 (en) * 2017-05-22 2018-11-22 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor chip, and fabrication and packaging methods thereof

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104409371A (en) * 2014-12-03 2015-03-11 无锡中微高科电子有限公司 Method for improving long-term reliability of gold-aluminum bonding
CN211788920U (en) 2017-07-24 2020-10-27 株式会社村田制作所 Semiconductor device with a plurality of semiconductor chips
JP2020113722A (en) * 2019-01-17 2020-07-27 日本特殊陶業株式会社 package

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027188A (en) * 1988-09-13 1991-06-25 Hitachi, Ltd. Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate
US5084752A (en) * 1989-10-17 1992-01-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having bonding pad comprising buffer layer
US5736791A (en) * 1995-02-07 1998-04-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and bonding pad structure therefor
US6100589A (en) * 1996-08-20 2000-08-08 Seiko Epson Corporation Semiconductor device and a method for making the same that provide arrangement of a connecting region for an external connecting terminal
US6130485A (en) * 1997-12-15 2000-10-10 Nec Corporation Semiconductor integrated circuit and layout method thereof
US6268642B1 (en) * 1999-04-26 2001-07-31 United Microelectronics Corp. Wafer level package
US6407345B1 (en) * 1998-05-19 2002-06-18 Ibiden Co., Ltd. Printed circuit board and method of production thereof
US6465895B1 (en) * 2001-04-05 2002-10-15 Samsung Electronics Co., Ltd. Bonding pad structures for semiconductor devices and fabrication methods thereof
US6538326B2 (en) * 2000-10-16 2003-03-25 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US6664642B2 (en) * 1997-03-31 2003-12-16 Hitachi, Ltd. Semiconductor integrated circuit device
US6781238B2 (en) * 2000-04-03 2004-08-24 Nec Corporation Semiconductor device and method of fabricating the same
US20070007599A1 (en) * 2005-07-06 2007-01-11 Seiko Epson Corporation Semiconductor device
US20070007662A1 (en) * 2005-07-06 2007-01-11 Seiko Epson Corporation Semiconductor device

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59181041A (en) * 1983-03-31 1984-10-15 Toshiba Corp Semiconductor integrated circuit device
JPH0224540A (en) 1988-07-13 1990-01-26 Ntn Corp Optical disk checking apparatus
JPH0373438A (en) 1989-08-14 1991-03-28 Asahi Chem Ind Co Ltd Production of optical recording medium
JPH0373438U (en) * 1989-11-21 1991-07-24
KR970077390A (en) 1996-05-15 1997-12-12 김광호 Semiconductor device using pads
KR100295240B1 (en) 1997-04-24 2001-11-30 마찌다 가쯔히꼬 Semiconductor device
JP2003179063A (en) 1997-04-24 2003-06-27 Sharp Corp Semiconductor device
JP3608393B2 (en) * 1997-08-21 2005-01-12 セイコーエプソン株式会社 Semiconductor device
JP3416040B2 (en) 1997-11-11 2003-06-16 富士通株式会社 Semiconductor device
KR19990052264A (en) * 1997-12-22 1999-07-05 윤종용 Semiconductor device with multi-layer pad and manufacturing method thereof
KR19990070614A (en) 1998-02-23 1999-09-15 구본준 Bit line planarization method of semiconductor device
JP2000058549A (en) 1998-08-04 2000-02-25 Nec Corp Formation of integrated circuit wiring
US6500750B1 (en) 1999-04-05 2002-12-31 Motorola, Inc. Semiconductor device and method of formation
US20020000665A1 (en) 1999-04-05 2002-01-03 Alexander L. Barr Semiconductor device conductive bump and interconnect barrier
JP2001110833A (en) 1999-10-06 2001-04-20 Matsushita Electronics Industry Corp Semiconductor device
KR100358567B1 (en) * 1999-12-28 2002-10-25 주식회사 하이닉스반도체 Fabricating method of semiconductor device
US6683380B2 (en) 2000-07-07 2004-01-27 Texas Instruments Incorporated Integrated circuit with bonding layer over active circuitry
US6737301B2 (en) 2000-07-13 2004-05-18 Isothermal Systems Research, Inc. Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor
JP2002319587A (en) * 2001-04-23 2002-10-31 Seiko Instruments Inc Semiconductor device
JP4168615B2 (en) 2001-08-28 2008-10-22 ソニー株式会社 Semiconductor device and manufacturing method of semiconductor device
JP2003297865A (en) 2002-03-29 2003-10-17 Optrex Corp Bare chip and electric component mounted with the bare chip
JP2003347333A (en) 2002-05-23 2003-12-05 Renesas Technology Corp Semiconductor device
JP4232584B2 (en) 2002-10-15 2009-03-04 株式会社デンソー Semiconductor device
US6818936B2 (en) 2002-11-05 2004-11-16 Taiwan Semiconductor Manufacturing Company Scaled EEPROM cell by metal-insulator-metal (MIM) coupling
JP2004207509A (en) * 2002-12-25 2004-07-22 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
US6780694B2 (en) 2003-01-08 2004-08-24 International Business Machines Corporation MOS transistor
JP4346322B2 (en) 2003-02-07 2009-10-21 株式会社ルネサステクノロジ Semiconductor device
JP2004363173A (en) 2003-06-02 2004-12-24 Seiko Epson Corp Semiconductor device and method of manufacturing the same
JP2004363224A (en) 2003-06-03 2004-12-24 Seiko Epson Corp Connection structure of semiconductor chip
JP2005050963A (en) * 2003-07-31 2005-02-24 Seiko Epson Corp Semiconductor device, electronic device, electronic apparatus and manufacturing method of semiconductor device
US7005369B2 (en) 2003-08-21 2006-02-28 Intersil American Inc. Active area bonding compatible high current structures
JP4012496B2 (en) * 2003-09-19 2007-11-21 カシオ計算機株式会社 Semiconductor device
CN1601735B (en) 2003-09-26 2010-06-23 松下电器产业株式会社 Semiconductor device and method for fabricating the same
JP4093165B2 (en) 2003-09-29 2008-06-04 松下電器産業株式会社 Semiconductor integrated circuit device
JP2005116974A (en) 2003-10-10 2005-04-28 Seiko Epson Corp Method of manufacturing semiconductor device
JP2005136170A (en) 2003-10-30 2005-05-26 Seiko Epson Corp Manufacturing method of semiconductor device
JP4696532B2 (en) 2004-05-20 2011-06-08 株式会社デンソー Power composite integrated semiconductor device and manufacturing method thereof
US20050285116A1 (en) 2004-06-29 2005-12-29 Yongqian Wang Electronic assembly with carbon nanotube contact formations or interconnections
US7256092B2 (en) 2004-07-25 2007-08-14 United Microelectronics Corp. Method for fabricating integrated circuits having both high voltage and low voltage devices
US7115985B2 (en) * 2004-09-30 2006-10-03 Agere Systems, Inc. Reinforced bond pad for a semiconductor device
US7071575B2 (en) 2004-11-10 2006-07-04 United Microelectronics Corp. Semiconductor chip capable of implementing wire bonding over active circuits

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027188A (en) * 1988-09-13 1991-06-25 Hitachi, Ltd. Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate
US5084752A (en) * 1989-10-17 1992-01-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having bonding pad comprising buffer layer
US5736791A (en) * 1995-02-07 1998-04-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and bonding pad structure therefor
US6100589A (en) * 1996-08-20 2000-08-08 Seiko Epson Corporation Semiconductor device and a method for making the same that provide arrangement of a connecting region for an external connecting terminal
US6664642B2 (en) * 1997-03-31 2003-12-16 Hitachi, Ltd. Semiconductor integrated circuit device
US6130485A (en) * 1997-12-15 2000-10-10 Nec Corporation Semiconductor integrated circuit and layout method thereof
US6407345B1 (en) * 1998-05-19 2002-06-18 Ibiden Co., Ltd. Printed circuit board and method of production thereof
US6268642B1 (en) * 1999-04-26 2001-07-31 United Microelectronics Corp. Wafer level package
US6781238B2 (en) * 2000-04-03 2004-08-24 Nec Corporation Semiconductor device and method of fabricating the same
US6538326B2 (en) * 2000-10-16 2003-03-25 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US6465895B1 (en) * 2001-04-05 2002-10-15 Samsung Electronics Co., Ltd. Bonding pad structures for semiconductor devices and fabrication methods thereof
US20070007599A1 (en) * 2005-07-06 2007-01-11 Seiko Epson Corporation Semiconductor device
US20070007662A1 (en) * 2005-07-06 2007-01-11 Seiko Epson Corporation Semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140264828A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method and Apparatus for a Conductive Pillar Structure
US8994171B2 (en) * 2013-03-12 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a conductive pillar structure
US9379080B2 (en) 2013-03-12 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a conductive pillar structure
US20180214956A1 (en) * 2015-07-17 2018-08-02 Ap&C Advanced Powders & Coatings Inc. Plasma atomization metal powder manufacturing processes and system therefor
US20180337143A1 (en) * 2017-05-22 2018-11-22 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor chip, and fabrication and packaging methods thereof
US10522479B2 (en) * 2017-05-22 2019-12-31 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor chip, and fabrication and packaging methods thereof
US11335648B2 (en) 2017-05-22 2022-05-17 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor chip fabrication and packaging methods thereof

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US8878365B2 (en) 2014-11-04
JP2007027264A (en) 2007-02-01
US20140361433A1 (en) 2014-12-11
JP4605378B2 (en) 2011-01-05
CN100456466C (en) 2009-01-28
CN1897268A (en) 2007-01-17
US20120032324A1 (en) 2012-02-09
KR100767152B1 (en) 2007-10-12

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