US20070066011A1 - Integrated circuitry production processes, methods, and systems - Google Patents
Integrated circuitry production processes, methods, and systems Download PDFInfo
- Publication number
- US20070066011A1 US20070066011A1 US11/602,744 US60274406A US2007066011A1 US 20070066011 A1 US20070066011 A1 US 20070066011A1 US 60274406 A US60274406 A US 60274406A US 2007066011 A1 US2007066011 A1 US 2007066011A1
- Authority
- US
- United States
- Prior art keywords
- substrate
- pad
- fluid
- layer
- carbon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/42—Stripping or agents therefor
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/42—Stripping or agents therefor
- G03F7/422—Stripping or agents therefor using liquids only
- G03F7/425—Stripping or agents therefor using liquids only containing mineral alkaline compounds; containing organic basic compounds, e.g. quaternary ammonium compounds; containing heterocyclic basic compounds containing nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
Abstract
The invention includes methods of forming capacitor structures and removing organic material. An organic material, such as a photoresist, is disposed on a substrate. The organic material is contacted with a chemical mechanical polishing pad and a polishing fluid to remove the organic material from the substrate. The polishing fluid can be essentially free of particles, and can be water.
Description
- This application is a continuation of U.S. application Ser. No. 11/499,096, filed Aug. 2, 2006, which is a continuation of U. S. application Ser. No. 10/734,995, filed Dec. 12, 2003, which is a continuation of U.S. application Ser. No. 10/134,201 filed Apr. 25, 2002, now U.S. Pat. No. 6,706,632 B2; the entirety of all of which are incorporated by reference herein.
- The present invention relates generally to semiconductor processing. In particular applications the invention pertains to methods of forming capacitor structures and methods of resist removal.
- Increased performance, both with regard to more complex functionality and higher speeds, is a continuing goal of efforts in advancing the semiconductor arts. One method that has been used for achieving this goal is scaling downward the size of individual devices used in forming advanced semiconductor integrated circuits. However, it is found that at times, changes in the components used in fabricating such down-sized devices are advantageous. For example, where capacitors, such as those used in memory integrated circuits, are scaled downward in size, dielectric materials such as silicon oxide and silicon nitride are often replaced with alternate materials having a higher dielectric constant to achieve desired capacitance. Where such replacements of dielectric materials are made, it can be advantageous to form capacitor electrodes comprising one or more of platinum, tantalum, ruthenium, iridium, and titanium. Such electrodes can comprise, for example, alloys of various metals and/or nitrides of various metals, including, for example, titanium nitride. The capacitors comprising metallic electrodes are well known in the art, and are frequently described as metal-insulator-metal capacitor constructions.
- One method for patterning various dielectric and conductive materials is chemical mechanical polishing (CMP). A material (such as platinum), can be blanket formed within an opening and over surfaces proximate the opening. The material can be removed from over the surfaces by a CMP method. The material within the opening, elevationally below that upper surface, will not be removed. The material within the opening can ultimately form a capacitor electrode structure. A problem with the CMP method can be scratching or smearing of the material, which can prevent the proper forming of the ultimately desired capacitor structure. For instance, if the material is platinum or an alloy of platinum, scratching or smearing of the platinum can occur in a CMP process. It can be difficult, and for all practical purposes impossible, to remove smeared platinum from within a container.
- It would be desirable, to develop a CMP method where the removal of portions of various materials (such as platinum or barrier materials) can be effected without scratching or smearing across surfaces of the materials. It would also be desirable if such a CMP method was cost-effective and could be performed using essentially standard CMP processing tools.
- In one aspect, the present invention can provide methods for forming structures (such as capacitor or plug structures) and/or removing resist from a semiconductor substrate. A material is formed over a substrate, and a resist layer is formed over the material. Subsequently, at least a portion of the resist layer is removed to expose a desired portion of the material. The resist layer can be removed by providing contact of a chemical mechanical polishing pad and a polishing fluid with the resist layer. Such contact can be provided by a chemical mechanical polishing system that encompasses a mechanism for moving the polishing pad and/or the substrate. In some embodiments of the present invention it is advantageous to provide that the polishing fluid has a particle concentration of less than or equal to about 0.1% by weight of a silica-comprising material, and in particular embodiments it is advantageous for the polishing fluid to be essentially free of particles. In particular aspects, the polishing fluid can comprise tetramethylammonium hydroxide (TMAH) or ammonia to increase a rate of removal of various compositions by the fluid.
- Some embodiments of the present invention provide for forming a recess within the semiconductor substrate prior to forming the material that is to be covered by the resist. For such embodiments, the material can be formed to partially fill the recess and extend outward over an upper surface of the semiconductor substrate. The resist layer can be formed within the partially filled recess.
- A suitable semiconductor substrate can encompass a semiconductive portion and an overlying insulative portion. For embodiments that encompass a recess, such recess can be formed within the insulative portion. In some embodiments the recess extends to expose, at a bottom and/or sidewalls of the recess, a portion of the semiconductive portion or a portion of a conductive device formed over or in the semiconductive portion. Where the material encompasses a conductive material, electrical communication between the conductive material and the semiconductive portion or conductive device can be provided through the bottom or sidewalls of the recess. In some embodiments of the present invention, the material can include more than one layer. For example, the material can encompass a first layer of a first composition and a second layer of a second composition overlying the first layer. The two compositions can be, for example, a first composition comprising metal, nitrogen, and silicon (such as TaSiN); and a second composition consisting essentially of metal and nitrogen (such as TaN).
- Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
-
FIG. 1 is a diagrammatic, cross-sectional, fragmentary view of a construction at a preliminary stage of an exemplary semiconductor fabrication process. -
FIG. 2 is a view of theFIG. 1 construction at a processing stage subsequent to that ofFIG. 1 . -
FIG. 3 is a view of theFIG. 1 construction at a processing stage subsequent to that ofFIG. 2 . -
FIG. 4 is a diagrammatic, cross-sectional, fragmentary view of a construction at a preliminary stage of a fabrication process of forming a barrier layer. -
FIG. 5 is a cross-sectional representation of a portion of a semiconductor substrate at an early process stage of an exemplary embodiment of the present invention. -
FIG. 6 is a cross-sectional representation of the portion of a semiconductor substrate depicted inFIG. 5 at a subsequent process stage of an exemplary embodiment of the present invention. -
FIG. 7 is a cross-sectional representation of the portion of a semiconductor substrate depicted inFIG. 6 at a subsequent process stage of an exemplary embodiment of the present invention. -
FIG. 8 is a cross-sectional representation of the portion of a semiconductor substrate depicted inFIG. 7 at a subsequent process stage of an exemplary embodiment of the present invention. -
FIGS. 9A and 9B are cross-sectional representations of the portion of a semiconductor substrate depicted inFIG. 8 at alternate subsequent process stages of exemplary embodiments of the present invention. -
FIG. 10 is a cross-sectional representation of the portion of a semiconductor substrate depicted inFIG. 9A at a subsequent process stage of an exemplary embodiment of the present invention. -
FIG. 11 is a cross-sectional representation of an integrated capacitor structure formed employing methods of exemplary embodiments of the present invention. - This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
- The present invention can encompass methods of polishing resist to remove the resist from over conductive materials. An exemplary embodiment of the present invention is described with reference to
FIGS. 1-3 . - Referring to
FIG. 1 , aconstruction 100 comprises amass 102 having anopening 104 extending therein.Mass 102 can comprise an insulative material such as, for example, borophosphosilicate glass (BPSG) and/or silicon dioxide deposited from TEOS, and can be supported by a semiconductor substrate (not shown). To aid in interpretation of the description of the illustrations and claims that follow, the term “semiconductor substrate” is defined to mean any construction encompassing silicon semiconductive material, including, but not limited to, bulk silicon semiconductive materials such as a silicon semiconductor wafer (either alone or in assemblies encompassing other materials thereon) and silicon semiconductive material layers (either alone or in assemblies encompassing other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. - A metal-containing
layer 106 extends overmass 102 and withinopening 104.Layer 106 can consist essentially of, for example, platinum or a platinum-containing alloy. Alayer 108 is formed overlayer 106.Layer 108 can comprise, for example, photoresist, and fillsopening 104. - Referring to
FIG. 2 ,layer 108 is polished from overlayer 106 to expose portions oflayer 106proximate opening 104. Thelayer 108 is not, however, removed from withinopening 104. The polishing oflayer 108 preferably utilizes a polishing pad in combination with a solution substantially lacking in particulates. Accordingly, in particular aspects of the invention, the polishing oflayer 108 occurs through mechanical action of the pad alone. The polishing proceeds throughlayer 108, but stops onlayer 106. The polishing can be accomplished with little, if any, smearing or scratching oflayer 106. It is noted that in some aspects of the invention the polishing solution can consist essentially of water, and in other aspects the polishing solution can comprise a combination of chemicals. For instance, the solution can comprise a combination of water and a base (such as, for example, TMAH), so that the solution has a basic pH. - Referring to
FIG. 3 , the exposed portions oflayer 106 are removed with a dry etch. In subsequent processing (not shown), resist 108 can be removed from within opening 104 by, for example, ashing. - A process similar to that described with reference to
FIGS. 1-3 can be utilized for etching of various so-called barrier layers. Barrier layers are provided, for example, to alleviate diffusion of Si and O at elevated temperatures, and can be incorporated into various capacitor structures. An exemplary material which can be utilized as a barrier layer is TaSixNy (which can also be referred to herein as TaSiN, with the Ta, Si and N of the representation “TaSiN” referring to the elements contained within the designated compound and not to any particular stoichiometric relationship of the elements). - A barrier layer fabrication process is described with reference to
FIG. 4 . Specifically,FIG. 4 shows aconstruction 120 comprising amass 122 having anopening 124 extending therein.Mass 122 can comprise an insulative material such as, for example, silicon dioxide, and can be supported by a semiconductor substrate (not shown). Abarrier layer 126 extends overmass 122 and withinopening 124.Layer 126 can comprise, for example, TaSixNy. Alayer 128 is formed overlayer 126.Layer 128 can comprise, for example, photoresist, and fillsopening 124. - Ultimately, the
barrier layer material 126 is to be removed from over an uppermost surface ofmass 122, but left withinopening 124. Such can be accomplished with processing analogous to that discussed above with reference toFIGS. 1-3 . -
FIG. 5 depicts a cross-sectional representation of a portion of asemiconductor substrate 10 having aninsulative portion 14 disposed over asemiconductive substrate 12.Insulative portion 14 can encompass one or more layers of a variety of exemplary materials such as, for example, silicon oxide, silicon nitride and silicon oxynitride. In particular embodiments of the present invention,portion 14 encompasses a BPSG (BoroPhosphoSilicate Glass) material or a TEOS-deposited silicon dioxide.Semiconductive portion 12 can encompass a single crystal silicon material. - Referring to
FIG. 6 ,structure 10 is illustrated after arecess 20 is formed withinportion 14.Recess 20 is typically formed by a patterning process that encompasses a masking step and an etching step.Recess 20 has a bottom 22 andsidewalls 24. As depicted, bottom 22 is elevationally at anupper surface 16 ofsemiconductive substrate 12. However, such is illustrative only and it will be understood that in some embodiments of the present invention bottom 22 is elevationally above and displaced fromupper surface 16. For example, in some embodiments, bottom 22 can be at an upper surface of an integrated circuit device such as a conductive line disposed on semiconductive substrate 12 (not shown). After formingrecess 20, a layer ofmaterial 30 is formed oversubstrate 10.Material 30 is withinrecess 20 and extends laterally outward fromrecess 20 overinsulative portion 14. More specifically,material 30 is over bottom 22 and sidewalls 24 ofrecess 20, only partially fillingrecess 20. -
Material 30 can encompass conductive materials such as platinum (Pt), iridium (Ir), ruthenium (Ru), tantalum (Ta), titanium (Ti) and mixtures or alloys of such materials. In addition, or alternatively,material 30 can encompass oxides, nitrides and silicides of various metals. For example, in some embodiments in accordance with the present invention,material 30 encompasses one or more of a platinum-ruthenium alloy, ruthenium oxide (RuO), tantalum silicon nitride (TaSiN) or ruthenium silicide (RuSi). In addition, it will be understood that for some embodiments of the present invention,material 30 is formed of more than one layer. In one exemplary embodiment of the present invention, a barrier layer (not shown) such as a tantalum silicon nitride (TaSiN) material is first formed overinsulative portion 14 and withinrecess 20 and a second layer of electrode material (not shown) such as tantalum nitride (TaN) is second formed over the barrier layer and withinrecess 20. - In particular aspects of the invention,
material 30 can comprises a tantalum-containing mass. Such mass can include one or both of silicon and nitrogen in addition to the tantalum. - Referring to
FIG. 7 , alayer 40 comprising, consisting essentially of or consisting of, an organic material (such as an organic polymer), is depicted oversubstrate 10. Specifically,layer 40 is formed overmaterial 30 and fillsrecess 20.Layer 40 can, in particular applications, comprise, consist essentially of, or consist of, a photoresist material. For example,layer 40 can comprise an exemplary photoresist material designated OiR 897 10i™ and manufactured by Arch Microelectronics, of Norwalk, Conn. Additionally, or alternatively,layer 40 can comprise resist compositions formed without a photosensitive component (non-photosensitive resists) and/or polyimide materials. - Resist or
organic material layer 40 can be formed using any of several appropriate process methods, for example by spin coating, spraying or dip-coating. In this manner a generallyuniform layer 40 is provided that advantageously fills recess 20 (FIG. 6 ) as depicted. Afterlayer 40 is formed, it can be subjected to what is commonly referred to as a “hard” bake. The specific processing conditions for the application and baking of the material used to form resistlayer 40 will be understood, by one of ordinary skill in the semiconductor arts, to depend on the specific material employed for resistlayer 40. Thus where the exemplary OiR 897 10i™ material is used, it has been found advantageous to apply such material by a spin-coating process and to subsequently hard bake the layer at a temperature of from about 85 degrees Celsius (° C.) to about 100° C. for a period of time from several tens of seconds to several minutes in duration. - Referring to
FIG. 8 , the structure ofFIG. 7 is depicted after a portion of resistlayer 40 is removed. As shown, resistlayer 40 is removed such thatsegments 34 ofmaterial 30 outward of and adjacent to recess 20 are exposed and a resistplug 42 withinrecess 20 is formed.Layer 40 has thus been removed selectively relative tomaterial 30. - The removal of the portion of resist or
organic material layer 40 can be accomplished by providing contact of a chemical mechanical polishing pad and a polishing fluid (not shown) with resistlayer 40. The term “chemical mechanical polishing (CMP) pad” refers to a construction traditionally employed for performing chemical mechanical polishing. Such constructions can include pads used in a system for chemical mechanical polishing where the CMP pad is provided to have at least one of rotational motion about an axis and linear motion along an axis. CMP pads utilized with embodiments of the present invention can encompass a polyurethane material and are manufactured by, for example, Rodel Products of Phoenix, Ariz. and Thomas West, Inc. of Sunnyvale, Calif. Chemical mechanical polishing systems that provide the at least one of linear motion and rotational motion include, for example, the TERES™ CMP System manufactured by LAM Research Corporation of Fremont, Calif. and the MIRRA MESA ADVANCED INTEGRATED CMP SYSTEM™ manufactured by Applied Materials, Inc., of Santa Clara, Calif., respectively. Exemplary pads are those formed of a rigid or semi-rigid microporous polyurethane material, or polyurethane-impregnated polyester material or a combination of such materials, although other appropriate materials can be used. The specific pad employed will depend, in part, on the specific resist material employed and the conditions at which the selected resist material was processed to formlayer 40. It is noted that harder pads can induce a faster CMP removal rate of resist than softer pads through increased mechanical action. However, the harder pads may also create more scratches than softer pads to anunderlying material 34. Accordingly, the physical characteristics of a polishing pad can be chosen to balance a desired removal rate with an acceptable level of scratching inmaterial 34. - In addition to the pad characteristics, the nature of the polishing fluid employed in contact with both the CMP pad and resist
layer 40 can be a factor in determining an advantageous CMP pad material and/or construction. Accordingly, it can be desired to adjust a pH of the polishing fluid to a desired range. In particular applications, TMAH can be utilized in a polishing solution when a basic pH is desired. - Chemical mechanical polishing is known in the art to be suitable for removing a wide variety of materials. Typically such materials are hard materials such as silicon oxide, silicon nitride, polycrystalline silicon and the like. While the polyurethane material typically employed to form CMP pads has some degree of roughness, material removal effected by such pads is believed the result, in significant part, of abrasive particles that are typically included into the polishing fluid or slurry and not the pad itself. In addition, the polishing fluid typically encompasses a material that is chemically reactive with regard to the materials being polished and thus is also generally significant in the removal of a material. Thus CMP is the combined action of (1) the chemical reactivity between the fluid and the materials being polished or removed, (2) the abrasiveness of the included particles, and (3) the effect of the CMP pad to create a pressure of contact and a linear velocity, in excess of zero, of that contact through which (1) and (2) can interact with the material being polished and/or removed.
- Embodiments of the present invention, however, can employ a polishing fluid that is selected to be essentially unreactive with both resist or
organic material layer 40 andconductive material layer 30. In addition, such fluid is typically provided having few, if any, particles. Exemplary materials for such a polishing fluid include, water having essentially no particles, or an aqueous based polishing fluid having silica-comprising particles where the concentration of such particles is less than or equal to 0.1% by weight. Thus absent the chemical reactivity and the abrasiveness of included particles, it is theorized that the principle mechanism for the removal of resistlayer 40 is the abrasiveness of the CMP pad and the pressure with which suchpad contacts layer 40. Advantageously, it is found that where such a polishing fluid and CMP pad are used for removing resistlayer 40 to expose substantially all ofupper surfaces 32 ofmaterial 30, the absence of particles in the polishing fluid and the generally unreactive nature of the polishing fluid itself, provide thatupper surfaces 32 are essentially unpolished. That is to say that exposedportions 34 ofmaterial 30 act essentially as an etch or polish stop layer and resist removal is essentially stopped with the forming of resistplug 42. It will be understood, as the polishing fluid employed by embodiments of the present invention use little or no particulates in the polishing fluid, that when resistlayer 40 is removed to exposeupper surface 32, there is little or no removal of such material. Thus scratches and/or smears are essentially or entirely eliminated. - It is noted that particles can be generated during polishing of a resist, with the particles corresponding to removed fragments of the resist. In particular applications of the invention, a total amount of particles within a fluid utilized for removing resist, other than particles generated from the removal of the resist, is less than or equal to 0.1%, by weight, of a polishing fluid. In some embodiments the number of particles in the fluid, other than particles generated from resist removal, is 0%, or in other words, non-detectable.
- In particular aspects of the invention, chemical reactivity of a polishing fluid can be enhanced by, for example, shifting a pH of the polishing fluid. Such can be accomplished by, for example, incorporating one or both of ammonia and TMAH within the polishing fluid. Preferably, the increase in chemical reactivity of the polishing fluid will be relative to mass 40 (
FIG. 7 ) and notmaterial 30. Accordingly, removal ofmass 40 relative tomaterial 30 will be further enhanced by the additional chemical reactivity of the polishing fluid. In applications in whichmaterial 30 comprises platinum andmass 40 comprises photoresist, it can be desirable to include one or both of ammonia and TMAH in the polishing fluid to obtain a pH of the polishing fluid of from about 8 to about 12. - While various organic materials are appropriate for forming resist
layer 40, and while various polishing fluids, CMP pad materials and the like can be selected for removinglayer 40 from overmaterial 30adjacent recess 20 to form the structure depicted inFIG. 4 , it has been found advantageous where an OiR 897 10i™ resist is selected and formed employing a hard bake step at a temperature of about 92° C. for about 60 seconds, to use a Rodel IC1000™ or 1400 CMP™ pad, or Sycamore OXP™ pad, and a polishing fluid having an initial particulate concentration of less than or equal to 0.1% by weight for the removal. As one of skill in the semiconductor arts will understand, where other materials and process conditions are employed for forming resist layer 40 (FIG. 3 ), tailoring CMP processing conditions to formplug 42 and to exposeportions 34 ofmaterial 30 is made possible by this disclosure. - In some embodiments of the present invention, an apparatus to determine a resist removal endpoint is employed. For example, the torque required to provide motion of the CMP pad with respect to the substrate will vary when
material 30 becomes substantially exposed, that is to say, when essentially all of the resist layer is removed from overupper surfaces 32 ofmaterial 30. Thus an apparatus for monitoring changes in torque can be effective for determining the endpoint. Other methods and devices for determining endpoint are also possible. For example, asmaterial 30 becomes exposed, the reflectivity ofsubstrate 10 will change. Thus an apparatus for monitoring reflectivity can also be effective for determining the endpoint of the resist removal. - Referring to
FIG. 9A , the structure ofFIG. 8 is shown at one alternate, subsequent processing stage. The exposedportions 34 of layer 30 (FIG. 8 ) are removed defining aportion 36 a oflayer 30 withinrecess 20 as well as an essentially planar upper surface 16 a ofsemiconductor substrate 10 laterallyadjacent recess 20.Exposed portions 34 can be removed employing a chemical mechanical polishing method where a second polishing fluid or slurry is provided, replacing the polishing fluid used for removing the resist, once the structure ofFIG. 8 is formed. In other embodiments, both the polishing fluid and CMP pad are changed. It will be understood that such changes of the polishing fluid and/or the CMP pad can be effected at a single polishing station or by movingsubstrate 10 to an alternate station, where such alternate station has the changed material(s). - Second polishing fluid, and where employed a second CMP pad, are selected to provide effective removal of exposed portions of layer 34 (
FIG. 8 ). Thus the second fluid is different from the first fluid in that it typically has an increased initial concentration of particles and will typically be chemically reactive to the conductive material oflayer 34. Where a second CMP pad is used, such second pad is compatible with the second fluid. In addition, the second fluid will typically have an enhanced reactivity toward the material of exposedportions 34 being removed, as compared to the first fluid's general absence of reactivity to the material of exposedportions 34. - It will be noted while the CMP processing used to remove exposed
portions 34 can also remove some of resist plug 42 a, such plug advantageously serves to protectrecess 20. That is to say, if the removal of exposed portions 34 (FIG. 8 ) during a CMP process results in scratches or smearing of the material ofportions 34, resist plug 42 a prevents such scratches and smears from effecting the structure formed withinrecess 20. In other words, resist plug 42 a can prevent the removed material of exposedportions 34 from enteringrecess 20 during CMP removal of such exposed portions and coming in contact with or being proximate toportions 36 a. - In a particular aspect of the invention the processing of
FIGS. 5-9A is utilized in formation of a material 34 comprising TaSiN and/or TaN (with the materials being described in terms of the atoms comprised by the materials rather than any particular stoichiometry). The polish utilized to remove resist 40 between the stage ofFIG. 7 and that ofFIG. 8 is a first polish comprising substantially no particles in the polishing fluid. The polish utilized to removematerial 30 in proceeding from the stage ofFIG. 8 to that ofFIG. 9A is a second polish utilizing particles. An exemplary polish for proceeding from the stage ofFIG. 8 to that ofFIG. 9A utilizes a polishing slurry comprising a material available from Hitachi as T605™, together with from about 0.1 wt % to about 0.5 wt % H2O2. The polishing of resist 40 thus utilizes a solution tailored to remove resist 40, and the polishing ofmaterial 30 utilizes a solution tailored to removematerial 30. Accordingly, the removal of each ofmaterials materials FIG. 7 to that ofFIG. 9A . -
FIG. 9B depicts an alternate embodiment where exposed portions 34 (FIG. 8 ) are removed using a chemical or a plasma etching method. As depicted, a raisedplug 42 b is seen to extend upward from surface 16 b ofsubstrate 10. Thus subsequent to the forming of resistplug 42 and exposed portions 34 (FIG. 8 ),substrate 10 is either exposed to a chemical solution or plasma that removes the material of such exposed portions. Such chemical solution or plasma is selected to be essentially unreactive with respect to the resist material and thus a raisedplug 42 b is formed. Analogous to what was seen for the structure ofFIG. 9A , plug 42 b serves to protectportion 36 b withinrecess 20. - Referring to
FIG. 10 , a structure is illustrated subsequent to the processing ofFIGS. 9A or 9B, and specifically, subsequent to the removal of resistplugs 42 a or 42 b.Plugs 42 a or 42 b can be removed by employing a chemical solution or plasma tailored to remove the material of the plugs. Where plugs 42 a and/or 42 b are a photoresist material, one exemplary removal method is an oxygen plasma, although any appropriate method can be used. As seen,material layer 30 is transformed intolayer 36 entirely withinrecess 20 and adjacent bottom 22 and sidewalls 24 ofsuch recess 20.Layer 36 can be, for example, an electrode of a capacitor structure, some or all of which to be formed withinrecess 20. Advantageously, the structure depicted inFIG. 10 has been formed without a photomasking step subsequent to the forming ofrecess 20. Rather, as shown above, the patterning to formlayer 36 withinrecess 20 can be accomplished, in some embodiments, using essentially blanket depositions and CMP processing only. In other embodiments, chemical or plasma processing can be used, after the forming of plug 42 (FIG. 8 ), to definelayer 36 as discussed above, also without the need for a photomasking step. - Referring to
FIG. 11 , a portion of asemiconductor substrate 10 a encompassing a semiconductive portion 12 a and overlyinginsulative portions 15 is depicted. A portion of acapacitor structure 70, in accordance with embodiments of the present invention, is shown disposed within an upper, second formed portion of insulative layers 15. - Within semiconductive portion 12 a is a
conductive node 64, disposed laterally between and elevationally belowconductive line structures 62.Conductive plug 60 is depicted disposed above and in electrical communication withconductive node 64. Whereconductive plug 60 encompasses a doped polysilicon material, generally a contactenhancement material layer 55 encompassing a metal silicide (such as titanium silicide) is disposed over and in electrical communication with the polysilicon ofconductive plug 60. - Turning to
capacitor structure 70, disposed within an upper or second formed part ofinsulative portion 15, such encompassesrecess 20 having amaterial layer 36 c formed therein.Recess 20 being formed in a manner analogous to the methods previously discussed with regard toFIG. 6 , andmaterial layer 36 c being formed and subsequently defined in a manner analogous to the defining oflayer 36 fromlayer 30 inFIGS. 9A or 9B.Material layer 36 c, however, encompasses a diffusion barrier material and can be formed of a single such diffusion barrier material, or alternatively of such a barrier material and a conductive material, such as described previously forlayer 30. Exemplary diffusion barrier materials include, among others, tantalum nitride and/or tantalum silicon nitride, while exemplary conductive materials include, among others, materials comprising Pt, Ru, Ta and mixtures or alloys thereof. It will be understood that while exemplary materials forlayer 36 c are provided, other barrier materials and/or combinations of barrier materials and conductive materials other can also be employed. Any and all of such materials can be formed by appropriate methods such as chemical vapor deposition of physical vapor deposition methods. - Typically where
capacitor structure 70 employs a high dielectricconstant material layer 50, barrier layer material is provided withinlayer 36 c to reduce and/or eliminate any reactive interactions, for example between such dielectric material and the material ofplug 60 or the material ofinsulative portion 15 or any other such interaction between materials in communication with one another. Exemplary high dielectric constant materials employed forlayer 50 include, but are not limited to, Al2O3, Ta2O5, and barium strontium titanate (BST). As depicted,layer 50 does not fillrecess 20 and a secondcapacitor electrode layer 54 is shown formed and patterned. Such second electrode layer generally encompasses a material similar to that of material layer 36 (FIG. 9A ). Advantageously the structure depicted forcapacitor structure 70 is formed by methods analogous to those previously described with respect toFIGS. 5-10 . - It will be recognized that embodiments of the present invention include methods for forming capacitor structures and removing resist that provide for the removal of portions of a material without preventing the proper forming of a desired capacitor structure. Embodiments of the present invention can also provide for reduced scratching and smearing of electrode materials by removing portions of the resist without the use of particulates within a polishing fluid or in the alternative with very low initial concentrations of particulates. In this manner, little or no scratching or smearing occurs as conductive materials are exposed. In addition, embodiments of the present invention can provide a CMP method that eliminates the use of a photomasking step for patterning at least one capacitor electrode. As is known, the removal of a photomasking step can serve to reduce processing costs and generally to increase process yield.
- In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.
Claims (21)
1-53. (canceled)
54. Removing carbon-comprising material from above a substrate with a pad and a fluid, the fluid comprising a particulate concentration of less than or equal to about 0.1 weight percent at an initiation of the removing.
55. The removing of claim 54 wherein, the pad is a chemical-mechanical-polishing pad.
56. The removing of claim 54 wherein, the substrate is semiconductive.
57. The removing of claim 54 wherein, the fluid is substantially unreactive with the substrate.
58. The removing of claim 54 wherein, the carbon-comprising material also comprises both oxygen and hydrogen.
59. The removing of claim 54 wherein, the carbon-comprising material comprises a resist-material.
60. A carbon-comprising material removal system, comprising:
a substrate support configured to support a substrate having a carbon-comprising material thereon;
a pad configured to physically contact the carbon-comprising material; and
a fluid source, the fluid source configured to provide a fluid to a location between the pad and the material, the fluid comprising a particulate concentration of less than or equal to about 0.1 weight percent.
61. The system of claim 60 wherein the substrate comprises both semiconductive material and conductive material, the conductive material forming a surface of the substrate and having the carbon-comprising material thereon.
62. The system of claim 60 wherein the pad is a chemical-mechanical-polishing pad.
63. The system of claim 62 wherein the pad includes a surface facing the carbon-comprising material, the surface of the pad comprising a polyurethane-material.
64. The system of claim 60 wherein the pad is configured to rotate about an axis.
65. The system of claim 60 wherein the pad is configured to have linear motion along an axis.
66. The system of claim 60 wherein the fluid comprises an additive, the additive being both reactive with the carbon-comprising material and unreactive with the substrate.
67. The system of claim 66 wherein the additive comprises TMAH.
68. An integrated circuitry manufacturing process, comprising:
applying a mask above a semiconductive substrate;
creating a recess within the substrate using the mask; and
removing at least a portion of the mask with a pad and fluid, the fluid substantially lacking in particulates.
69. The process of claim 68 wherein substrate comprises a conductive material and a semiconductive material, the conductive material being a surface of the substrate and contacting the mask.
70. The process of claim 68 wherein the recess is created in at least the conductive material.
71. The process of claim 68 wherein during the removing of the portion of the mask the fluid does not react with the conductive material.
72. The process of claim 68 wherein the mask comprises one of photoresist material or non-photosensitive resist material.
73. The process of claim 68 wherein the mask comprises a polyimide material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/602,744 US20070066011A1 (en) | 2002-04-25 | 2006-11-20 | Integrated circuitry production processes, methods, and systems |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/134,201 US6706632B2 (en) | 2002-04-25 | 2002-04-25 | Methods for forming capacitor structures; and methods for removal of organic materials |
US10/734,995 US7226863B2 (en) | 2002-04-25 | 2003-12-12 | Methods for removal of organic materials |
US11/499,096 US7273816B2 (en) | 2002-04-25 | 2006-08-02 | Methods for removal of organic materials |
US11/602,744 US20070066011A1 (en) | 2002-04-25 | 2006-11-20 | Integrated circuitry production processes, methods, and systems |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/499,096 Continuation US7273816B2 (en) | 2002-04-25 | 2006-08-02 | Methods for removal of organic materials |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070066011A1 true US20070066011A1 (en) | 2007-03-22 |
Family
ID=29249166
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/134,201 Expired - Fee Related US6706632B2 (en) | 2002-04-25 | 2002-04-25 | Methods for forming capacitor structures; and methods for removal of organic materials |
US10/734,995 Expired - Fee Related US7226863B2 (en) | 2002-04-25 | 2003-12-12 | Methods for removal of organic materials |
US11/208,793 Expired - Fee Related US7115515B2 (en) | 2002-04-25 | 2005-08-22 | Methods for forming capacitor structures |
US11/499,096 Expired - Fee Related US7273816B2 (en) | 2002-04-25 | 2006-08-02 | Methods for removal of organic materials |
US11/602,744 Abandoned US20070066011A1 (en) | 2002-04-25 | 2006-11-20 | Integrated circuitry production processes, methods, and systems |
Family Applications Before (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/134,201 Expired - Fee Related US6706632B2 (en) | 2002-04-25 | 2002-04-25 | Methods for forming capacitor structures; and methods for removal of organic materials |
US10/734,995 Expired - Fee Related US7226863B2 (en) | 2002-04-25 | 2003-12-12 | Methods for removal of organic materials |
US11/208,793 Expired - Fee Related US7115515B2 (en) | 2002-04-25 | 2005-08-22 | Methods for forming capacitor structures |
US11/499,096 Expired - Fee Related US7273816B2 (en) | 2002-04-25 | 2006-08-02 | Methods for removal of organic materials |
Country Status (1)
Country | Link |
---|---|
US (5) | US6706632B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110193150A1 (en) * | 2010-02-05 | 2011-08-11 | Hynix Semiconductor Inc. | Semiconductor device including reservoir capacitor and method of manufacturing the same |
Families Citing this family (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6590468B2 (en) * | 2000-07-20 | 2003-07-08 | Paratek Microwave, Inc. | Tunable microwave devices with auto-adjusting matching circuit |
US8744384B2 (en) | 2000-07-20 | 2014-06-03 | Blackberry Limited | Tunable microwave devices with auto-adjusting matching circuit |
US8064188B2 (en) | 2000-07-20 | 2011-11-22 | Paratek Microwave, Inc. | Optimized thin film capacitors |
US6774042B1 (en) * | 2002-02-26 | 2004-08-10 | Taiwan Semiconductor Manufacturing Company | Planarization method for deep sub micron shallow trench isolation process |
US6706632B2 (en) * | 2002-04-25 | 2004-03-16 | Micron Technology, Inc. | Methods for forming capacitor structures; and methods for removal of organic materials |
KR100688493B1 (en) * | 2003-06-17 | 2007-03-02 | 삼성전자주식회사 | Metal-insulator-metal capacitor having poly-silicon contact plug and method for manufacturing the same |
US7161247B2 (en) * | 2004-07-28 | 2007-01-09 | Cabot Microelectronics Corporation | Polishing composition for noble metals |
US9406444B2 (en) | 2005-11-14 | 2016-08-02 | Blackberry Limited | Thin film capacitors |
US8125399B2 (en) | 2006-01-14 | 2012-02-28 | Paratek Microwave, Inc. | Adaptively tunable antennas incorporating an external probe to monitor radiated power |
US7711337B2 (en) | 2006-01-14 | 2010-05-04 | Paratek Microwave, Inc. | Adaptive impedance matching module (AIMM) control architectures |
US8325097B2 (en) * | 2006-01-14 | 2012-12-04 | Research In Motion Rf, Inc. | Adaptively tunable antennas and method of operation therefore |
US7714676B2 (en) | 2006-11-08 | 2010-05-11 | Paratek Microwave, Inc. | Adaptive impedance matching apparatus, system and method |
US7535312B2 (en) | 2006-11-08 | 2009-05-19 | Paratek Microwave, Inc. | Adaptive impedance matching apparatus, system and method with improved dynamic range |
US8299867B2 (en) * | 2006-11-08 | 2012-10-30 | Research In Motion Rf, Inc. | Adaptive impedance matching module |
US7917104B2 (en) * | 2007-04-23 | 2011-03-29 | Paratek Microwave, Inc. | Techniques for improved adaptive impedance matching |
US8213886B2 (en) | 2007-05-07 | 2012-07-03 | Paratek Microwave, Inc. | Hybrid techniques for antenna retuning utilizing transmit and receive power information |
US7991363B2 (en) | 2007-11-14 | 2011-08-02 | Paratek Microwave, Inc. | Tuning matching circuits for transmitter and receiver bands as a function of transmitter metrics |
US8072285B2 (en) | 2008-09-24 | 2011-12-06 | Paratek Microwave, Inc. | Methods for tuning an adaptive impedance matching network with a look-up table |
US8472888B2 (en) | 2009-08-25 | 2013-06-25 | Research In Motion Rf, Inc. | Method and apparatus for calibrating a communication device |
US9026062B2 (en) * | 2009-10-10 | 2015-05-05 | Blackberry Limited | Method and apparatus for managing operations of a communication device |
US8803631B2 (en) | 2010-03-22 | 2014-08-12 | Blackberry Limited | Method and apparatus for adapting a variable impedance network |
US8860526B2 (en) | 2010-04-20 | 2014-10-14 | Blackberry Limited | Method and apparatus for managing interference in a communication device |
US9379454B2 (en) | 2010-11-08 | 2016-06-28 | Blackberry Limited | Method and apparatus for tuning antennas in a communication device |
US8712340B2 (en) | 2011-02-18 | 2014-04-29 | Blackberry Limited | Method and apparatus for radio antenna frequency tuning |
US8655286B2 (en) | 2011-02-25 | 2014-02-18 | Blackberry Limited | Method and apparatus for tuning a communication device |
US8594584B2 (en) | 2011-05-16 | 2013-11-26 | Blackberry Limited | Method and apparatus for tuning a communication device |
US8626083B2 (en) | 2011-05-16 | 2014-01-07 | Blackberry Limited | Method and apparatus for tuning a communication device |
WO2013022826A1 (en) | 2011-08-05 | 2013-02-14 | Research In Motion Rf, Inc. | Method and apparatus for band tuning in a communication device |
US8618661B2 (en) * | 2011-10-03 | 2013-12-31 | Texas Instruments Incorporated | Die having coefficient of thermal expansion graded layer |
US8948889B2 (en) | 2012-06-01 | 2015-02-03 | Blackberry Limited | Methods and apparatus for tuning circuit components of a communication device |
US8963134B2 (en) * | 2012-06-15 | 2015-02-24 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Display panel and method for manufacturing the same |
US9853363B2 (en) | 2012-07-06 | 2017-12-26 | Blackberry Limited | Methods and apparatus to control mutual coupling between antennas |
US9246223B2 (en) | 2012-07-17 | 2016-01-26 | Blackberry Limited | Antenna tuning for multiband operation |
US9350405B2 (en) | 2012-07-19 | 2016-05-24 | Blackberry Limited | Method and apparatus for antenna tuning and power consumption management in a communication device |
US9413066B2 (en) | 2012-07-19 | 2016-08-09 | Blackberry Limited | Method and apparatus for beam forming and antenna tuning in a communication device |
US9362891B2 (en) | 2012-07-26 | 2016-06-07 | Blackberry Limited | Methods and apparatus for tuning a communication device |
US10404295B2 (en) | 2012-12-21 | 2019-09-03 | Blackberry Limited | Method and apparatus for adjusting the timing of radio antenna tuning |
US9374113B2 (en) | 2012-12-21 | 2016-06-21 | Blackberry Limited | Method and apparatus for adjusting the timing of radio antenna tuning |
US9438319B2 (en) | 2014-12-16 | 2016-09-06 | Blackberry Limited | Method and apparatus for antenna selection |
US9604338B2 (en) * | 2015-08-04 | 2017-03-28 | Texas Instruments Incorporated | Method to improve CMP scratch resistance for non planar surfaces |
KR102447178B1 (en) | 2015-09-01 | 2022-09-26 | 삼성전자주식회사 | Methods of manufacturing semiconductor devices |
US11508585B2 (en) * | 2020-06-15 | 2022-11-22 | Taiwan Semiconductor Manufacturing Company Ltd. | Methods for chemical mechanical polishing and forming interconnect structure |
FR3115926B1 (en) * | 2020-11-03 | 2023-06-09 | St Microelectronics Rousset | Integrated circuit comprising a capacitive structure of the metal-insulator-metal type and corresponding manufacturing method |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3778530A (en) * | 1971-04-01 | 1973-12-11 | W Reimann | Flatpack lead positioning device |
US5391511A (en) * | 1992-02-19 | 1995-02-21 | Micron Technology, Inc. | Semiconductor processing method of producing an isolated polysilicon lined cavity and a method of forming a capacitor |
US6281535B1 (en) * | 1999-01-22 | 2001-08-28 | Agilent Technologies, Inc. | Three-dimensional ferroelectric capacitor structure for nonvolatile random access memory cell |
US6416685B1 (en) * | 2000-04-11 | 2002-07-09 | Honeywell International Inc. | Chemical mechanical planarization of low dielectric constant materials |
US6431953B1 (en) * | 2001-08-21 | 2002-08-13 | Cabot Microelectronics Corporation | CMP process involving frequency analysis-based monitoring |
US6468858B1 (en) * | 2001-03-23 | 2002-10-22 | Taiwan Semiconductor Manufacturing Company | Method of forming a metal insulator metal capacitor structure |
US6706632B2 (en) * | 2002-04-25 | 2004-03-16 | Micron Technology, Inc. | Methods for forming capacitor structures; and methods for removal of organic materials |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999055493A1 (en) * | 1998-04-28 | 1999-11-04 | Ebara Corporation | Polishing grinding wheel and substrate polishing method with this grinding wheel |
US6206759B1 (en) * | 1998-11-30 | 2001-03-27 | Micron Technology, Inc. | Polishing pads and planarizing machines for mechanical or chemical-mechanical planarization of microelectronic-device substrate assemblies, and methods for making and using such pads and machines |
JP2000349255A (en) * | 1999-06-03 | 2000-12-15 | Oki Electric Ind Co Ltd | Semiconductor storage device and manufacture thereof |
US7112121B2 (en) * | 2000-08-30 | 2006-09-26 | Micron Technology, Inc. | Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a microelectronic substrate |
US20030162399A1 (en) * | 2002-02-22 | 2003-08-28 | University Of Florida | Method, composition and apparatus for tunable selectivity during chemical mechanical polishing of metallic structures |
-
2002
- 2002-04-25 US US10/134,201 patent/US6706632B2/en not_active Expired - Fee Related
-
2003
- 2003-12-12 US US10/734,995 patent/US7226863B2/en not_active Expired - Fee Related
-
2005
- 2005-08-22 US US11/208,793 patent/US7115515B2/en not_active Expired - Fee Related
-
2006
- 2006-08-02 US US11/499,096 patent/US7273816B2/en not_active Expired - Fee Related
- 2006-11-20 US US11/602,744 patent/US20070066011A1/en not_active Abandoned
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3778530A (en) * | 1971-04-01 | 1973-12-11 | W Reimann | Flatpack lead positioning device |
US5391511A (en) * | 1992-02-19 | 1995-02-21 | Micron Technology, Inc. | Semiconductor processing method of producing an isolated polysilicon lined cavity and a method of forming a capacitor |
US6281535B1 (en) * | 1999-01-22 | 2001-08-28 | Agilent Technologies, Inc. | Three-dimensional ferroelectric capacitor structure for nonvolatile random access memory cell |
US6416685B1 (en) * | 2000-04-11 | 2002-07-09 | Honeywell International Inc. | Chemical mechanical planarization of low dielectric constant materials |
US6468858B1 (en) * | 2001-03-23 | 2002-10-22 | Taiwan Semiconductor Manufacturing Company | Method of forming a metal insulator metal capacitor structure |
US6431953B1 (en) * | 2001-08-21 | 2002-08-13 | Cabot Microelectronics Corporation | CMP process involving frequency analysis-based monitoring |
US6706632B2 (en) * | 2002-04-25 | 2004-03-16 | Micron Technology, Inc. | Methods for forming capacitor structures; and methods for removal of organic materials |
US7115515B2 (en) * | 2002-04-25 | 2006-10-03 | Micron Technology, Inc. | Methods for forming capacitor structures |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110193150A1 (en) * | 2010-02-05 | 2011-08-11 | Hynix Semiconductor Inc. | Semiconductor device including reservoir capacitor and method of manufacturing the same |
US8470667B2 (en) * | 2010-02-05 | 2013-06-25 | Hynix Semiconductor Inc | Semiconductor device including reservoir capacitor and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
US7115515B2 (en) | 2006-10-03 |
US7226863B2 (en) | 2007-06-05 |
US20040127043A1 (en) | 2004-07-01 |
US20060270141A1 (en) | 2006-11-30 |
US20060003537A1 (en) | 2006-01-05 |
US6706632B2 (en) | 2004-03-16 |
US7273816B2 (en) | 2007-09-25 |
US20030203633A1 (en) | 2003-10-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7273816B2 (en) | Methods for removal of organic materials | |
US5753967A (en) | Damascene process for reduced feature size | |
US5700383A (en) | Slurries and methods for chemical mechanical polish of aluminum and titanium aluminide | |
US7208404B2 (en) | Method to reduce Rs pattern dependence effect | |
US6017803A (en) | Method to prevent dishing in chemical mechanical polishing | |
WO2003021661A2 (en) | Process for making a mim capacitor | |
KR20000023003A (en) | Combined chemical mechanical polishing and reactive ion etching process | |
JP3904578B2 (en) | Manufacturing method of semiconductor device | |
US20060261041A1 (en) | Method for manufacturing metal line contact plug of semiconductor device | |
US20040253809A1 (en) | Forming a semiconductor structure using a combination of planarizing methods and electropolishing | |
JP2005537646A (en) | Method for forming a conductive material in an opening and structure relating to the method | |
US7259093B2 (en) | Methods of forming a conductive contact through a dielectric | |
JP2003077921A (en) | Method for manufacturing semiconductor device | |
JP3487051B2 (en) | Method for manufacturing semiconductor device | |
US6576553B2 (en) | Chemical mechanical planarization of conductive material | |
JP3660511B2 (en) | Polishing method and semiconductor device manufacturing method | |
US20020180052A1 (en) | Polish or etch stop layer | |
US6841470B2 (en) | Removal of residue from a substrate | |
US6127259A (en) | Phosphoric acid process for removal of contact BARC layer | |
US6274480B1 (en) | Method of Fabricating semiconductor device | |
KR100230402B1 (en) | Capacitor of semiconductor device and manufacturing method thereof | |
US20030003747A1 (en) | Chemical mechanical polishing slurry for ruthenium titanium nitride and polishing process using the same | |
US20020001877A1 (en) | Interconnect formation in a semiconductor device | |
JPH09135007A (en) | Semiconductor device and semiconductor device manufacturing method | |
JP2004241508A (en) | Method of manufacturing semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: EXPRESSLY ABANDONED -- DURING EXAMINATION |