US20070114649A1 - Low Profile Stacking System and Method - Google Patents

Low Profile Stacking System and Method Download PDF

Info

Publication number
US20070114649A1
US20070114649A1 US11/626,318 US62631807A US2007114649A1 US 20070114649 A1 US20070114649 A1 US 20070114649A1 US 62631807 A US62631807 A US 62631807A US 2007114649 A1 US2007114649 A1 US 2007114649A1
Authority
US
United States
Prior art keywords
integrated circuit
substrate
joints
contacts
present
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/626,318
Inventor
Julian Partridge
James Cady
James Wilder
David Roper
James Wehrly
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Entorian Technologies Inc
Original Assignee
Entorian Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/005,581 external-priority patent/US6576992B1/en
Application filed by Entorian Technologies Inc filed Critical Entorian Technologies Inc
Priority to US11/626,318 priority Critical patent/US20070114649A1/en
Publication of US20070114649A1 publication Critical patent/US20070114649A1/en
Assigned to ENTORIAN TECHNOLOGIES, LP reassignment ENTORIAN TECHNOLOGIES, LP ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PARTRIDGE, JULIAN, WEHRLY, JAMES DOUGLAS, CADY, JAMES W., ROPER, DAVID L., WILDER, JAMES
Priority to US12/356,432 priority patent/US7626273B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387Flexible insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/147Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116Lead [Pb] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011Chemical cleaning, e.g. etching, flux
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/8121Applying energy for connecting using a reflow oven
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06579TAB carriers; beam leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06582Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586Housing with external bump or bump-like connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/107Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01051Antimony [Sb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/189Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/05Flexible printed circuits [FPCs]
    • H05K2201/056Folded around rigid support or component
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10689Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3463Solder compositions in relation to features of the printed circuit board or the mounting process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/361Assembling flexible printed circuits with other printed circuits
    • H05K3/363Assembling flexible printed circuits with other printed circuits by soldering

Definitions

  • the present invention related to mounting integrated circuit devices on substrates and to mounting integrated circuits on substrates employed in stacked modules.
  • solder paste is selectively applied to the integrated circuit device or substrate to which the IC is to be attached.
  • the device and substrate are exposed to reflow temperatures of approximately 220° C.
  • the device is, consequently, soldered to the substrate.
  • solder joints will re-melt during subsequent processing.
  • Common tin-lead solders start to melt as 183° C. and, when exposed to such temperatures and higher, the exposed joint may re-melt and become unreliable.
  • the present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules.
  • the contact pads of a packaged integrated circuit device are substantially exposed.
  • a solder past that includes higher temperature solder paste alloy is applied to a substrate or the contacts of the packaged device.
  • the integrated circuit device is positioned to contact the contacts of the substrate with the higher temperature solder alloy paste between.
  • Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints.
  • the formed joints are less subject to re-melting in subsequent processing steps.
  • the method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.
  • a first solder used to construct a stacked module has a higher melting point than a second solder used to populate a board with that module.
  • FIG. 1 depicts a typical prior art packaged integrated circuit device.
  • FIG. 2 depicts the device of FIG. 1 from which the solder ball contacts have been removed.
  • FIG. 3 depicts a set of substrate contacts upon which a high temperature solder paste has been applied in accordance with a preferred embodiment of the present invention.
  • FIG. 4 depicts portions of two flexible circuit connectors prepared for mounting of an integrated circuit device in accordance with a preferred embodiment of the present invention.
  • FIG. 5 depicts a device-substrate assembly in accordance with a preferred embodiment of the present invention.
  • FIG. 6 depicts a two-high integrated circuit module mounted to the two flexible circuit connectors depicted in FIG. 4 in accordance with a preferred embodiment of the present invention.
  • FIG. 7 depicts a four-high stacked module devised in accordance with a preferred embodiment of the present invention.
  • FIG. 1 depicts an exemplar integrated circuit device 10 having upper surface 11 and lower surface 13 .
  • Device 10 is an example of one type of the general class of devices commonly known in the art as chip-scale-packaged integrated circuits (“CSPs”).
  • CSPs chip-scale-packaged integrated circuits
  • the present invention may employed with a wide variety of integrated circuit devices and is not, as those of skill in the art will understand, limited to devices having the profile depicted in FIG. 1 . Further, although its preferred use is with plastic-bodied CSP devices, the invention provides advantages in mounting a variety of packaged integrated circuit devices in a wide variety of configurations including leaded and CSP topologies.
  • Exemplar integrated circuit device 10 may include one or more integrated circuit die and body 12 and a set of contacts 14 .
  • the illustrated integrated circuit device 10 has CSP ball contacts 14 arrayed along surface 13 of its body 12 .
  • CSP ball contacts 14 are, as depicted, balls that are a mixture of tin and lead with common relative composition of 63% tin and 37% lead. Such contacts typically have a melting point of about 183° C.
  • Other contacts are sometimes found along a planar surface of integrated circuit devices and such other contacts may also be treated in accordance with the present invention where the opportunity may also be treated in accordance with the present invention where the opportunity arises as will be understood after gaining familiarity with the present disclosure.
  • CSP ball contacts 14 have been removed, leaving CSP pads 16 arrayed along lower surface 13 .
  • CSP pads 16 will typically exhibit a residual thin layer of tin/lead mixture after removal of CSP ball contacts 14 .
  • CSPs may be received without attached balls and the process and structures described herein will then not require “removal” of balls. Further, embodiments of the present invention may be implemented with CSPs already bearing ball contacts comprised of high temperature solders.
  • FIG. 3 depicts exemplar substrate 18 on which are disposed contacts 20 .
  • Substrate 18 is depicted as a rigid board such as a PWB or PCB such as are known in the art.
  • a solder paste 22 is applied to substrate contacts 20 .
  • solder paste 22 is applied to the CSP pads 16 and not the substrate contacts 20 .
  • solder paste 22 may applied to both substrate contacts 20 and CSP pads 16 (or a set of contacts of other configuration when devices that are not CSP are used in accordance with the invention.)
  • solder paste is a mixture of solder particles and flux.
  • solder alloy employed in solder paste 22 exhibits a melting point equal to or greater than 235° C. and, preferably between 235° C. and 312° C.
  • the alloy chosen should not have a melting point so high that the IC package is adversely affected, but it should also not be so low as to remelt during board assembly operations.
  • lead-free solders Such lead-free solders will typically have melting points higher than those found in lead inclusive solders. Typically, those who use lead-free solders to populate boards with stacked modules will, for example, employ temperatures up to 240° C. in the process of attachment of stacked modules to boards. Consequently, a HT joint implemented with a lead-free alloy will, in conformity with preferred embodiments of the present invention, exhibit a melting point greater than those lead-free solders used to populate boards. Consequently, a preferred implementation of the HT joints of the present invention will have a melting point range of between 245° C. and 265° C.
  • the lead-free solder alloy employed in such HT joints will be comprised of at least two of the following elements: tin, silver, copper, or indium.
  • an alloy used as a solder in the present invention will melt over a narrow temperature range. Disintegration of the module during board attachment or population will be less likely if the melt range is narrow. Most preferably, the top of the melting point range of the solder used in board attachment should be exceeded by 15° C. by the melting point of the solder used to manufacture the stacked module although in the case of lead-free solder, this is reduced to ameliorate issues that could arise from exposure of the package to high temperatures.
  • solder alloys appropriate for use in the present invention.
  • these examples are instructive in selecting other preferred particular combinations of lead, tin, silver copper, antimony, and indium that are readily employed to advantage in the present invention so as to arrive at alloys of at least two of the following solder elements: lead, tin, silver, copper, antimony, and indium that have in their combined mixture, a preferred melting point between 235° C. to 312° C. inclusive.
  • solder alloys or mixtures may also be employed in embodiments of the present invention that exhibit melting points lower than 235° C., as would be exhibited for example with a 97% Sn and a 3% Sb alloy, but preferred embodiments will employ solder mixtures or alloys that melt between 235° C. and 312° C. inclusive.
  • FIG. 4 depicts portions of two flexible circuit connectors 24 A and 24 B prepared for mounting of a device 10 in accordance with a preferred embodiment of the present invention.
  • Exemplar flex circuits 24 A and 24 B may be simple flex circuitry or may exhibit the more sophisticated designs of flex circuitry such as those that would be constructed in accordance with the detailed descriptions provided in U.S. patent application Ser. No. 10/005,581 which has been made part of this application by incorporation by reference.
  • depicted flex circuits 24 A and 24 B exhibit a single conductive layer 26 and a first outer layer 28 .
  • Conductive layer 26 is supported by substrate layer 30 , which , in a preferred embodiment, is a polymide.
  • Outer layer 32 resides along the lower surface of the flex circuits 24 A and 24 B.
  • Optional outer layers 28 and 32 when present, are typically a covercoat or solder mask material. Windows 34 are created through outer layer 32 and intermediate layer 30 to expose flex contacts 36 .
  • solder paste 22 is applied to flex contacts 36 which are demarked at the level of conductive layer 26 .
  • Solder paste 22 may also alternatively or in addition, be applied to the CSP pads 16 of a CSP.
  • Windows 34 provide openings through which module contacts may be disposed in a later stacked module assembly step.
  • FIG. 5 depicts a device-substrate assembly in accordance with a preferred embodiment of the present invention as may be employed in the construction of a low profile stacked module.
  • the features depicted in FIG. 5 are not drawn to scale, and show various features in an enlarged aspect for purposes of illustration.
  • integrated circuit device 10 is disposed upon flex circuits 24 A and 24 B which have been, in a preferred embodiment of the method of the present invention, previously prepared as shown in earlier FIG. 4 .
  • Module contacts 40 have been appended to flex circuits 24 A and 24 B to provide connective facility for the device-flex combination whether as part of a stacked module or otherwise.
  • High temperature joints contacts 38 are formed by the melting of the lead alloy in previously applied solder paste 22 and the application of a selected heat range appropriate for the solder mixtures identified previously.
  • HT joints 38 will, after solidification, typically not re-melt unless exposed subsequently to such temperature ranges.
  • the temperature range applied in this step of assembly will not typically be subsequently encountered in a later assembly operation such as, for example, the application of a stacked module to a DIMM board. Consequently, in one embodiment, the present invention is articulated as a stacked module having HT joints that is appended to a DIMM board with traditional lower melting point solder.
  • FIG. 6 depicts a two-high stacked module devised in accordance with a preferred embodiments of the present invention.
  • Stacked module 50 shown in FIG. 6 includes lower integrated circuit device 52 and upper integrated circuit device 54 .
  • a stacked module 50 may be devised in accordance with the present invention that includes more than two packaged integrated circuit devices.
  • Flex circuits 56 A and 56 B are depicted connecting lower integrated circuit device 52 and upper integrated circuit device 54 .
  • module 50 may be implemented with a single flexible circuit connector. Further, the flexible circuit connectors employed in accordance with the invention may exhibit one or more conductive layers. Flex circuits 56 A and 56 B may be any circuit connector structure that provides connective facility between two integrated circuits having a contact array.
  • flexible circuits 56 A and 56 B may exhibit single conductive layers (such as, for example, the flexible circuit connectors earlier illustrated herein and identified for descriptive purposes as flex circuits 24 A and 24 B in FIG. 5 ) or may exhibit multiple conductive layers. Examples of other preferred flexible circuit structures are found in U.S. application Ser. No. 10/005,581 which has been incorporated by reference and those of skill will readily appreciate how a variety of circuit structures may be employed in preferred embodiments. Further, the connective structures used to connect lower integrated circuit 52 with upper integrated circuit 54 need not literally be flexible circuit connectors but may be flexible in portions and rigid in other protions.
  • HT contacts 38 are employed in the preferred embodiment of FIG. 6 to provide connective facility between the respective integrated circuits and contacts borne by the flex circuits 56 A and 56 B.
  • HT joints 38 will exhibit a height dimension smaller than that of CSP ball contacts 14 shown earlier as part of typical CSPs in FIG. 1 .
  • HT joints 38 are depicted in a scale that is enlarged relative to joint sizes that would typically be encountered in actual practice of preferred modes of the invention.
  • module 50 will preferably present a lower profile that stacked modules created employing typical CSP contacts 14 on each of the constituent integrated circuit packages employed in a stacked module 50 .
  • FIG 7 depicts module 60 as having lower integrated circuit element 52 , upper IC element 54 , 3 rd IC element 58 , and 4 th IC element 62 .
  • some embodiments will present HT contacts that have minimal heights that do not cause appreciable separation between the flex circuitry associated IC 52 and IC 54 , for example, or between IC 54 and IC 62 , for example.
  • the apparent height for illustrated HT joints 39 particularly, that lie between respective layers of flex circuitry pairs 56 A and 56 B are also shown but, as in other embodiments, the invention may be implemented with a variety of substrates including single flex circuits in place of the depicted pair and with flexible circuits that have one or plural conductive layers.
  • the HT joints provide connections between integrated circuit devices and substrates and the overall profile of module 60 is reduced by use of the present invention that provides advantages in subsequent processing steps such as for example, affixation of module 60 to DIMM boards, for example.
  • CSP contacts 16 that typically exhibit a residual layer of solder.
  • a high temperature solder paste composed from a lead alloy or mixture that has a preferable melting point equal to or higher that 235° C. and preferably less than 312° C. is applied to substrate contacts 20 of a substrate such as a flexible circuit and/or the substrate contacts to which it is to be mounted.
  • the CSP is positioned to place the CSP pads 16 and substrate contacts 22 in appropriate proximity. Heat is applied sufficient to melt the lead solder alloy of solder paste 22 thus forming HT joints 38 .
  • the flexible circuit is positioned to place portions of the flexible circuit connector between the first CSP and a second CSP that is connected to the substrate with HT joints created using the process described for creating HT joints.
  • the present invention will provide a stacked high module that is assembled using the HT joints that exhibit melting point ranges between X and Y degrees where X is less that Y. Attachment of the stacked module to a board is then implemented with a solder having a melting point between A and B degrees where A and B are less that X.

Abstract

The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method is stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder past that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.

Description

    RELATED APPLICATIONS
  • The present application is a division of application Ser. No. 11/011,469, filed Dec. 14, 2004, pending, which is a division of application Ser. No. 10/457,608, filed Jun. 9, 2003, which is a continuation-in-part of U.S. patent application Ser. No. 10/005,581, filed Oct. 26, 2001, all of which are hereby incorporated by reference.
  • TECHNICAL FIELD
  • The present invention related to mounting integrated circuit devices on substrates and to mounting integrated circuits on substrates employed in stacked modules.
  • BACKGROUND OF THE INVENTION
  • A variety of methods are used to mount integrated circuit devices to substrates such as PWBs and flex circuitry. Solder paste is selectively applied to the integrated circuit device or substrate to which the IC is to be attached. The device and substrate are exposed to reflow temperatures of approximately 220° C. The device is, consequently, soldered to the substrate.
  • Typically, however, the formed solder joints will re-melt during subsequent processing. Common tin-lead solders start to melt as 183° C. and, when exposed to such temperatures and higher, the exposed joint may re-melt and become unreliable.
  • What is needed, therefore, is a technique and system for mounting integrated circuit devices on substrates that provide an efficient and readily implemented technique to create structures that reliably withstand subsequent exposure to typical tin-lead solder melting point temperatures.
  • SUMMARY OF THE INVENTION
  • The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder past that includes higher temperature solder paste alloy is applied to a substrate or the contacts of the packaged device. The integrated circuit device is positioned to contact the contacts of the substrate with the higher temperature solder alloy paste between. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile. In a method in accordance with the present invention, a first solder used to construct a stacked module has a higher melting point than a second solder used to populate a board with that module.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 depicts a typical prior art packaged integrated circuit device.
  • FIG. 2 depicts the device of FIG. 1 from which the solder ball contacts have been removed.
  • FIG. 3 depicts a set of substrate contacts upon which a high temperature solder paste has been applied in accordance with a preferred embodiment of the present invention.
  • FIG. 4 depicts portions of two flexible circuit connectors prepared for mounting of an integrated circuit device in accordance with a preferred embodiment of the present invention.
  • FIG. 5 depicts a device-substrate assembly in accordance with a preferred embodiment of the present invention.
  • FIG. 6 depicts a two-high integrated circuit module mounted to the two flexible circuit connectors depicted in FIG. 4 in accordance with a preferred embodiment of the present invention.
  • FIG. 7 depicts a four-high stacked module devised in accordance with a preferred embodiment of the present invention.
  • DESCRIPTION OF PREFERRED EMBODIMENTS
  • FIG. 1 depicts an exemplar integrated circuit device 10 having upper surface 11 and lower surface 13. Device 10 is an example of one type of the general class of devices commonly known in the art as chip-scale-packaged integrated circuits (“CSPs”). The present invention may employed with a wide variety of integrated circuit devices and is not, as those of skill in the art will understand, limited to devices having the profile depicted in FIG. 1. Further, although its preferred use is with plastic-bodied CSP devices, the invention provides advantages in mounting a variety of packaged integrated circuit devices in a wide variety of configurations including leaded and CSP topologies.
  • Exemplar integrated circuit device 10 may include one or more integrated circuit die and body 12 and a set of contacts 14. The illustrated integrated circuit device 10 has CSP ball contacts 14 arrayed along surface 13 of its body 12. Typically, when integrated circuit device 10 is a CSP device, CSP ball contacts 14 are, as depicted, balls that are a mixture of tin and lead with common relative composition of 63% tin and 37% lead. Such contacts typically have a melting point of about 183° C. Other contacts are sometimes found along a planar surface of integrated circuit devices and such other contacts may also be treated in accordance with the present invention where the opportunity may also be treated in accordance with the present invention where the opportunity arises as will be understood after gaining familiarity with the present disclosure.
  • In the depiction of FIG. 2, CSP ball contacts 14 have been removed, leaving CSP pads 16 arrayed along lower surface 13. CSP pads 16 will typically exhibit a residual thin layer of tin/lead mixture after removal of CSP ball contacts 14. As those of skill will know, CSPs may be received without attached balls and the process and structures described herein will then not require “removal” of balls. Further, embodiments of the present invention may be implemented with CSPs already bearing ball contacts comprised of high temperature solders.
  • FIG. 3 depicts exemplar substrate 18 on which are disposed contacts 20. Substrate 18 is depicted as a rigid board such as a PWB or PCB such as are known in the art. In accordance with a preferred embodiment of the present invention, a solder paste 22 is applied to substrate contacts 20. In accordance with an alternative preferred embodiment of the invention, solder paste 22 is applied to the CSP pads 16 and not the substrate contacts 20. However, as those skilled will recognize, solder paste 22 may applied to both substrate contacts 20 and CSP pads 16 (or a set of contacts of other configuration when devices that are not CSP are used in accordance with the invention.) As those of skill understand, solder paste is a mixture of solder particles and flux.
  • Two or more of the elements lead, tin, silver, copper, antimony, or indium may be employed in a variety of combinations to devise a solder to be employed in solder paste 22 in accordance with the present invention. Therefore, in accordance with preferred embodiments of the present invention, a solder alloy employed in solder paste 22 exhibits a melting point equal to or greater than 235° C. and, preferably between 235° C. and 312° C. The alloy chosen should not have a melting point so high that the IC package is adversely affected, but it should also not be so low as to remelt during board assembly operations.
  • Some market participants are starting to implement lead-free solders. Such lead-free solders will typically have melting points higher than those found in lead inclusive solders. Typically, those who use lead-free solders to populate boards with stacked modules will, for example, employ temperatures up to 240° C. in the process of attachment of stacked modules to boards. Consequently, a HT joint implemented with a lead-free alloy will, in conformity with preferred embodiments of the present invention, exhibit a melting point greater than those lead-free solders used to populate boards. Consequently, a preferred implementation of the HT joints of the present invention will have a melting point range of between 245° C. and 265° C. The lead-free solder alloy employed in such HT joints will be comprised of at least two of the following elements: tin, silver, copper, or indium.
  • Preferably , an alloy used as a solder in the present invention will melt over a narrow temperature range. Disintegration of the module during board attachment or population will be less likely if the melt range is narrow. Most preferably, the top of the melting point range of the solder used in board attachment should be exceeded by 15° C. by the melting point of the solder used to manufacture the stacked module although in the case of lead-free solder, this is reduced to ameliorate issues that could arise from exposure of the package to high temperatures.
  • The following combinations have been found to exhibit the following melting points, and the below recited combinations are merely a representative, but not exhaustive, list of examples of solder alloys appropriate for use in the present invention. As those of skill will recognize, these examples are instructive in selecting other preferred particular combinations of lead, tin, silver copper, antimony, and indium that are readily employed to advantage in the present invention so as to arrive at alloys of at least two of the following solder elements: lead, tin, silver, copper, antimony, and indium that have in their combined mixture, a preferred melting point between 235° C. to 312° C. inclusive.
      • a. A combination of 95% Sn and 5% Sb melts over a range of 235° C. to 240° C.
      • b. A combination of 83% Pb and 10% Sb and 5% Sn and 2% Ag melts over a range of 237° C. to 247° C.
      • c. A combination of 85% Pb and 10% Sb and 5% Sn melts over a range of 245° C. to 255° C.
      • d. A combination of 90% Pb and 10% Sb melts over a range of 252° C. to 260° C.
      • e. A combination of 92.5% Pb, 5% Sn and 2.5% Ag melts over a range of 287° C. to 296° C.
      • f. A combination of 90% Pb and 10% Sn melts over a range of 275° C. to 302° C.
      • g. A combination of 95% Pb and 5% Sn melts over a range of 275° C. to 302° C.
      • h. A combination of 75% Pb and 25% Indium melts over a range of 240° C. to 260° C.
  • Those of skill will note that solder alloys or mixtures may also be employed in embodiments of the present invention that exhibit melting points lower than 235° C., as would be exhibited for example with a 97% Sn and a 3% Sb alloy, but preferred embodiments will employ solder mixtures or alloys that melt between 235° C. and 312° C. inclusive.
  • FIG. 4 depicts portions of two flexible circuit connectors 24A and 24B prepared for mounting of a device 10 in accordance with a preferred embodiment of the present invention. Exemplar flex circuits 24A and 24B may be simple flex circuitry or may exhibit the more sophisticated designs of flex circuitry such as those that would be constructed in accordance with the detailed descriptions provided in U.S. patent application Ser. No. 10/005,581 which has been made part of this application by incorporation by reference. For clarity of exposition, depicted flex circuits 24A and 24B exhibit a single conductive layer 26 and a first outer layer 28. Conductive layer 26 is supported by substrate layer 30, which , in a preferred embodiment, is a polymide. Outer layer 32 resides along the lower surface of the flex circuits 24A and 24B. Optional outer layers 28 and 32, when present, are typically a covercoat or solder mask material. Windows 34 are created through outer layer 32 and intermediate layer 30 to expose flex contacts 36.
  • As depicted in FIG. 4, solder paste 22 is applied to flex contacts 36 which are demarked at the level of conductive layer 26. Solder paste 22 may also alternatively or in addition, be applied to the CSP pads 16 of a CSP. Windows 34 provide openings through which module contacts may be disposed in a later stacked module assembly step. Those of skill will recognize that the method of the present invention is applicable to a wide variety of substrates including solid PWB's, rigid flex, and flexible substrates such as flexible circuits, for example, and the substrate employed can be prepared in accordance with the present invention in a manner appropriate for the intended application. Where the invention is employed with rigid substrates such as a PWB, multilayer strategies and windowing in substrate layers are techniques which are useful in conjunction with the present invention, but not essential.
  • FIG. 5 depicts a device-substrate assembly in accordance with a preferred embodiment of the present invention as may be employed in the construction of a low profile stacked module. The features depicted in FIG. 5 are not drawn to scale, and show various features in an enlarged aspect for purposes of illustration. As shown, integrated circuit device 10 is disposed upon flex circuits 24A and 24B which have been, in a preferred embodiment of the method of the present invention, previously prepared as shown in earlier FIG. 4. Module contacts 40 have been appended to flex circuits 24A and 24B to provide connective facility for the device-flex combination whether as part of a stacked module or otherwise.
  • High temperature joints contacts 38 (“HT joints”) are formed by the melting of the lead alloy in previously applied solder paste 22 and the application of a selected heat range appropriate for the solder mixtures identified previously. Thus, HT joints 38 will, after solidification, typically not re-melt unless exposed subsequently to such temperature ranges. The temperature range applied in this step of assembly will not typically be subsequently encountered in a later assembly operation such as, for example, the application of a stacked module to a DIMM board. Consequently, in one embodiment, the present invention is articulated as a stacked module having HT joints that is appended to a DIMM board with traditional lower melting point solder.
  • FIG. 6 depicts a two-high stacked module devised in accordance with a preferred embodiments of the present invention. Stacked module 50 shown in FIG. 6 includes lower integrated circuit device 52 and upper integrated circuit device 54. A stacked module 50 may be devised in accordance with the present invention that includes more than two packaged integrated circuit devices. Flex circuits 56A and 56B are depicted connecting lower integrated circuit device 52 and upper integrated circuit device 54. Those of skill will also recognize that module 50 may be implemented with a single flexible circuit connector. Further, the flexible circuit connectors employed in accordance with the invention may exhibit one or more conductive layers. Flex circuits 56A and 56B may be any circuit connector structure that provides connective facility between two integrated circuits having a contact array. Those of skill will note that flexible circuits 56A and 56B may exhibit single conductive layers (such as, for example, the flexible circuit connectors earlier illustrated herein and identified for descriptive purposes as flex circuits 24A and 24B in FIG. 5) or may exhibit multiple conductive layers. examples of other preferred flexible circuit structures are found in U.S. application Ser. No. 10/005,581 which has been incorporated by reference and those of skill will readily appreciate how a variety of circuit structures may be employed in preferred embodiments. Further, the connective structures used to connect lower integrated circuit 52 with upper integrated circuit 54 need not literally be flexible circuit connectors but may be flexible in portions and rigid in other protions.
  • HT contacts 38 are employed in the preferred embodiment of FIG. 6 to provide connective facility between the respective integrated circuits and contacts borne by the flex circuits 56A and 56B. Preferably, HT joints 38 will exhibit a height dimension smaller than that of CSP ball contacts 14 shown earlier as part of typical CSPs in FIG. 1. As those of skill will recognize, HT joints 38 are depicted in a scale that is enlarged relative to joint sizes that would typically be encountered in actual practice of preferred modes of the invention. Thus, module 50 will preferably present a lower profile that stacked modules created employing typical CSP contacts 14 on each of the constituent integrated circuit packages employed in a stacked module 50.
  • FIG 7 depicts module 60 as having lower integrated circuit element 52, upper IC element 54, 3rd IC element 58, and 4th IC element 62. When the present invention is employed between flex circuits in stacking multiple levels of CSPs, as for example in FIG. 7, some embodiments will present HT contacts that have minimal heights that do not cause appreciable separation between the flex circuitry associated IC 52 and IC 54, for example, or between IC 54 and IC 62, for example. For such embodiments, the apparent height for illustrated HT joints 39, particularly, that lie between respective layers of flex circuitry pairs 56A and 56B are also shown but, as in other embodiments, the invention may be implemented with a variety of substrates including single flex circuits in place of the depicted pair and with flexible circuits that have one or plural conductive layers.
  • As shown, the HT joints provide connections between integrated circuit devices and substrates and the overall profile of module 60 is reduced by use of the present invention that provides advantages in subsequent processing steps such as for example, affixation of module 60 to DIMM boards, for example.
  • To construct a stacked module in accordance with a preferred embodiment of the present invention, if present, ball contact 14 are removed from a CSP leaving CSP contacts 16 that typically exhibit a residual layer of solder. A high temperature solder paste composed from a lead alloy or mixture that has a preferable melting point equal to or higher that 235° C. and preferably less than 312° C. is applied to substrate contacts 20 of a substrate such as a flexible circuit and/or the substrate contacts to which it is to be mounted. The CSP is positioned to place the CSP pads 16 and substrate contacts 22 in appropriate proximity. Heat is applied sufficient to melt the lead solder alloy of solder paste 22 thus forming HT joints 38. The flexible circuit is positioned to place portions of the flexible circuit connector between the first CSP and a second CSP that is connected to the substrate with HT joints created using the process described for creating HT joints.
  • In understanding the present invention, it may be helpful to articulate the relative melting points in terms of variables to illustrate the relationships between the HT joints used to construct a stacked module and the solders used to populate a board with such HT joint-implemented stacked module. In use in board population, the present invention will provide a stacked high module that is assembled using the HT joints that exhibit melting point ranges between X and Y degrees where X is less that Y. Attachment of the stacked module to a board is then implemented with a solder having a melting point between A and B degrees where A and B are less that X.
  • Although the present invention has been described in detail, it will be apparent to those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.

Claims (3)

1. A high temperature joint in a stacked circuit module in which a first integrated circuit element is disposed above a second integrated circuit element, the high temperature joint comprising:
an alloy comprised of lead and antimony having the proportion of no more that 95% tin and at least 5% antimony, the alloy having a melting point between 235° C. to 260° C.
2. A high temperature joint in a stacked circuit module in which a first integrated circuit element is disposed above a second integrated circuit element, the high temperature joint comprising:
an alloy comprised of lead and tin, the alloy having a melting point between 275° C. 312° C.
3. A high temperature joint in a stacked circuit module in which a first integrated circuit element is disposed above a second integrated circuit element, the high temperature joint comprising:
an alloy comprised of lead, the alloy having a melting point of between 235° C. and 312° C.
US11/626,318 2001-10-26 2007-01-23 Low Profile Stacking System and Method Abandoned US20070114649A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11/626,318 US20070114649A1 (en) 2001-10-26 2007-01-23 Low Profile Stacking System and Method
US12/356,432 US7626273B2 (en) 2001-10-26 2009-01-20 Low profile stacking system and method

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/005,581 US6576992B1 (en) 2001-10-26 2001-10-26 Chip scale stacking system and method
US10/457,608 US20030234443A1 (en) 2001-10-26 2003-06-09 Low profile stacking system and method
US11/011,469 US7180167B2 (en) 2001-10-26 2004-12-14 Low profile stacking system and method
US11/626,318 US20070114649A1 (en) 2001-10-26 2007-01-23 Low Profile Stacking System and Method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/011,469 Division US7180167B2 (en) 2001-10-26 2004-12-14 Low profile stacking system and method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/356,432 Continuation US7626273B2 (en) 2001-10-26 2009-01-20 Low profile stacking system and method

Publications (1)

Publication Number Publication Date
US20070114649A1 true US20070114649A1 (en) 2007-05-24

Family

ID=34713105

Family Applications (5)

Application Number Title Priority Date Filing Date
US10/457,608 Abandoned US20030234443A1 (en) 2001-10-26 2003-06-09 Low profile stacking system and method
US11/011,469 Expired - Fee Related US7180167B2 (en) 2001-10-26 2004-12-14 Low profile stacking system and method
US11/626,316 Abandoned US20070117262A1 (en) 2001-10-26 2007-01-23 Low Profile Stacking System and Method
US11/626,318 Abandoned US20070114649A1 (en) 2001-10-26 2007-01-23 Low Profile Stacking System and Method
US12/356,432 Expired - Lifetime US7626273B2 (en) 2001-10-26 2009-01-20 Low profile stacking system and method

Family Applications Before (3)

Application Number Title Priority Date Filing Date
US10/457,608 Abandoned US20030234443A1 (en) 2001-10-26 2003-06-09 Low profile stacking system and method
US11/011,469 Expired - Fee Related US7180167B2 (en) 2001-10-26 2004-12-14 Low profile stacking system and method
US11/626,316 Abandoned US20070117262A1 (en) 2001-10-26 2007-01-23 Low Profile Stacking System and Method

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/356,432 Expired - Lifetime US7626273B2 (en) 2001-10-26 2009-01-20 Low profile stacking system and method

Country Status (1)

Country Link
US (5) US20030234443A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090016033A1 (en) * 2007-07-12 2009-01-15 Seng Guan Chow Integrated circuit package system with flexible substrate and mounded package
US20090309197A1 (en) * 2008-06-11 2009-12-17 Seng Guan Chow Integrated circuit package system with internal stacking module

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7485951B2 (en) * 2001-10-26 2009-02-03 Entorian Technologies, Lp Modularized die stacking system and method
US7656678B2 (en) * 2001-10-26 2010-02-02 Entorian Technologies, Lp Stacked module systems
US6940729B2 (en) * 2001-10-26 2005-09-06 Staktek Group L.P. Integrated circuit stacking system and method
US7026708B2 (en) * 2001-10-26 2006-04-11 Staktek Group L.P. Low profile chip scale stacking system and method
US6576992B1 (en) * 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method
US7371609B2 (en) * 2001-10-26 2008-05-13 Staktek Group L.P. Stacked module systems and methods
US7254036B2 (en) 2004-04-09 2007-08-07 Netlist, Inc. High density memory module using stacked printed circuit boards
US7616452B2 (en) * 2004-09-03 2009-11-10 Entorian Technologies, Lp Flex circuit constructions for high capacity circuit module systems and methods
US7579687B2 (en) * 2004-09-03 2009-08-25 Entorian Technologies, Lp Circuit module turbulence enhancement systems and methods
US20060049513A1 (en) * 2004-09-03 2006-03-09 Staktek Group L.P. Thin module system and method with thermal management
US7606040B2 (en) * 2004-09-03 2009-10-20 Entorian Technologies, Lp Memory module system and method
US7289327B2 (en) * 2006-02-27 2007-10-30 Stakick Group L.P. Active cooling methods and apparatus for modules
US7606050B2 (en) * 2004-09-03 2009-10-20 Entorian Technologies, Lp Compact module system and method
US7446410B2 (en) * 2004-09-03 2008-11-04 Entorian Technologies, Lp Circuit module with thermal casing systems
US20060050492A1 (en) * 2004-09-03 2006-03-09 Staktek Group, L.P. Thin module system and method
US7443023B2 (en) * 2004-09-03 2008-10-28 Entorian Technologies, Lp High capacity thin module system
US7423885B2 (en) * 2004-09-03 2008-09-09 Entorian Technologies, Lp Die module system
US7760513B2 (en) * 2004-09-03 2010-07-20 Entorian Technologies Lp Modified core for circuit module system and method
US7468893B2 (en) * 2004-09-03 2008-12-23 Entorian Technologies, Lp Thin module system and method
US20060053345A1 (en) * 2004-09-03 2006-03-09 Staktek Group L.P. Thin module system and method
US7606049B2 (en) * 2004-09-03 2009-10-20 Entorian Technologies, Lp Module thermal management system and method
US7511968B2 (en) * 2004-09-03 2009-03-31 Entorian Technologies, Lp Buffered thin module system and method
US20060261449A1 (en) * 2005-05-18 2006-11-23 Staktek Group L.P. Memory module system and method
US7324352B2 (en) * 2004-09-03 2008-01-29 Staktek Group L.P. High capacity thin module system and method
FR2889405B1 (en) * 2005-07-29 2010-12-10 Thales Sa METHOD FOR ASSEMBLING ELECTRONIC COMPONENTS WITH BALL GRID CONTACTS, IN PARTICULAR ALLOY, SILVER AND COPPER, AND PROCESS FOR PRODUCING SUCH COMPONENTS
US7442050B1 (en) 2005-08-29 2008-10-28 Netlist, Inc. Circuit card with flexible connection for memory module with heat spreader
US7511969B2 (en) * 2006-02-02 2009-03-31 Entorian Technologies, Lp Composite core circuit module system and method
US7619893B1 (en) 2006-02-17 2009-11-17 Netlist, Inc. Heat spreader for electronic modules
KR100780691B1 (en) * 2006-03-29 2007-11-30 주식회사 하이닉스반도체 Folding chip planr stack package
US8018723B1 (en) 2008-04-30 2011-09-13 Netlist, Inc. Heat dissipation for electronic modules
JP5527806B2 (en) * 2010-02-17 2014-06-25 Necネットワークプロダクツ株式会社 Manufacturing method of semiconductor device
TWI406376B (en) * 2010-06-15 2013-08-21 Powertech Technology Inc Semiconductor chip package
US8884420B1 (en) * 2013-07-12 2014-11-11 Infineon Technologies Austria Ag Multichip device
JP6513465B2 (en) * 2015-04-24 2019-05-15 日本航空電子工業株式会社 Lead connection structure
CN111093316B (en) * 2018-10-24 2021-08-24 鹏鼎控股(深圳)股份有限公司 Circuit board and manufacturing method thereof
US10999938B1 (en) * 2020-04-29 2021-05-04 Raytheon Company Method of wire bonding a first and second circuit card

Citations (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3436804A (en) * 1968-04-23 1969-04-08 Olin Mathieson Process for forming composite aluminum alloy
US3654394A (en) * 1969-07-08 1972-04-04 Gordon Eng Co Field effect transistor switch, particularly for multiplexing
US3806767A (en) * 1973-03-15 1974-04-23 Tek Wave Inc Interboard connector
US4079511A (en) * 1976-07-30 1978-03-21 Amp Incorporated Method for packaging hermetically sealed integrated circuit chips on lead frames
US4381421A (en) * 1980-07-01 1983-04-26 Tektronix, Inc. Electromagnetic shield for electronic equipment
US4437235A (en) * 1980-12-29 1984-03-20 Honeywell Information Systems Inc. Integrated circuit package
US4513368A (en) * 1981-05-22 1985-04-23 Data General Corporation Digital data processing system having object-based logical memory addressing and self-structuring modular memory
US4645944A (en) * 1983-09-05 1987-02-24 Matsushita Electric Industrial Co., Ltd. MOS register for selecting among various data inputs
US4722691A (en) * 1986-02-03 1988-02-02 General Motors Corporation Header assembly for a printed circuit board
US4733461A (en) * 1984-12-28 1988-03-29 Micro Co., Ltd. Method of stacking printed circuit boards
US4821007A (en) * 1987-02-06 1989-04-11 Tektronix, Inc. Strip line circuit component and method of manufacture
US4823234A (en) * 1985-08-16 1989-04-18 Dai-Ichi Seiko Co., Ltd. Semiconductor device and its manufacture
US4891789A (en) * 1988-03-03 1990-01-02 Bull Hn Information Systems, Inc. Surface mounted multilayer memory printed circuit board
US4903169A (en) * 1986-04-03 1990-02-20 Matsushita Electric Industrial Co., Ltd. Shielded high frequency apparatus having partitioned shield case, and method of manufacture thereof
US4911643A (en) * 1988-10-11 1990-03-27 Beta Phase, Inc. High density and high signal integrity connector
US4983533A (en) * 1987-10-28 1991-01-08 Irvine Sensors Corporation High-density electronic modules - process and product
US4985703A (en) * 1988-02-03 1991-01-15 Nec Corporation Analog multiplexer
US5012323A (en) * 1989-11-20 1991-04-30 Micron Technology, Inc. Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
US5081067A (en) * 1989-02-10 1992-01-14 Fujitsu Limited Ceramic package type semiconductor device and method of assembling the same
US5099393A (en) * 1991-03-25 1992-03-24 International Business Machines Corporation Electronic package for high density applications
US5104820A (en) * 1989-07-07 1992-04-14 Irvine Sensors Corporation Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting
US5198955A (en) * 1990-07-30 1993-03-30 Nuheat Inc. Sealed plug-in GFCI
US5198988A (en) * 1989-09-15 1993-03-30 Hewlett-Packard Company Method of determining optimum operating conditions in an electrochemical detector and electrochemical detector using the method
US5276418A (en) * 1988-11-16 1994-01-04 Motorola, Inc. Flexible substrate electronic assembly
US5281852A (en) * 1991-12-10 1994-01-25 Normington Peter J C Semiconductor device including stacked die
US5289346A (en) * 1991-02-26 1994-02-22 Microelectronics And Computer Technology Corporation Peripheral to area adapter with protective bumper for an integrated circuit chip
US5289062A (en) * 1991-03-18 1994-02-22 Quality Semiconductor, Inc. Fast transmission gate switch
US5384690A (en) * 1993-07-27 1995-01-24 International Business Machines Corporation Flex laminate package for a parallel processor
US5386341A (en) * 1993-11-01 1995-01-31 Motorola, Inc. Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape
US5394303A (en) * 1992-09-11 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor device
US5396573A (en) * 1993-08-03 1995-03-07 International Business Machines Corporation Pluggable connectors for connecting large numbers of electrical and/or optical cables to a module through a seal
US5397916A (en) * 1991-12-10 1995-03-14 Normington; Peter J. C. Semiconductor device including stacked die
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
US5502333A (en) * 1994-03-30 1996-03-26 International Business Machines Corporation Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
US5509197A (en) * 1994-06-10 1996-04-23 Xetel Corporation Method of making substrate edge connector
US5594275A (en) * 1993-11-18 1997-01-14 Samsung Electronics Co., Ltd. J-leaded semiconductor package having a plurality of stacked ball grid array packages
US5610833A (en) * 1992-06-02 1997-03-11 Hewlett-Packard Company Computer-aided design methods and apparatus for multilevel interconnect technologies
US5612570A (en) * 1995-04-13 1997-03-18 Dense-Pac Microsystems, Inc. Chip stack and method of making same
US5717556A (en) * 1995-04-26 1998-02-10 Nec Corporation Printed-wiring board having plural parallel-connected interconnections
US5729894A (en) * 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages
US5744627A (en) * 1994-01-28 1998-04-28 Prolinx, Inc. Boronic compound complexing reagents and complexes
US5869353A (en) * 1997-11-17 1999-02-09 Dense-Pac Microsystems, Inc. Modular panel stacking process
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US5895969A (en) * 1992-05-25 1999-04-20 Hitachi, Ltd. And Hitachi Vlsi Engineering Corp. Thin type semiconductor device, module structure using the device and method of mounting the device on board
US5895970A (en) * 1997-05-02 1999-04-20 Nec Corporation Semiconductor package having semiconductor element, mounting structure of semiconductor package mounted on circuit board, and method of assembling semiconductor package
US5895705A (en) * 1997-07-11 1999-04-20 Highland Industries, Inc. Awning and backlit sign fabric having a selectively eradicable ink layer and a process for producing same
US6014316A (en) * 1997-06-13 2000-01-11 Irvine Sensors Corporation IC stack utilizing BGA contacts
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6028352A (en) * 1997-06-13 2000-02-22 Irvine Sensors Corporation IC stack utilizing secondary leadframes
US6028365A (en) * 1998-03-30 2000-02-22 Micron Technology, Inc. Integrated circuit package and method of fabrication
US6034876A (en) * 1996-06-27 2000-03-07 Japan Aviation Electronics Industry, Limited Electronic device comprising structure fixing electrical connector directly to device case through no printed circuit board having the electrical connector
US6040624A (en) * 1997-10-02 2000-03-21 Motorola, Inc. Semiconductor device package and method
US6172874B1 (en) * 1998-04-06 2001-01-09 Silicon Graphics, Inc. System for stacking of integrated circuit packages
US6178093B1 (en) * 1996-06-28 2001-01-23 International Business Machines Corporation Information handling system with circuit assembly having holes filled with filler material
US6186106B1 (en) * 1997-12-29 2001-02-13 Visteon Global Technologies, Inc. Apparatus for routing electrical signals in an engine
US6187652B1 (en) * 1998-09-14 2001-02-13 Fujitsu Limited Method of fabrication of multiple-layer high density substrate
US6205654B1 (en) * 1992-12-11 2001-03-27 Staktek Group L.P. Method of manufacturing a surface mount package
US6208521B1 (en) * 1997-05-19 2001-03-27 Nitto Denko Corporation Film carrier and laminate type mounting structure using same
US6218731B1 (en) * 1999-05-21 2001-04-17 Siliconware Precision Industries Co., Ltd. Tiny ball grid array package
US6336262B1 (en) * 1996-10-31 2002-01-08 International Business Machines Corporation Process of forming a capacitor with multi-level interconnection technology
US20020006032A1 (en) * 2000-05-23 2002-01-17 Chris Karabatsos Low-profile registered DIMM
US6351029B1 (en) * 1999-05-05 2002-02-26 Harlan R. Isaak Stackable flex circuit chip package and method of making same
US20020030995A1 (en) * 2000-08-07 2002-03-14 Masao Shoji Headlight
US6360935B1 (en) * 1999-01-26 2002-03-26 Board Of Regents Of The University Of Texas System Apparatus and method for assessing solderability
US6360433B1 (en) * 1999-04-23 2002-03-26 Andrew C. Ross Universal package and method of forming the same
US6504104B2 (en) * 1997-12-10 2003-01-07 Siemens Aktiengesellschaft Flexible wiring for the transformation of a substrate with edge contacts into a ball grid array
US6509639B1 (en) * 2001-07-27 2003-01-21 Charles W. C. Lin Three-dimensional stacked semiconductor package
US20030016710A1 (en) * 2001-07-19 2003-01-23 Satoshi Komoto Semiconductor laser device including light receiving element for receiving monitoring laser beam
US6514793B2 (en) * 1999-05-05 2003-02-04 Dpac Technologies Corp. Stackable flex circuit IC package and method of making same
US6522018B1 (en) * 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US6528870B2 (en) * 2000-01-28 2003-03-04 Kabushiki Kaisha Toshiba Semiconductor device having a plurality of stacked wiring boards
US6527984B1 (en) * 1999-10-22 2003-03-04 Sony Chemicals Corporation Low temperature-curable connecting material for anisotropically electroconductive connection
US20030045025A1 (en) * 2000-01-26 2003-03-06 Coyle Anthony L. Method of fabricating a molded package for micromechanical devices
US6532162B2 (en) * 2001-05-26 2003-03-11 Intel Corporation Reference plane of integrated circuit packages
US20030049886A1 (en) * 2001-09-07 2003-03-13 Salmon Peter C. Electronic system modules and method of fabrication
US6538895B2 (en) * 1999-07-15 2003-03-25 Infineon Technologies Ag TSOP memory chip housing configuration
US20040000708A1 (en) * 2001-10-26 2004-01-01 Staktek Group, L.P. Memory expansion and chip scale stacking system and method
US6673651B2 (en) * 1999-07-01 2004-01-06 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor device including semiconductor elements mounted on base plate
US20040004281A1 (en) * 2002-07-03 2004-01-08 Jin-Chuan Bai Semiconductor package with heat sink
US6677670B2 (en) * 2000-04-25 2004-01-13 Seiko Epson Corporation Semiconductor device
US6683377B1 (en) * 2000-05-30 2004-01-27 Amkor Technology, Inc. Multi-stacked memory package
US20040021211A1 (en) * 2002-08-05 2004-02-05 Tessera, Inc. Microelectronic adaptors, assemblies and methods
US6690584B2 (en) * 2000-08-14 2004-02-10 Fujitsu Limited Information-processing device having a crossbar-board connected to back panels on different sides
US6689634B1 (en) * 1999-09-22 2004-02-10 Texas Instruments Incorporated Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability
US20040031972A1 (en) * 2001-10-09 2004-02-19 Tessera, Inc. Stacked packages
US6699730B2 (en) * 1996-12-13 2004-03-02 Tessers, Inc. Stacked microelectronic assembly and method therefor
US20040045159A1 (en) * 1996-12-13 2004-03-11 Tessera, Inc. Electrical connection with inwardly deformable contacts
US6707664B2 (en) * 2001-02-11 2004-03-16 Micron Technology, Inc. Expandable keyboard for portable computers
US6707148B1 (en) * 2002-05-21 2004-03-16 National Semiconductor Corporation Bumped integrated circuits for optical applications
US6709893B2 (en) * 1998-05-11 2004-03-23 Micron Technology, Inc. Interconnections for a semiconductor device and method for forming same
US6841855B2 (en) * 2003-04-28 2005-01-11 Intel Corporation Electronic package having a flexible substrate with ends connected to one another
US20050018495A1 (en) * 2004-01-29 2005-01-27 Netlist, Inc. Arrangement of integrated circuits in a memory module
US6849949B1 (en) * 1999-09-27 2005-02-01 Samsung Electronics Co., Ltd. Thin stacked package
US20050035440A1 (en) * 2001-08-22 2005-02-17 Tessera, Inc. Stacked chip assembly with stiffening layer
US20050040508A1 (en) * 2003-08-22 2005-02-24 Jong-Joo Lee Area array type package stack and manufacturing method thereof
US6867496B1 (en) * 1999-10-01 2005-03-15 Seiko Epson Corporation Interconnect substrate, semiconductor device, methods of fabricating, inspecting, and mounting the semiconductor device, circuit board, and electronic instrument
US6869825B2 (en) * 2002-12-31 2005-03-22 Intel Corporation Folded BGA package design with shortened communication paths and more electrical routing flexibility
US6998704B2 (en) * 2002-08-30 2006-02-14 Nec Corporation Semiconductor device and method for manufacturing the same, circuit board, electronic apparatus, and semiconductor device manufacturing apparatus

Family Cites Families (137)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3411122A (en) 1966-01-13 1968-11-12 Ibm Electrical resistance element and method of fabricating
US3436604A (en) * 1966-04-25 1969-04-01 Texas Instruments Inc Complex integrated circuit array and method for fabricating same
US3772776A (en) 1969-12-03 1973-11-20 Thomas & Betts Corp Method of interconnecting memory plane boards
US3727064A (en) * 1971-03-17 1973-04-10 Monsanto Co Opto-isolator devices and method for the fabrication thereof
US3746934A (en) 1971-05-06 1973-07-17 Siemens Ag Stack arrangement of semiconductor chips
US3766439A (en) 1972-01-12 1973-10-16 Gen Electric Electronic module using flexible printed circuit board with heat sink means
US3983547A (en) 1974-06-27 1976-09-28 International Business Machines - Ibm Three-dimensional bubble device
US4103318A (en) 1977-05-06 1978-07-25 Ford Motor Company Electronic multichip module
US4288841A (en) 1979-09-20 1981-09-08 Bell Telephone Laboratories, Incorporated Double cavity semiconductor chip carrier
US4398235A (en) 1980-09-11 1983-08-09 General Motors Corporation Vertical integrated circuit package integration
JPS57181146A (en) 1981-04-30 1982-11-08 Hitachi Ltd Resin-sealed semiconductor device
US4406508A (en) 1981-07-02 1983-09-27 Thomas & Betts Corporation Dual-in-line package assembly
US4420794A (en) 1981-09-10 1983-12-13 Research, Incorporated Integrated circuit switch
US4712129A (en) 1983-12-12 1987-12-08 Texas Instruments Incorporated Integrated circuit device with textured bar cover
KR890004820B1 (en) 1984-03-28 1989-11-27 인터내셔널 비지네스 머신즈 코포레이션 Stacked double density memory module using industry standard memory chips
US4587596A (en) * 1984-04-09 1986-05-06 Amp Incorporated High density mother/daughter circuit board connector
US4654944A (en) * 1985-09-13 1987-04-07 Graf Richard W Overhead cam valve spring compressor adapter
US4696525A (en) 1985-12-13 1987-09-29 Amp Incorporated Socket for stacking integrated circuit packages
US4763188A (en) * 1986-08-08 1988-08-09 Thomas Johnson Packaging system for multiple semiconductor devices
US4839717A (en) 1986-12-19 1989-06-13 Fairchild Semiconductor Corporation Ceramic package for high frequency semiconductor devices
US5159535A (en) 1987-03-11 1992-10-27 International Business Machines Corporation Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate
US4862249A (en) 1987-04-17 1989-08-29 Xoc Devices, Inc. Packaging system for stacking integrated circuits
US4855810A (en) 1987-06-02 1989-08-08 Gelb Allan S Thermoelectric heat pump
IT1214254B (en) 1987-09-23 1990-01-10 Sgs Microelettonica S P A SEMICONDUCTOR DEVICE IN PLASTIC OR CERAMIC CONTAINER WITH "CHIPS" FIXED ON BOTH SIDES OF THE CENTRAL ISLAND OF THE "FRAME".
US5016138A (en) * 1987-10-27 1991-05-14 Woodman John K Three dimensional integrated circuit package
US5198888A (en) * 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device
US4833568A (en) * 1988-01-29 1989-05-23 Berhold G Mark Three-dimensional circuit component assembly and method corresponding thereto
US5138434A (en) 1991-01-22 1992-08-11 Micron Technology, Inc. Packaging for semiconductor logic devices
US4956694A (en) 1988-11-04 1990-09-11 Dense-Pac Microsystems, Inc. Integrated circuit chip stacking
EP0388157B1 (en) 1989-03-15 1994-02-16 Ngk Insulators, Ltd. Ceramic lid for sealing semiconductor element and method of sealing a semiconductor element in a ceramic package
JP2647194B2 (en) 1989-04-17 1997-08-27 住友電気工業株式会社 Semiconductor package sealing method
US4953060A (en) 1989-05-05 1990-08-28 Ncr Corporation Stackable integrated circuit chip package with improved heat removal
US5057903A (en) 1989-07-17 1991-10-15 Microelectronics And Computer Technology Corporation Thermal heat sink encapsulated integrated circuit
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5068708A (en) 1989-10-02 1991-11-26 Advanced Micro Devices, Inc. Ground plane for plastic encapsulated integrated circuit die packages
US5229641A (en) 1989-11-25 1993-07-20 Hitachi Maxell, Ltd. Semiconductor card and manufacturing method therefor
US5041902A (en) 1989-12-14 1991-08-20 Motorola, Inc. Molded electronic package with compression structures
JPH03227541A (en) 1990-02-01 1991-10-08 Hitachi Ltd Semiconductor device
US5083697A (en) * 1990-02-14 1992-01-28 Difrancesco Louis Particle-enhanced joining of metal surfaces
US5041015A (en) 1990-03-30 1991-08-20 Cal Flex, Inc. Electrical jumper assembly
US5345205A (en) 1990-04-05 1994-09-06 General Electric Company Compact high density interconnected microwave system
US5261068A (en) 1990-05-25 1993-11-09 Dell Usa L.P. Dual path memory retrieval system for an interleaved dynamic RAM memory unit
US5050039A (en) 1990-06-26 1991-09-17 Digital Equipment Corporation Multiple circuit chip mounting and cooling arrangement
US5377077A (en) 1990-08-01 1994-12-27 Staktek Corporation Ultra high density integrated circuit packages method and apparatus
US5475920A (en) 1990-08-01 1995-12-19 Burns; Carmen D. Method of assembling ultra high density integrated circuit packages
US5446620A (en) 1990-08-01 1995-08-29 Staktek Corporation Ultra high density integrated circuit packages
US5499160A (en) * 1990-08-01 1996-03-12 Staktek Corporation High density integrated circuit module with snap-on rail assemblies
AU8519891A (en) * 1990-08-01 1992-03-02 Staktek Corporation Ultra high density integrated circuit packages, method and apparatus
US5148265A (en) * 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
JP3242101B2 (en) 1990-10-05 2001-12-25 三菱電機株式会社 Semiconductor integrated circuit
JPH04162556A (en) 1990-10-25 1992-06-08 Mitsubishi Electric Corp Lead frame and its manufacturing
US5117282A (en) * 1990-10-29 1992-05-26 Harris Corporation Stacked configuration for integrated circuit devices
JPH04284661A (en) * 1991-03-13 1992-10-09 Toshiba Corp Semiconductor device
US5219794A (en) 1991-03-14 1993-06-15 Hitachi, Ltd. Semiconductor integrated circuit device and method of fabricating same
US5158912A (en) 1991-04-09 1992-10-27 Digital Equipment Corporation Integral heatsink semiconductor package
US5138430A (en) 1991-06-06 1992-08-11 International Business Machines Corporation High performance versatile thermally enhanced IC chip mounting
JPH0513666A (en) 1991-06-29 1993-01-22 Sony Corp Complex semiconductor device
US5214307A (en) * 1991-07-08 1993-05-25 Micron Technology, Inc. Lead frame for semiconductor devices having improved adhesive bond line control
US5311401A (en) * 1991-07-09 1994-05-10 Hughes Aircraft Company Stacked chip assembly and manufacturing method therefor
US5252857A (en) 1991-08-05 1993-10-12 International Business Machines Corporation Stacked DCA memory chips
JP2967621B2 (en) 1991-08-27 1999-10-25 日本電気株式会社 Method of manufacturing package for semiconductor device
US5168926A (en) 1991-09-25 1992-12-08 Intel Corporation Heat sink design integrating interface material
US5198965A (en) * 1991-12-18 1993-03-30 International Business Machines Corporation Free form packaging of specific functions within a computer system
US5241454A (en) 1992-01-22 1993-08-31 International Business Machines Corporation Mutlilayered flexible circuit package
US5262927A (en) 1992-02-07 1993-11-16 Lsi Logic Corporation Partially-molded, PCB chip carrier package
US5224023A (en) * 1992-02-10 1993-06-29 Smith Gary W Foldable electronic assembly module
US5243133A (en) 1992-02-18 1993-09-07 International Business Machines, Inc. Ceramic chip carrier with lead frame or edge clip
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5229916A (en) 1992-03-04 1993-07-20 International Business Machines Corporation Chip edge interconnect overlay element
US5259770A (en) 1992-03-19 1993-11-09 Amp Incorporated Impedance controlled elastomeric connector
US5438224A (en) 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
US5361228A (en) 1992-04-30 1994-11-01 Fuji Photo Film Co., Ltd. IC memory card system having a common data and address bus
US5247423A (en) 1992-05-26 1993-09-21 Motorola, Inc. Stacking three dimensional leadless multi-chip module and method for making the same
US5343366A (en) 1992-06-24 1994-08-30 International Business Machines Corporation Packages for stacked integrated circuit chip cubes
US5432630A (en) 1992-09-11 1995-07-11 Motorola, Inc. Optical bus with optical transceiver modules and method of manufacture
US5731633A (en) * 1992-09-16 1998-03-24 Gary W. Hamilton Thin multichip module
US5402006A (en) * 1992-11-10 1995-03-28 Texas Instruments Incorporated Semiconductor device with enhanced adhesion between heat spreader and leads and plastic mold compound
US5313097A (en) * 1992-11-16 1994-05-17 International Business Machines, Corp. High density memory module
US5375041A (en) 1992-12-02 1994-12-20 Intel Corporation Ra-tab array bump tab tape based I.C. package
US5347428A (en) 1992-12-03 1994-09-13 Irvine Sensors Corporation Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip
US5455740A (en) * 1994-03-07 1995-10-03 Staktek Corporation Bus communication system for stacked high density integrated circuit packages
US5428190A (en) * 1993-07-02 1995-06-27 Sheldahl, Inc. Rigid-flex board with anisotropic interconnect and method of manufacture
US5337388A (en) 1993-08-03 1994-08-09 International Business Machines Corporation Matrix of pluggable connectors for connecting large numbers of clustered electrical and/or opticcal cables to a module
US5477082A (en) 1994-01-11 1995-12-19 Exponential Technology, Inc. Bi-planar multi-chip module
JPH07312469A (en) * 1994-05-16 1995-11-28 Nippon Mektron Ltd Structure of bent part of multilayer flexible circuit board
US5448511A (en) * 1994-06-01 1995-09-05 Storage Technology Corporation Memory stack with an integrated interconnect and mounting structure
US5523695A (en) * 1994-08-26 1996-06-04 Vlsi Technology, Inc. Universal test socket for exposing the active surface of an integrated circuit in a die-down package
US5592364A (en) * 1995-01-24 1997-01-07 Staktek Corporation High density integrated circuit module with complex electrical interconnect rails
US5514907A (en) * 1995-03-21 1996-05-07 Simple Technology Incorporated Apparatus for stacking semiconductor chips
US6025642A (en) * 1995-08-17 2000-02-15 Staktek Corporation Ultra high density integrated circuit packages
JPH09139559A (en) * 1995-11-13 1997-05-27 Minolta Co Ltd Connection structure of circuit board
KR0184076B1 (en) * 1995-11-28 1999-03-20 김광호 Three-dimensional stacked package
US5646446A (en) * 1995-12-22 1997-07-08 Fairchild Space And Defense Corporation Three-dimensional flexible assembly of integrated circuits
DE19626126C2 (en) * 1996-06-28 1998-04-16 Fraunhofer Ges Forschung Method for forming a spatial chip arrangement and spatial chip arrangement
US6121676A (en) * 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
US7149095B2 (en) * 1996-12-13 2006-12-12 Tessera, Inc. Stacked microelectronic assemblies
JP3455040B2 (en) * 1996-12-16 2003-10-06 株式会社日立製作所 Source clock synchronous memory system and memory unit
US5917709A (en) * 1997-06-16 1999-06-29 Eastman Kodak Company Multiple circuit board assembly having an interconnect mechanism that includes a flex connector
US5986209A (en) * 1997-07-09 1999-11-16 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
US6097087A (en) * 1997-10-31 2000-08-01 Micron Technology, Inc. Semiconductor package including flex circuit, interconnects and dense array external contacts
US5949657A (en) * 1997-12-01 1999-09-07 Karabatsos; Chris Bottom or top jumpered foldable electronic assembly
US5953215A (en) * 1997-12-01 1999-09-14 Karabatsos; Chris Apparatus and method for improving computer memory speed and capacity
US6266252B1 (en) * 1997-12-01 2001-07-24 Chris Karabatsos Apparatus and method for terminating a computer memory bus
US6233650B1 (en) * 1998-04-01 2001-05-15 Intel Corporation Using FET switches for large memory arrays
US6072233A (en) * 1998-05-04 2000-06-06 Micron Technology, Inc. Stackable ball grid array package
US6300679B1 (en) * 1998-06-01 2001-10-09 Semiconductor Components Industries, Llc Flexible substrate for packaging a semiconductor component
JP3842444B2 (en) * 1998-07-24 2006-11-08 富士通株式会社 Manufacturing method of semiconductor device
JP2000088921A (en) * 1998-09-08 2000-03-31 Sony Corp Semiconductor device
DE69938582T2 (en) * 1998-09-09 2009-06-04 Seiko Epson Corp. SEMICONDUCTOR ELEMENT, ITS MANUFACTURE, PCB AND ELECTRONIC APPARATUS
JP3602000B2 (en) * 1999-04-26 2004-12-15 沖電気工業株式会社 Semiconductor device and semiconductor module
JP2000353767A (en) * 1999-05-14 2000-12-19 Universal Instr Corp Board for mounting electronic component, package, mounting method, and method for housing integrated circuit chip in package
US6446158B1 (en) * 1999-05-17 2002-09-03 Chris Karabatsos Memory system using FET switches to select memory banks
US6376769B1 (en) * 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
US6675469B1 (en) * 1999-08-11 2004-01-13 Tessera, Inc. Vapor phase connection techniques
US6572387B2 (en) * 1999-09-24 2003-06-03 Staktek Group, L.P. Flexible circuit connector for stacked chip module
US6441476B1 (en) * 2000-10-18 2002-08-27 Seiko Epson Corporation Flexible tape carrier with external terminals formed on interposers
JP2001203319A (en) * 2000-01-18 2001-07-27 Sony Corp Laminated semiconductor device
JP2001217388A (en) * 2000-02-01 2001-08-10 Sony Corp Electronic device and method for manufacturing the same
US6444921B1 (en) * 2000-02-03 2002-09-03 Fujitsu Limited Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like
US6660561B2 (en) * 2000-06-15 2003-12-09 Dpac Technologies Corp. Method of assembling a stackable integrated circuit chip
US6560117B2 (en) * 2000-06-28 2003-05-06 Micron Technology, Inc. Packaged microelectronic die assemblies and methods of manufacture
US6552910B1 (en) * 2000-06-28 2003-04-22 Micron Technology, Inc. Stacked-die assemblies with a plurality of microelectronic devices and methods of manufacture
KR100340285B1 (en) * 2000-10-24 2002-06-15 윤종용 Memory module having series-connected printed circuit boards
US6392162B1 (en) * 2000-11-10 2002-05-21 Chris Karabatsos Double-sided flexible jumper assembly and method of manufacture
US6737891B2 (en) * 2001-02-01 2004-05-18 Chris Karabatsos Tri-directional, high-speed bus switch
US6410857B1 (en) * 2001-03-01 2002-06-25 Lockheed Martin Corporation Signal cross-over interconnect for a double-sided circuit card assembly
US6884653B2 (en) * 2001-03-21 2005-04-26 Micron Technology, Inc. Folded interposer
US6910268B2 (en) * 2001-03-27 2005-06-28 Formfactor, Inc. Method for fabricating an IC interconnect system including an in-street integrated circuit wafer via
US6707684B1 (en) * 2001-04-02 2004-03-16 Advanced Micro Devices, Inc. Method and apparatus for direct connection between two integrated circuits via a connector
US7115986B2 (en) * 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
US6627984B2 (en) * 2001-07-24 2003-09-30 Dense-Pac Microsystems, Inc. Chip stack with differing chip package types
KR20030029743A (en) * 2001-10-10 2003-04-16 삼성전자주식회사 Stack package using flexible double wiring substrate
US6620651B2 (en) * 2001-10-23 2003-09-16 National Starch And Chemical Investment Holding Corporation Adhesive wafers for die attach application
US6590282B1 (en) * 2002-04-12 2003-07-08 Industrial Technology Research Institute Stacked semiconductor package formed on a substrate and method for fabrication
US6600222B1 (en) * 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6838761B2 (en) * 2002-09-17 2005-01-04 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US7291906B2 (en) * 2002-12-31 2007-11-06 Ki Bon Cha Stack package and fabricating method thereof

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3436804A (en) * 1968-04-23 1969-04-08 Olin Mathieson Process for forming composite aluminum alloy
US3654394A (en) * 1969-07-08 1972-04-04 Gordon Eng Co Field effect transistor switch, particularly for multiplexing
US3806767A (en) * 1973-03-15 1974-04-23 Tek Wave Inc Interboard connector
US4079511A (en) * 1976-07-30 1978-03-21 Amp Incorporated Method for packaging hermetically sealed integrated circuit chips on lead frames
US4381421A (en) * 1980-07-01 1983-04-26 Tektronix, Inc. Electromagnetic shield for electronic equipment
US4437235A (en) * 1980-12-29 1984-03-20 Honeywell Information Systems Inc. Integrated circuit package
US4513368A (en) * 1981-05-22 1985-04-23 Data General Corporation Digital data processing system having object-based logical memory addressing and self-structuring modular memory
US4645944A (en) * 1983-09-05 1987-02-24 Matsushita Electric Industrial Co., Ltd. MOS register for selecting among various data inputs
US4733461A (en) * 1984-12-28 1988-03-29 Micro Co., Ltd. Method of stacking printed circuit boards
US4823234A (en) * 1985-08-16 1989-04-18 Dai-Ichi Seiko Co., Ltd. Semiconductor device and its manufacture
US4722691A (en) * 1986-02-03 1988-02-02 General Motors Corporation Header assembly for a printed circuit board
US4903169A (en) * 1986-04-03 1990-02-20 Matsushita Electric Industrial Co., Ltd. Shielded high frequency apparatus having partitioned shield case, and method of manufacture thereof
US4821007A (en) * 1987-02-06 1989-04-11 Tektronix, Inc. Strip line circuit component and method of manufacture
US4983533A (en) * 1987-10-28 1991-01-08 Irvine Sensors Corporation High-density electronic modules - process and product
US4985703A (en) * 1988-02-03 1991-01-15 Nec Corporation Analog multiplexer
US4891789A (en) * 1988-03-03 1990-01-02 Bull Hn Information Systems, Inc. Surface mounted multilayer memory printed circuit board
US4911643A (en) * 1988-10-11 1990-03-27 Beta Phase, Inc. High density and high signal integrity connector
US5276418A (en) * 1988-11-16 1994-01-04 Motorola, Inc. Flexible substrate electronic assembly
US5081067A (en) * 1989-02-10 1992-01-14 Fujitsu Limited Ceramic package type semiconductor device and method of assembling the same
US5104820A (en) * 1989-07-07 1992-04-14 Irvine Sensors Corporation Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting
US5198988A (en) * 1989-09-15 1993-03-30 Hewlett-Packard Company Method of determining optimum operating conditions in an electrochemical detector and electrochemical detector using the method
US5012323A (en) * 1989-11-20 1991-04-30 Micron Technology, Inc. Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
US5198955A (en) * 1990-07-30 1993-03-30 Nuheat Inc. Sealed plug-in GFCI
US5289346A (en) * 1991-02-26 1994-02-22 Microelectronics And Computer Technology Corporation Peripheral to area adapter with protective bumper for an integrated circuit chip
US5289062A (en) * 1991-03-18 1994-02-22 Quality Semiconductor, Inc. Fast transmission gate switch
US5099393A (en) * 1991-03-25 1992-03-24 International Business Machines Corporation Electronic package for high density applications
US5397916A (en) * 1991-12-10 1995-03-14 Normington; Peter J. C. Semiconductor device including stacked die
US5281852A (en) * 1991-12-10 1994-01-25 Normington Peter J C Semiconductor device including stacked die
US5895969A (en) * 1992-05-25 1999-04-20 Hitachi, Ltd. And Hitachi Vlsi Engineering Corp. Thin type semiconductor device, module structure using the device and method of mounting the device on board
US5610833A (en) * 1992-06-02 1997-03-11 Hewlett-Packard Company Computer-aided design methods and apparatus for multilevel interconnect technologies
US5729894A (en) * 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages
US5394303A (en) * 1992-09-11 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor device
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
US6205654B1 (en) * 1992-12-11 2001-03-27 Staktek Group L.P. Method of manufacturing a surface mount package
US5384690A (en) * 1993-07-27 1995-01-24 International Business Machines Corporation Flex laminate package for a parallel processor
US5620782A (en) * 1993-07-27 1997-04-15 International Business Machines Corporation Method of fabricating a flex laminate package
US5396573A (en) * 1993-08-03 1995-03-07 International Business Machines Corporation Pluggable connectors for connecting large numbers of electrical and/or optical cables to a module through a seal
US5386341A (en) * 1993-11-01 1995-01-31 Motorola, Inc. Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape
US5594275A (en) * 1993-11-18 1997-01-14 Samsung Electronics Co., Ltd. J-leaded semiconductor package having a plurality of stacked ball grid array packages
US5744627A (en) * 1994-01-28 1998-04-28 Prolinx, Inc. Boronic compound complexing reagents and complexes
US5502333A (en) * 1994-03-30 1996-03-26 International Business Machines Corporation Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
US5509197A (en) * 1994-06-10 1996-04-23 Xetel Corporation Method of making substrate edge connector
US5612570A (en) * 1995-04-13 1997-03-18 Dense-Pac Microsystems, Inc. Chip stack and method of making same
US5717556A (en) * 1995-04-26 1998-02-10 Nec Corporation Printed-wiring board having plural parallel-connected interconnections
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6034876A (en) * 1996-06-27 2000-03-07 Japan Aviation Electronics Industry, Limited Electronic device comprising structure fixing electrical connector directly to device case through no printed circuit board having the electrical connector
US6178093B1 (en) * 1996-06-28 2001-01-23 International Business Machines Corporation Information handling system with circuit assembly having holes filled with filler material
US6336262B1 (en) * 1996-10-31 2002-01-08 International Business Machines Corporation Process of forming a capacitor with multi-level interconnection technology
US6699730B2 (en) * 1996-12-13 2004-03-02 Tessers, Inc. Stacked microelectronic assembly and method therefor
US20040045159A1 (en) * 1996-12-13 2004-03-11 Tessera, Inc. Electrical connection with inwardly deformable contacts
US5895970A (en) * 1997-05-02 1999-04-20 Nec Corporation Semiconductor package having semiconductor element, mounting structure of semiconductor package mounted on circuit board, and method of assembling semiconductor package
US6208521B1 (en) * 1997-05-19 2001-03-27 Nitto Denko Corporation Film carrier and laminate type mounting structure using same
US6014316A (en) * 1997-06-13 2000-01-11 Irvine Sensors Corporation IC stack utilizing BGA contacts
US6028352A (en) * 1997-06-13 2000-02-22 Irvine Sensors Corporation IC stack utilizing secondary leadframes
US5895705A (en) * 1997-07-11 1999-04-20 Highland Industries, Inc. Awning and backlit sign fabric having a selectively eradicable ink layer and a process for producing same
US6040624A (en) * 1997-10-02 2000-03-21 Motorola, Inc. Semiconductor device package and method
US5869353A (en) * 1997-11-17 1999-02-09 Dense-Pac Microsystems, Inc. Modular panel stacking process
US6504104B2 (en) * 1997-12-10 2003-01-07 Siemens Aktiengesellschaft Flexible wiring for the transformation of a substrate with edge contacts into a ball grid array
US6186106B1 (en) * 1997-12-29 2001-02-13 Visteon Global Technologies, Inc. Apparatus for routing electrical signals in an engine
US6028365A (en) * 1998-03-30 2000-02-22 Micron Technology, Inc. Integrated circuit package and method of fabrication
US6172874B1 (en) * 1998-04-06 2001-01-09 Silicon Graphics, Inc. System for stacking of integrated circuit packages
US6709893B2 (en) * 1998-05-11 2004-03-23 Micron Technology, Inc. Interconnections for a semiconductor device and method for forming same
US6187652B1 (en) * 1998-09-14 2001-02-13 Fujitsu Limited Method of fabrication of multiple-layer high density substrate
US6360935B1 (en) * 1999-01-26 2002-03-26 Board Of Regents Of The University Of Texas System Apparatus and method for assessing solderability
US6360433B1 (en) * 1999-04-23 2002-03-26 Andrew C. Ross Universal package and method of forming the same
US6514793B2 (en) * 1999-05-05 2003-02-04 Dpac Technologies Corp. Stackable flex circuit IC package and method of making same
US6351029B1 (en) * 1999-05-05 2002-02-26 Harlan R. Isaak Stackable flex circuit chip package and method of making same
US6218731B1 (en) * 1999-05-21 2001-04-17 Siliconware Precision Industries Co., Ltd. Tiny ball grid array package
US6673651B2 (en) * 1999-07-01 2004-01-06 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor device including semiconductor elements mounted on base plate
US6538895B2 (en) * 1999-07-15 2003-03-25 Infineon Technologies Ag TSOP memory chip housing configuration
US6689634B1 (en) * 1999-09-22 2004-02-10 Texas Instruments Incorporated Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability
US6849949B1 (en) * 1999-09-27 2005-02-01 Samsung Electronics Co., Ltd. Thin stacked package
US6867496B1 (en) * 1999-10-01 2005-03-15 Seiko Epson Corporation Interconnect substrate, semiconductor device, methods of fabricating, inspecting, and mounting the semiconductor device, circuit board, and electronic instrument
US6527984B1 (en) * 1999-10-22 2003-03-04 Sony Chemicals Corporation Low temperature-curable connecting material for anisotropically electroconductive connection
US20030045025A1 (en) * 2000-01-26 2003-03-06 Coyle Anthony L. Method of fabricating a molded package for micromechanical devices
US6528870B2 (en) * 2000-01-28 2003-03-04 Kabushiki Kaisha Toshiba Semiconductor device having a plurality of stacked wiring boards
US6677670B2 (en) * 2000-04-25 2004-01-13 Seiko Epson Corporation Semiconductor device
US6522018B1 (en) * 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US20020006032A1 (en) * 2000-05-23 2002-01-17 Chris Karabatsos Low-profile registered DIMM
US6683377B1 (en) * 2000-05-30 2004-01-27 Amkor Technology, Inc. Multi-stacked memory package
US20020030995A1 (en) * 2000-08-07 2002-03-14 Masao Shoji Headlight
US6690584B2 (en) * 2000-08-14 2004-02-10 Fujitsu Limited Information-processing device having a crossbar-board connected to back panels on different sides
US6707664B2 (en) * 2001-02-11 2004-03-16 Micron Technology, Inc. Expandable keyboard for portable computers
US6532162B2 (en) * 2001-05-26 2003-03-11 Intel Corporation Reference plane of integrated circuit packages
US20030016710A1 (en) * 2001-07-19 2003-01-23 Satoshi Komoto Semiconductor laser device including light receiving element for receiving monitoring laser beam
US6509639B1 (en) * 2001-07-27 2003-01-21 Charles W. C. Lin Three-dimensional stacked semiconductor package
US20050035440A1 (en) * 2001-08-22 2005-02-17 Tessera, Inc. Stacked chip assembly with stiffening layer
US20030049886A1 (en) * 2001-09-07 2003-03-13 Salmon Peter C. Electronic system modules and method of fabrication
US20040031972A1 (en) * 2001-10-09 2004-02-19 Tessera, Inc. Stacked packages
US20040000708A1 (en) * 2001-10-26 2004-01-01 Staktek Group, L.P. Memory expansion and chip scale stacking system and method
US6707148B1 (en) * 2002-05-21 2004-03-16 National Semiconductor Corporation Bumped integrated circuits for optical applications
US20040004281A1 (en) * 2002-07-03 2004-01-08 Jin-Chuan Bai Semiconductor package with heat sink
US20040021211A1 (en) * 2002-08-05 2004-02-05 Tessera, Inc. Microelectronic adaptors, assemblies and methods
US6998704B2 (en) * 2002-08-30 2006-02-14 Nec Corporation Semiconductor device and method for manufacturing the same, circuit board, electronic apparatus, and semiconductor device manufacturing apparatus
US6869825B2 (en) * 2002-12-31 2005-03-22 Intel Corporation Folded BGA package design with shortened communication paths and more electrical routing flexibility
US6841855B2 (en) * 2003-04-28 2005-01-11 Intel Corporation Electronic package having a flexible substrate with ends connected to one another
US20050040508A1 (en) * 2003-08-22 2005-02-24 Jong-Joo Lee Area array type package stack and manufacturing method thereof
US20050018495A1 (en) * 2004-01-29 2005-01-27 Netlist, Inc. Arrangement of integrated circuits in a memory module

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090016033A1 (en) * 2007-07-12 2009-01-15 Seng Guan Chow Integrated circuit package system with flexible substrate and mounded package
US8031475B2 (en) 2007-07-12 2011-10-04 Stats Chippac, Ltd. Integrated circuit package system with flexible substrate and mounded package
US9030006B2 (en) 2008-06-09 2015-05-12 Stats Chippac Ltd. Integrated circuit package system with internal stacking module
US20090309197A1 (en) * 2008-06-11 2009-12-17 Seng Guan Chow Integrated circuit package system with internal stacking module
US8278141B2 (en) * 2008-06-11 2012-10-02 Stats Chippac Ltd. Integrated circuit package system with internal stacking module

Also Published As

Publication number Publication date
US20030234443A1 (en) 2003-12-25
US7180167B2 (en) 2007-02-20
US7626273B2 (en) 2009-12-01
US20050146031A1 (en) 2005-07-07
US20070117262A1 (en) 2007-05-24
US20090124045A1 (en) 2009-05-14

Similar Documents

Publication Publication Date Title
US7180167B2 (en) Low profile stacking system and method
US7094632B2 (en) Low profile chip scale stacking system and method
JP4938980B2 (en) Non-eutectic solder composition
EP0527044B1 (en) Memory package
US7488896B2 (en) Wiring board with semiconductor component
JPH04273453A (en) Method for direct chip mounting
JPH098447A (en) Chip mounting circuit card structure
JPH098451A (en) Method of manufacturing chip mounting circuit card
WO1993006964A1 (en) Method for forming solder bump interconnections to a solder-plated circuit trace
JP2004526309A (en) Method of forming electronic structure
WO2021012228A1 (en) Electronic packaging assembly, camera, movable platform, and preparation method for electronic packaging assembly
US7215030B2 (en) Lead-free semiconductor package
JP4181759B2 (en) Electronic component mounting method and mounting structure manufacturing method
JP2000151095A (en) Method of soldering part on printed wiring board and manufacture of printed wiring board
JP2008071779A (en) Mounting structure
US20060049238A1 (en) Solderable structures and methods for soldering
JP2007141973A (en) Wiring circuit board with semiconductor components
JP2008171975A (en) Mounting method and mounting structure of semiconductor component
JP2011216813A (en) Solder joint method, semiconductor device and method of manufacturing the same
JP4667208B2 (en) Wiring board with semiconductor parts
JP3434775B2 (en) Mounting method of back electrode type electric component and integrated land
JP4527617B2 (en) Circuit board and electronic device using the same
JPH04342185A (en) Hybrid ic
JPH11261203A (en) Bump carrier and its using method
JP2005354096A (en) Method for mounting electronic component, and method for manufacturing mounting structure

Legal Events

Date Code Title Description
AS Assignment

Owner name: ENTORIAN TECHNOLOGIES, LP, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PARTRIDGE, JULIAN;CADY, JAMES W.;WILDER, JAMES;AND OTHERS;REEL/FRAME:021577/0527;SIGNING DATES FROM 20030605 TO 20030606

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION