Búsqueda Imágenes Maps Play YouTube Noticias Gmail Drive Más »
Iniciar sesión
Usuarios de lectores de pantalla: deben hacer clic en este enlace para utilizar el modo de accesibilidad. Este modo tiene las mismas funciones esenciales pero funciona mejor con el lector.

Patentes

  1. Búsqueda avanzada de patentes
Número de publicaciónUS20070117262 A1
Tipo de publicaciónSolicitud
Número de solicitudUS 11/626,316
Fecha de publicación24 May 2007
Fecha de presentación23 Ene 2007
Fecha de prioridad26 Oct 2001
También publicado comoUS7180167, US7626273, US20030234443, US20050146031, US20070114649, US20090124045
Número de publicación11626316, 626316, US 2007/0117262 A1, US 2007/117262 A1, US 20070117262 A1, US 20070117262A1, US 2007117262 A1, US 2007117262A1, US-A1-20070117262, US-A1-2007117262, US2007/0117262A1, US2007/117262A1, US20070117262 A1, US20070117262A1, US2007117262 A1, US2007117262A1
InventoresJulian Partridge, James Cady, James Wilder, David Roper, James Wehrly
Cesionario originalStaktek Group L.P., A Texas Limited Partnership
Exportar citaBiBTeX, EndNote, RefMan
Enlaces externos: USPTO, Cesión de USPTO, Espacenet
Low Profile Stacking System and Method
US 20070117262 A1
Resumen
The present invention provides a system and method that amounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.
Imágenes(5)
Previous page
Next page
Reclamaciones(9)
1. A method of constructing a stacked circuit module comprising the steps of:
providing a first CSP having a plurality of ball contacts;
removing the plurality of ball contacts from the first CSP leaving a plurality of CSP pads on the first CSP;
providing substrate having a plurality of substrate contacts;
applying a solder paste to the plurality of substrate contacts of the substrate, the solder paste being comprised of an alloy of lead having at melting point, the melting point being equal to or greater than 235° C.;
positioning the first CSP and the substrate relative to each other to place the CSP pads of the first CSP in contact with the substrate contacts of the substrate to which the solder paste has been applied;
heating the first CSP and the substrate to cause the temperature at the CSP contacts and substrate contacts to reach the melting point.
2. The method of claim 1 in which solder remains upon the plurality of CSP contacts after the removal of the ball contacts from the first CSP.
3. The method of claim 1 in which the substrate is a flexible circuit.
4. The method of claim 1 further comprising the step of connecting a second CSP to the substrate.
5. The method of claim 1 in which the substrate is a flexible circuit and further comprising the step of connecting a second CSP to the flexible circuit with one alloy of lead having a second CSP melting point equal to or greater than 235° C. and disposing the second CSP above the first CSP.
6. The method of claim 5 in which portions of the flexible circuit are disposed between the first and second CSPs.
7. A method of constructinig a stacked circuit module comprising the steps of:
providing a first CSP having a plurality of ball contacts;
removing, the plurality of ball contacts from the first CSP leaving a plurality of CSP pads on the first CSP;
providing a substrate having a plurality of substrate contacts;
applying a solder paste to the plurality of CSP pads, the solder paste being comprised of an alloy of lead having a melting point, the melting point being equal to or greater than 235° C.;
positioning the first CSP and the substrate relative to each other to place the CSP pads to which the solder paste has been applied in contact with the substrate contacts of the substrate;
heating the first CSP and the substrate to cause the temperature at the CSP contacts and substrate contacts to reach the melting point.
8. A method of populating a circuit board comprising the steps of:
obtaining a high-density circuit module comprised of:
two or more packaged integrated circuits;
a flexible circuit for connection between the two or more packaged integrated circuits, the connection between the two or more packaged integrated circuits, being implemented through HT joints, the HT joints having, a melting point range of between X and Y degrees Centigrade, where X is less than Y;
attaching the high-density circuit module to the circuit board with solder joints, the solder joints having a melting point range of between A, and B degrees Centigrade, where A is less than B and A and B are both less than X.
9. A method of populating a circuit board comprising the steps of:
constructing a high-density circuit module having two or more integrated circuits with one integrated circuit disposed above another, the construction being implemented with a first solder having a melting point of X degrees; and
attaching the stacked circuit module to a circuit board with a second solder having a melting point of Y degrees where Y is less than X.
Descripción
    RELATED APPLICATIONS
  • [0001]
    The present application is a division of application Ser. No. 11/011,469, filed Dec. 14, 2004, pending, which is a division of application Ser. No. 10/457,608, filed Jun. 9, 2003, which is a continuation-in-part of U.S. Pat. application Ser. No. 10/005,581, filed Oct. 26, 2001, all of which are hereby incorporated by reference.
  • TECHNICAL FIELD
  • [0002]
    The present invention relates to mounting integrated circuit devices on substrates and to mounting integrated circuits on substrates employed in stacked modules.
  • BACKGROUND OF THE INVENTION
  • [0003]
    A variety of methods are used to mount integrated circuit devices to substrates such as PWBs and flex circuitry. Solder paste is selectively applied to the integrated circuit device or substrate to which the IC is to be attached. The device and substrate are exposed to reflow temperatures of approximately 220° C. The device is, consequently, soldered to the substrate.
  • [0004]
    Typically, however, the formed solder joints will re-melt during subsequent processing. Common tin-lead solders start to melt at 183° C. and, when exposed to such temperatures and higher, the exposed joint may re-melt and become unreliable.
  • [0005]
    What is needed, therefore, is a technique and system for mounting integrated circuit devices on substrates that provides an efficient and readily implemented technique to create structures that reliably withstand subsequent exposure to typical tin-lead solder melting point temperatures.
  • SUMMARY OF THE INVENTION
  • [0006]
    The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or the contacts of the packaged device. The integrated circuit device is positioned to contact the contacts of the substrate with the higher temperature soldier alloy paste between. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically the created joints are low in profile. In a method in accordance with the present invention, a first solder used to construct a stacked module has a higher melting point than a second solder used to populate a board with that module.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0007]
    FIG. 1 depicts a typical prior art packaged integrated circuit device.
  • [0008]
    FIG. 2 depicts the device of FIG. 1 from which the solder ball contacts have been removed.
  • [0009]
    FIG. 3 depicts a set of substrate contacts upon which a high temperature solder paste has been applied in accordance with a preferred embodiment of the present invention.
  • [0010]
    FIG. 4 depicts portions of two flexible circuit connectors prepared for mounting of an integrated circuit device in accordance with a preferred embodiment of the present invention.
  • [0011]
    FIG. 5 depicts a device-substrate assembly in accordance with a preferred embodiment of the present invention.
  • [0012]
    FIG. 6 depicts a two-high integrated circuit module mounted to the two flexible circuit connectors depicted in FIG. 4 in accordance with a preferred embodiment of the present invention.
  • [0013]
    FIG. 7 depicts a four-high stacked module devised in accordance with a preferred embodiment of the present invention.
  • DESCRIPTION OF PREFERRED EMBODIMENTS
  • [0014]
    FIG. 1 depicts an exemplar integrated circuit device 10 having upper surface 11 and lower surface 13. Device 10 is an example of one type of the general class of devices commonly known in the art as chip-scale-packaged integrated circuits (“CSPs”). The present invention may employed with a wide variety of integrated circuit devices and is not, as those of skill in the art will understand, limited to devices heaving the profile depicted in FIG. 1. Further, although its preferred use is with plastic-bodied CSP devices, the invention provides advantages in mounting a variety of packaged integrated circuit devices in a wide variety of configurations including leaded and CSP topologies.
  • [0015]
    Exemplar integrated circuit device 10 may include one or more integrated circuit die and body 12 and a set of contacts 14. The illustrated integrated circuit device 10 has CSP ball contacts 14 arrayed along surface 13 of its body 12. Typically, when integrated circuit device 10 is a CSP device, CSP bail contacts 14 are, as depicted, balls that are a mixture of tin and lead with a common relative composition of 63% tin and 37% lead. Such contacts typically have a melting point of about 183° C. Other contacts are sometimes found along a planar surface of integrated circuit devices and such other contacts may also be treated in accordance with the present invention where the opportunity arises as will be understood after gaining familiarity with the present disclosure.
  • [0016]
    In the depiction of FIG. 2, CSP ball contacts 14 have been removed, leaving CSP pads 16 arrayed along lower surface 13. CSP pads 16 will typically exhibit a residual thin layer of tin/lead mixture after removal of CSP ball contacts 14. As those of skill will know, CSPs may be received without attached balls and the process and structures described herein will then not require “removal” of balls. Further, embodiments of the present invention may be implemented with CSPs already bearing ball contacts comprised of high temperature solders.
  • [0017]
    FIG. 3 depicts exemplar substrate 18 on which are disposed contacts 20. Substrate 18 is depicted as a rigid board such as a PWB or PCB such as are known in the art. In accordance with a preferred embodiment of the present invention, a solder paste 22 is applied to substrate contacts 20. In accordance with an alternative preferred embodiment of the invention, solder paste 22 is applied to the (CSP pads 16 and not the substrate contacts 20. However, as those of skill will recognize, solder paste 22 may applied to both substrate contacts 20 and CSP pads 16 (or a set of contacts of other configuration when devices that are not CSP are used in accordance with the invention.) As those of skill understand, solder paste is a mixture of solder particles and flux.
  • [0018]
    Two or more of the elements lead, tin, silver, copper, antimony or indium may be employed in a variety of combinations to devise a solder to be employed in solder paste 22 in accordance with the present invention. Therefore, in accordance with preferred embodiments of the present invention, a solder alloy employed in solder paste 22 exhibits a melting point equal to or greater than 235° C. and preferably between 235° C. and 312° C. The alloy chosen should not have a melting point so high that the IC package is adversely affected, but it should also not be so low as to remelt during board assembly operations.
  • [0019]
    Some market participants are starting to implement lead-free solders. Such lead-free solders will typically have melting points higher than those found in lead inclusive solders. Typically, those who use lead-free solders to populate boards with stacked modules will for example, employ temperatures up to 240° C. in the process of attachment of stacked modules to boards. Consequently, a HT joint implemented with a lead-free alloy will, in conformity with preferred embodiments of the present invention, exhibit a melting point greater than those lead-free solders used to populate boards. Consequently, a preferred implementation of the HT joints of the present invention will have a melting point range of between 245° C. and 265° C. The lead-free solder alloy employed in such HT joints will be comprised of it least two of the following elements: tin, silver, copper, or indium.
  • [0020]
    Preferably, an alloy used as a solder in the present invention will melt over a narrow temperature range. Disintegration of the module during, board attachment or population will be less likely if the melt range is narrow. Most preferably, the top of the melting point range of the solder used in board attachment should be exceeded by 15° C. by the melting point of the solder used to manufacture the stacked module although in the case of lead-free solders, this is reduced to ameliorate issues that could arise from exposure of the package to high temperatures.
  • [0021]
    The followings combinations have been found to exhibit the following melting points, and the below recited combinations are merely a representative, but not exhaustive, list of examples of solder alloys appropriate for use in the present invention. As those of skill will recognize, these examples are instructive in selecting other preferred particular combinations of lead, tin, silver, copper, antimony, and indium that are readily employed to advantage in the present invention so as to arrive at alloys of at least two of the following solder elements: lead, tin, silver, copper, antimony, and indium that have in their combined mixture, a preferred melting point between 235° C. to 312° C. inclusive.
  • [0022]
    a. A combination of 95% Sn and 5% Sb melts over a range of 235° C. to 240° C.
  • [0023]
    b. A combination of 83% Pb and 10% Sb and 5% Sn and 2% Ag melts over a range of 237° C. to 247° C.
  • [0024]
    c. A combination of 85% Pb and 10% Sb and 5% Sn melts over a range of 245° C. to 255° C.
  • [0025]
    d. A combination of 90% Pb and 10% Sb melts over a range of 252° C. to 260° C.
  • [0026]
    e. A combination of 92.5% Pb, 5% Sn and 2.5% Ag melts over a range of 287° C. to 296° C.
  • [0027]
    f. A combination of 90% Pb and 10% Sn melts over a range of 275° C. to 302° C.
  • [0028]
    g. A combination of 95% Pb and 5% Sn melts over a range of 308° C. to 312°C.
  • [0029]
    h. A combination of 75% Pb and 25% Indium melts over a range of 240° C. to 260° C.
  • [0030]
    Those of skill will note that solder alloys or mixtures may also be employed in embodiments of the present invention that exhibit melting points lower than 235° C., as would be exhibited for example with a 97% Sn and a 3% Sb alloy, but preferred embodiments will employ solder mixtures or alloys that melt between 235° C. and 312° C. inclusive.
  • [0031]
    FIG. 4 depicts portions of two flexible circuit connectors 24A and 24B prepared for mounting of a device 10 in accordance with a preferred embodiment of the present invention. Exemplar flex circuits 24A and 24B may be simple flex circuitry or may exhibit the more sophisticated designs of flex circuitry such as those that would be constructed in accordance with the detailed descriptions provided in U.S. Pat. application Ser. No. 10/005,581 which has been made part of this application by incorporation by reference. For clarity of exposition, depicted flex circuits 24A and 24B exhibit a single conductive layer 26 and a first outer layer 28. Conductive layer 26 is supported by substrate layer 30, which, in a preferred embodiment, is a polyimide. Outer layer 32 resides along the lower surface of the flex circuits 24A and 24B. Optional outer layers 28 and 32, when present, are typically a covercoat or solder mask material. Windows 34 are created through outer layer 32 and intermediate layer 30 to expose flex contacts 36.
  • [0032]
    As depicted in FIG. 4, solder paste 22 is applied to flex contacts 36 which are remarked at the level of conductive layer 26. Solder paste 22 may also alternatively or in addition, be applied to the CSP pads 16 of a CSP. Windows 34 provide openings through which module contacts may be disposed in a later stacked module assembly step. Those of skill will recognize that the method of the present invention is applicable to a wide variety of substrates including solid PWB's, rigid flex, and flexible substrates such as flexible circuits, for example, and the substrate employed can be prepared in accordance with the present invention in a manner appropriate for the intended application. Where the invention is employed with rigid substrates such as a PWB, multilayer strategies and windowing in substrate layers are techniques which are useful in conjunction with the present invention, but not essential.
  • [0033]
    FIG. 5 depicts a device-substrate assembly in accordance with a preferred embodiment of the present invention as may be employed in the construction of a low profile stacked module. The features depicted in FIG. 5 are not drawn to scale, and show various features in an enlarged aspect for purposes of illustration. As shown, integrated circuit device 10 is disposed upon flex circuits 24A and 24B which have been, in a preferred embodiment of the method of the present invention, previously prepared as shown in earlier FIG. 4. Module contacts 40 have been appended to flex circuits 24A and 24B to provide connective facility for the device-flex combination whether as part of a stacked module or otherwise.
  • [0034]
    High temperature joint contacts 38 (“HT joints”) are formed by the melting of the lead alloy in previously applied solder paste 22 and the application of a selected heat range appropriate for the solder mixtures identified previously. Thus, HT joints 38 will, after solidification, typically not re-melt unless exposed subsequently to such temperature ranges. The temperature range applied in this step of assembly will not typically be subsequently encountered in a later assembly operation such as, for example, the application of a stacked module to a DIMM board. Consequently, in one embodiment, the present invention is articulated as a stacked module having HT joints that is appended to a DIMM board with traditional lower melting point solder.
  • [0035]
    FIG. 6 depicts a two-high stacked module devised in accordance with a preferred embodiment of the present invention. Stacked module 5O shown in FIG. 6 includes lower integrated circuit device 52 and upper integrated circuit device 54. A stacked module 50 may be devised in accordance with the present invention that includes more than two packaged integrated circuit devices. Flex circuits 56A and 56B are depicted connecting lower integrated circuit device 52 and upper integrated circuit device 54, Those of skill will also recognize that module 50 may be implemented with a single flexible circuit connector. Further, the flexible circuit connectors employed in accordance with the invention may exhibit one or more conductive layers. Flex circuits 56A and 56B may be any circuit connector structure that provides connective facility between two integrated circuits having a contact array. Those of skill will note that flexible circuits 56A and 56B may exhibit single conductive layers (such as, for example, the flexible circuit connectors earlier illustrated herein and identified for descriptive purposes as flex circuits 24A and 24B in FIG. 5) or may exhibit multiple conductive layers. Examples of other preferred flexible circuit structures are found in U.S. application Ser. No. 10/005,581 which has been incorporated by reference and those of skill will readily appreciate how a variety of circuit structures may be employed in preferred embodiments. Further, the connective structures used to connect lower integrated circuit 52 with upper integrated circuit 54 need not literally be flexible circuit connectors but may be flexible in portions and rigid in other portions.
  • [0036]
    HT contacts 38 are employed in the preferred embodiment of FIG. 6 to provide connective facility between the respective integrated circuits and contacts borne by the flex circuits 56A and 56B. Preferably, HT joints 38 will exhibit a height dimension smaller than that of CSP ball contacts 14 shown earlier as part of typical CSPs in FIG. 1. As those of skill will recognize, HT joints 38 are depicted in a scale that is enlarged relative to joint sizes that would typically be encountered in actual practice of preferred modes of the invention. Thus, module 50 will preferably present a lower profile than stacked modules created employing typical CSP contacts 14 on each of the constituent integrated circuit packages employed in a stacked module 50.
  • [0037]
    FIG. 7 depicts module 60 as having lower integrated circuit element 52, upper IC element 54, 3rd IC element 58, and 4th IC element 62. When the present invention is employed between flex circuits in stacking multiple levels of CSPs, as for example in FIG. 7, some embodiments will present HT contacts that have minimal heights that do not cause appreciable separation between the flex circuitry associated IC 52 and IC 54, for example, or between IC 54 and 62, for example. For such embodiments, the apparent height for illustrated HT joints 39, particularly, that lie between respective layers of flex circuitry will be understood to be exaggerated in the depiction of FIG. 7. Three sets of flex circuitry pairs 56A and 56B are a shown but, as in other embodiments, the invention may be implemented with a variety of substrates including single flex circuits in place of the depicted pair and with flexible circuits that have one or plural conductive layers.
  • [0038]
    As shown, the HT joints provide connections between integrated circuit devices and substrates and the overall profile of module 60 is reduced by use of the present invention that provides advantages in subsequent processing steps such as, for example, affixation of module 60 to DIMM boards, for example.
  • [0039]
    To construct a stacked module in accordance with a preferred embodiment of the present invention, if present, ball contacts 14 are removed from a CSP leaving CSP contacts 16 that typically exhibit a residual layer of solder. A high temperature solder paste composed from a lead alloy or mixture that has a preferable melting point equal to or higher than 235° C. and preferably less than 312° C. is applied to substrate contacts 20 of a substrate such as a flexible circuit and/or the substrate contacts to which it is to be mounted. The CSP is positioned to place the CSP pads 16 and substrate contacts 22 in appropriate proximity. Heat is applied sufficient to melt the lead solder alloy of solder paste 22 thus forming HT joints 38. The flexible circuit is positioned to place portions of the flexible circuit connector between the first CSP and a second CSP that is connected to the substrate with HT joints created using the process described for creating HT joints.
  • [0040]
    In understanding the present invention, it may be helpful to articulate the relative melting points in terms of variables to illustrate the relationships between the HT joints used to construct a stacked module and the solders used to populate a board with such a HT joint-implemented stacked module. In use in board population, the present invention will provide a stacked high module that is assembled using the HT joints that exhibit melting point ranges between X and Y degrees where X is less than Y. Attachment of the stacked module to a board is then implemented with a solder having a melting point between A and B degrees where A and B are less than X.
  • [0041]
    Although the present invention has been described in detail, it will be apparent to those skilled in the art that the invention may be embodied in a variety of specific firms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.
Citas de patentes
Patente citada Fecha de presentación Fecha de publicación Solicitante Título
US3436604 *25 Abr 19661 Abr 1969Texas Instruments IncComplex integrated circuit array and method for fabricating same
US3654394 *8 Jul 19694 Abr 1972Gordon Eng CoField effect transistor switch, particularly for multiplexing
US3806767 *15 Mar 197323 Abr 1974Tek Wave IncInterboard connector
US4079511 *30 Jul 197621 Mar 1978Amp IncorporatedMethod for packaging hermetically sealed integrated circuit chips on lead frames
US4381421 *1 Jul 198026 Abr 1983Tektronix, Inc.Electromagnetic shield for electronic equipment
US4437235 *23 Ago 198220 Mar 1984Honeywell Information Systems Inc.Integrated circuit package
US4513368 *22 May 198123 Abr 1985Data General CorporationDigital data processing system having object-based logical memory addressing and self-structuring modular memory
US4645944 *4 Sep 198424 Feb 1987Matsushita Electric Industrial Co., Ltd.MOS register for selecting among various data inputs
US4722691 *3 Feb 19862 Feb 1988General Motors CorporationHeader assembly for a printed circuit board
US4733461 *24 Dic 198529 Mar 1988Micro Co., Ltd.Method of stacking printed circuit boards
US4821007 *6 Feb 198711 Abr 1989Tektronix, Inc.Strip line circuit component and method of manufacture
US4823234 *1 Jul 198618 Abr 1989Dai-Ichi Seiko Co., Ltd.Semiconductor device and its manufacture
US4891789 *3 Mar 19882 Ene 1990Bull Hn Information Systems, Inc.Surface mounted multilayer memory printed circuit board
US4903169 *19 Sep 198820 Feb 1990Matsushita Electric Industrial Co., Ltd.Shielded high frequency apparatus having partitioned shield case, and method of manufacture thereof
US4911643 *3 Ago 198927 Mar 1990Beta Phase, Inc.High density and high signal integrity connector
US4983533 *28 Oct 19878 Ene 1991Irvine Sensors CorporationHigh-density electronic modules - process and product
US4985703 *2 Feb 198915 Ene 1991Nec CorporationAnalog multiplexer
US5012323 *20 Nov 198930 Abr 1991Micron Technology, Inc.Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
US5081067 *10 May 199114 Ene 1992Fujitsu LimitedCeramic package type semiconductor device and method of assembling the same
US5099393 *25 Mar 199124 Mar 1992International Business Machines CorporationElectronic package for high density applications
US5104820 *24 Jun 199114 Abr 1992Irvine Sensors CorporationMethod of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting
US5198888 *20 Dic 199030 Mar 1993Hitachi, Ltd.Semiconductor stacked device
US5198965 *18 Dic 199130 Mar 1993International Business Machines CorporationFree form packaging of specific functions within a computer system
US5276418 *25 Mar 19914 Ene 1994Motorola, Inc.Flexible substrate electronic assembly
US5281852 *10 Dic 199125 Ene 1994Normington Peter J CSemiconductor device including stacked die
US5289062 *23 Mar 199322 Feb 1994Quality Semiconductor, Inc.Fast transmission gate switch
US5289346 *16 Feb 199322 Feb 1994Microelectronics And Computer Technology CorporationPeripheral to area adapter with protective bumper for an integrated circuit chip
US5384690 *27 Jul 199324 Ene 1995International Business Machines CorporationFlex laminate package for a parallel processor
US5386341 *1 Nov 199331 Ene 1995Motorola, Inc.Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape
US5394303 *9 Sep 199328 Feb 1995Kabushiki Kaisha ToshibaSemiconductor device
US5396573 *3 Ago 19937 Mar 1995International Business Machines CorporationPluggable connectors for connecting large numbers of electrical and/or optical cables to a module through a seal
US5397916 *26 Jul 199314 Mar 1995Normington; Peter J. C.Semiconductor device including stacked die
US5484959 *11 Dic 199216 Ene 1996Staktek CorporationHigh density lead-on-package fabrication method and apparatus
US5502333 *30 Mar 199426 Mar 1996International Business Machines CorporationSemiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
US5509197 *10 Jun 199423 Abr 1996Xetel CorporationMethod of making substrate edge connector
US5594275 *18 Nov 199414 Ene 1997Samsung Electronics Co., Ltd.J-leaded semiconductor package having a plurality of stacked ball grid array packages
US5610833 *25 Sep 199511 Mar 1997Hewlett-Packard CompanyComputer-aided design methods and apparatus for multilevel interconnect technologies
US5612570 *13 Abr 199518 Mar 1997Dense-Pac Microsystems, Inc.Chip stack and method of making same
US5620782 *2 Jun 199515 Abr 1997International Business Machines CorporationMethod of fabricating a flex laminate package
US5717556 *25 Abr 199610 Feb 1998Nec CorporationPrinted-wiring board having plural parallel-connected interconnections
US5729894 *14 Jun 199624 Mar 1998Lsi Logic CorporationMethod of assembling ball bump grid array semiconductor packages
US5744827 *26 Nov 199628 Abr 1998Samsung Electronics Co., Ltd.Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements
US5869353 *17 Nov 19979 Feb 1999Dense-Pac Microsystems, Inc.Modular panel stacking process
US5895969 *29 Oct 199720 Abr 1999Hitachi, Ltd. And Hitachi Vlsi Engineering Corp.Thin type semiconductor device, module structure using the device and method of mounting the device on board
US5895970 *1 May 199820 Abr 1999Nec CorporationSemiconductor package having semiconductor element, mounting structure of semiconductor package mounted on circuit board, and method of assembling semiconductor package
US6013948 *1 Abr 199811 Ene 2000Micron Technology, Inc.Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6014316 *10 Jun 199811 Ene 2000Irvine Sensors CorporationIC stack utilizing BGA contacts
US6028352 *10 Jun 199822 Feb 2000Irvine Sensors CorporationIC stack utilizing secondary leadframes
US6028365 *30 Mar 199822 Feb 2000Micron Technology, Inc.Integrated circuit package and method of fabrication
US6034878 *16 Dic 19977 Mar 2000Hitachi, Ltd.Source-clock-synchronized memory system and memory unit
US6040624 *2 Oct 199721 Mar 2000Motorola, Inc.Semiconductor device package and method
US6172874 *6 Abr 19989 Ene 2001Silicon Graphics, Inc.System for stacking of integrated circuit packages
US6178093 *3 Mar 199823 Ene 2001International Business Machines CorporationInformation handling system with circuit assembly having holes filled with filler material
US6186106 *29 Dic 199713 Feb 2001Visteon Global Technologies, Inc.Apparatus for routing electrical signals in an engine
US6187652 *14 Sep 199813 Feb 2001Fujitsu LimitedMethod of fabrication of multiple-layer high density substrate
US6205654 *28 Dic 199827 Mar 2001Staktek Group L.P.Method of manufacturing a surface mount package
US6208521 *19 May 199827 Mar 2001Nitto Denko CorporationFilm carrier and laminate type mounting structure using same
US6218731 *26 Ago 199917 Abr 2001Siliconware Precision Industries Co., Ltd.Tiny ball grid array package
US6222737 *23 Abr 199924 Abr 2001Dense-Pac Microsystems, Inc.Universal package and method of forming the same
US6336262 *30 Abr 19978 Ene 2002International Business Machines CorporationProcess of forming a capacitor with multi-level interconnection technology
US6351029 *19 May 200026 Feb 2002Harlan R. IsaakStackable flex circuit chip package and method of making same
US6360433 *19 Sep 200026 Mar 2002Andrew C. RossUniversal package and method of forming the same
US6360935 *26 Ene 199926 Mar 2002Board Of Regents Of The University Of Texas SystemApparatus and method for assessing solderability
US6504104 *30 Abr 20017 Ene 2003Siemens AktiengesellschaftFlexible wiring for the transformation of a substrate with edge contacts into a ball grid array
US6509639 *30 Abr 200221 Ene 2003Charles W. C. LinThree-dimensional stacked semiconductor package
US6514793 *25 Jun 20014 Feb 2003Dpac Technologies Corp.Stackable flex circuit IC package and method of making same
US6522018 *16 May 200018 Feb 2003Micron Technology, Inc.Ball grid array chip packages having improved testing and stacking characteristics
US6528870 *26 Ene 20014 Mar 2003Kabushiki Kaisha ToshibaSemiconductor device having a plurality of stacked wiring boards
US6532162 *26 May 200111 Mar 2003Intel CorporationReference plane of integrated circuit packages
US6538895 *15 Ene 200225 Mar 2003Infineon Technologies AgTSOP memory chip housing configuration
US6673651 *11 Ene 20016 Ene 2004Oki Electric Industry Co., Ltd.Method of manufacturing semiconductor device including semiconductor elements mounted on base plate
US6677670 *25 Abr 200113 Ene 2004Seiko Epson CorporationSemiconductor device
US6683377 *30 May 200027 Ene 2004Amkor Technology, Inc.Multi-stacked memory package
US6689634 *22 Sep 199910 Feb 2004Texas Instruments IncorporatedModeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability
US6690584 *20 Mar 200110 Feb 2004Fujitsu LimitedInformation-processing device having a crossbar-board connected to back panels on different sides
US6699730 *2 Feb 20012 Mar 2004Tessers, Inc.Stacked microelectronic assembly and method therefor
US6707148 *21 May 200216 Mar 2004National Semiconductor CorporationBumped integrated circuits for optical applications
US6707684 *2 Abr 200116 Mar 2004Advanced Micro Devices, Inc.Method and apparatus for direct connection between two integrated circuits via a connector
US6709893 *11 Dic 200123 Mar 2004Micron Technology, Inc.Interconnections for a semiconductor device and method for forming same
US6841855 *28 Abr 200311 Ene 2005Intel CorporationElectronic package having a flexible substrate with ends connected to one another
US6849949 *23 Mar 20001 Feb 2005Samsung Electronics Co., Ltd.Thin stacked package
US6867496 *29 Sep 200015 Mar 2005Seiko Epson CorporationInterconnect substrate, semiconductor device, methods of fabricating, inspecting, and mounting the semiconductor device, circuit board, and electronic instrument
US6869825 *31 Dic 200222 Mar 2005Intel CorporationFolded BGA package design with shortened communication paths and more electrical routing flexibility
US6998704 *21 Ago 200314 Feb 2006Nec CorporationSemiconductor device and method for manufacturing the same, circuit board, electronic apparatus, and semiconductor device manufacturing apparatus
US20020006032 *11 Ene 200117 Ene 2002Chris KarabatsosLow-profile registered DIMM
US20020030995 *20 Jul 200114 Mar 2002Masao ShojiHeadlight
US20020044423 *1 Oct 200118 Abr 2002Primavera Anthony A.Method and apparatus for mounting and packaging electronic components
US20020048849 *25 Jun 200125 Abr 2002Isaak Harlan R.Stackable flex circuit IC package and method of making same
US20030016710 *18 Jul 200223 Ene 2003Satoshi KomotoSemiconductor laser device including light receiving element for receiving monitoring laser beam
US20030045025 *16 Oct 20026 Mar 2003Coyle Anthony L.Method of fabricating a molded package for micromechanical devices
US20030049886 *6 Sep 200213 Mar 2003Salmon Peter C.Electronic system modules and method of fabrication
US20040000708 *3 Jun 20031 Ene 2004Staktek Group, L.P.Memory expansion and chip scale stacking system and method
US20040004281 *4 Oct 20028 Ene 2004Jin-Chuan BaiSemiconductor package with heat sink
US20040021211 *6 Sep 20025 Feb 2004Tessera, Inc.Microelectronic adaptors, assemblies and methods
US20040031972 *4 Jun 200319 Feb 2004Tessera, Inc.Stacked packages
US20040045159 *10 Sep 200311 Mar 2004Tessera, Inc.Electrical connection with inwardly deformable contacts
US20050018495 *29 Ene 200427 Ene 2005Netlist, Inc.Arrangement of integrated circuits in a memory module
US20050035440 *22 Ago 200217 Feb 2005Tessera, Inc.Stacked chip assembly with stiffening layer
US20050040508 *12 Mar 200424 Feb 2005Jong-Joo LeeArea array type package stack and manufacturing method thereof
Eventos legales
FechaCódigoEventoDescripción
24 Sep 2008ASAssignment
Owner name: ENTORIAN TECHNOLOGIES, LP, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PARTRIDGE, JULIAN;CADY, JAMES W.;WILDER, JAMES;AND OTHERS;REEL/FRAME:021577/0644;SIGNING DATES FROM 20030605 TO 20030606