US20070117404A1 - Modification of electrical properties for semiconductor wafers - Google Patents
Modification of electrical properties for semiconductor wafers Download PDFInfo
- Publication number
- US20070117404A1 US20070117404A1 US11/625,474 US62547407A US2007117404A1 US 20070117404 A1 US20070117404 A1 US 20070117404A1 US 62547407 A US62547407 A US 62547407A US 2007117404 A1 US2007117404 A1 US 2007117404A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor wafer
- wafer
- semiconductor
- topside
- relationship
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 235000012431 wafers Nutrition 0.000 title claims abstract description 232
- 239000004065 semiconductor Substances 0.000 title claims abstract description 192
- 238000012986 modification Methods 0.000 title description 3
- 230000004048 modification Effects 0.000 title description 3
- 239000000463 material Substances 0.000 claims abstract description 97
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 24
- 229910052681 coesite Inorganic materials 0.000 claims description 18
- 229910052906 cristobalite Inorganic materials 0.000 claims description 18
- 229910052682 stishovite Inorganic materials 0.000 claims description 18
- 229910052905 tridymite Inorganic materials 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 24
- 235000012239 silicon dioxide Nutrition 0.000 description 17
- 239000000377 silicon dioxide Substances 0.000 description 16
- 239000000945 filler Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 8
- 239000007789 gas Substances 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000009533 lab test Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Definitions
- the present invention relates to a structure and associated method for manufacturing a plurality of semiconductor wafers.
- microelectronic devices require multiple processing steps. Some of these steps influence electrical characteristics of these devices. Variability in a process often results in unacceptable variability in the devices. Thus, there exists a need to control or eliminate variability of certain critical processing steps.
- the present invention provides an electrical structure, comprising:
- the plurality of semiconductor wafers comprises a first semiconductor wafer and a second semiconductor wafer, wherein the first semiconductor wafer is located directly adjacent to the second semiconductor wafer such that no additional semiconductor wafers of said plurality of semiconductor wafers are located between a topside of the first semiconductor wafer and a backside of a portion of the second semiconductor wafer;
- the material is located directly between the topside of the first semiconductor wafer and the backside of the of the second semiconductor wafer, wherein a relationship exists between a plurality of values for an electrical characteristic and a plurality of materials comprising the material, and wherein the first semiconductor wafer comprises a discrete value from the plurality of values for the electrical characteristic that correlates with the material in said relationship.
- the present invention provides an electrical structure, comprising:
- the plurality of semiconductor wafers comprises a first semiconductor wafer, a second semiconductor wafer, a third semiconductor wafer, and a fourth semiconductor wafer
- the first semiconductor wafer is located directly adjacent to the second semiconductor wafer such that no additional semiconductor wafers of said plurality of semiconductor wafers are located between a topside of the first semiconductor wafer and a backside of a portion of the second semiconductor wafer
- the third semiconductor wafer is located directly adjacent to the fourth semiconductor wafer such that no additional semiconductor wafers of said plurality of semiconductor wafers are located between a topside of the third semiconductor wafer and a backside of a portion of the fourth semiconductor wafer
- first material located directly between the topside of the first semiconductor wafer and the backside of the of the second semiconductor wafer, wherein a relationship exists between a plurality of values for an electrical characteristic and a plurality of materials, wherein the plurality of materials comprises the first material, and wherein the first semiconductor wafer comprises a first discrete value from the plurality of values for the electrical characteristic that correlates with the first material in said relationship;
- the second material is located directly between the topside of the third semiconductor wafer and the backside of the of the fourth semiconductor wafer, wherein the plurality of materials comprises the second material, wherein the third semiconductor wafer comprises a second discrete value from the plurality of values for the electrical characteristic that correlates with the second material in said relationship, and wherein the first discrete value is not a same value as the second discrete value.
- the present invention advantageously provides a structure to control or eliminate variability of certain critical processing steps during a fabrication of microelectronic devices.
- FIG. 1 illustrates a front cross-sectional view of a first semiconductor wafer and a second semiconductor wafer, in accordance with embodiments of the present invention.
- FIGS. 2A and 2B illustrate an alternative to FIG. 1 , in accordance with embodiments of the present invention.
- FIG. 3 illustrates an alternative to FIGS. 1, 2A , and 2 B, in accordance with embodiments of the present invention.
- FIG. 4 is a flowchart depicting an algorithm for the wafer/semiconductor device manufacturing process of FIGS. 1-3 , in accordance with embodiments of the present invention.
- FIG. 5 illustrates a perspective view of a plurality of wafers in a wafer holder for placement in a furnace for a wafer/semiconductor device manufacturing process, in accordance with embodiments of the present invention.
- FIG. 6 illustrates a graph for providing a first relationship between a plurality of values for an electrical characteristic, in accordance with embodiments of the present invention.
- FIG. 7 illustrates a graph for providing a second relationship between a plurality of values for an electrical characteristic, in accordance with embodiments of the present invention.
- FIG. 8 illustrates a graph of laboratory test data showing polysilicon sheet resistance verses various semiconductor wafers, in accordance with embodiments of the present invention.
- FIG. 9 illustrates a graph of laboratory test data showing Gate oxide thickness verses various semiconductor wafers, in accordance with embodiments of the present invention.
- FIG. 1 illustrates a front cross-sectional view of a first semiconductor wafer 4 and a second semiconductor wafer 7 , in accordance with embodiments of the present invention.
- the first semiconductor wafer 4 comprises a topside 8 and a backside 10 .
- the second semiconductor wafer 7 comprises a topside 12 and a backside 15 .
- topside of a semiconductor wafer e.g., topside 8 of the semiconductor wafer 4 and topside 12 of the semiconductor wafer 7
- active electrical components e.g., transistors, resistors, capacitors, etc.
- backside of a semiconductor wafer e.g., backside 10 of the semiconductor wafer 4 and backside 15 of the semiconductor wafer 7
- backside is defined herein including in the claims as a surface of a semiconductor wafer that does not comprise active electrical components (e.g., transistors, resistors, capacitors, etc.).
- wafer/semiconductor device manufacturing process is defined herein as a process to form a layer(s) of a material (i.e., for producing active electrical components, a mask, a junction (for transistors), an insulating layer, etc.) on a top side of a semiconductor wafer (e.g., topside 8 of the semiconductor wafer 4 and topside 12 of the semiconductor wafer 7 ).
- any wafer/semiconductor device manufacturing process known to a person of ordinary skill in the art may be used for the present invention including, inter alia, diffusion, chemical vapor deposition (CVD) processing, etc.
- CVD chemical vapor deposition
- a furnace provides an environment comprising a high temperature (e.g., about 500° C. to about 650° C.) and a controlled gas 99 flow to form the layer(s)of a material.
- Gases 99 used during a CVD process may include, inter alia, SiH4, nitrogen, etc.
- a furnace is used to expose the semiconductor wafer to an oxidizing environment at an elevated temperature (e.g., about 600° C. to about 1300° C.) to form the layer(s)of a material.
- Gases 99 used during a diffusion process may include, inter alia, oxygen, nitrogen, nitrous oxide, hydrogen, etc.
- a layer formation i.e., for producing active electrical components, a mask, a junction (for transistors), an insulating layer, etc.
- a material e.g., layer 21
- a topside e.g., topside 12
- an electrical characteristic(s) e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc
- the semiconductor wafer 4 comprises a film layer 21 of a specified material attached to the backside 10 .
- the film layer 21 comprising the specified material may be selected by providing a relationship between a plurality of values for an electrical characteristic and a plurality of materials (see FIGS. 6-9 ). The relationship may be, inter alia, graphical (as shown in FIGS. 6 and 7 ), tabular, etc.
- the specified material comprised by the film layer 21 may be any material including, inter alia, Si, Si3N4, SiO2, etc.
- the gas 99 occupies an entire space 98 between film layer 21 and the topside 12 of semiconductor wafer 7 .
- the film layer 21 comprising the specified material is applied to the backside 10 of the semiconductor wafer 4 so that during the wafer/semiconductor device manufacturing process a desired value (i.e., a controlled value) of an electrical characteristic (e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc) for active electrical component(s) (e.g., transistors, resistors, capacitors, etc.) on the topside 12 of the semiconductor wafer 7 may be obtained.
- an electrical characteristic e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc
- active electrical component(s) e.g., transistors, resistors, capacitors, etc.
- specific discrete values for electrical characteristics of active electrical components may be selected based upon specific materials selected (i.e., using the a relationship between a plurality of values for an electrical characteristic and a plurality of materials as shown in FIGS. 6 and 7 ).
- the film layer 21 (comprising a specific material) may be applied (i.e., coupled) to the backside 10 of the semiconductor wafer 4 prior to the wafer/semiconductor device manufacturing process as shown in FIG. 1 .
- a film layer may be removed (in a case where a semiconductor wafer comprises a plurality of film layers) to expose a film layer comprising a specific material as shown in FIGS. 2A and 2B .
- FIGS. 2A and 2B illustrate an alternative to FIG. 1 showing the front cross-sectional view of a first semiconductor wafer 4 and a second semiconductor wafer 7 , in accordance with embodiments of the present invention.
- FIG. 2A comprises a first film layer 24 and a second film layer 21 .
- the first film layer 24 and the second film layer 21 each comprise a different material.
- the first film layer 24 may comprise any material including, inter alia, Si, Si3N4, SiO2, etc.
- the second film layer 21 may comprise any material including, inter alia, Si, Si3N4, SiO2, etc.
- the second film layer 21 has been removed so that the first film layer 24 is exposed and adjacent to the topside 12 of the semiconductor wafer 7 .
- a material comprised by the first film layer 24 will produce a desired value (i.e., a controlled value) of an electrical characteristic (e.g., resistance such as polysilicon sheet resistance, capacitance, oxide thickness, threshhold voltage, standby current, etc) for active electrical component(s) (e.g., transistors, resistors, capacitors, etc.) on the topside 12 of the semiconductor wafer 7 during the wafer/semiconductor device manufacturing process.
- the material used to produce the desired value is selected using the a relationship between a plurality of values for an electrical characteristic and a plurality of materials as shown in FIGS. 6 and 7 .
- FIG. 3 illustrates an alternative to FIGS. 1, 2A , and 2 B showing a front cross-sectional view of a first semiconductor wafer 4 , a second semiconductor wafer 7 , and a filler wafer 28 , in accordance with embodiments of the present invention.
- FIG. 3 comprises a filler wafer 28 (instead of a film layer (e.g., film layer 21 in FIG. 1 or film layer 24 in FIG.
- the desired value i.e., a controlled value
- an electrical characteristic e.g., resistance such as polysilicon sheet resistance, capacitance, oxide thickness, threshhold voltage, standby current, etc
- active electrical component(s) e.g., transistors, resistors, capacitors, etc.
- the filler wafer is placed between a backside 10 of the semiconductor wafer 4 and a topside 12 of the semiconductor wafer 7 .
- the filler wafer 28 any material including, inter alia, Si, Si3N4, SiO2, etc.
- the material used to produce the desired value is selected using the a relationship between a plurality of values for an electrical characteristic and a plurality of materials as shown in FIGS. 6 and 7 .
- the gas 99 i.e., as described with reference to FIG. 1
- the gas 99 i.e., as described with reference to FIG. 1
- FIG. 4 is a flowchart depicting an algorithm 37 for the wafer/semiconductor device manufacturing process of FIGS. 1-3 , in accordance with embodiments of the present invention.
- step 39 a plurality of wafers are provided.
- step 40 a decision is made as to whether or not a desired (specific) value for an electrical characteristic(s) (e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc) is required. If a desired value is not required in step 40 then the wafers are subjected to a wafer/semiconductor device manufacturing process.
- an electrical characteristic(s) e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc.
- step 40 a relationship between a plurality of values for an electrical characteristic and a plurality of materials must be developed (as shown in FIGS. 6 and 7 ) in step 42 .
- the relationship may be, inter alia, graphical (as shown in FIGS. 6 and 7 ), tabular, etc.
- step 43 the desired value and associated material to produce the desired value during a wafer/semiconductor device manufacturing process is selected using the relationship developed in step 42 .
- step 44 a method of adding the associated material to produce the desired value of an electrical characteristic(s) (e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc) will be determined.
- an electrical characteristic(s) e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc
- step 50 is executed such that the film layer 21 (see FIG. 1 ) is applied (i.e., coupled) to the wafer 4 (such that the film layer 21 is located between the topside 12 of the semiconductor wafer 7 and a backside 10 the semiconductor wafer 4 ).
- step 52 the wafers 4 and 7 are placed in a furnace for a wafer/semiconductor device manufacturing process thereby producing a desired value (i.e., a controlled value) of an electrical characteristic (e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc) for active electrical component(s) (e.g., transistors, resistors, capacitors, etc.) on the topside 12 of the semiconductor wafer 7 .
- an electrical characteristic e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc
- active electrical component(s) e.g., transistors, resistors, capacitors, etc.
- step 46 is executed such that the film layer 21 (see FIG. 2 ) is removed from the wafer 4 thereby exposing the film layer 21 (coupled to the semiconductor wafer 4 ) to the topside 12 of the semiconductor wafer 7 .
- step 56 the wafers 4 and 7 are placed in a furnace for wafer/semiconductor device manufacturing process thereby producing a desired value (i.e., a controlled value) of an electrical characteristic (e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc) for active electrical component(s) (e.g., transistors, resistors, capacitors, etc.) on the topside 12 of the semiconductor wafer 7 .
- an electrical characteristic e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc
- active electrical component(s) e.g., transistors, resistors, capacitors, etc.
- step 48 is executed such that the filler wafer 28 (see FIG. 3 ) is placed (i.e., without attaching to wafer 4 or 7 ) between the backside 10 of the wafer 4 and the topside 12 of the wafer 7 .
- step 54 the wafers 4 and 7 and the filler wafer 28 are placed in a furnace for wafer/semiconductor device manufacturing process in step 54 thereby producing a desired value (i.e., a controlled value) of an electrical characteristic (e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc) for active electrical component(s) (e.g., transistors, resistors, capacitors, etc.) on the topside 12 of the semiconductor wafer 7 .
- an electrical characteristic e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc
- active electrical component(s) e.g., transistors, resistors, capacitors, etc.
- FIG. 5 illustrates a perspective view of a plurality of wafers 63 in a wafer holder 64 for placement in a furnace 62 for wafer/semiconductor device manufacturing process, in accordance with embodiments of the present invention.
- the plurality of wafers 63 may include a film layer 65 similar to the film layer 21 applied to the wafer 4 and the wafer 7 of FIG. 1 .
- the film layer 65 could be replaced by a film layer analogous to the film layer 24 exposed to the wafer 7 of FIG. 2 , the filler wafer 28 between the wafer 4 and the wafer 7 of FIG. 3 , or any combination thereof.
- the wafer holder 64 may comprise any wafer holder material known to a person of ordinary skill in the art including, inter alia, quartz, silicon carbide, etc.
- the furnace 62 may be any wafer processing furnace known to a person of ordinary skill in the art including, inter alia, Polysilicon LPCVD furnace, a gate oxidation furnace, etc.
- FIG. 6 illustrates a graph for providing a first relationship (graphical) between a plurality of values for an electrical characteristic (i.e., polysilicon resistance) and a plurality of materials so that a specific value for an electrical characteristic may selected based on a material selected, in accordance with embodiments of the present invention.
- the Y-axis represents values for polysilicon resistance in arbitrary units.
- the X-axis represents the plurality of materials (i.e., Si, Si3N4, and SiO2).
- the values for polysilicon resistance with respect to a material are represented by data points 67 , 68 , and 69 .
- the polysilicon resistance values increase as the materials change from Si to Si3N4 to SiO2. Additionally, any combination of materials (i.e., Si, Si3N4, and SiO2) may be used to provide values for polysilicon resistance that fall between the data points 67 , 68 , and 69 .
- FIG. 7 illustrates a graph for providing a second relationship (graphical) between a plurality of values for an electrical characteristic (i.e., gate oxide thickness) and a plurality of materials so that specific value for an electrical characteristic may selected based on a material selected, in accordance with embodiments of the present invention.
- the Y-axis represents values for gate oxide thickness in arbitrary units.
- the X-axis represents the plurality of materials (i.e., Si, Si3N4, and SiO2).
- the values for gate oxide thickness with respect to a material i.e., Si, Si3N4, and SiO2 are represented by data points 71 , 72 , and 73 .
- the gate oxide thickness increases as the materials change from Si to Si3N4 to SiO2. Additionally, any combination of materials (i.e., Si, Si3N4, and SiO2) may be used to provide values for gate oxide thickness that fall between the data points 71 , 72 , and 73 .
- FIG. 8 illustrates a graph of laboratory test data showing polysilicon sheet resistance verses various semiconductor wafers W 1 -W 23 with various materials placed above the semiconductor wafers W 1 -W 23 during a wafer/semiconductor device manufacturing process, in accordance with embodiments of the present invention.
- the semiconductor wafers W 1 -W 23 were placed in a polysilicon LPCVD furnace for 20 minutes at a temperature of 620° C. and a pressure of 150 milliTorr.
- the semiconductor wafers W 1 -W 23 each comprise a same material (e.g., polysilicon, etc).
- the X-axis represents the semiconductor wafers W 1 -W 23 .
- the Y-axis represents resistance in ohms.
- the values for resistance for semiconductor wafers W 1 -W 23 with various materials placed above the semiconductor wafers W 1 -W 23 are represented by the data points 101 , 102 , . . . , 115 . . . , 123 .
- Data points 102 , 103 , . . . 114 , 116 . . . 123 represent values of resistance (about 1380 ohms ⁇ 30) for semiconductor wafers comprising a layer of SiO2 above them.
- Data point 101 represents a value of resistance (about 1225 ohms/ ) for a semiconductor wafer comprising a layer of Si3N4 above.
- Data point 115 represents a value of resistance (about 1135 ohms/ ) for a semiconductor wafer comprising a layer of Si above.
- the polysilicon sheet resistance values increase as the materials change from Si to Si3N4 to SiO2 and that based on a material placed above a semiconductor wafer during a wafer/semiconductor device manufacturing process a value of an electrical characteristic (e.g., polysilicon sheet resistance) may be changed.
- an electrical characteristic e.g., polysilicon sheet resistance
- FIG. 9 illustrates a graph of laboratory test data showing Gate oxide thickness verses various semiconductor wafers V 1 -V 15 with various materials placed above the semiconductor wafers V 1 -V 15 during a wafer/semiconductor device manufacturing process, in accordance with embodiments of the present invention.
- the semiconductor wafers V 1 -V 15 were placed in a gate oxidation furnace for 60 minutes at a temperature of 800° C. degrees and a pressure of 760 Torr.
- the semiconductor wafers V 1 -V 15 each comprise a same material (e.g., silicon oxynitride).
- the X-axis represents the semiconductor wafers V 1 -V 15 .
- the Y-axis represents gate oxide thickness in angstroms.
- the values for gate oxide thickness for semiconductor wafers V 1 -V 15 with various materials placed above the semiconductor wafers V 1 -V 15 are represented by the data points 201 , 202 , . . . 215 .
- Data points 202 . . . 215 represent values of gate oxide thickness (about 22.8 angstroms ⁇ 0.3) for semiconductor wafers comprising a layer of Si above them.
- Data point 201 represents a value of gate oxide thickness (about 24 angstroms) for a semiconductor wafer comprising a layer of SiO2 above. As illustrated by the data points 201 , 202 , . . .
- gate oxide thickness increases as the materials change from Si to SiO2 and that based on a material placed above a semiconductor wafer during a wafer/semiconductor device manufacturing process a value of an electrical characteristic (e.g., gate oxide thickness ) may be changed.
- an electrical characteristic e.g., gate oxide thickness
Abstract
Description
- This application is a divisional of Ser. No. 10/710,700, filed Jul. 29, 2004.
- 1. Technical Field
- The present invention relates to a structure and associated method for manufacturing a plurality of semiconductor wafers.
- 2. Related Art
- The fabrication of microelectronic devices requires multiple processing steps. Some of these steps influence electrical characteristics of these devices. Variability in a process often results in unacceptable variability in the devices. Thus, there exists a need to control or eliminate variability of certain critical processing steps.
- The present invention provides an electrical structure, comprising:
- a plurality of semiconductor wafers, wherein the plurality of semiconductor wafers comprises a first semiconductor wafer and a second semiconductor wafer, wherein the first semiconductor wafer is located directly adjacent to the second semiconductor wafer such that no additional semiconductor wafers of said plurality of semiconductor wafers are located between a topside of the first semiconductor wafer and a backside of a portion of the second semiconductor wafer; and
- a material, wherein the material is located directly between the topside of the first semiconductor wafer and the backside of the of the second semiconductor wafer, wherein a relationship exists between a plurality of values for an electrical characteristic and a plurality of materials comprising the material, and wherein the first semiconductor wafer comprises a discrete value from the plurality of values for the electrical characteristic that correlates with the material in said relationship.
- The present invention provides an electrical structure, comprising:
- a plurality of semiconductor wafers, wherein the plurality of semiconductor wafers comprises a first semiconductor wafer, a second semiconductor wafer, a third semiconductor wafer, and a fourth semiconductor wafer, wherein the first semiconductor wafer is located directly adjacent to the second semiconductor wafer such that no additional semiconductor wafers of said plurality of semiconductor wafers are located between a topside of the first semiconductor wafer and a backside of a portion of the second semiconductor wafer, wherein the third semiconductor wafer is located directly adjacent to the fourth semiconductor wafer such that no additional semiconductor wafers of said plurality of semiconductor wafers are located between a topside of the third semiconductor wafer and a backside of a portion of the fourth semiconductor wafer;
- a first material, wherein the first material is located directly between the topside of the first semiconductor wafer and the backside of the of the second semiconductor wafer, wherein a relationship exists between a plurality of values for an electrical characteristic and a plurality of materials, wherein the plurality of materials comprises the first material, and wherein the first semiconductor wafer comprises a first discrete value from the plurality of values for the electrical characteristic that correlates with the first material in said relationship; and
- a second material, wherein the second material is located directly between the topside of the third semiconductor wafer and the backside of the of the fourth semiconductor wafer, wherein the plurality of materials comprises the second material, wherein the third semiconductor wafer comprises a second discrete value from the plurality of values for the electrical characteristic that correlates with the second material in said relationship, and wherein the first discrete value is not a same value as the second discrete value.
- The present invention advantageously provides a structure to control or eliminate variability of certain critical processing steps during a fabrication of microelectronic devices.
-
FIG. 1 illustrates a front cross-sectional view of a first semiconductor wafer and a second semiconductor wafer, in accordance with embodiments of the present invention. -
FIGS. 2A and 2B illustrate an alternative toFIG. 1 , in accordance with embodiments of the present invention. -
FIG. 3 illustrates an alternative toFIGS. 1, 2A , and 2B, in accordance with embodiments of the present invention. -
FIG. 4 is a flowchart depicting an algorithm for the wafer/semiconductor device manufacturing process ofFIGS. 1-3 , in accordance with embodiments of the present invention. -
FIG. 5 illustrates a perspective view of a plurality of wafers in a wafer holder for placement in a furnace for a wafer/semiconductor device manufacturing process, in accordance with embodiments of the present invention. -
FIG. 6 illustrates a graph for providing a first relationship between a plurality of values for an electrical characteristic, in accordance with embodiments of the present invention. -
FIG. 7 illustrates a graph for providing a second relationship between a plurality of values for an electrical characteristic, in accordance with embodiments of the present invention. -
FIG. 8 illustrates a graph of laboratory test data showing polysilicon sheet resistance verses various semiconductor wafers, in accordance with embodiments of the present invention. -
FIG. 9 illustrates a graph of laboratory test data showing Gate oxide thickness verses various semiconductor wafers, in accordance with embodiments of the present invention. -
FIG. 1 illustrates a front cross-sectional view of afirst semiconductor wafer 4 and asecond semiconductor wafer 7, in accordance with embodiments of the present invention. Thefirst semiconductor wafer 4 comprises atopside 8 and abackside 10. Thesecond semiconductor wafer 7 comprises atopside 12 and abackside 15. The term “topside” of a semiconductor wafer (e.g.,topside 8 of thesemiconductor wafer 4 andtopside 12 of the semiconductor wafer 7) is defined herein including in the claims as a surface of a semiconductor wafer that comprises or will comprise (i.e., through a wafer/semiconductor device manufacturing process) active electrical components (e.g., transistors, resistors, capacitors, etc.) and/or conductive wiring between active electrical components. The term “backside” of a semiconductor wafer (e.g.,backside 10 of thesemiconductor wafer 4 andbackside 15 of the semiconductor wafer 7) is defined herein including in the claims as a surface of a semiconductor wafer that does not comprise active electrical components (e.g., transistors, resistors, capacitors, etc.). The term “wafer/semiconductor device manufacturing process” is defined herein as a process to form a layer(s) of a material (i.e., for producing active electrical components, a mask, a junction (for transistors), an insulating layer, etc.) on a top side of a semiconductor wafer (e.g.,topside 8 of thesemiconductor wafer 4 andtopside 12 of the semiconductor wafer 7). Any wafer/semiconductor device manufacturing process known to a person of ordinary skill in the art may be used for the present invention including, inter alia, diffusion, chemical vapor deposition (CVD) processing, etc. During a CVD process a furnace provides an environment comprising a high temperature (e.g., about 500° C. to about 650° C.) and a controlledgas 99 flow to form the layer(s)of a material.Gases 99 used during a CVD process may include, inter alia, SiH4, nitrogen, etc. During diffusion process a furnace is used to expose the semiconductor wafer to an oxidizing environment at an elevated temperature (e.g., about 600° C. to about 1300° C.) to form the layer(s)of a material.Gases 99 used during a diffusion process may include, inter alia, oxygen, nitrogen, nitrous oxide, hydrogen, etc. During a wafer/semiconductor device manufacturing process, a layer formation (i.e., for producing active electrical components, a mask, a junction (for transistors), an insulating layer, etc.) on a first wafer (e.g., wafer 7) is modulated by a material (e.g., layer 21) that is adjacent to a topside (e.g., topside 12) of the first wafer (e.g., wafer 7) thereby producing values of an electrical characteristic(s) (e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc) that are dependent upon the material (e.g., layer 21). For example, thesemiconductor wafer 4 comprises afilm layer 21 of a specified material attached to thebackside 10. Thefilm layer 21 comprising the specified material may be selected by providing a relationship between a plurality of values for an electrical characteristic and a plurality of materials (seeFIGS. 6-9 ). The relationship may be, inter alia, graphical (as shown inFIGS. 6 and 7 ), tabular, etc. The specified material comprised by thefilm layer 21 may be any material including, inter alia, Si, Si3N4, SiO2, etc. Thegas 99 occupies an entire space 98 betweenfilm layer 21 and thetopside 12 ofsemiconductor wafer 7. Thefilm layer 21 comprising the specified material is applied to thebackside 10 of the semiconductor wafer 4 so that during the wafer/semiconductor device manufacturing process a desired value (i.e., a controlled value) of an electrical characteristic (e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc) for active electrical component(s) (e.g., transistors, resistors, capacitors, etc.) on thetopside 12 of thesemiconductor wafer 7 may be obtained. Therefore specific discrete values for electrical characteristics of active electrical components (e.g., resistance (e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc) may be selected based upon specific materials selected (i.e., using the a relationship between a plurality of values for an electrical characteristic and a plurality of materials as shown inFIGS. 6 and 7 ). Based on a desired value for electrical characteristics of active electrical components, the film layer 21 (comprising a specific material) may be applied (i.e., coupled) to thebackside 10 of thesemiconductor wafer 4 prior to the wafer/semiconductor device manufacturing process as shown inFIG. 1 . Alternatively a film layer may be removed (in a case where a semiconductor wafer comprises a plurality of film layers) to expose a film layer comprising a specific material as shown inFIGS. 2A and 2B . -
FIGS. 2A and 2B illustrate an alternative toFIG. 1 showing the front cross-sectional view of afirst semiconductor wafer 4 and asecond semiconductor wafer 7, in accordance with embodiments of the present invention. In contrast toFIG. 1 ,FIG. 2A comprises afirst film layer 24 and asecond film layer 21. Thefirst film layer 24 and thesecond film layer 21 each comprise a different material. Thefirst film layer 24 may comprise any material including, inter alia, Si, Si3N4, SiO2, etc. Thesecond film layer 21 may comprise any material including, inter alia, Si, Si3N4, SiO2, etc. InFIG. 2B thesecond film layer 21 has been removed so that thefirst film layer 24 is exposed and adjacent to thetopside 12 of thesemiconductor wafer 7. A material comprised by thefirst film layer 24 will produce a desired value (i.e., a controlled value) of an electrical characteristic (e.g., resistance such as polysilicon sheet resistance, capacitance, oxide thickness, threshhold voltage, standby current, etc) for active electrical component(s) (e.g., transistors, resistors, capacitors, etc.) on thetopside 12 of thesemiconductor wafer 7 during the wafer/semiconductor device manufacturing process. The material used to produce the desired value is selected using the a relationship between a plurality of values for an electrical characteristic and a plurality of materials as shown inFIGS. 6 and 7 . -
FIG. 3 illustrates an alternative toFIGS. 1, 2A , and 2B showing a front cross-sectional view of afirst semiconductor wafer 4, asecond semiconductor wafer 7, and afiller wafer 28, in accordance with embodiments of the present invention. In contrast toFIGS. 1, 2A , and 2B,FIG. 3 comprises a filler wafer 28 (instead of a film layer (e.g.,film layer 21 inFIG. 1 orfilm layer 24 inFIG. 2B ) for producing the desired value (i.e., a controlled value) of an electrical characteristic (e.g., resistance such as polysilicon sheet resistance, capacitance, oxide thickness, threshhold voltage, standby current, etc) for active electrical component(s) (e.g., transistors, resistors, capacitors, etc.) on thetopside 12 of thesemiconductor wafer 7 during the wafer/semiconductor device manufacturing process. The filler wafer is placed between abackside 10 of thesemiconductor wafer 4 and atopside 12 of thesemiconductor wafer 7. Thefiller wafer 28 any material including, inter alia, Si, Si3N4, SiO2, etc. The material used to produce the desired value is selected using the a relationship between a plurality of values for an electrical characteristic and a plurality of materials as shown inFIGS. 6 and 7 . InFIG.3 , the gas 99 (i.e., as described with reference toFIG. 1 ) occupies anentire space 98 a between afirst surface 77 offiller wafer 28 and theback side 10 ofsemiconductor wafer 7. Additionally, the gas 99 (i.e., as described with reference toFIG. 1 ) occupies an entire space 98 b between asecond surface 78 offiller wafer 28 and thetopside 10 ofsemiconductor wafer 7. -
FIG. 4 is a flowchart depicting analgorithm 37 for the wafer/semiconductor device manufacturing process ofFIGS. 1-3 , in accordance with embodiments of the present invention. In step 39 a plurality of wafers are provided. In step 40 a decision is made as to whether or not a desired (specific) value for an electrical characteristic(s) (e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc) is required. If a desired value is not required instep 40 then the wafers are subjected to a wafer/semiconductor device manufacturing process. If a desired value is required instep 40 then a relationship between a plurality of values for an electrical characteristic and a plurality of materials must be developed (as shown inFIGS. 6 and 7 ) instep 42. The relationship may be, inter alia, graphical (as shown inFIGS. 6 and 7 ), tabular, etc. Instep 43 the desired value and associated material to produce the desired value during a wafer/semiconductor device manufacturing process is selected using the relationship developed instep 42. In step 44 a method of adding the associated material to produce the desired value of an electrical characteristic(s) (e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc) will be determined. - If the method of
FIG. 1 is selected instep 44 then step 50 is executed such that the film layer 21 (seeFIG. 1 ) is applied (i.e., coupled) to the wafer 4 (such that thefilm layer 21 is located between the topside 12 of thesemiconductor wafer 7 and abackside 10 the semiconductor wafer 4). Instep 52, thewafers topside 12 of thesemiconductor wafer 7. - If the method of
FIG. 2 is selected instep 44 then step 46 is executed such that the film layer 21 (seeFIG. 2 ) is removed from thewafer 4 thereby exposing the film layer 21 (coupled to the semiconductor wafer 4) to thetopside 12 of thesemiconductor wafer 7. Instep 56 thewafers topside 12 of thesemiconductor wafer 7. - If the method of
FIG. 3 is selected instep 44 then step 48 is executed such that the filler wafer 28 (seeFIG. 3 ) is placed (i.e., without attaching towafer 4 or 7) between thebackside 10 of thewafer 4 and thetopside 12 of thewafer 7. Instep 54, thewafers filler wafer 28 are placed in a furnace for wafer/semiconductor device manufacturing process instep 54 thereby producing a desired value (i.e., a controlled value) of an electrical characteristic (e.g., resistance such as polysilicon sheet resistance, capacitance, gate oxide thickness, threshhold voltage, standby current, etc) for active electrical component(s) (e.g., transistors, resistors, capacitors, etc.) on thetopside 12 of thesemiconductor wafer 7. -
FIG. 5 illustrates a perspective view of a plurality ofwafers 63 in awafer holder 64 for placement in afurnace 62 for wafer/semiconductor device manufacturing process, in accordance with embodiments of the present invention. The plurality ofwafers 63 may include afilm layer 65 similar to thefilm layer 21 applied to thewafer 4 and thewafer 7 ofFIG. 1 . Alternatively, thefilm layer 65 could be replaced by a film layer analogous to thefilm layer 24 exposed to thewafer 7 ofFIG. 2 , thefiller wafer 28 between thewafer 4 and thewafer 7 ofFIG. 3 , or any combination thereof. Thewafer holder 64 may comprise any wafer holder material known to a person of ordinary skill in the art including, inter alia, quartz, silicon carbide, etc. Thefurnace 62 may be any wafer processing furnace known to a person of ordinary skill in the art including, inter alia, Polysilicon LPCVD furnace, a gate oxidation furnace, etc. -
FIG. 6 illustrates a graph for providing a first relationship (graphical) between a plurality of values for an electrical characteristic (i.e., polysilicon resistance) and a plurality of materials so that a specific value for an electrical characteristic may selected based on a material selected, in accordance with embodiments of the present invention. The Y-axis represents values for polysilicon resistance in arbitrary units. The X-axis represents the plurality of materials (i.e., Si, Si3N4, and SiO2). The values for polysilicon resistance with respect to a material (i.e., Si, Si3N4, and SiO2) are represented bydata points -
FIG. 7 illustrates a graph for providing a second relationship (graphical) between a plurality of values for an electrical characteristic (i.e., gate oxide thickness) and a plurality of materials so that specific value for an electrical characteristic may selected based on a material selected, in accordance with embodiments of the present invention. The Y-axis represents values for gate oxide thickness in arbitrary units. The X-axis represents the plurality of materials (i.e., Si, Si3N4, and SiO2). The values for gate oxide thickness with respect to a material (i.e., Si, Si3N4, and SiO2) are represented bydata points -
FIG. 8 illustrates a graph of laboratory test data showing polysilicon sheet resistance verses various semiconductor wafers W1-W23 with various materials placed above the semiconductor wafers W1-W23 during a wafer/semiconductor device manufacturing process, in accordance with embodiments of the present invention. The semiconductor wafers W1-W23 were placed in a polysilicon LPCVD furnace for 20 minutes at a temperature of 620° C. and a pressure of 150 milliTorr. The semiconductor wafers W1-W23 each comprise a same material (e.g., polysilicon, etc). The X-axis represents the semiconductor wafers W1-W23. The Y-axis represents resistance in ohms. The values for resistance for semiconductor wafers W1-W23 with various materials placed above the semiconductor wafers W1-W23 are represented by the data points 101, 102, . . . , 115 . . . , 123. Data points 102, 103, . . . 114, 116 . . . 123 represent values of resistance (about 1380 ohms ±30) for semiconductor wafers comprising a layer of SiO2 above them.Data point 101 represents a value of resistance (about 1225 ohms/) for a semiconductor wafer comprising a layer of Si3N4 above.Data point 115 represents a value of resistance (about 1135 ohms/) for a semiconductor wafer comprising a layer of Si above. As illustrated by the data points 101, 102, . . . , 115 . . . , 123 it may be determined that the polysilicon sheet resistance values increase as the materials change from Si to Si3N4 to SiO2 and that based on a material placed above a semiconductor wafer during a wafer/semiconductor device manufacturing process a value of an electrical characteristic (e.g., polysilicon sheet resistance) may be changed. -
FIG. 9 illustrates a graph of laboratory test data showing Gate oxide thickness verses various semiconductor wafers V1-V15 with various materials placed above the semiconductor wafers V1-V15 during a wafer/semiconductor device manufacturing process, in accordance with embodiments of the present invention. The semiconductor wafers V1-V15 were placed in a gate oxidation furnace for 60 minutes at a temperature of 800° C. degrees and a pressure of 760 Torr. The semiconductor wafers V1-V15 each comprise a same material (e.g., silicon oxynitride). The X-axis represents the semiconductor wafers V1-V15. The Y-axis represents gate oxide thickness in angstroms. The values for gate oxide thickness for semiconductor wafers V1-V15 with various materials placed above the semiconductor wafers V1-V15 are represented by the data points 201, 202, . . . 215. Data points 202 . . . 215 represent values of gate oxide thickness (about 22.8 angstroms ±0.3) for semiconductor wafers comprising a layer of Si above them.Data point 201 represents a value of gate oxide thickness (about 24 angstroms) for a semiconductor wafer comprising a layer of SiO2 above. As illustrated by the data points 201, 202, . . . 215, it may be determined that gate oxide thickness increases as the materials change from Si to SiO2 and that based on a material placed above a semiconductor wafer during a wafer/semiconductor device manufacturing process a value of an electrical characteristic (e.g., gate oxide thickness ) may be changed. - While embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/625,474 US20070117404A1 (en) | 2004-07-29 | 2007-01-22 | Modification of electrical properties for semiconductor wafers |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/710,700 US7205216B2 (en) | 2004-07-29 | 2004-07-29 | Modification of electrical properties for semiconductor wafers |
US11/625,474 US20070117404A1 (en) | 2004-07-29 | 2007-01-22 | Modification of electrical properties for semiconductor wafers |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/710,700 Division US7205216B2 (en) | 2004-07-29 | 2004-07-29 | Modification of electrical properties for semiconductor wafers |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070117404A1 true US20070117404A1 (en) | 2007-05-24 |
Family
ID=35732862
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/710,700 Expired - Fee Related US7205216B2 (en) | 2004-07-29 | 2004-07-29 | Modification of electrical properties for semiconductor wafers |
US11/625,474 Abandoned US20070117404A1 (en) | 2004-07-29 | 2007-01-22 | Modification of electrical properties for semiconductor wafers |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/710,700 Expired - Fee Related US7205216B2 (en) | 2004-07-29 | 2004-07-29 | Modification of electrical properties for semiconductor wafers |
Country Status (1)
Country | Link |
---|---|
US (2) | US7205216B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140070378A1 (en) * | 2012-09-07 | 2014-03-13 | Kabushiki Kaisha Toshiba | Method of fabricating a semiconductor device, semiconductor wafer, and apparatus for fabricating a semiconductor device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL2008632C2 (en) * | 2012-04-12 | 2013-10-16 | Consultatie Implementatie Tech Beheer B V | MOBILE DEVICE AND METHOD FOR ANALYZING BREATH SAMPLES. |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3769104A (en) * | 1970-03-27 | 1973-10-30 | Hitachi Ltd | Method of preventing autodoping during the epitaxial growth of compound semiconductors from the vapor phase |
US4603059A (en) * | 1984-01-23 | 1986-07-29 | Oki Electric Industry Co., Ltd. | Method of manufacturing MIS capacitors for semiconductor IC devices |
US4687682A (en) * | 1986-05-02 | 1987-08-18 | American Telephone And Telegraph Company, At&T Technologies, Inc. | Back sealing of silicon wafers |
US4925809A (en) * | 1987-05-23 | 1990-05-15 | Osaka Titanium Co., Ltd. | Semiconductor wafer and epitaxial growth on the semiconductor wafer with autodoping control and manufacturing method therefor |
US5121705A (en) * | 1991-04-05 | 1992-06-16 | Mbk Microtek Inc. | Loading lock for chemical vapor deposition apparatus |
US5296385A (en) * | 1991-12-31 | 1994-03-22 | Texas Instruments Incorporated | Conditioning of semiconductor wafers for uniform and repeatable rapid thermal processing |
US5571333A (en) * | 1994-06-02 | 1996-11-05 | Shin-Etsu Handotai Co. Ltd. | Heat treatment furnace with an exhaust baffle |
US5972784A (en) * | 1997-04-24 | 1999-10-26 | Georgia Tech Research Corporation | Arrangement, dopant source, and method for making solar cells |
US6448180B2 (en) * | 2000-03-09 | 2002-09-10 | Advanced Micro Devices, Inc. | Deposition of in-situ doped semiconductor film and undoped semiconductor film in the same reaction chamber |
US6454854B1 (en) * | 1998-10-29 | 2002-09-24 | Shin-Etsu Handotai Co., Ltd. | Semiconductor wafer and production method therefor |
US6670283B2 (en) * | 2001-11-20 | 2003-12-30 | International Business Machines Corporation | Backside protection films |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5298452A (en) * | 1986-09-12 | 1994-03-29 | International Business Machines Corporation | Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers |
US6180497B1 (en) * | 1998-07-23 | 2001-01-30 | Canon Kabushiki Kaisha | Method for producing semiconductor base members |
JP2003077845A (en) * | 2001-09-05 | 2003-03-14 | Hitachi Kokusai Electric Inc | Manufacturing method of semiconductor device and substrate treatment apparatus |
-
2004
- 2004-07-29 US US10/710,700 patent/US7205216B2/en not_active Expired - Fee Related
-
2007
- 2007-01-22 US US11/625,474 patent/US20070117404A1/en not_active Abandoned
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3769104A (en) * | 1970-03-27 | 1973-10-30 | Hitachi Ltd | Method of preventing autodoping during the epitaxial growth of compound semiconductors from the vapor phase |
US4603059A (en) * | 1984-01-23 | 1986-07-29 | Oki Electric Industry Co., Ltd. | Method of manufacturing MIS capacitors for semiconductor IC devices |
US4687682A (en) * | 1986-05-02 | 1987-08-18 | American Telephone And Telegraph Company, At&T Technologies, Inc. | Back sealing of silicon wafers |
US4925809A (en) * | 1987-05-23 | 1990-05-15 | Osaka Titanium Co., Ltd. | Semiconductor wafer and epitaxial growth on the semiconductor wafer with autodoping control and manufacturing method therefor |
US5121705A (en) * | 1991-04-05 | 1992-06-16 | Mbk Microtek Inc. | Loading lock for chemical vapor deposition apparatus |
US5296385A (en) * | 1991-12-31 | 1994-03-22 | Texas Instruments Incorporated | Conditioning of semiconductor wafers for uniform and repeatable rapid thermal processing |
US5571333A (en) * | 1994-06-02 | 1996-11-05 | Shin-Etsu Handotai Co. Ltd. | Heat treatment furnace with an exhaust baffle |
US5972784A (en) * | 1997-04-24 | 1999-10-26 | Georgia Tech Research Corporation | Arrangement, dopant source, and method for making solar cells |
US6454854B1 (en) * | 1998-10-29 | 2002-09-24 | Shin-Etsu Handotai Co., Ltd. | Semiconductor wafer and production method therefor |
US6448180B2 (en) * | 2000-03-09 | 2002-09-10 | Advanced Micro Devices, Inc. | Deposition of in-situ doped semiconductor film and undoped semiconductor film in the same reaction chamber |
US6670283B2 (en) * | 2001-11-20 | 2003-12-30 | International Business Machines Corporation | Backside protection films |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140070378A1 (en) * | 2012-09-07 | 2014-03-13 | Kabushiki Kaisha Toshiba | Method of fabricating a semiconductor device, semiconductor wafer, and apparatus for fabricating a semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US7205216B2 (en) | 2007-04-17 |
US20060024916A1 (en) | 2006-02-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5861651A (en) | Field effect devices and capacitors with improved thin film dielectrics and method for making same | |
KR100258493B1 (en) | Semiconductor device having pesistor element and method of fabricating same | |
US20020185711A1 (en) | Graded composite layer and method for fabrication thereof | |
US20070117404A1 (en) | Modification of electrical properties for semiconductor wafers | |
US5327224A (en) | Semiconductor device with hydrogen ion intercepting layer | |
US6657284B1 (en) | Graded dielectric layer and method for fabrication thereof | |
US20020109230A1 (en) | Highly linear integrated resistive contact | |
US8084314B2 (en) | Semiconductor device and manufacturing method thereof | |
JPH10209299A (en) | Semiconductor device and its manufacture | |
US20020084886A1 (en) | Method for fabricating a thin film resistor | |
JPS60193333A (en) | Manufacture of semiconductor device | |
US7642892B1 (en) | Negative voltage coefficient resistor and method of manufacture | |
KR100846391B1 (en) | Method for fabricating WSix gate in semiconductor device | |
KR100523658B1 (en) | Method for manufacturing copper diffusion barrier | |
US7425736B2 (en) | Silicon layer with high resistance and fabricating method thereof | |
JP4099462B2 (en) | Method for forming semiconductor device | |
US7241703B2 (en) | Film forming method for semiconductor device | |
JPH05102069A (en) | Manufacture of semiconductor element | |
JPH0314232A (en) | Manufacture of semiconductor device | |
US6949448B2 (en) | Local oxidation of silicon (LOCOS) method employing graded oxidation mask | |
RU1609399C (en) | Method of manufacturing mos integral circuit with polysilicon resistors | |
US6953749B2 (en) | Methods of forming refractory metal silicide components and methods of restricting silicon surface migration of a silicon structure | |
JPH0370170A (en) | Method of making semiconductor element | |
Deaton | Rapid thermal oxidation of silicon | |
JPH01296656A (en) | Polysi resistor and semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |