US20070119705A1

US20070119705A1 - Back-biased face target sputtering based memory data sensing technique

Info

Publication number: US20070119705A1
Application number: US11/522,080
Authority: US
Inventors: Makoto Nagashima
Original assignee: Individual
Current assignee: 4D S Pty Ltd
Priority date: 2003-09-15
Filing date: 2006-09-14
Publication date: 2007-05-31
Also published as: US20050183945A1; KR20060089207A; EP1670968A1; JP2008542525A; KR101127259B1; US6962648B2; EP1670968A4; US20050258027A1; WO2005028700A1; US20050056534A1; US20070007124A1

Abstract

Systems and methods are disclosed to form an exemplary memory structure by flowing argon gas and oxygen gas in a deposition chamber; providing a low oxygen flow rate approximately between 0 and ten percent (10%) of an argon flow rate, a pressure approximately between 2×10⁻⁵Torr and 1×10⁻³Torr, and a deposition temperature approximately between 340° C. and 450° C.; and the composition of sputtering target is PCMO (Pr_1-xCa_xMnO₃, where X is between 0.1 and 0.9). The process forms a PCMO (Pr_1-xCa_xMnO₃, X=0.1-0.9) material film on the wafer and a plurality of current sensors coupled to PCMO memory cells.

Description

BACKGROUND

This application is a continuation in part (CIP) application of Ser. No. 10/662,862, the content of which is incorporated by reference.
The present invention relates to systems and methods for fabricating semiconductor devices at low temperature.
Electronic systems have become a ubiquitous fixture in modern society. These electronic systems range from simple, hand-held calculators to more complex systems including computers, personal digital assistants (PDAs), embedded controllers and complex satellite imaging and communications systems. As noted in U.S. Pat. No. 6,862,211, many electronic systems include a microprocessor that performs one or more functions based on data provided to the microprocessor. This data is typically stored in a memory device of the electronic system such as a common dynamic random access memory (DRAM) device. A DRAM typically includes an array of memory cells that store data as binary values, e.g., 1's and 0's. In a conventional DRAM, the data is stored by controlling the charge on capacitors in each cell of the DRAM. Data in the array is “randomly accessible” since a processor can retrieve data from any location in memory by providing the appropriate address to the memory device. One problem with conventional DRAM is that the device is “volatile.” This means that when power is turned off to the system using the DRAM, the data in the memory device is lost.
In a parallel trend, various semiconductor fabrication steps need to be done at low temperature. For instance, when applying a ferroelectric thin film to a highly integrated device, conventional processes do not provide a ferroelectric thin film which sufficiently fulfills various conditions, such as denseness and evenness on the thin film surface required for fine processing and formation of film at a relatively low temperature.
U.S. Pat. No. 5,000,834 discloses a vacuum deposition technique known as face target sputtering to form thin films on magnetic recording heads at low temperature. The sputtering method is widely used for forming a thin film on a substrate made of PMMA because of intimacy between the substrate and the thin film formed therethrough. The amorphous thin film of rare earth—transition metal alloy formed through the sputtering method is applied to an erasable magneto-optical recording medium. The sputtering method is performed as follows: Positive ions of an inert gas such as Argon (Ar) first created by a glow discharge are accelerated toward a cathode or target, and then they impinge upon the target. As a result of ionic bombardment, neutral atoms and ions are removed from the target surface into a vacuum chamber due to the exchange of momentum therebetween. The liberated or sputtered atoms and ions are consequently deposited on a preselected substrate disposed in the vacuum chamber.
U.S. Pat. No. 6,156,172 discloses a plasma generating unit and a compact configuration of the combination of plasma space and substrate holders for a facing target type sputtering apparatus which includes: an arrangement for defining box-type plasma units supplied therein with sputtering gas mounted on outside wall-plates of a closed vacuum vessel; at least a pair of targets arranged to be spaced apart from and face one another within the box-type plasma unit, with each of the targets having a sputtering surface thereof; a framework for holding five planes of the targets or a pair of facing targets and three plate-like members providing the box-type plasma unit so as to define a predetermined space apart from the pair of facing targets and the plate-like members, which framework is capable of being removably mounted on the outside walls of the vacuum vessel with vacuum seals; a holder for the target having conduits for a coolant; an electric power source for the targets to cause sputtering from the surfaces of the targets; permanent magnets arranged around each of the pair of targets for generating at least a perpendicular magnetic field extending in a direction perpendicular to the sputtering surfaces of the facing targets; devices for containing the permanent magnets with target holders, removably mounted on the framework; and a substrate holder at a position adjacent the outlet space of the sputtering plasma unit in the vacuum vessel. The unified configuration composed of a cooling device for cooling both the backside plane of the targets and a container of magnets in connection with the framework improves the compactness of sputtering apparatus.

SUMMARY

In one aspect, systems and methods are disclosed to form an exemplary memory structure by flowing argon gas and oxygen gas in a deposition chamber; providing a low oxygen flow rate approximately between 0 and ten percent (10%) of an argon flow rate, a pressure approximately between 2×10⁻⁵Torr and 1×10⁻³Torr, and a deposition temperature approximately between 340° C. and 450° C.; and forming a PCMO (Pr_1-xCa_xMnO₃, where X is approximately between 0.1 and 0.9) material.
Implementations of the above aspect may include one or more of the following. The PCMO material maintains a uniform ratio of Pr:Ca:Mn:O is across the PCMO material. A poly-crystalline PCMO can be formed at a temperature below 400° C. with the low oxygen flow rate. A memory device can be formed. The PCMO structure includes a layer of with a thickness of 2,000 Å or less. Materials can be deposited using a radio frequency (RF) rate of 13.56 Megahertz. The method includes providing at least one target and a substrate having a film-forming surface portion and a back portion; creating a magnetic field so that the film-forming surface portion is placed in the magnetic field with the magnetic field induced normal to the substrate surface portion; back-biasing the back portion of the substrate; and sputtering material onto the film-forming surface portion, wherein the thin forming surface portion comprises non-volatile data storage devices interconnected thereto.
In another aspect, a facing targets sputtering device for semiconductor fabrication includes an air-tight chamber in which an inert gas is admittable and exhaustible; a pair of target plates placed at opposite ends of said air-tight chamber respectively so as to face each other and form a plasma region therebetween; a pair of magnets respectively disposed adjacent to said target plates such that magnet poles of different polarities face each other across said plasma region thereby to establish a magnetic field of said plasma region between said target plates; a substrate holder disposed adjacent to said plasma region, said substrate holder adapted to hold a substrate on which an alloyed thin film is to be deposited; and a back-bias power supply coupled to the substrate holder.
In another aspect, a method for sputtering a thin film onto a substrate includes providing at least one target and a substrate having a film-forming surface portion and a back portion; creating a magnetic field so that the film-forming surface portion is placed in the magnetic field with the magnetic field induced normal to the substrate surface portion; back-biasing the back portion of the substrate; and sputtering material onto the film-forming surface portion.
Advantages of the invention may include one or more of the following. The substrate temperature in forming a thin film is approximately below 400 degrees C. and the process requires a short time. Since the thin film is formed at a very low temperature during substantially the whole process, the process can be applied to a highly integrated device to deposit an additional layer with a plurality of elements without damaging other elements previously deposited using conventional deposition.

BRIEF DESCRIPTION OF THE FIGURES

In order that the manner in which the above-recited and other advantages and features of the invention are obtained, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof, which are illustrated, in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered to be limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:
FIG. 1 shows one embodiment of an apparatus for fabricating semiconductor.
FIG. 2 is an exemplary electron distribution chart.
FIG. 3 shows one embodiment of an FTS unit.
FIG. 4A shows one embodiment of a second apparatus for fabricating semiconductor.
FIG. 4B shows one embodiment of a second apparatus for fabricating semiconductor.
FIG. 5 shows a TEM image of a cross sectional view of an exemplary device fabricated with the system of FIG. 1.
FIG. 6 is an enlarged view of one portion of the TEM image of FIG. 5.
FIG. 7 shows an exemplary memory circuit.
FIG. 8 shows another process for forming a semiconductor device.
FIG. 9 shows an exemplary chart showing the uniformity of the PCMO composition formed using the process of FIG. 8.
FIG. 10 shows an exemplary chart showing the effect of the oxygen rate flow and the impact on the PCMO structure.

DESCRIPTION

Referring now to the drawings in greater detail, there is illustrated therein structure diagrams for a semiconductor processing system and logic flow diagrams for processes a system will utilize to deposit a memory device at low temperature, as will be more readily understood from a study of the diagrams.
FIG. 1 shows one embodiment of an apparatus for fabricating semiconductor. An embodiment reactor 10 is schematically illustrated in FIG. 1. The reactor 10 includes a metal chamber 14 that is electrically grounded. A wafer or substrate 22 to be sputter coated is supported on a pedestal electrode 24 in opposition to the target 16. An electrical bias source 26 is connected to the pedestal electrode 24. Preferably, the bias source 26 is an RF bias source coupled to the pedestal electrode 24 through an isolation capacitor. Such bias source produces a negative DC self-bias VB on the pedestal electrode 24 on the order of tens of volts. A working gas such as argon is supplied from a gas source 28 through a mass flow controller 30 and thence through a gas inlet 32 into the chamber. A vacuum pump system 34 pumps the chamber through a pumping port 36.
An FTS unit is positioned to face the wafer 22 and has a plurality of magnets 102, 104, 106, and 108. A first target 110 is positioned between magnets 102 and 104, while a second target 120 is positioned between magnets 106 and 108. The first and second targets 110 and 120 define an electron confining region 130. A power supply 140 is connected to the magnets 102-108 and targets 110-120 so that positive charges are attracted to the targets 110-120. During operation, particles are sputtered onto a substrate 22 which, in one embodiment where the targets 110 and 120 are laterally positioned, is vertically positioned relative to the lateral targets 110 and 120. The substrate 22 is arranged to be perpendicular to the planes of the targets 110 and 120. A substrate holder 24 supports the substrate 22.
The targets 110 and 120 are positioned in the reactor 10 in such a manner that two rectangular shape cathode targets face each other so as to define the plasma confining region 130 therebetween. Magnetic fields are then generated to cover vertically the outside of the space between facing target planes by the arrangement of magnets installed in touch with the backside planes of facing targets 110 and 120. The facing targets 110 and 120 are used as a cathode, and the shield plates are used as an anode, and the cathode/anode are connected to output terminals of the direct current (DC) power supply 140. The vacuum vessel and the shield plates are also connected to the anode.
Under pressure, sputtering plasma is formed in the space 130 between the facing targets 110 and 120 while power from the power source is applied. Since magnetic fields are generated around the peripheral area extending in a direction perpendicular to the surfaces of facing targets 110 and 120, highly energized electrons sputtered from surfaces of the facing targets 110 and 120 are confined in the space between facing targets 110 and 120 to cause increased ionized gases by collision in the space 130. The ionization rate of the sputtering gases corresponds to the deposition rate of thin films on the substrate 22, then, high rate deposition is realized due to the confinement of electrons in the space 130 between the facing targets. The substrate 22 is arranged so as to be isolated from the plasma space between the facing targets 110 and 120.
Film deposition on the substrate 22 is processed at a low temperature range due to a very small number of impingement of plasma from the plasma space and small amount of thermal radiation from the target planes. A typical facing target type of sputtering method has superior properties of depositing ferromagnetic materials at high rate deposition and low substrate temperature in comparison with a magnetron sputtering method. When sufficient target voltage VT is applied, plasma is excited from the argon. The chamber enclosure is grounded. The RF power supply 26 to the chuck or pedestal 24 causes an effective DC ‘back-bias’ between the wafer and the chamber. This bias is negative, so it repels the low-velocity electrons and negative ions, such as O²⁻.
FIG. 2 illustrates an exemplary electron distribution for the apparatus of FIG. 1. The electron distribution follows a standard Maxwellian curve. Low energy electrons have two characteristics: they are numerous and they tend to have non-elastic collisions with the deposited atoms, resulting in amorphization during deposition. High-energy electrons come through the back-biased shield, but they effectively “bounce” off the atoms without significant energy transfer—these electrons do not affect the way bonds are formed. This is especially true because high energy electrons spend very little time in the vicinity of the atoms, while the low energy electrons spend more time next to the atoms and can interfere with bond formation.
The presence of the large positively biased shield affects the plasma, particularly those close to the pedestal electrode 24. As a result, the DC self-bias developed on the pedestal 24, particularly by an RF bias source, may be more positive than for the conventional large grounded shield, that is, less negative since the DC self-bias is negative in typical applications. It is believed that the change in DC self-bias arises from the fact that the positively biased shield drains electrons from the plasma, thereby causing the plasma and hence the pedestal electrode to become more positive.
FIG. 3 shows another embodiment of an FTS system. In this embodiment, a wafer 200 is positioned in a chamber 210. The wafer 200 is moved into the chamber 210 using a robot arm 220. The robot arm 220 places the wafer 200 on a wafer chuck 230. The wafer chuck 230 is moved by a chuck motor 240. One or more chuck heaters 250 heats the wafer 200 during processing.
Additionally, the wafer 200 is positioned between the heater 250 and a magnetron 260. The magnetron 260 serves as highly efficient sources of microwave energy. In one embodiment, microwave magnetrons employ a constant magnetic field to produce a rotating electron space charge. The space charge interacts with a plurality of microwave resonant cavities to generate microwave radiation. One electrical node 270 is provided to a back-bias generator such as the generator 26 of FIG. 1.
In the system of FIG. 3, two target plates are respectively connected and disposed onto two target holders which are fixed to both inner ends of the chamber 210 so as to make the target plates face each other. A pair of permanent magnets are accommodated in the target holders so as to create a magnetic field therebetween substantially perpendicular to the surface of the target plates. The wafer 200 is disposed closely to the magnetic field (which will define a plasma region) so as to preferably face it. The electrons emitted from the both target plates by applying the voltage are confined between the target plates because of the magnetic field to promote the ionization of the inert gas so as to form a plasma region. The positive ions of the inert gas existing in the plasma region are accelerated toward the target plates. The bombardment of the target plates by the accelerated particles of the inert gas and ions thereof causes atoms of the material forming the plates to be emitted. The wafer 200 on which the thin film is to be disposed is placed around the plasma region, so that the bombardment of these high energy particles and ions against the thin film plane is avoided because of effective confinement of the plasma region by the magnetic field. The back-bias RF power supply causes an effective DC ‘back-bias’ between the wafer 200 and the chamber 210. This bias is negative, so it repels the low-velocity electrons.
FIG. 4A shows one embodiment of a second apparatus for fabricating semiconductor. In the system of FIG. 4A, multiple 1-D deposition sources are stacked in the deposition chamber. The stacking of the sources reduces the amount of wafer travel, while significantly increasing deposition uniformity. A wafer 300 is inserted into a chamber 410 using a robot arm 420 moving through a transfer chamber 430. The wafer 300 is positioned onto a rotary chuck 440 with chuck heater(s) 450 positioned above the wafer. A linear motor 460 moves the chuck through a plurality of deposition chambers 470.
The system of FIG. 4A provides a plurality of one dimensional sputter deposition chambers. Each chamber can deposit a line of material. By moving the wafer 300 with the linear motor 460, 2-d coverage is obtained.
Turning now to FIG. 4B, a second embodiment of a fabrication apparatus is shown. In this embodiment, a chuck 500 is positioned inside a chamber. The chuck 500 supports a wafer 502. The chamber has vacuum bellows 510. The chuck 500 is driven by a wafer rotator 520 which rotates the wafer 502 and the chuck 500 in a pendulum-like manner. The chuck 500 is also powered by a linear motor 530 to provide up/down motion. A plurality of sources 540-544 perform deposition of materials on the wafer 502.
The system of FIG. 4B gets linear motion of the wafer 502 past the three sources for uniform deposition. This is done through a chuck supported from underneath rather than from the side. A jointed pendulum supports the wafer and keeps the wafer at a constant vertical distance from the target as the pendulum swings. The system swings the wafer using a pendulum. The system is more stable than a system with a lateral linear arm since the chuck 500 is heavy and supports the weight of the wafer, a heater, and RF back-bias circuitry and would require a very thick support arm otherwise the arm would wobble. Also, the linear arm would need to extend away from the source, resulting in large equipment. In this implementation, the arm sits below the chuck, resulting in a smaller piece of equipment and also the arm does not have to support much weight.
In one embodiment, a process for obtain 2D deposition coverage is as follows:
Receive desired 2D pattern from user
Move chuck into a selected deposition chamber;
Actuate linear motor and rotary chuck to in accordance with the 2D pattern
Move current wafer to next deposition chamber
Get next wafer into the current chamber and repeat process.
FIG. 5 shows a TEM image of an exemplary device fabricated with the system of FIG. 1, while FIG. 6 is an enlarged view of one portion of the TEM image of FIG. 5. The device of FIG. 5 was fabricated at a low temperature (below 400° C.). At the bottom of FIG. 5 is an oxide layer (20 nm thick). Above the oxide layer is a metal layer, in this case a titanium layer (24 nm thick). Above this layer is an interface layer, in this case a platinum (Pt) interface face layer (about 5 nm). Finally, a crystallite PCMO layer (79 nm thick) is formed at the top. Grains in this layer can be seen extending from the bottom toward the top with a slightly angled tilt. FIG. 6 shows a zoomed view showing the Ti metal layer, the Pt interface layer and the PCMO grain in more details.
Although one back-biased power supply is mentioned, a plurality of back-bias power supplies can be used. These power supplies can be controllable independently from each other. The electric energies supplied can be independently controlled. Therefore, the components of the thin film to be formed are easily controlled in every sputtering batch process. In addition, the composition of the thin film can be changed in the direction of the thickness of the film by using the Facing Targets Sputtering device.
FIG. 8 shows an exemplary process for forming a memory structure. The process flow argon gas and oxygen gas in a deposition chamber (1400). A low oxygen flow rate approximately between 0 and ten percent (10%) of an argon flow rate is maintained at a pressure approximately between 2×10⁻⁵Torr and 1×10⁻³Torr and a deposition temperature approximately between 340° C. and 450° C. (1402). The composition of sputtering target is PCMO (Pr_1-xCa_xMnO₃, where X is between 0.1 and 0.9). The process forms a PCMO (Pr_1-xCa_xMnO₃, X=0.1-0.9) material film on the wafer (1404).
The material has a ratio of Pr:Ca:Mn:O that is highly uniform across the PCMO film. The uniformity is shown in FIG. 9. As shown therein, at a depth of 0.5 microns or less, the ratio is constant. The low oxygen flow allows the system to deposit the poly-crystalline PCMO at a relatively low temperature below 400° C. The high flow (high partial pressure) of oxygen (O2) prevent the growth of poly-crystalline under low temperature. The reactive sputtering using three target of Pr, Ca and Mn under high flow of oxygen with Ar can not accomplish the low-temperature deposition of crystalline PCMO.
The PCMO deposition method uses a PCMO target under a low oxygen flow the presence of argon. The oxygen flow is between 0 to 10% of argon. The low temperature deposition (T<400° C.) enables memory structures to be formed above semiconductor structures while minimizing potential damage to the preformed semiconductor structures.
FIG. 10 shows an exemplary chart of a plot of PCMO crystalline formation as a percentage of argon and oxygen rate flow parameters at an exemplary temperature of 340 degrees. As shown therein, when the percentage of oxygen over argon flow rate is above 20%, the crystalline fraction is around 20%. At a percentage of 15% or less, the crystalline fraction increases to between 25% and 95%. The effect of the low flow oxygen on crystalline formation is shown in the two cross-sectional images of the deposited structure.
Turning now to the images, the top image of FIG. 10 shows the crystal formation when the flow is all argon. The amorphous or micro-crystalline formation is a relatively small portion of the entire PCMO structure. In contrast, in the bottom image, when the flow ratio of oxygen to argon is approximately 15%, the resulting PCMO structure is substantially amorphous or micro-crystalline with a small crystal portion. The amorphous PCMO forms the desired memory structure.
FIG. 11 illustrates a resistance sensing circuit for sensing the resistance value of a resistor-based memory cell, in accordance with a first exemplary embodiment of the invention. A current source 400 delivers a small current (e.g., 1 mA) to the memory array 150 such that each of the unused row lines 450 of the memory array 150 conducts approximately 1 uA (i.e., assuming a 1024×1024 array). The row line 500 associated with a selected cell 460 is driven to ground. Each of the unused row lines 450 coupled to the column line 230 associated with the selected cell 460 is shorted to the others so that an equivalent resistance of approximately 1 Kohm is read at column line 230.
Turning now to FIG. 12, a flowchart of an operational flow of an exemplary resistance memory containing the memory cell reading circuit of FIG. 10 is depicted. The flow begins at process segment 6000. At segment 6100, a cell 460 is selected. One side of the resistor 210 of the selected memory cell 460 is grounded by grounding the associated wordline (row) at segment 6200. At segment 6300, a current is driven through all unselected row lines. At segment 6400, a voltage measurement is taken from the column line 230 that is associated with the selected memory cell 460 to ground. The measured voltage is compared with a reference voltage at segment 6500 to determine the cell resistance value and, ultimately, the logic value stored in the cell 460. The process flow ends at segment 6600.
It is to be understood that various terms employed in the description herein are interchangeable. Accordingly, the above description of the invention is illustrative and not limiting. Further modifications will be apparent to one of ordinary skill in the art in light of this disclosure.
The invention has been described in terms of specific examples which are illustrative only and are not to be construed as limiting. The invention may be implemented in digital electronic circuitry or in computer hardware, firmware, software, or in combinations of them.
Apparatus of the invention for controlling the fabrication equipment may be implemented in a computer program product tangibly embodied in a machine-readable storage device for execution by a computer processor; and method steps of the invention may be performed by a computer processor executing a program to perform functions of the invention by operating on input data and generating output. Suitable processors include, by way of example, both general and special purpose microprocessors. Storage devices suitable for tangibly embodying computer program instructions include all forms of non-volatile memory including, but not limited to: semiconductor memory devices such as EPROM, EEPROM, and flash devices; magnetic disks (fixed, floppy, and removable); other magnetic media such as tape; optical media such as CD-ROM disks; and magneto-optic devices. Any of the foregoing may be supplemented by, or incorporated in, specially-designed application-specific integrated circuits (ASICs) or suitably programmed field programmable gate arrays (FPGAs).
While the preferred forms of the invention have been shown in the drawings and described herein, the invention should not be construed as limited to the specific forms shown and described since variations of the preferred forms will be apparent to those skilled in the art. Thus the scope of the invention is defined by the following claims and their equivalents.

Claims

1. A method for forming a semiconductor, comprising:

flowing argon gas and oxygen gas in a deposition chamber;

providing a low oxygen flow rate approximately between 0 and ten percent (10%) of an argon flow rate, a pressure approximately between 2×10⁻⁵Torr and 1×10⁻³Torr, and a deposition temperature approximately between 340° C. and 450° C.;

providing a sputtering target made of PCMO (Pr_1-xCa_xMnO₃, where X is between 0.1 and 0.9); and

forming a plurality of current sensors coupled to an array of PCMO memory cells.

2. The method of claim 1, wherein the PCMO material maintains a uniform ratio of Pr:Ca:Mn:O is across the PCMO material.

3. The method of claim 1, comprising forming a poly-crystalline PCMO at a temperature below 400° C. with the low oxygen flow rate.

4. The method of claim 1, comprising forming a memory device.

5. The method of claim 1, wherein the PCMO structure comprises a layer of with a thickness of 2,000 Å or less.

6. The method of claim 1, comprising depositing materials using a radio frequency (RF) rate of 13.56 Megahertz.

7. The method of claim 1, comprising:

providing at least one target and a substrate having a film-forming surface portion and a back portion; creating a magnetic field so that the film-forming surface portion is placed in the magnetic field with the magnetic field induced normal to the substrate surface portion; back-biasing the back portion of the substrate; and sputtering material onto the film-forming surface portion, wherein the thin forming surface portion comprises non-volatile data storage devices interconnected thereto.

8. A facing targets sputtering device for semiconductor fabrication, comprising:

an air-tight chamber in which an inert gas is admittable and exhaustible;

a pair of target plates placed at opposite ends of said air-tight chamber respectively so as to face each other and form a plasma region therebetween;

a pair of magnets respectively disposed adjacent to said target plates such that magnet poles of different polarities face each other across said plasma region thereby to establish a magnetic field of said plasma region between said target plates; a substrate holder disposed adjacent to said plasma region, said substrate holder adapted to hold a substrate on which an alloyed thin film is to be deposited; a back-bias power supply coupled to the substrate holder;

wherein the substrate includes one or more memory arrays formed thereon, wherein the argon gas and oxygen gas flows into the deposition chamber at a low oxygen flow rate approximately between 0 and ten percent (10%) of an argon flow rate, a pressure approximately between 2×10⁻⁵Torr and 1×10⁻³Torr, and a deposition temperature approximately between 340° C. and 450° C. on a sputtering target with PCMO (Pr_1-xCa_xMnO₃, where X is between 0.1 and 0.9) and wherein a first reference cell containing a first resistor of a first resistance value; a second reference cell containing a second resistor of a second resistance value, wherein a current source is coupled to said first and second reference cells for passing a current through said first and second reference cells, and wherein said first and second reference cells are coupled to each other so as to enable a detection of a reference voltage to be fed into an input of a comparator for comparing said reference voltage with a voltage sensed from a selected memory cell of said memory array.

9. A facing targets sputtering device according to claim 11, wherein the back-bias power supply is a DC or an AC electric power source.

10. A facing targets sputtering device according to claim 11, further comprising a first target power supply coupled to one of the target plates.

11. A facing targets sputtering device according to claim 13, wherein the first target power supply is a DC or an AC electric power source.

12. A facing targets sputtering device according to claim 11, further comprising a second target power supply coupled to the remaining target plate.

13. A facing targets sputtering device according to claim 11, wherein the first and second target power supplies comprises DC and AC electric power sources.

14. A facing targets sputtering device according to claim 11, further comprising a robot arm to move the wafer.

15. A facing targets sputtering device according to claim 11, further comprising a magnetron coupled to the chamber.

16. A facing targets sputtering device according to claim 11, further comprising a chuck heater mounted above the wafer.

17. The apparatus of claim 11, wherein the FTS further comprises first and second targets mounted in parallel.