US20070148853A1 - Novel masked nitrogen enhanced gate oxide - Google Patents

Novel masked nitrogen enhanced gate oxide Download PDF

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US20070148853A1
US20070148853A1 US11/711,548 US71154807A US2007148853A1 US 20070148853 A1 US20070148853 A1 US 20070148853A1 US 71154807 A US71154807 A US 71154807A US 2007148853 A1 US2007148853 A1 US 2007148853A1
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oxide layer
hardened
gate oxide
resist
forming
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John Moore
Mark Fischer
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to fabrication of transistors in integrated circuit devices. Specifically, the present invention provides an improved method for fabricating an integrated circuit device including N-channel and P-channel transistors having selectively hardened gate oxides.
  • IC devices generally require transistors including hardened gate oxides.
  • gate oxides are hardened in order to prevent diffusion of dopants from overlying layers into and through the gate oxide, to prevent breakdown at voltages below normal operating parameters, and to confer resistance to hot electron degradation.
  • transistors including hardened gate oxides therefore, often possess performance and reliability advantages relative to transistors including non-hardened gate oxides applied in the same context.
  • hardened gate oxides are not desirable in all IC applications, and known methods for hardening gate oxides often require significant design and performance tradeoffs.
  • V T threshold voltage
  • P-channel or N-channel devices having gate oxides of varying thicknesses within a single IC device.
  • N-channel devices with gate oxides which are thicker than the thin, hardened gate oxides generally included in P-channel devices.
  • Increasing the thickness of non-hardened N-channel gate oxides increases the V T of the corresponding N-channel devices, thereby decreasing control and performance the same.
  • an ideal method for fabricating IC devices would facilitate simple and low-cost fabrication of IC devices including P-channel and N-channel devices which have been selectively hardened and which may include hardened or non-hardened gate oxides of varying thicknesses.
  • known methods for hardening gate oxides generally do not provide the flexibility needed to enable selective hardening of gate oxides within an IC device.
  • such techniques generally require additional etch steps, which are costly and serve as an additional source of error in a fabrication process.
  • CMOS complementary metal-oxide-semiconductor
  • DRAM dynamic random access memory
  • Blanket hardening processes simply do not enable selective hardening of particular areas of the gate oxide layer and, thereby, compromise the quality of IC devices fabricated by such methods.
  • blanket hardening techniques cause difficultly in fabricating IC devices including gate oxides of varying thicknesses.
  • Hardened oxide layers generally will not grow significantly during subsequent thermal oxidation processes. Therefore, to fabricate an IC device having gate oxides of various thicknesses using a blanket hardening process, the gate oxide layer must be formed such that, after hardening, the hardened gate oxide layer is as thick as the thickest desired gate oxide.
  • the hardened gate oxide layer must then be selectively etched back to a desired thickness where P-channel or N-channel devices having thinner gate oxides are to be formed.
  • Such a process is disadvantageous because it adds the cost and complication associated with one or more additional etch steps.
  • known etching processes are difficult to control where only minute amounts of material must be removed.
  • the need to etch back a hardened gate oxide layer becomes increasingly problematic and can only serve as a source of error, decreasing fabrication throughput as well as device reliability.
  • an improved method for fabricating IC devices including selectively hardening gate oxides is needed. Such an improved method should not only enable fabrication of P-channel and N-channel devices including selectively hardened gate oxides but also enable fabrication of such devices including hardened or non-hardened gate oxides of varying thicknesses without requiring additional etch steps.
  • the present invention provides a method for fabricating IC devices which answers the foregoing needs.
  • the method of the present invention includes providing a semiconductor substrate having a gate oxide layer formed thereover.
  • a resist is then formed over the gate oxide layer and patterned to expose one or more areas of the gate oxide layer which are to be hardened.
  • the exposed portions of the gate oxide layer are then hardened using a true remote plasma nitridation (RPN) scheme or a high-density plasma (HDP) RPN scheme. Because the RPN scheme used in the method of the present invention runs at low temperature, the patterned resist remains stable through the RPN process. Therefore, those areas of gate oxide layer which are exposed by the patterned resist are selectively hardened by the RPN treatment, while those areas covered by the patterned resist remain unaffected.
  • RPN remote plasma nitridation
  • HDP high-density plasma
  • the method of the present invention may also include additional steps for growing or hardening non-hardened areas of the gate oxide layer remaining after the first RPN treatment.
  • the non-hardened portion of the gate oxide layer, or a portion thereof may be grown to provide thick, non-hardened gate oxides for N-channel devices.
  • the non-hardened portion of the gate oxide layer, or a portion thereof may be grown and subsequently hardened to provide P-channel devices or N-channel devices having hardened gate oxides of varying thickness.
  • the portion of the gate oxide layer hardened by the first RPN need not be masked during subsequent thermal oxidation and hardening steps because, once hardened, the gate oxide will not grow significantly when exposed to subsequent thermal oxidation processes. In fact, where implants are required through the gate oxide layer, it is beneficial not to mask the hardened portion of the gate oxide layer during subsequent thermal oxidation, as such a process will heal any implant damage done to the gate oxide layer.
  • the present invention enables fabrication of an IC device including N-channel and P-channel devices having hardened or non-hardened gate oxides of varying thicknesses made necessary by known methods.
  • the method of the present invention may be easily integrated into known fabrication processes using known technology, and, because the method of the present invention does not require etching of the gate oxide layer to achieve gate oxides of varying thicknesses, the method of the present invention is cost effective and will continue to be useful as device dimensions shrink beyond the dimensions of those devices currently considered to be state of the art.
  • FIGS. 1 through 8 are cross-sectional views illustrating various steps of three different embodiments of the method of the present invention.
  • the method of fabricating an IC device according to the present invention includes providing a semiconductor substrate 10 upon which N-channel devices and P-channel devices may be formed. Any suitable semiconductor substrate known in the art may be used, though a silicon semiconductor substrate is preferred. Further, if desired, the semiconductor substrate may include wells doped with N-type or P-type impurities, as is known in the art. As is shown in drawing FIG. 1 , a gate oxide layer 14 is formed over the top surface 12 of the semiconductor substrate 10 using known deposition or thermal oxidation process. Thermal growth of the gate oxide layer 14 , however, is preferred, as it provides an SiO 2 layer that is substantially free of contaminants.
  • the gate oxide layer may be formed to any desired thickness, though, in the context of 0.18 ⁇ m technology, it is preferred to provide a gate oxide layer having a thickness in the range of substantially 30 ⁇ acute over ( ⁇ ) ⁇ to substantially 50 ⁇ acute over ( ⁇ ) ⁇ .
  • a first resist layer 16 is deposited over the upper surface 18 of the gate oxide layer 14 , as is shown in drawing FIG. 2 .
  • Any suitable resist may be used, and the resist may be deposited using well-known techniques, such as, for example, spin coating.
  • the first resist layer 16 is then patterned to expose an area 20 (seen in drawing FIG. 3 ) of the gate oxide layer 14 which is to be hardened.
  • the exposed area 20 is then subjected to a first RPN treatment (indicated by arrows 22 ), which selectively hardens only the exposed area 20 of the gate oxide layer 14 .
  • RPN treatments are well known in the art, and in the context of this invention, either a true RPN treatment or an HDP RPN treatment may be used.
  • the process parameters of the RPN treatment used to harden the exposed area 20 of the gate oxide layer may be varied to produce desired results in various fabrication contexts.
  • the temperature of the RPN treatment must be low enough that the patterned first resist layer 16 remains stable through the entire process.
  • an HDP RPN conducted for approximately 1 second to approximately 30 seconds at about 30° C. to about 90° C. using about 800 watts to 3000 watts of power.
  • Such a method effectively hardens the exposed area 20 of the gate oxide layer 14 , yet runs at a temperature well below that which might render the resist unstable.
  • the first intermediate structure 24 includes the semiconductor substrate 10 with a partially hardened gate oxide layer 26 , which may be used as desired in the fabrication of N-channel or P-channel devices.
  • the non-hardened portion 28 of the partially hardened gate oxide layer 26 will be used to fabricate at least one N-channel device, while the hardened portion 30 of the partially hardened gate oxide layer 26 will be used to fabricate at least one P-channel device.
  • the method of the present invention may include any suitable fabrication process necessary to complete fabrication of a desired IC device.
  • the partially hardened gate oxide layer 26 of the first intermediate structure 24 is further processed to provide an area of increased oxide thickness.
  • the second embodiment of the method of the present invention includes subjecting the first intermediate structure 24 to a thermal oxidation process (indicated by arrows 23 ). Thermal oxidation of the first intermediate structure causes the growth of the non-hardened portion 28 of the partially hardened gate oxide layer 26 .
  • the non-hardened portion may be grown to any desired thickness, where the original thickness of the gate oxide layer is in the range of substantially 30 ⁇ acute over ( ⁇ ) ⁇ to substantially 50 ⁇ acute over ( ⁇ ) ⁇ , it is presently preferred to grow the non-hardened gate oxide to a thickness in the range of substantially 50 ⁇ acute over ( ⁇ ) ⁇ to substantially 70 ⁇ acute over ( ⁇ ) ⁇ .
  • the hardened portion 30 of the partially hardened gate oxide layer 26 will not grow substantially, the thermal oxidation process will heal any implant damage caused to all portions of the gate oxide layer due to any necessary implant steps. Thermal oxidation of the first intermediate structure 24 , therefore, results in a second intermediate structure 31 (illustrated in drawing FIG. 6 ) including a second partially hardened gate oxide layer 32 characterized by a hardened portion 30 and a thick, non-hardened portion 34 .
  • the second partially hardened gate oxide layer 32 may be used as desired to form gate oxides for N-channel or P-channel devices.
  • the thick, non-hardened portion 34 of the second partially hardened gate oxide layer 32 may be used to form a gate oxide for one or more N-channel devices
  • the hardened portion 30 of the second partially hardened gate oxide layer 32 may be used to form a gate oxide for one or more P-channel devices.
  • various methods for fabricating an IC device including N-channel and P-channel devices using an intermediate structure, such as the second intermediate structure 31 illustrated in drawing FIG. 6 are well known, and the method of the present invention may include any such suitable method.
  • the second embodiment of the method of the present invention is desirable because it allows fabrication of an IC device including both an array of P-channels having thin, hardened gate oxides and an array of N-channel devices having thick, non-hardened gate oxides. Thickening the non-hardened gate oxides of N-channel devices results in N-channel devices characterized by a higher V T , and increasing device V T provides increased device control and enables better differentiation between N-channel and P-channel devices.
  • the second intermediate structure 31 is further processed to produce a third partially hardened gate oxide layer 33 having a first hardened portion 36 , a second hardened portion 38 (shown in FIG. 8 ), and a non-hardened portion 40 .
  • both the second hardened portion 38 and the non-hardened portion 40 are thicker than the first hardened portion 36 of the third partially hardened gate oxide layer 33 .
  • a second resist layer 42 is formed over the top surface 43 of the third partially hardened gate oxide layer 33 of the second intermediate structure 31 (illustrated in drawing FIG. 7 ).
  • the second resist layer 42 is then patterned by techniques known in the art to expose at least an area 44 of the thick, non-hardened portion 40 of the third partially hardened gate oxide layer 33 .
  • the exposed area 44 is then subjected to a second RPN treatment 47 , such as the preferred RPN treatment discussed herein.
  • the second RPN treatment selectively hardens the exposed area 44 of the non-hardened portion 40 of the third partially hardened gate oxide layer 33 .
  • the third embodiment of the method of the present invention provides a third intermediate structure 48 that may be further processed by known techniques to provide a desired IC device.
  • the first hardened portion 36 of the third partially hardened gate oxide layer 33 may be used to form one or more P-channel devices having thin, hardened gate oxides
  • the second hardened portion 38 of the third partially hardened gate oxide layer 33 may be used to form one or more P-channel devices having thick (preferably in the range of substantially 50 ⁇ acute over ( ⁇ ) ⁇ to substantially 70 ⁇ acute over ( ⁇ ) ⁇ ), hardened gate oxides
  • the thick, non-hardened portion 40 of the third partially hardened gate oxide layer 33 may be used to form N-channel devices including thick (preferably in the range of substantially 50 ⁇ acute over ( ⁇ ) ⁇ to substantially 70 ⁇ acute over ( ⁇ ) ⁇ ), non-hardened gate oxides.
  • the three embodiments of the method of the present invention discussed herein are provided for illustrative purposes only.
  • the method of the present invention is easily varied to provide IC devices having any desired combinations of hardened or non-hardened gate oxides of varying thicknesses.
  • the first resist layer used in the first and second embodiments of the method of the present invention may be patterned such that, following the RPN process, multiple hardened or non-hardened portions are formed within the gate oxide layer.
  • the intermediate structure may be processed according to the second embodiment of the method of the present invention to produce a partially hardened gate oxide layer including one or more hardened portions as well as multiple thick, non-hardened portions, which may be used in fabricating thick gate oxides for N-channel devices.
  • use of additional masking, growth, and RPN steps can produce virtually any number of different hardened areas of varying thicknesses within a single gate oxide layer.
  • Such a gate oxide layer can be used to form an IC device having any desired combination of selectively hardened N-channel or P-channel devices having gate oxides of different thicknesses.
  • any of the hardened portions of the partially hardened gate oxide layers produced in any embodiment of the present invention may be used to fabricate one or more hardened N-channel devices.
  • the patterned resist used in any embodiment of the method of the present invention may be patterned such that one or more specific areas of the gate oxide layer to be used for fabrication of hardened N-channel devices are hardened by the RPN treatment.
  • the method of the present invention is advantageous from more than one perspective.
  • the method of the present invention enables fabrication of IC devices including any desired combination of selectively hardened N-channel and P-channel devices. Selectively hardening the various devices included in the IC device enhances performance characteristics of the IC device and avoids the compounding performance problems generally presented by hardened N-channel devices.
  • the method of the present invention allows fabrication of hardened or non-hardened N-channel and P-channel devices having gate oxides of varying thicknesses without the need for the additional etch steps required by known fabrication processes. By eliminating the need for one or more etch steps, the method of the present invention provides a more cost effective alternative to known methods and eliminates at least one unnecessary source of error in the fabrication process.

Abstract

A method for fabricating improved integrated circuit devices. The method enables selective hardening of gate oxide layers and includes providing a semiconductor substrate having a gate oxide layer formed thereover. A resist is then formed over the gate oxide layer and patterned to expose one or more areas of the gate oxide layer which are to be hardened. The exposed portions of the gate oxide layer are then hardened using a true remote plasma nitridation (RPN) scheme or a high-density plasma (HDP) RPN scheme. Because the RPN scheme used in the method of the present invention runs at low temperature, the patterned resist remains stable through the RPN process, and those areas of gate oxide layer which are exposed by the patterned resist are selectively hardened by the RPN treatment, while those areas covered by the patterned resist remain unaffected.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of application Ser. No. 10/791,006, filed Mar. 2, 2004, pending, which is a continuation of application Ser. No. 10/198,215, filed Jul. 17, 2002, now U.S. Pat. No. 6,699,743, issued Mar. 2, 2004, which is a continuation of application Ser. No. 09/641,067, filed Aug. 17, 2000, now U.S. Pat. No. 6,458,663, issued Oct. 1, 2002. The disclosure of the previously referenced U.S. patent applications and patents referenced are hereby incorporated by reference in its entirety.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to fabrication of transistors in integrated circuit devices. Specifically, the present invention provides an improved method for fabricating an integrated circuit device including N-channel and P-channel transistors having selectively hardened gate oxides.
  • 2. State of the Art
  • State of the art integrated circuit (IC) devices generally require transistors including hardened gate oxides. As feature dimensions continually decrease, gate oxides are hardened in order to prevent diffusion of dopants from overlying layers into and through the gate oxide, to prevent breakdown at voltages below normal operating parameters, and to confer resistance to hot electron degradation. State of the art transistors including hardened gate oxides, therefore, often possess performance and reliability advantages relative to transistors including non-hardened gate oxides applied in the same context. However, hardened gate oxides are not desirable in all IC applications, and known methods for hardening gate oxides often require significant design and performance tradeoffs.
  • While it is generally preferred to harden the gate oxides of P-channel devices due to the nature of P-type dopants, such is not the case for N-channel devices. Hardening of N-channel devices is generally not necessary as N-type dopants do not readily diffuse through non-hardened gate oxides. Moreover, hardening N-channel devices is often undesirable due to compounding performance problems. As is well known, hardening of gate oxides included in N-channel devices leads to significant threshold voltage (VT) roll-off. While VT roll-off can be counteracted through enhancement implants, the increased dopant concentration resulting from enhancement implants causes additional performance problems, such as refresh degradation and reduced surface mobility. Therefore, it would generally be advantageous not to harden the gate oxides of N-channel devices included within an IC device.
  • Despite the difficulties generally resulting from hardening the gate oxides of N-channel devices, however, the ability to selectively harden the gate oxides of N-channel devices in particular instances would be advantageous.
  • Additionally, as is also well known, it is often desirable to include P-channel or N-channel devices having gate oxides of varying thicknesses within a single IC device. For instance, it is beneficial to provide N-channel devices with gate oxides which are thicker than the thin, hardened gate oxides generally included in P-channel devices. Increasing the thickness of non-hardened N-channel gate oxides increases the VT of the corresponding N-channel devices, thereby decreasing control and performance the same. Moreover, it may also be advantageous to fabricate an IC device including hardened P-channel or N-channel devices incorporating hardened gate oxides of varying thicknesses.
  • Therefore, an ideal method for fabricating IC devices would facilitate simple and low-cost fabrication of IC devices including P-channel and N-channel devices which have been selectively hardened and which may include hardened or non-hardened gate oxides of varying thicknesses. However, known methods for hardening gate oxides generally do not provide the flexibility needed to enable selective hardening of gate oxides within an IC device. Furthermore, though it is possible to fabricate hardened gate oxides of varying thicknesses using known techniques, such techniques generally require additional etch steps, which are costly and serve as an additional source of error in a fabrication process.
  • For example, known methods for hardening gate oxides included in an IC device, such as a dynamic random access memory (DRAM) device, often require blanket hardening of a gate oxide layer deposited over a semiconductor substrate. During subsequent fabrication steps, both N-channel and P-channel gate oxides must then be formed using the blanket hardened gate oxide layer. Consequently, every one of the N-channel and P-Channel devices included in the subsequently formed IC device includes a hardened gate oxide. Blanket hardening processes simply do not enable selective hardening of particular areas of the gate oxide layer and, thereby, compromise the quality of IC devices fabricated by such methods.
  • Additionally, blanket hardening techniques cause difficultly in fabricating IC devices including gate oxides of varying thicknesses. Hardened oxide layers generally will not grow significantly during subsequent thermal oxidation processes. Therefore, to fabricate an IC device having gate oxides of various thicknesses using a blanket hardening process, the gate oxide layer must be formed such that, after hardening, the hardened gate oxide layer is as thick as the thickest desired gate oxide. The hardened gate oxide layer must then be selectively etched back to a desired thickness where P-channel or N-channel devices having thinner gate oxides are to be formed. Such a process is disadvantageous because it adds the cost and complication associated with one or more additional etch steps. Moreover, known etching processes are difficult to control where only minute amounts of material must be removed. Thus, as the thickness of state of the art gate oxides shrinks well below 70 Angstroms, the need to etch back a hardened gate oxide layer becomes increasingly problematic and can only serve as a source of error, decreasing fabrication throughput as well as device reliability.
  • As can be appreciated, an improved method for fabricating IC devices including selectively hardening gate oxides is needed. Such an improved method should not only enable fabrication of P-channel and N-channel devices including selectively hardened gate oxides but also enable fabrication of such devices including hardened or non-hardened gate oxides of varying thicknesses without requiring additional etch steps.
    • BRIEF SUMMARY OF THE INVENTION
  • The present invention provides a method for fabricating IC devices which answers the foregoing needs. The method of the present invention includes providing a semiconductor substrate having a gate oxide layer formed thereover. A resist is then formed over the gate oxide layer and patterned to expose one or more areas of the gate oxide layer which are to be hardened. The exposed portions of the gate oxide layer are then hardened using a true remote plasma nitridation (RPN) scheme or a high-density plasma (HDP) RPN scheme. Because the RPN scheme used in the method of the present invention runs at low temperature, the patterned resist remains stable through the RPN process. Therefore, those areas of gate oxide layer which are exposed by the patterned resist are selectively hardened by the RPN treatment, while those areas covered by the patterned resist remain unaffected.
  • The method of the present invention may also include additional steps for growing or hardening non-hardened areas of the gate oxide layer remaining after the first RPN treatment. For example, the non-hardened portion of the gate oxide layer, or a portion thereof, may be grown to provide thick, non-hardened gate oxides for N-channel devices. Alternatively, the non-hardened portion of the gate oxide layer, or a portion thereof, may be grown and subsequently hardened to provide P-channel devices or N-channel devices having hardened gate oxides of varying thickness. The portion of the gate oxide layer hardened by the first RPN need not be masked during subsequent thermal oxidation and hardening steps because, once hardened, the gate oxide will not grow significantly when exposed to subsequent thermal oxidation processes. In fact, where implants are required through the gate oxide layer, it is beneficial not to mask the hardened portion of the gate oxide layer during subsequent thermal oxidation, as such a process will heal any implant damage done to the gate oxide layer.
  • As can be easily appreciated by one of skill in the art, the present invention enables fabrication of an IC device including N-channel and P-channel devices having hardened or non-hardened gate oxides of varying thicknesses made necessary by known methods. Moreover, the method of the present invention may be easily integrated into known fabrication processes using known technology, and, because the method of the present invention does not require etching of the gate oxide layer to achieve gate oxides of varying thicknesses, the method of the present invention is cost effective and will continue to be useful as device dimensions shrink beyond the dimensions of those devices currently considered to be state of the art.
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • The figures presented in conjunction with this description are not actual views of any particular portion of an actual semiconducting device or component, but are merely representations employed to more clearly and fully depict the present invention.
  • FIGS. 1 through 8 are cross-sectional views illustrating various steps of three different embodiments of the method of the present invention.
    • DETAILED DESCRIPTION OF THE INVENTION
  • According to a first embodiment, the method of fabricating an IC device according to the present invention includes providing a semiconductor substrate 10 upon which N-channel devices and P-channel devices may be formed. Any suitable semiconductor substrate known in the art may be used, though a silicon semiconductor substrate is preferred. Further, if desired, the semiconductor substrate may include wells doped with N-type or P-type impurities, as is known in the art. As is shown in drawing FIG. 1, a gate oxide layer 14 is formed over the top surface 12 of the semiconductor substrate 10 using known deposition or thermal oxidation process. Thermal growth of the gate oxide layer 14, however, is preferred, as it provides an SiO2 layer that is substantially free of contaminants. The gate oxide layer may be formed to any desired thickness, though, in the context of 0.18 μm technology, it is preferred to provide a gate oxide layer having a thickness in the range of substantially 30 {acute over (Å)} to substantially 50 {acute over (Å)}.
  • After formation of the gate oxide layer 14, a first resist layer 16 is deposited over the upper surface 18 of the gate oxide layer 14, as is shown in drawing FIG. 2. Any suitable resist may be used, and the resist may be deposited using well-known techniques, such as, for example, spin coating. Using known exposure and developing techniques, the first resist layer 16 is then patterned to expose an area 20 (seen in drawing FIG. 3) of the gate oxide layer 14 which is to be hardened. The exposed area 20 is then subjected to a first RPN treatment (indicated by arrows 22), which selectively hardens only the exposed area 20 of the gate oxide layer 14.
  • RPN treatments are well known in the art, and in the context of this invention, either a true RPN treatment or an HDP RPN treatment may be used. Generally, the process parameters of the RPN treatment used to harden the exposed area 20 of the gate oxide layer may be varied to produce desired results in various fabrication contexts. However, the temperature of the RPN treatment must be low enough that the patterned first resist layer 16 remains stable through the entire process. For example, it is presently preferred to use an HDP RPN conducted for approximately 1 second to approximately 30 seconds at about 30° C. to about 90° C. using about 800 watts to 3000 watts of power. Such a method effectively hardens the exposed area 20 of the gate oxide layer 14, yet runs at a temperature well below that which might render the resist unstable.
  • As can be seen in drawing FIG. 4, following the first RPN treatment 22, the remaining portions of the first resist layer 16 are removed, resulting in a first intermediate structure 24. The first intermediate structure 24 includes the semiconductor substrate 10 with a partially hardened gate oxide layer 26, which may be used as desired in the fabrication of N-channel or P-channel devices. Generally, the non-hardened portion 28 of the partially hardened gate oxide layer 26 will be used to fabricate at least one N-channel device, while the hardened portion 30 of the partially hardened gate oxide layer 26 will be used to fabricate at least one P-channel device. As will be appreciated by one of skill in the art, various methods for fabricating both N-channel and P-channel devices are well known, and after selectively hardening the gate oxide layer, the method of the present invention may include any suitable fabrication process necessary to complete fabrication of a desired IC device.
  • In a second embodiment of the method of the present invention, the partially hardened gate oxide layer 26 of the first intermediate structure 24 is further processed to provide an area of increased oxide thickness. As depicted in drawing FIG. 5, the second embodiment of the method of the present invention includes subjecting the first intermediate structure 24 to a thermal oxidation process (indicated by arrows 23). Thermal oxidation of the first intermediate structure causes the growth of the non-hardened portion 28 of the partially hardened gate oxide layer 26. Though the non-hardened portion may be grown to any desired thickness, where the original thickness of the gate oxide layer is in the range of substantially 30 {acute over (Å)} to substantially 50 {acute over (Å)}, it is presently preferred to grow the non-hardened gate oxide to a thickness in the range of substantially 50 {acute over (Å)} to substantially 70 {acute over (Å)}. Moreover, though the hardened portion 30 of the partially hardened gate oxide layer 26 will not grow substantially, the thermal oxidation process will heal any implant damage caused to all portions of the gate oxide layer due to any necessary implant steps. Thermal oxidation of the first intermediate structure 24, therefore, results in a second intermediate structure 31 (illustrated in drawing FIG. 6) including a second partially hardened gate oxide layer 32 characterized by a hardened portion 30 and a thick, non-hardened portion 34.
  • As was true with the partially hardened gate oxide layer 26 of the first intermediate structure 24 formed by the first embodiment of the method of the present invention, the second partially hardened gate oxide layer 32 may be used as desired to form gate oxides for N-channel or P-channel devices. For example, the thick, non-hardened portion 34 of the second partially hardened gate oxide layer 32 may be used to form a gate oxide for one or more N-channel devices, while the hardened portion 30 of the second partially hardened gate oxide layer 32 may be used to form a gate oxide for one or more P-channel devices. Again, various methods for fabricating an IC device including N-channel and P-channel devices using an intermediate structure, such as the second intermediate structure 31 illustrated in drawing FIG. 6, are well known, and the method of the present invention may include any such suitable method.
  • The second embodiment of the method of the present invention is desirable because it allows fabrication of an IC device including both an array of P-channels having thin, hardened gate oxides and an array of N-channel devices having thick, non-hardened gate oxides. Thickening the non-hardened gate oxides of N-channel devices results in N-channel devices characterized by a higher VT, and increasing device VT provides increased device control and enables better differentiation between N-channel and P-channel devices.
  • In a third embodiment of the method of the present invention, the second intermediate structure 31 is further processed to produce a third partially hardened gate oxide layer 33 having a first hardened portion 36, a second hardened portion 38 (shown in FIG. 8), and a non-hardened portion 40. As can be easily appreciated from drawing FIG. 8, both the second hardened portion 38 and the non-hardened portion 40 are thicker than the first hardened portion 36 of the third partially hardened gate oxide layer 33.
  • According to the third embodiment, a second resist layer 42 is formed over the top surface 43 of the third partially hardened gate oxide layer 33 of the second intermediate structure 31 (illustrated in drawing FIG. 7). The second resist layer 42 is then patterned by techniques known in the art to expose at least an area 44 of the thick, non-hardened portion 40 of the third partially hardened gate oxide layer 33. The exposed area 44 is then subjected to a second RPN treatment 47, such as the preferred RPN treatment discussed herein. The second RPN treatment selectively hardens the exposed area 44 of the non-hardened portion 40 of the third partially hardened gate oxide layer 33. However, those areas of the thick, non-hardened portion 40 of the third partially hardened gate oxide layer 33 underlying the second resist layer 42 are not affected by the RPN treatment because the second resist layer 42 remains stable through the RPN process. Therefore, after the remaining portions of the second resist layer 42 are removed, the third embodiment of the method of the present invention provides a third intermediate structure 48 that may be further processed by known techniques to provide a desired IC device. For example, the first hardened portion 36 of the third partially hardened gate oxide layer 33 may be used to form one or more P-channel devices having thin, hardened gate oxides, the second hardened portion 38 of the third partially hardened gate oxide layer 33 may be used to form one or more P-channel devices having thick (preferably in the range of substantially 50 {acute over (Å)} to substantially 70 {acute over (Å)}), hardened gate oxides, and the thick, non-hardened portion 40 of the third partially hardened gate oxide layer 33 may be used to form N-channel devices including thick (preferably in the range of substantially 50 {acute over (Å)} to substantially 70 {acute over (Å)}), non-hardened gate oxides.
  • Of course, it should be understood that the three embodiments of the method of the present invention discussed herein are provided for illustrative purposes only. The method of the present invention is easily varied to provide IC devices having any desired combinations of hardened or non-hardened gate oxides of varying thicknesses. For example, the first resist layer used in the first and second embodiments of the method of the present invention may be patterned such that, following the RPN process, multiple hardened or non-hardened portions are formed within the gate oxide layer. Additionally, where multiple non-hardened portions are formed within the gate oxide layer, the intermediate structure may be processed according to the second embodiment of the method of the present invention to produce a partially hardened gate oxide layer including one or more hardened portions as well as multiple thick, non-hardened portions, which may be used in fabricating thick gate oxides for N-channel devices. Finally, use of additional masking, growth, and RPN steps can produce virtually any number of different hardened areas of varying thicknesses within a single gate oxide layer. Such a gate oxide layer can be used to form an IC device having any desired combination of selectively hardened N-channel or P-channel devices having gate oxides of different thicknesses.
  • Moreover, though the described embodiments have discussed the use of the non-hardened portions of a gate oxide layer for fabrication of N-channel devices, it should be understood that, as mentioned, it is often desirable to create an IC device including one or more N-channel devices having a hardened gate oxide, particularly where long, peripheral N-channel devices are included in an IC device. Hardening of long N-channel devices increases the VT of such devices and decreases problems with charge leakage, and, as can be easily appreciated by the ordinarily skilled artisan, any of the hardened portions of the partially hardened gate oxide layers produced in any embodiment of the present invention may be used to fabricate one or more hardened N-channel devices. Further, the patterned resist used in any embodiment of the method of the present invention may be patterned such that one or more specific areas of the gate oxide layer to be used for fabrication of hardened N-channel devices are hardened by the RPN treatment.
  • In many of its embodiments, the method of the present invention is advantageous from more than one perspective. The method of the present invention enables fabrication of IC devices including any desired combination of selectively hardened N-channel and P-channel devices. Selectively hardening the various devices included in the IC device enhances performance characteristics of the IC device and avoids the compounding performance problems generally presented by hardened N-channel devices. Moreover, the method of the present invention allows fabrication of hardened or non-hardened N-channel and P-channel devices having gate oxides of varying thicknesses without the need for the additional etch steps required by known fabrication processes. By eliminating the need for one or more etch steps, the method of the present invention provides a more cost effective alternative to known methods and eliminates at least one unnecessary source of error in the fabrication process.
  • It should be understood that the method of the present invention is broadly applicable and is easily adapted for use in any desired process for fabricating IC devices. Therefore, even though the method of the present invention is described herein with reference to specific examples and figures, such examples and figures are provided for illustrative purposes only. The scope of the present invention is defined by the appended claims and is not limited by the preceding description and drawings.

Claims (20)

1. A method that eliminates an etching process in the manufacture of a semiconductor device having a substrate having an oxide layer thereon comprising:
forming a resist over at least a portion of said oxide layer;
patterning said resist to create at least one exposed area of said oxide layer;
hardening said at least one exposed area of said oxide layer using a remote plasma nitrogen hardening treatment;
forming a second resist over at least a portion of said oxide layer;
patterning said second resist to create at least one exposed area of said oxide layer; and
conducting a second remote plasma nitrogen hardening treatment to create at least one second hardened area and at least one non-hardened area within said oxide layer.
2. The method of claim 1, wherein the substrate comprises a silicon substrate.
3. The method of claim 2, wherein forming the oxide layer over at least a portion of the substrate comprises thermally growing an oxide layer.
4. The method of claim 1, wherein hardening the at least one exposed area of the oxide layer using the remote plasma nitrogen hardening treatment comprises using a high-density plasma remote plasma nitrogen hardening treatment.
5. The method of claim 4, wherein using the high-density plasma remote plasma nitrogen hardening treatment comprises using a process run in a range of approximately 1 second to approximately 30 seconds at a temperature of between about 30° C. and about 90° C. using about 800 watts to 3000 watts of power.
6. The method of claim 1, wherein forming the oxide layer over the at least a portion of the substrate comprises forming an oxide layer having a thickness of about 30 Angstroms to about 50 Angstroms.
7. The method of claim 1, wherein patterning the resist to create the at least one exposed area of the oxide layer comprises patterning the resist to create a plurality of exposed areas of the oxide layer.
8. A method for forming gate oxide layers having varying thicknesses without the use of etching in the manufacture of a semiconductor device having a substrate having an oxide layer thereon comprising:
forming a resist over at least a portion of said oxide layer;
patterning said resist to create at least one exposed area of said oxide layer;
hardening said at least one exposed area of said oxide layer using a remote plasma nitrogen hardening treatment;
forming a second resist over at least a portion of said oxide layer;
patterning said second resist to create at least one exposed area of said oxide layer; and
conducting a second remote plasma nitrogen hardening treatment to create at least one second hardened area and at least one non-hardened area within said oxide layer.
9. The method of claim 8, wherein the substrate comprises a silicon substrate.
10. The method of claim 9, wherein forming the oxide layer over at least a portion of the substrate comprises thermally growing an oxide layer.
11. The method of claim 8, wherein hardening the at least one exposed area of the oxide layer using the remote plasma nitrogen hardening treatment comprises using a high-density plasma remote plasma nitrogen hardening treatment.
12. The method of claim 11, wherein using the high-density plasma remote plasma nitrogen hardening treatment comprises using a process run in a range of approximately 1 second to approximately 30 seconds at a temperature of between about 30° C. and about 90° C. using about 800 watts to 3000 watts of power.
13. The method of claim 8, wherein forming the oxide layer over the at least a portion of the substrate comprises forming an oxide layer having a thickness of about 30 Angstroms to about 50 Angstroms.
14. The method of claim 8, wherein patterning the resist to create the at least one exposed area of the oxide layer comprises patterning the resist to create a plurality of exposed areas of the oxide layer.
15. A method for forming gate oxide layers having varying thicknesses without the use of etching for N-channel devices in the manufacture of an integrated circuit located on a portion of a substrate having an oxide layer thereon comprising:
forming a resist over at least a portion of said oxide layer;
patterning said resist to create at least one exposed area of said oxide layer;
hardening said at least one exposed area of said oxide layer using a remote plasma nitrogen hardening treatment;
forming a second resist over at least a portion of said oxide layer;
patterning said second resist to create at least one exposed area of said oxide layer; and
conducting a second remote plasma nitrogen hardening treatment to create at least one second hardened area and at least one non-hardened area within said oxide layer.
16. The method of claim 15, wherein the substrate comprises a silicon substrate.
17. The method of claim 16, wherein forming the oxide layer over at least a portion of the substrate comprises thermally growing an oxide layer.
18. The method of claim 15, wherein hardening the at least one exposed area of the oxide layer using the remote plasma nitrogen hardening treatment comprises using a high-density plasma remote plasma nitrogen hardening treatment.
19. The method of claim 18, wherein using the high-density plasma remote plasma nitrogen hardening treatment comprises using a process run in a range of approximately 1 second to approximately 30 seconds at a temperature of between about 30° C. and about 90° C. using about 800 watts to 3000 watts of power.
20. The method of claim 15, wherein forming the oxide layer over the at least a portion of the substrate comprises forming an oxide layer having a thickness of about 30 Angstroms to about 50 Angstroms.
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