US20070161168A1 - Method for fabricating a semiconductor device having a multi-bridge-channel - Google Patents
Method for fabricating a semiconductor device having a multi-bridge-channel Download PDFInfo
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- US20070161168A1 US20070161168A1 US11/710,580 US71058007A US2007161168A1 US 20070161168 A1 US20070161168 A1 US 20070161168A1 US 71058007 A US71058007 A US 71058007A US 2007161168 A1 US2007161168 A1 US 2007161168A1
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000009413 insulation Methods 0.000 claims abstract description 108
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- 238000002955 isolation Methods 0.000 claims description 39
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Definitions
- the present invention relates to a semiconductor device and a method for fabricating the same. More particularly, the present invention relates to a semiconductor device having a multi-bridge-channel (MBC) metal oxide semiconductor field effect transistor (MBCFET) formed by self-alignment and a method for fabricating the same.
- MCC multi-bridge-channel
- MBCFET metal oxide semiconductor field effect transistor
- a short channel length generates several problems, such as a short channel effect, a fine pattern formation, and limitations on operation speed.
- the short channel effect is a particularly severe problem. For example, an electric field increase in a vicinity of a drain region causes a punch-through, in which a drain depletion region penetrates up to an electric potential wall in a vicinity of a source region. Further, thermal electrons cause an avalanche and a vertical electric field decreases mobility of carriers.
- a conventional MBCFET includes, e.g., a gate electrode layer enclosing a plurality of thin channel semiconductor layers having a rectangular shape.
- a channel semiconductor layer has a very wide area.
- the MBCFET is under a small influence of an electric field in the vicinity of a drain region, which eliminates the short channel effect.
- Such a conventional MBCFET is subjected to two separate photoetching processes including a process for forming the channel semiconductor layer and a process for forming the gate electrode covering and surrounding the channel semiconductor layer.
- misalignments are generated between the gate electrodes and the channel semiconductor layers during these processes.
- the present invention is therefore directed to a semiconductor device having a multi-bridge-channel (MBC) metal oxide semiconductor field effect transistor (MBCFET) formed by self-alignment and a method for fabricating the same, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
- MCC multi-bridge-channel
- MBCFET metal oxide semiconductor field effect transistor
- a semiconductor device having a multi-bridge-channel including a first semiconductor post protruding a first predetermined height from a surface of a semiconductor substrate and having a source region in an upper side portion thereof, a second semiconductor post protruding a second predetermined height from the surface of the semiconductor substrate, the second semiconductor post facing the first semiconductor post and having a drain region in an upper side portion thereof, a pair of channel semiconductor layers connecting the upper side portion of the first semiconductor post to the upper side portion of the second semiconductor post, a gate insulation layer on the pair of channel semiconductor layers and the semiconductor substrate, the gate insulation layer surrounding at least a portion of the pair of channel semiconductor layers, a gate electrode layer on the gate insulation layer to enclose at least a portion of a region between the pair of channel semiconductor layers, and a pair of junction auxiliary layers formed between the pair of channel semiconductor layers, the pair of junction auxiliary layers contacting the gate electrode layer, the upper side portion of the first semiconductor post, and the upper side
- the first predetermined height and the second predetermined height may be the same.
- the surface of the semiconductor substrate may be a bottom of a trench etched a predetermined depth from an upper surface of the semiconductor substrate.
- the semiconductor device may further include an insulation mask pattern on the first and second semiconductor posts and insulation spacers on facing lateral walls of the insulation mask pattern.
- a width of the insulation spacers may be the same as a width of the pair of junction auxiliary layers.
- a width of the insulation spacers may be constant from a lower portion thereof to an upper portion thereof.
- An upper surface of the pair of channel semiconductor layers may be coplanar with upper surfaces of the first and second semiconductor posts.
- the pair of channel semiconductor layers may connect both ends of the upper side portion of the first semiconductor post to both ends of the upper side portion of the second semiconductor post.
- the gate electrode layer may enclose both lateral walls and an upper surface of the pair of channel semiconductor layers and may be self-aligned between the insulation spacers.
- the pair of channel semiconductor layers and the pair of junction auxiliary layers may be silicon epitaxial layers.
- At least one of the above and other features and advantages of the present invention may be realized by providing a method for fabricating a semiconductor device having a multi-bridge-channel including forming a semiconductor wall having a predetermined height from a surface of a semiconductor substrate, the semiconductor wall extending in a first direction, forming an isolation layer surrounding the semiconductor wall, forming a pair of semiconductor posts facing and spaced apart from each other by removing a portion of the semiconductor wall, forming a sacrificial layer between the pair of semiconductor posts and the isolation layer, the sacrificial layer being a same distance apart from each of the pair of semiconductor posts and the isolation layer, epitaxially growing a single crystal layer on the sacrificial layer, lateral walls of the pair of semiconductor posts, and the isolation layer, forming a pair of channel semiconductor layers connecting facing upper side portions of the pair of semiconductor posts and forming a pair of junction auxiliary layers between the pair of channel semiconductor layers to contact the pair of semiconductor posts by removing a portion of the single crystal layer so that a height of the single
- Forming the pair of semiconductor posts facing each other and spaced apart from each other by removing a portion of the semiconductor wall may include forming an insulation mask pattern defining a space therein and extending in a second direction, which is perpendicular to the first direction, on both sides of the semiconductor wall, and removing the portion of the semiconductor wall exposed by the space in the insulation mask pattern using the insulation mask pattern and the isolation layer for etching masks.
- the method may further include forming an etch stop layer covering a lateral wall of the insulation mask pattern, after forming the insulation mask pattern.
- the sacrificial layer may be a silicon germanium (SiGe) epitaxial layer.
- Forming the sacrificial layer between the pair of semiconductor posts may include forming an interim insulation spacer material layer covering lateral walls of the pair of semiconductor posts, a bottom of an opening formed in the semiconductor wall by the removal of the portion of the semiconductor wall, and a lateral wall of an insulation mask pattern defining a space therein and extending in a second direction, which is perpendicular to the first direction, forming interim insulation spacers exposing the bottom of the opening formed in the semiconductor wall by performing anisotropic-dry etching on the interim insulation spacer material layer, and epitaxially growing a sacrificial layer in an opening between the interim insulation spacers.
- the interim insulation spacer material layer may be a nitride film/oxide film or an oxide film.
- a width of the interim insulation spacer may be constant from a lower portion thereof to an upper portion thereof.
- a length of the pair of channel semiconductor layers may be determined by a width of the interim insulation spacers.
- the method may further include removing the interim insulation spacers using a wet etching before epitaxially growing the single crystal layer between the pair of semiconductor posts and the isolation layer.
- FIG. 1A illustrates a perspective view of a semiconductor device having a multi-bridge-channel formed by self-alignment according to an embodiment of the present invention
- FIGS. 1B and 1C illustrate cross-sectional views taken along lines B-B and C-C of FIG. 1A , respectively;
- FIG. 2A illustrates a perspective view of a semiconductor device having a multi-bridge-channel according to an embodiment of the present invention wherein a portion of an isolation layer is removed so that a portion of an activation region may be exposed
- FIG. 2B illustrates a perspective view of the semiconductor device shown in FIG. 2A including a gate electrode layer covering a channel semiconductor layer;
- FIGS. 3A through 14A illustrate perspective views of stages in a process for fabricating a semiconductor device having a multi-bridge-channel according to an embodiment of the present invention
- FIGS. 3B through 14B illustrate cross-sectional views of stages in a process for fabricating a semiconductor device having a multi-bridge-channel according to an embodiment of the present invention taken along line A-A of FIG. 3A .
- FIG. 1A illustrates a perspective view of a semiconductor device having a multi-bridge-channel formed by self-alignment according to an embodiment of the present invention.
- FIGS. 1B and 1C illustrate cross-sectional views taken along lines B-B and C-C of FIG. 1A , respectively.
- the first predetermined height and the second predetermined height may be the same.
- the surface 12 of the semiconductor substrate 10 may be a bottom surface 12 of a trench etched a predetermined depth from an upper surface of the semiconductor substrate 10 .
- An isolation layer 22 defines an activation region of the semiconductor substrate 10 .
- At least a pair of channel semiconductor layers 44 which are grown in an epitaxial manner, are connected to each other in a form of a bridge-type connection between the upper side portions of the first and second semiconductor posts 32 and 34 .
- the channel semiconductor layers 44 extend in a first direction, i.e., the x-direction in FIG. 1A .
- the channel semiconductor layers 44 may have a thin rectangular shape. Further, the channel semiconductor layers 44 may be connected between both ends of the upper side portions of the first and second semiconductor posts 32 and 34 . Upper surfaces of the channel semiconductor layers 44 may be coplanar with upper surfaces of the first and second semiconductor posts 32 and 34 .
- the present embodiment includes a pair of junction auxiliary layers 46 , which are grown in an epitaxial manner, having a same width as the channel semiconductor layers 44 .
- the junction auxiliary layers 46 are formed between the channel semiconductor layers 44 and contact a gate electrode layer 52 and the upper side portions of the first and second semiconductor posts 32 and 34 . More specifically, the junction auxiliary layers 46 extend in a second direction, i.e., the y-direction in FIG. 1A , which is perpendicular to the first direction.
- the channel semiconductor layers 44 and the junction auxiliary layers 46 are connected to each other and have a same width and height to form a structure defining an empty quadrangle.
- the channel semiconductor layers 44 and the junction auxiliary layers 46 may be silicon epitaxial layers.
- An insulation mask pattern 30 defining a space therein is formed on the first and second semiconductor posts 32 and 34 with a pad oxide film pattern 28 interposed therebetween.
- Insulation spacers 48 are formed on facing lateral walls of the insulation mask pattern 30 .
- An etch stop layer 36 may be interposed between the insulation spacers 48 and the insulation mask pattern 30 . Accordingly, the insulation spacers 48 cover a lateral wall of the etch stop layer 36 and are positioned on the junction auxiliary layers 46 .
- the lateral wall of the etch stop layer 36 in turn covers a lateral wall of the pad oxide film 28 .
- Bottom surfaces of the insulation spacer 48 have a same width as a width of the junction auxiliary layers 46 , which are grown in an epitaxial manner. Further, a width at a lower portion of the insulation spacers 48 and a width at an upper portion thereof may be constant. In the alternative, a width at the lower portion of the insulation spacers 48 may be rounded toward the upper portion thereof.
- a gate insulation layer 50 may be interposed between the gate electrode layer 52 and the channel semiconductor layers 44 and the semiconductor substrate 10 .
- the gate insulation layer 50 may have a shape enclosing at least a portion of a center of the channel semiconductor layers 44 .
- the gate electrode layer 52 may have a structure covering both lateral surfaces of the channel semiconductor layers 44 and the upper surfaces thereof. Further, the gate electrode layer 52 may enclose and surround the channel semiconductor layers 44 and may be buried in a self-aligning manner between the insulation spacers 48 , which face each other.
- FIG. 2A illustrates a perspective view of a semiconductor device having a multi-bridge-channel according to an embodiment of the present invention wherein a portion of the isolation layer 22 is removed so that a portion of an activation region may be exposed.
- FIG. 2B illustrates a perspective view of the semiconductor device having a multi-bridge-channel shown in FIG. 2A including the gate electrode layer 52 covering the channel semiconductor layers 44 .
- the activation layer protrudes from the isolation layer 22 a, a portion of which has been removed.
- the activation layer includes the channel semiconductor layers 44 , the junction auxiliary layers 46 , and the first and second semiconductor posts 32 and 34 separated by the channel semiconductor layers 44 , as explained in connection with FIGS. 1A through 1C .
- the gate electrode layer 52 covers both lateral surfaces of the channel semiconductor layers 44 and an upper surface thereof while exposing the junction auxiliary layers 46 .
- a width of the gate electrode layer 52 is the same as an interval between the junction auxiliary layers 46 . Accordingly, the junction auxiliary layers 46 and the channel semiconductor layers 44 between the first and second semiconductor posts 32 and 34 can be used for source/drain regions. In the present embodiment, areas of the source/drain regions are greatly extended so that electrical resistance can be reduced.
- FIGS. 3A through 14A illustrate perspective views of stages in a process for fabricating a semiconductor device having a multi-bridge-channel according to an embodiment of the present invention.
- FIGS. 3B through 14B illustrate cross-sectional views of stages in a process for fabricating a semiconductor device having a multi-bridge-channel according to an embodiment of the present invention taken along line A-A of FIG. 3A .
- a wall 16 having a predetermined height from the surface 12 of the semiconductor substrate 10 made of single crystal silicon and extending in the first direction, i.e., the x-direction of FIG. 1A is formed.
- the wall 16 is formed of the semiconductor substrate 10 and may have a stripe shape. More specifically, by filling a trench 14 including the surface 12 of the semiconductor substrate 10 with an insulation material to form the isolation layer 22 , the semiconductor substrate 10 enclosed by the isolation layer 22 becomes the wall 16 of the semiconductor substrate 10 having a predetermined height from the surface 12 of the semiconductor substrate 10 .
- the surface 12 may be an etched surface of the semiconductor substrate 10 that has been removed in order to form the isolation layer 22 .
- a variety of insulation material layers may be used for the isolation layer 22 .
- the present embodiment may use a high density plasma (HDP) oxide film.
- HDP high density plasma
- a material for the isolation layer 22 is selected with consideration of an etching selection ratio with respect to an adjacent material.
- a process for forming the isolation layer 22 is not illustrated in detail, general technology may be used to form an isolation layer in a vicinity of a surface of a semiconductor substrate. More specifically, a pad oxide layer (not shown) and a nitride layer (not shown) are first formed on an upper surface of the semiconductor substrate 10 . A mask pattern consisting of a pad oxide film pattern 18 and a nitride film pattern 20 for defining an isolation layer 22 is formed by applying general photoetching technology using a photoresist layer. The semiconductor substrate 10 is then anisotropic dry-etched to a predetermined depth using the mask pattern to form the trench 14 in a vicinity of the surface 12 of the semiconductor substrate 10 .
- an upper surface thereof is planarized and the mask pattern is removed, so that the isolation layer 22 surrounding the lateral walls of the wall 16 of the semiconductor substrate 10 is formed.
- an insulation material layer 26 for a mask is formed on an upper surface of the wall 16 and the isolation layer 22 .
- silicon nitride is exemplarily used for a material layer of the insulation mask pattern 30 in the present embodiment, other appropriate materials may be used with consideration of an etching selection ratio with respect to adjacent material layers.
- a pad oxide material layer 24 for a mask may additionally be formed under the insulation material layer 26 for the mask.
- an insulation mask pattern 30 defining a space therein is formed using a photoetching process.
- the insulation mask pattern 30 extends in a second direction, which is perpendicular to the first direction, in which the wall 16 of the semiconductor substrate 10 extends.
- the insulation mask pattern 30 may be used when forming the subsequent gate electrode layer using a damascene method. By controlling a size of the space defined by the insulation mask pattern 30 , it is possible to easily control an effective channel length of the gate electrode, as described below.
- the pad oxide film pattern 28 having a same lateral wall profile as the insulation mask pattern 30 can be formed under the insulation mask pattern 30 .
- the wall 16 having an upper surface coplanar with an upper surface of the isolation layer 22 , is exposed by the space defined by the insulation mask pattern 30 and the isolation layer 22 .
- the etch stop layer 36 may be formed using an isotropic dry-etching. A thickness of the etch stop layer 36 can be determined with consideration of the etching selection ratio.
- the etch stop layer 36 covers lateral walls of the insulation mask pattern 30 and the pad oxide film pattern 28 . Formation of the etch stop layer 36 may be omitted in some embodiments of the present invention.
- a portion of the wall 16 that is exposed between the etch stop layer 36 and the isolation layer 22 is etched, so that an opening 31 is formed. Portions of upper side portions of the wall 16 are spaced apart from each other by the opening 31 , so that the wall 16 is divided into the first and second semiconductor posts 32 and 34 , which are a plurality of semiconductor post types. A source region and a drain region are respectively formed in upper side portions of the first and second semiconductor posts 32 and 34 . Since a depth of the opening 31 is directly associated with an area of the subsequently formed channel semiconductor layers 44 of FIG. 2A , the depth is set according to a measure designed in advance. More specifically, as the depth of the opening 31 increases, an area of the channel semiconductor layers 44 is widened and as the depth decreases, the area of the channel semiconductor layer is narrowed.
- an insulation material layer is deposited on the upper side of the semiconductor substrate 10 , in which the opening 31 defined by the isolation layer 22 and the semiconductor posts 32 and 34 at a lower portion of the insulation mask pattern 30 is formed, a front-anisotropic etching is performed, so that interim insulation spacers 38 are formed on lateral walls of the opening 31 and lateral walls of the etch stop layer 36 .
- the interim insulation spacers 38 may be made of various materials such as oxides or nitrides. For example, when a nitride is used for the interim insulation spacers 38 , an oxide film may be further formed as the etch stop layer 36 between the insulation mask pattern 30 and the interim insulation spacers 38 .
- Oxides may be used with consideration of an etching selection ratio with respect to the semiconductor substrate 10 and the insulation mask pattern 30 . If the interim insulation spacers 38 are an oxide, the etch stop layer 36 described in connection with FIG. 6A cannot be formed and is omitted.
- a thickness of the interim insulation spacers 38 together with the above-described insulation mask pattern 30 is a factor that controls an effective channel length of the gate electrode, which will be described below, it is important to precisely form the thickness according to a designed measure. Further, a thickness of the interim insulation spacers 38 determines a width of the channel semiconductor layers 44 , which will be described below. Since the widths of the channel semiconductor layers should be the same to have the same threshold voltage, the thickness of the interim insulation spacers 38 at the respective lateral walls of the opening 31 may be constant.
- a sacrificial layer 40 is formed on the exposed semiconductor substrate 10 between the interim insulation spacers 38 to fill the opening 31 .
- the sacrificial layer 40 is not present in a final product of a semiconductor device, but is a material layer that can be temporarily used during a fabricating process.
- the sacrificial layer 40 may be provided in various ways.
- the sacrificial layer 40 may be formed using a material film having a lattice constant similar to that of the semiconductor substrate 10 and having an etching selection ratio with respect to the semiconductor substrate 10 .
- the sacrificial layer 40 may be an epitaxial silicon germanium (SiGe) layer. If necessary, it is possible to remove surface defects of the sacrificial layer 40 using hydrogen annealing.
- the sacrificial layer 40 may be formed using a molecular beam epitaxy method. SiH 4 , SiH 2 Cl 2 , SiCl 4 or Si 2 H 6 gases may be used as a silicon source gas to grow the sacrificial layer 40 . Alternatively, GeH 4 gas may be used as a germanium source gas to grow the sacrificial layer 40 .
- the sacrificial layer 40 may also be formed using a method such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).
- CVD chemical vapor deposition
- PVD physical vapor deposition
- the sacrificial layer 40 may be also formed by performing an appropriate etching process after a polysilicon layer is deposited by CVD and thermally treated.
- the sacrificial layer 40 Since the sacrificial layer 40 is defined by the interim insulation spacers 38 having the same thickness, the sacrificial layer 40 maintains the same interval from the pair of semiconductor posts 32 and 34 and the sides of the isolation layer 22 .
- An upper surface of the sacrificial layer 40 may be coplanar with an upper surface of the pair of semiconductor posts 32 and 34 .
- the interim insulation spacers 38 are removed by wet-etching using the etch stop layer 36 , the isolation layer 22 , and the sacrificial layer 40 for etching masks. Resultantly, the pair of semiconductor posts 32 and 34 and the isolation layer 22 , and the sacrificial layer 40 are spaced apart by the same interval in the first and second directions.
- a single crystal layer 42 is epitaxially grown in a space vacated by the interim insulation spacers 38 .
- the present embodiment may form an epitaxial silicon layer with consideration of alignment with the semiconductor substrate 10 made of single crystal silicon.
- SiH 4 , SiH 2 Cl 2 , SiCl 4 or Si 2 H 6 gases may be used for a silicon source gas to grow the silicon layer.
- an upper surface of the sacrificial layer 40 is exposed by removing a portion of the single crystal layer 42 so that the remaining single crystal layer 42 may have a same height as the sacrificial layer 40 .
- the single crystal layer 42 a portion of which has been removed, is divided into the pair of channel semiconductor layers 44 connected, in a form of a bridge, with the upper side portions of the pair of semiconductor posts 32 and 34 extending in the first direction and the pair of junction auxiliary layers 46 perpendicular to the first direction, formed between the channel semiconductor layers 44 and contacting the pair of semiconductor posts 32 and 34 .
- the insulation spacers 48 having the same thickness as the junction auxiliary layers 46 , or having a shape of being rounded toward an upper portion thereof, are formed on the junction auxiliary layers 46 .
- outer sidewalls of the channel semiconductor layers 44 are exposed by etching the isolation layer 22 beyond the channel semiconductor layers 44 using the sacrificial layer 40 , the channel semiconductor layers 44 , and the insulation spacers 48 for etching masks. Subsequently, the semiconductor substrate 10 is exposed by removing the sacrificial layer 40 . Alternatively, the sacrificial layer 40 may be first removed and then the isolation layer 22 outside of the channel semiconductor layers 44 can be removed. The sacrificial layer 40 may also be removed using an etching solution including a mixed solution of H 2 O 2 , HF, and CH 3 COOH, and peracetic acid, and isotropic-dry etching.
- the gate insulation layer 50 is formed on the resultant structure between the insulation spacers 48 to surround the channel semiconductor layers 44 .
- the gate insulation layer 50 may be made of a thermal oxide film and an insulation film having a high dielectric constant, e.g., an oxide film or an ONO film.
- the gate electrode layer 52 is formed on the gate insulation layer 50 .
- the gate electrode layer 52 may be formed using a single layer or a complex layer selected from among amorphous polysilicon, doped polysilicon, poly-SiGe, and a conductive metal content material.
- the conductive metal content material may be made of at least one layer selected from among a metal such as tungsten and molybdenum and conductive metal nitride films such as a titanium nitride film, a tantalum nitride film, and a tungsten nitride film.
- the gate electrode layer is formed in a self-aligning manner, thereby preventing misalignment with respect to the channel semiconductor layer.
Abstract
In a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, the device includes first and second semiconductor posts protruding from a surface of a semiconductor substrate and having a source and a drain region, respectively, in upper side portions thereof, channel semiconductor layers connecting upper side portions of the first and second semiconductor posts, a gate insulation layer on the channel semiconductor layers and the semiconductor substrate, the gate insulation layer surrounding at least a portion of the channel semiconductor layers, a gate electrode layer on the gate insulation layer to enclose at least a portion of a region between the channel semiconductor layers, and junction auxiliary layers formed between the channel semiconductor layers, the junction auxiliary layers contacting the gate electrode layer and upper side portions of the first and second semiconductor posts, and having a same width as the channel semiconductor layers.
Description
- This is a divisional application based on pending application Ser. No. 11/285,300, filed Nov. 23, 2005, the entire contents of which is hereby incorporated by reference.
- 1. Field of the Invention
- The present invention relates to a semiconductor device and a method for fabricating the same. More particularly, the present invention relates to a semiconductor device having a multi-bridge-channel (MBC) metal oxide semiconductor field effect transistor (MBCFET) formed by self-alignment and a method for fabricating the same.
- 2. Description of the Related Art
- To more highly integrate semiconductor devices, a length of gate channels is decreased. A short channel length, however, generates several problems, such as a short channel effect, a fine pattern formation, and limitations on operation speed. The short channel effect is a particularly severe problem. For example, an electric field increase in a vicinity of a drain region causes a punch-through, in which a drain depletion region penetrates up to an electric potential wall in a vicinity of a source region. Further, thermal electrons cause an avalanche and a vertical electric field decreases mobility of carriers.
- In an effort to eliminate the short channel effect, several gate structures including a MOSFET having a multi-bridge-channel (MBCFET) have been suggested. A conventional MBCFET includes, e.g., a gate electrode layer enclosing a plurality of thin channel semiconductor layers having a rectangular shape. In such a conventional MBCFET, a channel semiconductor layer has a very wide area. Thus, the MBCFET is under a small influence of an electric field in the vicinity of a drain region, which eliminates the short channel effect.
- Such a conventional MBCFET, however, is subjected to two separate photoetching processes including a process for forming the channel semiconductor layer and a process for forming the gate electrode covering and surrounding the channel semiconductor layer. Disadvantageously, misalignments are generated between the gate electrodes and the channel semiconductor layers during these processes.
- The present invention is therefore directed to a semiconductor device having a multi-bridge-channel (MBC) metal oxide semiconductor field effect transistor (MBCFET) formed by self-alignment and a method for fabricating the same, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
- It is therefore a feature of an embodiment of the present invention to provide a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, that is able to prevent misalignment between a gate electrode and channel semiconductor layers by forming the gate electrode in a self-aligning manner.
- It is therefore another feature of an embodiment of the present invention to provide a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, in which it is possible to form channel semiconductor layers having a same threshold voltage using interim insulation spacers having a same thickness.
- At least one of the above and other features and advantages of the present invention may be realized by providing a semiconductor device having a multi-bridge-channel including a first semiconductor post protruding a first predetermined height from a surface of a semiconductor substrate and having a source region in an upper side portion thereof, a second semiconductor post protruding a second predetermined height from the surface of the semiconductor substrate, the second semiconductor post facing the first semiconductor post and having a drain region in an upper side portion thereof, a pair of channel semiconductor layers connecting the upper side portion of the first semiconductor post to the upper side portion of the second semiconductor post, a gate insulation layer on the pair of channel semiconductor layers and the semiconductor substrate, the gate insulation layer surrounding at least a portion of the pair of channel semiconductor layers, a gate electrode layer on the gate insulation layer to enclose at least a portion of a region between the pair of channel semiconductor layers, and a pair of junction auxiliary layers formed between the pair of channel semiconductor layers, the pair of junction auxiliary layers contacting the gate electrode layer, the upper side portion of the first semiconductor post, and the upper side portion of the second semiconductor post, and having a same width as a width of the pair of channel semiconductor layers.
- The first predetermined height and the second predetermined height may be the same.
- The surface of the semiconductor substrate may be a bottom of a trench etched a predetermined depth from an upper surface of the semiconductor substrate.
- The semiconductor device may further include an insulation mask pattern on the first and second semiconductor posts and insulation spacers on facing lateral walls of the insulation mask pattern. A width of the insulation spacers may be the same as a width of the pair of junction auxiliary layers. A width of the insulation spacers may be constant from a lower portion thereof to an upper portion thereof.
- An upper surface of the pair of channel semiconductor layers may be coplanar with upper surfaces of the first and second semiconductor posts.
- The pair of channel semiconductor layers may connect both ends of the upper side portion of the first semiconductor post to both ends of the upper side portion of the second semiconductor post.
- The gate electrode layer may enclose both lateral walls and an upper surface of the pair of channel semiconductor layers and may be self-aligned between the insulation spacers.
- The pair of channel semiconductor layers and the pair of junction auxiliary layers may be silicon epitaxial layers.
- At least one of the above and other features and advantages of the present invention may be realized by providing a method for fabricating a semiconductor device having a multi-bridge-channel including forming a semiconductor wall having a predetermined height from a surface of a semiconductor substrate, the semiconductor wall extending in a first direction, forming an isolation layer surrounding the semiconductor wall, forming a pair of semiconductor posts facing and spaced apart from each other by removing a portion of the semiconductor wall, forming a sacrificial layer between the pair of semiconductor posts and the isolation layer, the sacrificial layer being a same distance apart from each of the pair of semiconductor posts and the isolation layer, epitaxially growing a single crystal layer on the sacrificial layer, lateral walls of the pair of semiconductor posts, and the isolation layer, forming a pair of channel semiconductor layers connecting facing upper side portions of the pair of semiconductor posts and forming a pair of junction auxiliary layers between the pair of channel semiconductor layers to contact the pair of semiconductor posts by removing a portion of the single crystal layer so that a height of the single crystal layer and a height of the sacrificial layer are the same, forming insulation spacers on the pair of junction auxiliary layers, removing the sacrificial layer, forming a gate insulation layer on and surrounding the pair of channel semiconductor layers between the insulation spacers, and forming a gate electrode layer on the gate insulation layer between the insulation spacers.
- Forming the pair of semiconductor posts facing each other and spaced apart from each other by removing a portion of the semiconductor wall may include forming an insulation mask pattern defining a space therein and extending in a second direction, which is perpendicular to the first direction, on both sides of the semiconductor wall, and removing the portion of the semiconductor wall exposed by the space in the insulation mask pattern using the insulation mask pattern and the isolation layer for etching masks.
- The method may further include forming an etch stop layer covering a lateral wall of the insulation mask pattern, after forming the insulation mask pattern.
- The sacrificial layer may be a silicon germanium (SiGe) epitaxial layer.
- Forming the sacrificial layer between the pair of semiconductor posts may include forming an interim insulation spacer material layer covering lateral walls of the pair of semiconductor posts, a bottom of an opening formed in the semiconductor wall by the removal of the portion of the semiconductor wall, and a lateral wall of an insulation mask pattern defining a space therein and extending in a second direction, which is perpendicular to the first direction, forming interim insulation spacers exposing the bottom of the opening formed in the semiconductor wall by performing anisotropic-dry etching on the interim insulation spacer material layer, and epitaxially growing a sacrificial layer in an opening between the interim insulation spacers.
- The interim insulation spacer material layer may be a nitride film/oxide film or an oxide film.
- A width of the interim insulation spacer may be constant from a lower portion thereof to an upper portion thereof.
- A length of the pair of channel semiconductor layers may be determined by a width of the interim insulation spacers.
- The method may further include removing the interim insulation spacers using a wet etching before epitaxially growing the single crystal layer between the pair of semiconductor posts and the isolation layer.
- The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
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FIG. 1A illustrates a perspective view of a semiconductor device having a multi-bridge-channel formed by self-alignment according to an embodiment of the present invention, andFIGS. 1B and 1C illustrate cross-sectional views taken along lines B-B and C-C ofFIG. 1A , respectively; -
FIG. 2A illustrates a perspective view of a semiconductor device having a multi-bridge-channel according to an embodiment of the present invention wherein a portion of an isolation layer is removed so that a portion of an activation region may be exposed, andFIG. 2B illustrates a perspective view of the semiconductor device shown inFIG. 2A including a gate electrode layer covering a channel semiconductor layer; and -
FIGS. 3A through 14A illustrate perspective views of stages in a process for fabricating a semiconductor device having a multi-bridge-channel according to an embodiment of the present invention, andFIGS. 3B through 14B illustrate cross-sectional views of stages in a process for fabricating a semiconductor device having a multi-bridge-channel according to an embodiment of the present invention taken along line A-A ofFIG. 3A . - Korean Patent Application No. 10-2004-0101662, filed on Dec. 6, 2004, in the Korean Intellectual Property Office, and entitled: “Semiconductor Device Having Multi-Bridge-Channel and Method for Fabricating the Same,” is incorporated by reference herein in its entirety.
- The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the figures, the dimensions of layers and regions are exaggerated for clarity of illustration. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.
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FIG. 1A illustrates a perspective view of a semiconductor device having a multi-bridge-channel formed by self-alignment according to an embodiment of the present invention.FIGS. 1B and 1C illustrate cross-sectional views taken along lines B-B and C-C ofFIG. 1A , respectively. - Referring to
FIGS. 1A through 1C , afirst semiconductor post 32 having a source region in an upper side portion thereof protrudes a first predetermined height from asurface 12 of asemiconductor substrate 10. Asecond semiconductor post 34 having a drain region in an upper side portion thereof faces thefirst semiconductor post 32 and protrudes a second predetermined height from thesurface 12 of thesemiconductor substrate 10. The first predetermined height and the second predetermined height may be the same. Thesurface 12 of thesemiconductor substrate 10 may be abottom surface 12 of a trench etched a predetermined depth from an upper surface of thesemiconductor substrate 10. Anisolation layer 22 defines an activation region of thesemiconductor substrate 10. - At least a pair of channel semiconductor layers 44, which are grown in an epitaxial manner, are connected to each other in a form of a bridge-type connection between the upper side portions of the first and second semiconductor posts 32 and 34. The channel semiconductor layers 44 extend in a first direction, i.e., the x-direction in
FIG. 1A . The channel semiconductor layers 44 may have a thin rectangular shape. Further, the channel semiconductor layers 44 may be connected between both ends of the upper side portions of the first and second semiconductor posts 32 and 34. Upper surfaces of the channel semiconductor layers 44 may be coplanar with upper surfaces of the first and second semiconductor posts 32 and 34. - The present embodiment includes a pair of junction auxiliary layers 46, which are grown in an epitaxial manner, having a same width as the channel semiconductor layers 44. The junction auxiliary layers 46 are formed between the channel semiconductor layers 44 and contact a
gate electrode layer 52 and the upper side portions of the first and second semiconductor posts 32 and 34. More specifically, the junction auxiliary layers 46 extend in a second direction, i.e., the y-direction inFIG. 1A , which is perpendicular to the first direction. The channel semiconductor layers 44 and the junction auxiliary layers 46 are connected to each other and have a same width and height to form a structure defining an empty quadrangle. The channel semiconductor layers 44 and the junction auxiliary layers 46 may be silicon epitaxial layers. - An
insulation mask pattern 30 defining a space therein is formed on the first and second semiconductor posts 32 and 34 with a padoxide film pattern 28 interposed therebetween.Insulation spacers 48 are formed on facing lateral walls of theinsulation mask pattern 30. Anetch stop layer 36 may be interposed between theinsulation spacers 48 and theinsulation mask pattern 30. Accordingly, theinsulation spacers 48 cover a lateral wall of theetch stop layer 36 and are positioned on the junction auxiliary layers 46. The lateral wall of theetch stop layer 36 in turn covers a lateral wall of thepad oxide film 28. Bottom surfaces of theinsulation spacer 48 have a same width as a width of the junction auxiliary layers 46, which are grown in an epitaxial manner. Further, a width at a lower portion of theinsulation spacers 48 and a width at an upper portion thereof may be constant. In the alternative, a width at the lower portion of theinsulation spacers 48 may be rounded toward the upper portion thereof. - A
gate insulation layer 50 may be interposed between thegate electrode layer 52 and the channel semiconductor layers 44 and thesemiconductor substrate 10. Thegate insulation layer 50 may have a shape enclosing at least a portion of a center of the channel semiconductor layers 44. Thegate electrode layer 52 may have a structure covering both lateral surfaces of the channel semiconductor layers 44 and the upper surfaces thereof. Further, thegate electrode layer 52 may enclose and surround the channel semiconductor layers 44 and may be buried in a self-aligning manner between theinsulation spacers 48, which face each other. -
FIG. 2A illustrates a perspective view of a semiconductor device having a multi-bridge-channel according to an embodiment of the present invention wherein a portion of theisolation layer 22 is removed so that a portion of an activation region may be exposed.FIG. 2B illustrates a perspective view of the semiconductor device having a multi-bridge-channel shown inFIG. 2A including thegate electrode layer 52 covering the channel semiconductor layers 44. - Referring to
FIGS. 2A and 2B , the activation layer protrudes from theisolation layer 22 a, a portion of which has been removed. The activation layer includes the channel semiconductor layers 44, the junction auxiliary layers 46, and the first and second semiconductor posts 32 and 34 separated by the channel semiconductor layers 44, as explained in connection withFIGS. 1A through 1C . Thegate electrode layer 52 covers both lateral surfaces of the channel semiconductor layers 44 and an upper surface thereof while exposing the junction auxiliary layers 46. A width of thegate electrode layer 52 is the same as an interval between the junction auxiliary layers 46. Accordingly, the junction auxiliary layers 46 and the channel semiconductor layers 44 between the first and second semiconductor posts 32 and 34 can be used for source/drain regions. In the present embodiment, areas of the source/drain regions are greatly extended so that electrical resistance can be reduced. -
FIGS. 3A through 14A illustrate perspective views of stages in a process for fabricating a semiconductor device having a multi-bridge-channel according to an embodiment of the present invention.FIGS. 3B through 14B illustrate cross-sectional views of stages in a process for fabricating a semiconductor device having a multi-bridge-channel according to an embodiment of the present invention taken along line A-A ofFIG. 3A . - Referring to
FIGS. 3A through 14B , awall 16 having a predetermined height from thesurface 12 of thesemiconductor substrate 10 made of single crystal silicon and extending in the first direction, i.e., the x-direction ofFIG. 1A , is formed. Thewall 16 is formed of thesemiconductor substrate 10 and may have a stripe shape. More specifically, by filling atrench 14 including thesurface 12 of thesemiconductor substrate 10 with an insulation material to form theisolation layer 22, thesemiconductor substrate 10 enclosed by theisolation layer 22 becomes thewall 16 of thesemiconductor substrate 10 having a predetermined height from thesurface 12 of thesemiconductor substrate 10. Thesurface 12 may be an etched surface of thesemiconductor substrate 10 that has been removed in order to form theisolation layer 22. - A variety of insulation material layers, e.g., an oxide layer and a nitride layer, may be used for the
isolation layer 22. For example, the present embodiment may use a high density plasma (HDP) oxide film. In the present invention, since a process for using an etching mask is associated with theisolation layer 22, a material for theisolation layer 22 is selected with consideration of an etching selection ratio with respect to an adjacent material. - Though a process for forming the
isolation layer 22 is not illustrated in detail, general technology may be used to form an isolation layer in a vicinity of a surface of a semiconductor substrate. More specifically, a pad oxide layer (not shown) and a nitride layer (not shown) are first formed on an upper surface of thesemiconductor substrate 10. A mask pattern consisting of a padoxide film pattern 18 and anitride film pattern 20 for defining anisolation layer 22 is formed by applying general photoetching technology using a photoresist layer. Thesemiconductor substrate 10 is then anisotropic dry-etched to a predetermined depth using the mask pattern to form thetrench 14 in a vicinity of thesurface 12 of thesemiconductor substrate 10. - Referring to
FIGS. 4A and 4B , after an insulation material made of oxides or nitrides fills thetrench 14, an upper surface thereof is planarized and the mask pattern is removed, so that theisolation layer 22 surrounding the lateral walls of thewall 16 of thesemiconductor substrate 10 is formed. - Referring to
FIGS. 5A and 5B , after theisolation layer 22 and thewall 16 defined by theisolation layer 22 are formed, aninsulation material layer 26 for a mask is formed on an upper surface of thewall 16 and theisolation layer 22. Though silicon nitride is exemplarily used for a material layer of theinsulation mask pattern 30 in the present embodiment, other appropriate materials may be used with consideration of an etching selection ratio with respect to adjacent material layers. A padoxide material layer 24 for a mask may additionally be formed under theinsulation material layer 26 for the mask. - Referring to
FIGS. 6A and 6B , aninsulation mask pattern 30 defining a space therein is formed using a photoetching process. Theinsulation mask pattern 30 extends in a second direction, which is perpendicular to the first direction, in which thewall 16 of thesemiconductor substrate 10 extends. Theinsulation mask pattern 30 may be used when forming the subsequent gate electrode layer using a damascene method. By controlling a size of the space defined by theinsulation mask pattern 30, it is possible to easily control an effective channel length of the gate electrode, as described below. The padoxide film pattern 28 having a same lateral wall profile as theinsulation mask pattern 30 can be formed under theinsulation mask pattern 30. Thewall 16, having an upper surface coplanar with an upper surface of theisolation layer 22, is exposed by the space defined by theinsulation mask pattern 30 and theisolation layer 22. - After an etch stop layer material layer (not shown) is deposited in a blanket manner on the upper surface of the
semiconductor substrate 10 including theinsulation mask pattern 30, theetch stop layer 36 may be formed using an isotropic dry-etching. A thickness of theetch stop layer 36 can be determined with consideration of the etching selection ratio. Theetch stop layer 36 covers lateral walls of theinsulation mask pattern 30 and the padoxide film pattern 28. Formation of theetch stop layer 36 may be omitted in some embodiments of the present invention. - Referring to
FIGS. 7A and 7B , using theetch stop layer 36 covering the lateral walls of theinsulation mask pattern 30 and thepad oxide layer 28 and theisolation layer 22 for etching masks, a portion of thewall 16 that is exposed between theetch stop layer 36 and theisolation layer 22 is etched, so that anopening 31 is formed. Portions of upper side portions of thewall 16 are spaced apart from each other by theopening 31, so that thewall 16 is divided into the first and second semiconductor posts 32 and 34, which are a plurality of semiconductor post types. A source region and a drain region are respectively formed in upper side portions of the first and second semiconductor posts 32 and 34. Since a depth of theopening 31 is directly associated with an area of the subsequently formed channel semiconductor layers 44 ofFIG. 2A , the depth is set according to a measure designed in advance. More specifically, as the depth of theopening 31 increases, an area of the channel semiconductor layers 44 is widened and as the depth decreases, the area of the channel semiconductor layer is narrowed. - Referring to
FIGS. 8A and 8B , after an insulation material layer is deposited on the upper side of thesemiconductor substrate 10, in which theopening 31 defined by theisolation layer 22 and the semiconductor posts 32 and 34 at a lower portion of theinsulation mask pattern 30 is formed, a front-anisotropic etching is performed, so thatinterim insulation spacers 38 are formed on lateral walls of theopening 31 and lateral walls of theetch stop layer 36. Theinterim insulation spacers 38 may be made of various materials such as oxides or nitrides. For example, when a nitride is used for theinterim insulation spacers 38, an oxide film may be further formed as theetch stop layer 36 between theinsulation mask pattern 30 and theinterim insulation spacers 38. Oxides may be used with consideration of an etching selection ratio with respect to thesemiconductor substrate 10 and theinsulation mask pattern 30. If theinterim insulation spacers 38 are an oxide, theetch stop layer 36 described in connection withFIG. 6A cannot be formed and is omitted. - Since a thickness of the
interim insulation spacers 38 together with the above-describedinsulation mask pattern 30 is a factor that controls an effective channel length of the gate electrode, which will be described below, it is important to precisely form the thickness according to a designed measure. Further, a thickness of theinterim insulation spacers 38 determines a width of the channel semiconductor layers 44, which will be described below. Since the widths of the channel semiconductor layers should be the same to have the same threshold voltage, the thickness of theinterim insulation spacers 38 at the respective lateral walls of theopening 31 may be constant. - Referring to
FIGS. 9A and 9B , asacrificial layer 40 is formed on the exposedsemiconductor substrate 10 between theinterim insulation spacers 38 to fill theopening 31. Thesacrificial layer 40 is not present in a final product of a semiconductor device, but is a material layer that can be temporarily used during a fabricating process. Thus, thesacrificial layer 40 may be provided in various ways. Thesacrificial layer 40 may be formed using a material film having a lattice constant similar to that of thesemiconductor substrate 10 and having an etching selection ratio with respect to thesemiconductor substrate 10. For example, when thesemiconductor substrate 10 is a single crystal silicon layer, thesacrificial layer 40 may be an epitaxial silicon germanium (SiGe) layer. If necessary, it is possible to remove surface defects of thesacrificial layer 40 using hydrogen annealing. - The
sacrificial layer 40 may be formed using a molecular beam epitaxy method. SiH4, SiH2Cl2, SiCl4 or Si2H6 gases may be used as a silicon source gas to grow thesacrificial layer 40. Alternatively, GeH4 gas may be used as a germanium source gas to grow thesacrificial layer 40. - However, if selective etching is possible for a silicon layer constituting the
semiconductor layer 10 and an oxide material layer constituting theinterim insulation spacers 38, which does not necessarily use the epitaxially grown material layer, thesacrificial layer 40 may also be formed using a method such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). For example, thesacrificial layer 40 may be also formed by performing an appropriate etching process after a polysilicon layer is deposited by CVD and thermally treated. - Since the
sacrificial layer 40 is defined by theinterim insulation spacers 38 having the same thickness, thesacrificial layer 40 maintains the same interval from the pair ofsemiconductor posts isolation layer 22. An upper surface of thesacrificial layer 40 may be coplanar with an upper surface of the pair ofsemiconductor posts - Referring to
FIGS. 10A and 10B , theinterim insulation spacers 38 are removed by wet-etching using theetch stop layer 36, theisolation layer 22, and thesacrificial layer 40 for etching masks. Resultantly, the pair ofsemiconductor posts isolation layer 22, and thesacrificial layer 40 are spaced apart by the same interval in the first and second directions. - Referring to
FIGS. 11A and 11B , asingle crystal layer 42 is epitaxially grown in a space vacated by theinterim insulation spacers 38. The present embodiment may form an epitaxial silicon layer with consideration of alignment with thesemiconductor substrate 10 made of single crystal silicon. SiH4, SiH2Cl2, SiCl4 or Si2H6 gases may be used for a silicon source gas to grow the silicon layer. - Referring to
FIGS. 12A and 12B , an upper surface of thesacrificial layer 40 is exposed by removing a portion of thesingle crystal layer 42 so that the remainingsingle crystal layer 42 may have a same height as thesacrificial layer 40. Resultantly, thesingle crystal layer 42, a portion of which has been removed, is divided into the pair of channel semiconductor layers 44 connected, in a form of a bridge, with the upper side portions of the pair ofsemiconductor posts auxiliary layers 46 perpendicular to the first direction, formed between the channel semiconductor layers 44 and contacting the pair ofsemiconductor posts insulation spacers 48 having the same thickness as the junction auxiliary layers 46, or having a shape of being rounded toward an upper portion thereof, are formed on the junction auxiliary layers 46. - Referring to
FIGS. 13A and 13B , outer sidewalls of the channel semiconductor layers 44 are exposed by etching theisolation layer 22 beyond the channel semiconductor layers 44 using thesacrificial layer 40, the channel semiconductor layers 44, and theinsulation spacers 48 for etching masks. Subsequently, thesemiconductor substrate 10 is exposed by removing thesacrificial layer 40. Alternatively, thesacrificial layer 40 may be first removed and then theisolation layer 22 outside of the channel semiconductor layers 44 can be removed. Thesacrificial layer 40 may also be removed using an etching solution including a mixed solution of H2O2, HF, and CH3COOH, and peracetic acid, and isotropic-dry etching. - Referring to
FIGS. 14A and 14B , thegate insulation layer 50 is formed on the resultant structure between theinsulation spacers 48 to surround the channel semiconductor layers 44. Thegate insulation layer 50 may be made of a thermal oxide film and an insulation film having a high dielectric constant, e.g., an oxide film or an ONO film. Subsequently, thegate electrode layer 52 is formed on thegate insulation layer 50. Thegate electrode layer 52 may be formed using a single layer or a complex layer selected from among amorphous polysilicon, doped polysilicon, poly-SiGe, and a conductive metal content material. The conductive metal content material may be made of at least one layer selected from among a metal such as tungsten and molybdenum and conductive metal nitride films such as a titanium nitride film, a tantalum nitride film, and a tungsten nitride film. - Advantageously, according to the semiconductor device having the multi-bridge-channel and the method for fabricating the same, the gate electrode layer is formed in a self-aligning manner, thereby preventing misalignment with respect to the channel semiconductor layer.
- Further, it is possible to form the channel semiconductor layer having the same threshold voltage using the interim insulation spacers having the same thickness.
- Exemplary embodiments of the present invention have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
Claims (20)
1-10. (canceled)
11. A method for fabricating a semiconductor device having a multi-bridge-channel, comprising:
forming a semiconductor wall having a predetermined height from a surface of a semiconductor substrate, the semiconductor wall extending in a first direction;
forming an isolation layer surrounding the semiconductor wall;
forming a pair of semiconductor posts facing and spaced apart from each other by removing a portion of the semiconductor wall;
forming a sacrificial layer between the pair of semiconductor posts and the isolation layer, the sacrificial layer being a same distance apart from each of the pair of semiconductor posts and the isolation layer;
epitaxially growing a single crystal layer on the sacrificial layer, lateral walls of the pair of semiconductor posts, and the isolation layer;
forming a pair of channel semiconductor layers connecting facing upper side portions of the pair of semiconductor posts and forming a pair of junction auxiliary layers between the pair of channel semiconductor layers to contact the pair of semiconductor posts by removing a portion of the single crystal layer so that a height of the single crystal layer and a height of the sacrificial layer are the same;
forming insulation spacers on the pair of junction auxiliary layers;
removing the sacrificial layer;
forming a gate insulation layer on and surrounding the pair of channel semiconductor layers between the insulation spacers; and
forming a gate electrode layer on the gate insulation layer between the insulation spacers.
12. The method as claimed in claim 11 , wherein forming the pair of semiconductor posts facing each other and spaced apart from each other by removing a portion of the semiconductor wall comprises:
forming an insulation mask pattern defining a space therein and extending in a second direction, which is perpendicular to the first direction, on both sides of the semiconductor wall; and
removing the portion of the semiconductor wall exposed by the space in the insulation mask pattern using the insulation mask pattern and the isolation layer for etching masks.
13. The method as claimed in claim 12 , further comprising forming an etch stop layer covering a lateral wall of the insulation mask pattern, after forming the insulation mask pattern.
14. The method as claimed in claim 11 , wherein the sacrificial layer is a silicon germanium (SiGe) epitaxial layer.
15. The method as claimed in claim 11 , wherein forming the sacrificial layer between the pair of semiconductor posts comprises:
forming an interim insulation spacer material layer covering lateral walls of the pair of semiconductor posts, a bottom of an opening formed in the semiconductor wall by the removal of the portion of the semiconductor wall, and a lateral wall of an insulation mask pattern defining a space therein and extending in a second direction, which is perpendicular to the first direction;
forming interim insulation spacers exposing the bottom of the opening formed in the semiconductor wall by performing anisotropic-dry etching on the interim insulation spacer material layer; and
epitaxially growing a sacrificial layer in an opening between the interim insulation spacers.
16. The method as claimed in claim 15 , wherein the interim insulation spacer material layer is a nitride film/oxide film or an oxide film.
17. The method as claimed in claim 15 , wherein a width of the interim insulation spacer is constant from a lower portion thereof to an upper portion thereof.
18. The method as claimed in claim 15 , wherein a length of the pair of channel semiconductor layers is determined by a width of the interim insulation spacers.
19. The method as claimed in claim 11 , further comprising removing the interim insulation spacers using a wet etching before epitaxially growing the single crystal layer between the pair of semiconductor posts and the isolation layer.
20. A method for fabricating a semiconductor device having a multi-bridge-channel, the method comprising:
forming a first semiconductor post protruding a first predetermined height from a surface of a semiconductor substrate and having a source region in an upper side portion thereof;
forming a second semiconductor post protruding a second predetermined height from the surface of the semiconductor substrate, the second semiconductor post facing the first semiconductor post and having a drain region in an upper side portion thereof;
forming a pair of channel semiconductor layers connecting the upper side portion of the first semiconductor post to the upper side portion of the second semiconductor post;
forming a gate insulation layer on the pair of channel semiconductor layers and the semiconductor substrate, the gate insulation layer surrounding at least a portion of the pair of channel semiconductor layers;
forming a gate electrode layer on the gate insulation layer to enclose at least a portion of a region between the pair of channel semiconductor layers; and
forming a pair of junction auxiliary layers formed between the pair of channel semiconductor layers, the pair of junction auxiliary layers contacting the gate electrode layer, the upper side portion of the first semiconductor post, and the upper side portion of the second semiconductor post, and having a same width as a width of the pair of channel semiconductor layers.
21. The method as claimed in claim 20 , wherein the first predetermined height and the second predetermined height are the same.
22. The method as claimed in claim 20 , wherein the surface of the semiconductor substrate is a bottom of a trench etched a predetermined depth from an upper surface of the semiconductor substrate.
23. The method as claimed in claim 20 , further comprising:
forming an insulation mask pattern on the first and second semiconductor posts; and
forming insulation spacers on facing lateral walls of the insulation mask pattern.
24. The method as claimed in claim 23 , wherein a width of the insulation spacers is the same as a width of the pair of junction auxiliary layers.
25. The method as claimed in claim 23 , wherein a width of the insulation spacers is constant from a lower portion thereof to an upper portion thereof.
26. The method as claimed in claim 20 , wherein an upper surface of the pair of channel semiconductor layers is coplanar with upper surfaces of the first and second semiconductor posts.
27. The method as claimed in claim 20 , wherein the pair of channel semiconductor layers connects both ends of the upper side portion of the first semiconductor post to both ends of the upper side portion of the second semiconductor post.
28. The method as claimed in claim 20 , wherein the gate electrode layer encloses both lateral walls and an upper surface of the pair of channel semiconductor layers and is self-aligned between the insulation spacers.
29. The method as claimed in claim 20 , wherein the pair of channel semiconductor layers and the pair of junction auxiliary layers are silicon epitaxial layers.
Priority Applications (1)
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US11/710,580 US20070161168A1 (en) | 2004-12-06 | 2007-02-26 | Method for fabricating a semiconductor device having a multi-bridge-channel |
Applications Claiming Priority (4)
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KR1020040101662A KR100630723B1 (en) | 2004-12-06 | 2004-12-06 | Semiconductor device having multibridge-channel and method of fabricating the same |
KR10-2004-0101662 | 2004-12-06 | ||
US11/285,300 US7187022B2 (en) | 2004-12-06 | 2005-11-23 | Semiconductor device having a multi-bridge-channel and method for fabricating the same |
US11/710,580 US20070161168A1 (en) | 2004-12-06 | 2007-02-26 | Method for fabricating a semiconductor device having a multi-bridge-channel |
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US11/285,300 Division US7187022B2 (en) | 2004-12-06 | 2005-11-23 | Semiconductor device having a multi-bridge-channel and method for fabricating the same |
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US11/710,580 Abandoned US20070161168A1 (en) | 2004-12-06 | 2007-02-26 | Method for fabricating a semiconductor device having a multi-bridge-channel |
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US11/285,300 Active US7187022B2 (en) | 2004-12-06 | 2005-11-23 | Semiconductor device having a multi-bridge-channel and method for fabricating the same |
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KR (1) | KR100630723B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11935790B2 (en) | 2020-09-04 | 2024-03-19 | Samsung Electronics Co., Ltd. | Field effect transistor and method of manufacturing the same |
Families Citing this family (5)
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KR100630723B1 (en) * | 2004-12-06 | 2006-10-02 | 삼성전자주식회사 | Semiconductor device having multibridge-channel and method of fabricating the same |
US20080012067A1 (en) * | 2006-07-14 | 2008-01-17 | Dongping Wu | Transistor and memory cell array and methods of making the same |
FR2905800A1 (en) * | 2006-09-11 | 2008-03-14 | St Microelectronics Crolles 2 | Multigate i.e. dual gate, fin-FET manufacturing method for computing equipment, involves forming wall i.e. spacer, that delimits cavity, in matrix layer, where wall has structural properties that are different from rest of matrix layer |
KR101835483B1 (en) | 2011-12-09 | 2018-03-08 | 삼성전자주식회사 | Multi-chip package and method of manufacturing the same |
US10790155B2 (en) * | 2018-06-27 | 2020-09-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing semiconductor devices |
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US6207511B1 (en) * | 1997-04-30 | 2001-03-27 | Texas Instruments Incorporated | Self-aligned trenched-channel lateral-current-flow transistor |
US6562665B1 (en) * | 2000-10-16 | 2003-05-13 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology |
US6800910B2 (en) * | 2002-09-30 | 2004-10-05 | Advanced Micro Devices, Inc. | FinFET device incorporating strained silicon in the channel region |
US7187022B2 (en) * | 2004-12-06 | 2007-03-06 | Samsung Electronics Co., Ltd. | Semiconductor device having a multi-bridge-channel and method for fabricating the same |
Family Cites Families (1)
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KR100521377B1 (en) | 2003-02-21 | 2005-10-12 | 삼성전자주식회사 | Method for forming fin field effect transistor |
-
2004
- 2004-12-06 KR KR1020040101662A patent/KR100630723B1/en active IP Right Grant
-
2005
- 2005-11-23 US US11/285,300 patent/US7187022B2/en active Active
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2007
- 2007-02-26 US US11/710,580 patent/US20070161168A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6207511B1 (en) * | 1997-04-30 | 2001-03-27 | Texas Instruments Incorporated | Self-aligned trenched-channel lateral-current-flow transistor |
US6562665B1 (en) * | 2000-10-16 | 2003-05-13 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology |
US6800910B2 (en) * | 2002-09-30 | 2004-10-05 | Advanced Micro Devices, Inc. | FinFET device incorporating strained silicon in the channel region |
US7187022B2 (en) * | 2004-12-06 | 2007-03-06 | Samsung Electronics Co., Ltd. | Semiconductor device having a multi-bridge-channel and method for fabricating the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US11935790B2 (en) | 2020-09-04 | 2024-03-19 | Samsung Electronics Co., Ltd. | Field effect transistor and method of manufacturing the same |
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US20060121687A1 (en) | 2006-06-08 |
US7187022B2 (en) | 2007-03-06 |
KR20060062725A (en) | 2006-06-12 |
KR100630723B1 (en) | 2006-10-02 |
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