US20070178712A1 - Planarization for Integrated Circuits - Google Patents

Planarization for Integrated Circuits Download PDF

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Publication number
US20070178712A1
US20070178712A1 US11/625,476 US62547607A US2007178712A1 US 20070178712 A1 US20070178712 A1 US 20070178712A1 US 62547607 A US62547607 A US 62547607A US 2007178712 A1 US2007178712 A1 US 2007178712A1
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United States
Prior art keywords
layer
pillar
planarization
integrated circuit
extrusion
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US11/625,476
Inventor
Michael Brenner
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Texas Instruments Inc
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Texas Instruments Inc
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Filing date
Publication date
Priority claimed from US10/113,008 external-priority patent/US20030186536A1/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to US11/625,476 priority Critical patent/US20070178712A1/en
Publication of US20070178712A1 publication Critical patent/US20070178712A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Definitions

  • This invention relates to fabrication of integrated circuits, and more particularly to a method for planarizing surfaces of integrated circuit layers.
  • a typical digital integrated circuit comprises a number to transistors and other electrical elements.
  • the integrated circuit chip is a sandwiched structure made up of the silicon substrate, dielectric layers, metal interconnects, devices and so on. The layers are formed by various deposition, photolithographic, and etching techniques.
  • Deposition means such as chemical vapor deposition or spin coating are conformal, which requires them to be subsequently planarized.
  • CMP chemical mechanical planarization
  • contact planarization involves the application of a malleable coating on the surface of a chip; the coating then is pressed against an optically clear, flat surface and cured with ultraviolet light. The coating may be left in place or removed, leaving the flat substrate.
  • One aspect of the invention is a method of planarizing a layer of an integrated circuit.
  • a liquid film is applied over the layer, using extrusion coating techniques.
  • the layer itself may be applied as a liquid film, using extrusion coating techniques.
  • An advantage of the invention is that the extrusion coating is “self-planarizing”. No subsequent planarization steps are needed. As a result, clean-up steps are eliminated and defects are reduced.
  • FIG. 1 illustrates the formation of pillar-like structures over a metal lead of an integrated circuit.
  • FIG. 2 illustrates the application of an insulating layer over the pillar-like structure.
  • FIG. 3 illustrates the removal of a portion of the insulating layer to expose the top of the pillar-like structure.
  • FIG. 4 illustrates removal of the pillar-like structure.
  • FIG. 5 illustrates formation of a conductive line.
  • planarization is performed for an insulating layer, through which there is a via.
  • the layer in question is applied using extrusion techniques.
  • a layer of another material could be planarized by applying an extrusion coating on the surface of that layer.
  • Extrusion coating is meant here in its conventional sense.
  • the extruder is mounted above the substrate, and liquid is forced through a die onto the substrate.
  • the liquid is fed into an extruder, and pumped to the substrate.
  • granules of solid form of the liquid are fed into an extruder, where they are melted and homogenized before being pumped through the die.
  • the coating is a hot melt liquid applied at an elevated temperature.
  • the extruder is motion relative to the substrate, thinner coatings can be produced where the line speed is faster than the speed of the extrusion.
  • FIG. 1 illustrates the formation of a pillar 21 over a metal line 22 , which has already been patterned on a semiconductor substrate 23 .
  • Pillar 21 may be formed from photoresist, using conventional lithographic techniques, including patterning and etching.
  • the material used to form pillar 21 is typically photoresist, but may be any “sacrificial” material, that may subsequently be removed as explained below. Pillar 21 need not be column-shaped, but rather may be any structure having a shape such that when sacrificially removed, will form a via.
  • FIG. 2 illustrates the application of an insulating layer 31 .
  • insulating layer 31 encapsulates pillar 21 .
  • Insulating layer 31 may be any material suitable for an interlevel dielectric layer of an integrated circuit.
  • Extrusion coating is especially described for applying layer 31 because of its ability to provide a planarized surface.
  • other deposition methods such as chemical vapor deposition or spin coating, are conformal and require an etch back or chemical mechanical planarization to achieve a desired planar surface.
  • the desired material may be applied in the form of a solution gel or liquid film.
  • application of the film may be followed by other processing, such as thermal or photochemical steps, in which the uniformity achieved through deposition is maintained. During these subsequent process steps, the chemical or physical structures of the film or underlying layers or interfaces may change, that is, these steps have a curing effect.
  • FIG. 3 illustrates an etch back of insulating layer 31 to expose pillar 21 .
  • the etch may be either a wet or dry etch, such as a wet chemical or dry plasma etch.
  • the etching is performed for a duration sufficient to expose at least the top surface of pillar 21 .
  • FIG. 4 illustrates the removal of pillar 21 .
  • This may be achieved with a relatively gentle etch, such as gentle plasma etch.
  • This type of plasma etch is commonly called an ash process, but other selective isotropic etches may be used, if suitable for removing the material from which pillar 21 is made may be used.
  • the avoidance of anisotropic etching eliminates etch residue issues.

Abstract

A method of planarizing a layer of an integrated circuit. In one embodiment, a liquid film is applied over the layer, using extrusion coating techniques. In another embodiment, the layer itself may be applied as a liquid film, using extrusion techniques.

Description

    RELATED APPLICATION
  • This application is a divisional of application Ser. No. 10/923,435 filed Aug. 20, 2004 which is a divisional of application Ser. No. 10/195,678, filed Jul. 15, 2002, now U.S. Pat. No. 7,060,633 which is a continuation-in-part application of application Ser. No. 10/113,008 filed Mar. 29, 2002 and entitled, “Via Formation in Integrated Circuits By Use of Sacrificial Structures”, now abandoned.
    • TECHNICAL FIELD OF THE INVENTION
  • This invention relates to fabrication of integrated circuits, and more particularly to a method for planarizing surfaces of integrated circuit layers.
    • BACKGROUND OF THE INVENTION
  • A typical digital integrated circuit comprises a number to transistors and other electrical elements. The integrated circuit chip is a sandwiched structure made up of the silicon substrate, dielectric layers, metal interconnects, devices and so on. The layers are formed by various deposition, photolithographic, and etching techniques.
  • Advances in integrated circuit capacity and complexity depend on increases in the density of semiconductor devices and layering of metal circuitry. Each layer must be planarized prior to the next lithography step to achieve desired device performance. Deposition means such as chemical vapor deposition or spin coating are conformal, which requires them to be subsequently planarized.
  • To ensure flatness, manufactures typically use chemical mechanical planarization (CMP), which is essentially a chemical polishing process. Another approach to planarization is contact planarization, which involves the application of a malleable coating on the surface of a chip; the coating then is pressed against an optically clear, flat surface and cured with ultraviolet light. The coating may be left in place or removed, leaving the flat substrate.
    • SUMMARY OF THE INVENTION
  • One aspect of the invention is a method of planarizing a layer of an integrated circuit. A liquid film is applied over the layer, using extrusion coating techniques. In another embodiment, the layer itself may be applied as a liquid film, using extrusion coating techniques.
  • An advantage of the invention is that the extrusion coating is “self-planarizing”. No subsequent planarization steps are needed. As a result, clean-up steps are eliminated and defects are reduced.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates the formation of pillar-like structures over a metal lead of an integrated circuit.
  • FIG. 2 illustrates the application of an insulating layer over the pillar-like structure.
  • FIG. 3 illustrates the removal of a portion of the insulating layer to expose the top of the pillar-like structure.
  • FIG. 4 illustrates removal of the pillar-like structure.
  • FIG. 5 illustrates formation of a conductive line.
    • DETAILED DESCRIPTION OF THE INVENTION
  • The following description is directed to a method of planarizing one or more layers of an integrated circuit. For purposes of example, the planarization is performed for an insulating layer, through which there is a via. In the example below, the layer in question is applied using extrusion techniques. In other embodiments, a layer of another material could be planarized by applying an extrusion coating on the surface of that layer.
  • “Extrusion” coating is meant here in its conventional sense. The extruder is mounted above the substrate, and liquid is forced through a die onto the substrate. In the extrusion coating of a hot melt liquid, the liquid is fed into an extruder, and pumped to the substrate. Alternatively, granules of solid form of the liquid are fed into an extruder, where they are melted and homogenized before being pumped through the die. Typically, then, the coating is a hot melt liquid applied at an elevated temperature. The extruder is motion relative to the substrate, thinner coatings can be produced where the line speed is faster than the speed of the extrusion.
  • FIG. 1 illustrates the formation of a pillar 21 over a metal line 22, which has already been patterned on a semiconductor substrate 23. Pillar 21 may be formed from photoresist, using conventional lithographic techniques, including patterning and etching. The material used to form pillar 21 is typically photoresist, but may be any “sacrificial” material, that may subsequently be removed as explained below. Pillar 21 need not be column-shaped, but rather may be any structure having a shape such that when sacrificially removed, will form a via.
  • FIG. 2 illustrates the application of an insulating layer 31. As illustrated, insulating layer 31 encapsulates pillar 21. Insulating layer 31 may be any material suitable for an interlevel dielectric layer of an integrated circuit.
  • Extrusion coating is especially described for applying layer 31 because of its ability to provide a planarized surface. In contrast, other deposition methods, such as chemical vapor deposition or spin coating, are conformal and require an etch back or chemical mechanical planarization to achieve a desired planar surface.
  • For extrusion coating, the desired material may be applied in the form of a solution gel or liquid film. For liquid films applied by extrusion coating, application of the film may be followed by other processing, such as thermal or photochemical steps, in which the uniformity achieved through deposition is maintained. During these subsequent process steps, the chemical or physical structures of the film or underlying layers or interfaces may change, that is, these steps have a curing effect.
  • Experimental testing with extrusion coating has indicated that surface features may be coated and planarized to less than 250 angstroms. The same features covered by a spin coating typically result in nonplanarities of approximately 1800 angstroms.
  • FIG. 3 illustrates an etch back of insulating layer 31 to expose pillar 21. The etch may be either a wet or dry etch, such as a wet chemical or dry plasma etch. The etching is performed for a duration sufficient to expose at least the top surface of pillar 21.
  • FIG. 4 illustrates the removal of pillar 21. This may be achieved with a relatively gentle etch, such as gentle plasma etch. This type of plasma etch is commonly called an ash process, but other selective isotropic etches may be used, if suitable for removing the material from which pillar 21 is made may be used. The avoidance of anisotropic etching eliminates etch residue issues. After the sacrificial structure, that is, pillar 21, has been removed, a via 51 is formed in layer 31 and extends to metal line 22. As shown in FIG. 5, a conductive line 61 can be formed over via 51 and layer 31.
    • OTHER EMBODIMENTS
  • Although the present invention has been described in detail, it should be understood that various changes, substitutions, and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (5)

1. A method of providing a planarized layer of an integrated circuit, comprising:
depositing a layer as a liquid film by means of extrusion;
forming a recess in the layer; and
forming a conductor within the recess in the layer.
2. The method of claim 1 and further comprising curing the liquid film by performing a thermal step.
3. The method of claim 1 and further comprising curing the liquid by performing a photochemical step.
4. The method of claim 1 wherein the substantially planar surface is planarized to less than 250 angstroms.
5. The method of claim 1 wherein forming a recess in the layer comprises removing a sacrificial material.
US11/625,476 2002-03-29 2007-01-22 Planarization for Integrated Circuits Abandoned US20070178712A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/625,476 US20070178712A1 (en) 2002-03-29 2007-01-22 Planarization for Integrated Circuits

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/113,008 US20030186536A1 (en) 2002-03-29 2002-03-29 Via formation in integrated circuits by use of sacrificial structures
US10/195,678 US7060633B2 (en) 2002-03-29 2002-07-15 Planarization for integrated circuits
US10/923,435 US7166546B2 (en) 2002-03-29 2004-08-20 Planarization for integrated circuits
US11/625,476 US20070178712A1 (en) 2002-03-29 2007-01-22 Planarization for Integrated Circuits

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/923,435 Division US7166546B2 (en) 2002-03-29 2004-08-20 Planarization for integrated circuits

Publications (1)

Publication Number Publication Date
US20070178712A1 true US20070178712A1 (en) 2007-08-02

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US10/195,678 Expired - Lifetime US7060633B2 (en) 2002-03-29 2002-07-15 Planarization for integrated circuits
US10/923,435 Expired - Lifetime US7166546B2 (en) 2002-03-29 2004-08-20 Planarization for integrated circuits
US11/625,476 Abandoned US20070178712A1 (en) 2002-03-29 2007-01-22 Planarization for Integrated Circuits

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US10/195,678 Expired - Lifetime US7060633B2 (en) 2002-03-29 2002-07-15 Planarization for integrated circuits
US10/923,435 Expired - Lifetime US7166546B2 (en) 2002-03-29 2004-08-20 Planarization for integrated circuits

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7060633B2 (en) * 2002-03-29 2006-06-13 Texas Instruments Incorporated Planarization for integrated circuits
WO2004017439A2 (en) * 2002-07-29 2004-02-26 Siemens Aktiengesellschaft Electronic component comprising predominantly organic functional materials and method for the production thereof
JP4052955B2 (en) * 2003-02-06 2008-02-27 Ｎｅｃエレクトロニクス株式会社 Manufacturing method of semiconductor device
US7790231B2 (en) 2003-07-10 2010-09-07 Brewer Science Inc. Automated process and apparatus for planarization of topographical surfaces
US7775785B2 (en) * 2006-12-20 2010-08-17 Brewer Science Inc. Contact planarization apparatus
US9218976B2 (en) * 2013-08-13 2015-12-22 Globalfoundries Inc. Fully silicided gate formed according to the gate-first HKMG approach

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US4514583A (en) * 1983-11-07 1985-04-30 Energy Conversion Devices, Inc. Substrate for photovoltaic devices
US5516721A (en) * 1993-12-23 1996-05-14 International Business Machines Corporation Isolation structure using liquid phase oxide deposition
US5861331A (en) * 1998-04-20 1999-01-19 United Microelectronics Corp. Method for fabricating capacitors of a dynamic random access memory
US5891795A (en) * 1996-03-18 1999-04-06 Motorola, Inc. High density interconnect substrate
US5945254A (en) * 1996-12-18 1999-08-31 The Boeing Company Fabrication process for multichip modules using low temperature bake and cure
US5985752A (en) * 1997-10-08 1999-11-16 Winbond Electronics Corp. Self-aligned via structure and method of manufacture
US6033977A (en) * 1997-06-30 2000-03-07 Siemens Aktiengesellschaft Dual damascene structure
US6159611A (en) * 1997-09-11 2000-12-12 E. I. Du Pont De Nemours And Company High dielectric constant flexible polyimide film and process of preparation
US6191053B1 (en) * 1997-06-16 2001-02-20 Silicon Valley Group, Inc. High efficiency photoresist coating
US20020035961A1 (en) * 2000-06-21 2002-03-28 Seiko Epson Corporation Ceramic film and method of manufacturing the same, semiconductor device and piezoelectric device
US20030186536A1 (en) * 2002-03-29 2003-10-02 Brenner Michael F. Via formation in integrated circuits by use of sacrificial structures
US7060633B2 (en) * 2002-03-29 2006-06-13 Texas Instruments Incorporated Planarization for integrated circuits

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US2003A (en) * 1841-03-12 Improvement in horizontal windivhlls

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3597080A (en) * 1968-10-25 1971-08-03 Grace W R & Co Apparatus for preparing a printing plate from a photosensitive composition
US4514583A (en) * 1983-11-07 1985-04-30 Energy Conversion Devices, Inc. Substrate for photovoltaic devices
US5516721A (en) * 1993-12-23 1996-05-14 International Business Machines Corporation Isolation structure using liquid phase oxide deposition
US5891795A (en) * 1996-03-18 1999-04-06 Motorola, Inc. High density interconnect substrate
US5945254A (en) * 1996-12-18 1999-08-31 The Boeing Company Fabrication process for multichip modules using low temperature bake and cure
US6191053B1 (en) * 1997-06-16 2001-02-20 Silicon Valley Group, Inc. High efficiency photoresist coating
US6033977A (en) * 1997-06-30 2000-03-07 Siemens Aktiengesellschaft Dual damascene structure
US6159611A (en) * 1997-09-11 2000-12-12 E. I. Du Pont De Nemours And Company High dielectric constant flexible polyimide film and process of preparation
US5985752A (en) * 1997-10-08 1999-11-16 Winbond Electronics Corp. Self-aligned via structure and method of manufacture
US5861331A (en) * 1998-04-20 1999-01-19 United Microelectronics Corp. Method for fabricating capacitors of a dynamic random access memory
US20020035961A1 (en) * 2000-06-21 2002-03-28 Seiko Epson Corporation Ceramic film and method of manufacturing the same, semiconductor device and piezoelectric device
US20030186536A1 (en) * 2002-03-29 2003-10-02 Brenner Michael F. Via formation in integrated circuits by use of sacrificial structures
US7060633B2 (en) * 2002-03-29 2006-06-13 Texas Instruments Incorporated Planarization for integrated circuits

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US20030186558A1 (en) 2003-10-02
US7060633B2 (en) 2006-06-13
US7166546B2 (en) 2007-01-23
US20050020046A1 (en) 2005-01-27

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