|Número de publicación||US20070252127 A1|
|Tipo de publicación||Solicitud|
|Número de solicitud||US 11/394,263|
|Fecha de publicación||1 Nov 2007|
|Fecha de presentación||30 Mar 2006|
|Fecha de prioridad||30 Mar 2006|
|También publicado como||CN101047230A, CN101047230B, US7923712, US20100001253|
|Número de publicación||11394263, 394263, US 2007/0252127 A1, US 2007/252127 A1, US 20070252127 A1, US 20070252127A1, US 2007252127 A1, US 2007252127A1, US-A1-20070252127, US-A1-2007252127, US2007/0252127A1, US2007/252127A1, US20070252127 A1, US20070252127A1, US2007252127 A1, US2007252127A1|
|Inventores||John Arnold, Lawrence Clevenger, Timothy Dalton, Michael Gaidis, Louis Hsu, Carl Radens, Keith Wong, Chih-Chao Yang|
|Cesionario original||Arnold John C, Clevenger Lawrence A, Dalton Timothy J, Gaidis Michael C, Hsu Louis L, Radens Carl J, Wong Keith K H, Chih-Chao Yang|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citada por (23), Clasificaciones (11), Eventos legales (1)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
The present invention relates to memory devices, and more particularly a Phase Change Memory (PCM) cell structure and methods of making and using the same.
Recently nonvolatile chalcogenide Random Access Memory (RAM) devices, made of the germanium-antimony-tellurium (Ge2Sb2Te5) chalcogenide material, have been regarded as the most promising next-generation memory devices. The term “chalcogen” refers to the Group VI elements of the periodic table; and the term “chalcogenide” refers to alloys containing at least one of these elements, e.g. the alloy of germanium, antimony, and tellurium, etc. Chalcogenide materials have been used in PCM devices, especially in both rewritable Compact Disk (CD) and Digital Video Disk or Digital Versatile Disc (DVD) devices. This kind of memory when introduced into semiconductor chips has many advantages over others in areas, e.g. scalability, high sensing margin, low energy consumption, and cycling endurance. In a common design for chalcogenide memory cells, the data is stored in a flat chalcogenide layer that can be deposited near the end of the CMOS interconnect process making it ideal for embedded applications.
A chalcogenide memory element can be programmed and reprogrammed into high/low resistance states. In short, when a chalcogenide memory element is in the amorphous phase (or so called RESET state) it has high resistance; when it is in the crystalline phase, it shows low resistance (or called SET state). The resistance ratio between two SET and RESET states can be greater than 1,000 times, which provides high sensing margins.
Adequate energy must be driven into the device to change state from the “RESET” state to the “SET” state in the dynamic ON state for a device in the RESET state.
On the other hand,
Because the rate of Joule heating of the phase change material during the RESET and SET cycles is determined largely by current density, reducing the contact area between the phase change material and the adjacent electrode is sufficient to reduce the switched volume. For example, during the RESET cycle, it is not necessary to melt the entire volume of phase change material if the current density, and thus Joule heating rate, and thus material temperature, is high enough to melt the material near one of the electrodes. Once enough material has been amorphized to span the breadth of the current path through the cell, the overall resistance of the cell will be high. Similarly, during the SET cycle, the overall cell resistance will fall once a sufficiently broad path of crystalline material is formed. In both cases, adjacent material may be left in the opposite state without affecting the overall cell resistance significantly.
To read a chalcogenide memory device, a “READ” voltage is applied on the device; thus permitting detection of the current difference resulting from the different device resistance. The read voltage must be lower than the threshold voltage (e.g. 1.2V) to avoid changing the state of the material.
Currently, chalcogenide devices are used in reversible (RW) optical information storage devices, e.g. CD-RW and DVD-RW disks. Compounds, e.g. a germanium-antimony-tellurium material (Ge2Sb2Te5), can change phase from amorphous to crystalline in about 50 ns after proper exposure to radiation from a laser beam. However, the crystallization speed of a germanium-antimony-tellurium material tends to decrease with thinner films. To avoid this, it is suggested that tin be doped into a Ge—Sb—Te compound to form a Ge—Sb—Sn—Te compound and increase the crystallization speed.
TABLE I Possible Phase Change Materials Binary Ternary Quaternary GaSb Ge2Sb2Te5 AgInSbTe InSb InSbTe (GeSn)SbTe InSe GeSeTe GeSb(SeTe) Sb2Te3 SnSb2Te4 Te81Ge15Sb2S2 GeTe InSbGe
A simplified cell structure of chalcogenide PCM type of memory comprises a conventional MOS FET transfer transistor connected to a memory cell. One source/Drain (S/D) junction of the transistor is connected to a metal wire called a bit-line. The other S/D junction of the MOS FET is connected to the memory element. The gate electrode of the transistor is connected to another metal line called the word-line. The PCM element comprises a sandwich of top electrode, a bistable dielectric, and a bottom electrode. Both electrodes are made of metal or refractory metal, while the bistable dielectric is a thin layer of a chalcogenide material.
As to the cycling endurance of a chalcogenide memory element, it has been reported by Lai et al. that one can conduct more than 1E12 set/reset cycles, which is much higher than a conventional Flash memory (about 1E5). The report was made by Stefan Lai et al. in “Current Status of the Phase Change Memory and its Future” Electron Devices Meeting, 2003. IEDM 2003 Technical Digest. IEEE International 8-10 Dec. 2003, Pages: 10.1.1-10.1.4
Application of this class of PCM to a practical multi-bit memory device requires two additional characteristics beyond those discussed above as follows:
If the switched volume is too large relative to the technology node at which the transistors are fabricated, the power required to switch that material (particularly during the Reset cycle) will be higher than the transistors connected to the PCM device can support reliably. Simulations and other studies have suggested that appropriate dimensions for the switched material will be on the order of one half (½) or one quarter (¼) of the nominal technology node. Thus, for the 90 nm node, the memory cell will need to have characteristic dimensions in the 30-50 nm range. This is well below the lithographic capabilities defined for that technology node; and because the capacity for power delivery scales down with the technology node, it will be required that the PCM device will be sub-lithographic at all nodes.
Furthermore, accurate control of the memory cell dimensions is essential. If the dimensions vary excessively, on an all-cells/all-die/all-days basis, there is a risk that the current applied during the Reset pulse may actually set the material in some cells, and vice-versa.
Thus, the principal challenge in fabricating practical memory devices is in producing and controlling dimensions well below the norms for standard photolithography.
This invention is one of several approaches designed to reduce the effective dimensions of the memory cell through additional processing after lithography. Other approaches include “trimming” photoresist blocks prior to transferring their dimensions into phase change materials, depositing phase change material in holes or trenches whose sidewalls have been intentionally tapered to provide a smaller contact area at the bottom of the hole than was defined by lithography at the top, and depositing dielectric liners inside conventionally-defined holes to reduce their dimensions prior to filling them with phase change material.
Several prior art PCM cell designs have been reported. In the Lai et al. paper described above, “Current Status of the Phase Change Memory and its Future,” FIGS. 7A/7B therein show configurations in which use is made of edge contact to reduce switching current. The PCM device includes a top electrode contact TEC, a top electrode TE, a chalcogenide PCM (GeSbT) layer GST, a bottom electrode BE, and a bottom electrode contact BEC. The programming current is significantly reduced by using an edge instead of conventional top and bottom electrode contact. The programmable volume in diagram 7B is much smaller than that of the conventional design.
Another prior art approach is embodied in U.S. Pat. No. 6,764,894 B2, of Lowrey entitled “Elevated Pore Phase-Change Memory.” As shown in
U.S. Pat. No. 6,800,563 of Xu entitled “Forming Tapered Lower Electrode Phase-Change Memories” shows in
U.S. Pat. No. 6,649,928, of Dennison entitled “Method to Selectively Remove One Side of a Conductive Bottom Electrode of a Phase-Change Memory Cell and Structure Obtained Thereby,” relates to a PCM device including a lower electrode disposed in a recess of a first dielectric. The lower electrode comprises a first side and a second side. The first side communicates to a volume of phase change material. The second side has a length that is less than the first side. A second dielectric, which may overlie the lower electrode, has a shape that is substantially similar to the lower electrode. The method of the Dennison invention includes providing a lower electrode material in a recess and removing at least a portion of the second side.
U.S. Pat. No. 6,791,102 of Johnson entitled “Phase Change Memory” describes a PCM device with phase change material having a bottom portion, a lateral portion, and a top portion. The PCM device may include a first electrode material contacting the bottom portion and the lateral portion of the phase change material and a second electrode material contacting the top portion of the phase change material. A first conductive material is cup-shaped and surrounds the bottom portion and the lateral portion of the phase change material. A lower electrode which is cup shaped, circular, or ring-shaped may be formed surrounding and contacting the lateral and bottom surfaces of the PCM memory material.
U.S. Pat. No. 6,815,704 of Chen entitled “Phase Change Memory Device Employing Thermally Insulating Voids” describes a PCM device, and method of making the same, that includes contact holes formed in insulation material that extend down to and expose source regions for adjacent FET transistors. Lower electrodes are disposed in the holes with surfaces defining openings narrowed along a depth of the opening by spacers. A layer of phase change material is disposed along the spacer material surfaces and along the lower electrodes. Upper electrodes are formed in the openings and on the phase change material layer. Voids are formed in the spacer material to impede heat from the phase change material from conducting through the insulation material. For each contact hole, the upper electrode and phase change material layer form an electrical current path that narrows as the current path approaches the lower electrode. The electrical current pulse flowing through the upper electrode generates heat, concentrated in the lower portion thereof, where current density is greatest. The narrow current path of the upper electrode produces a maximum current density and maximum heat generation, adjacent to the memory material to be programmed, minimizing the amplitude and duration of electrical programming for the PCM device. The spacers surrounding the heating electrode increase the distance and thermal isolation between heating electrodes and programming material layers from adjacent cells. An indentation sharpens the tip of the upper electrode lower portion, focusing heat generation at the chalcogenide material disposed directly between the tip and the lower electrode. In one embodiment, voids isolate the memory cells thermally.
U.S. Patent Application No. 2004/0113135 by Wicker entitled “Shunted Phase Change Memory” teaches that by using a resistive-film shunt to carry a shunting current around the amorphous phase change material the snapback exhibited when transitioning from the reset state or amorphous phase of a phase change material, may be largely reduced or eliminated. The resistance from the resistive-film shunt may be significantly higher than the set resistance of the memory element so that the phase change resistance difference is detectable. The resistive-film shunt may be sufficiently resistive that it heats the phase change material and causes the appropriate phase transitions without requiring a dielectric breakdown of the phase change material. The resistance of the resistive-film shunt may be low enough so that when voltages are present which approach the threshold voltage of the memory element, the resistive-film shunt heats significantly. In other words, the resistance of the resistive-film shunt may be higher than the set resistance and lower than the reset resistance of the memory.
In a first aspect of the invention, an apparatus is provided. A first embodiment of the apparatus comprises a memory cell with a reduction in switched volume through distribution of the phase change material in a thin layer which lines a conventionally-defined hole with either a round configuration or an alternative convenient shape.
Because effective heating of the phase change material requires only a high current density, reducing the contact area between the phase change material and one of the electrodes is sufficient to manage the power requirements. Thus, for example, good performance can be obtained from a long, narrow cylinder of phase change material, because the cross-sectional area is small even if the length, and therefore total volume of material, is large. Similarly, a conical or pyramidal structure can form an efficient PCM cell if the contact area between one electrode and the phase change material is small.
In accordance with this invention, the contact area between the phase change material and one electrode (typically the “upper” electrode) is made small by confining the phase change material to the outer perimeter of a feature of some convenient shape (typically but not necessarily cylindrical). The remainder of the feature cross-section is occupied by a dielectric material.
If, for example, the feature is a cylinder of diameter d and the adjacent electrode completely spans the end of the cylinder, the contact area between electrode and phase change material will be given by πdt, where t is the thickness of the phase change material as measured perpendicular to the wall of the feature. Because t is typically controlled by film deposition rather than lithography, t can be made much smaller than d and therefore the contact area can be much smaller than the π(d/2)2 which a solid cylinder of phase change material would have. Similar arguments apply for non-cylindrical features which may be of square, elliptical, star shaped, or other alternative configurations.
In accordance with an aspect of this invention, a phase change memory cell structure comprises a phase change element, and a thin film electrode having a periphery. The phase change element is electrically connected to at least a portion of the periphery of the thin film electrode.
In accordance with another aspect of this invention a method of forming a phase change memory cell structure comprises forming a thin film electrode having a periphery, and forming a phase change element over said periphery of said thin film electrode. The phase change element is electrically connected to at least a portion of the periphery of the thin film electrode.
FIGS. 9A′ and 9B′ show plan views and FIGS. 10A′ and 10B′ show corresponding cross-sectional views taken along line B-B′ in FIGS. 9A′ and 9B′ of an alternative PCM cell structure in accordance with this invention being manufactured employing an alternative process illustrated by the flow chart shown in
The present invention provides an improved Phase Change Memory (PCM) cell structure. By reducing the contact area between the phase change material of the PCM cell and one of the electrodes connected thereto, the resulting high current density can induce the necessary heating and phase changes within the PCM effectively with relatively low current (and, thus, low operating power).
Prior art structures often attempt to realize this method of operating power reduction, but are hampered by complex integration schemes and designs that can result in poor uniformity across arrays of the memory elements. Uniformity is necessary to ensure each element can be switched with the same characteristic current pulse, and, although less difficult with PCM, to ensure that each element's readout resistance is in a desired range for a “high” state and a “low” state—without the two states overlapping. Complex integration schemes are undesirable because they are expensive, and offer greater chance of yield loss. This invention provides an elegant means of creating a high-current-density structure with extremely repeatable and uniform characteristics, and with a minimum of process steps to reduce complexity and yield loss.
Step A is an early stage of the process illustrated by the flow charts of
In step A, referring to
In accordance with conventional semiconductor electronic devices, underlayer structures including conventional microelectronics devices and multilevel interconnect structures may be included in the substrate 10 prior to commencing the process of this invention.
In summary, the via 30 is embedded in ILD insulator layer 20 by employing a damascene process which includes anisotropic RIE masked by photoresist mask 22 with window 22W therethrough forming via hole 24 as shown in
FIGS. 7A/7B show plan and cross-sectional views of the structure of FIGS. 6A/6B after deposition of a blanket second dielectric insulator layer 65 composed of a material, e.g. SiO2, SiN, BN, SiC, SiCH, or low-k material, which is deposited and planarized to the level of the top surface of lower conductor liner layer 60L. Insulator 65 may be planarized by CMP, or by a dry etching process, e.g. RIE. The excess portion of the second dielectric insulator layer 65 above the top surface of first dielectric insulator layer 40 is removed from the surface of the device 8 but remains filling the pattern hole 50H.
FIGS. 9A′ and 9B′ show plan and cross-sectional views of the structure of
In other words, unwanted portions of the lower conductor liner layer 60L are removed concomitantly with the patterning of the film of phase change material layer 70F and the upper electrode 80 as shown in FIGS. 10A′/10B′. In this case, the resulting structure will have a thin film of liner 60L beneath the PCM element 70E and thus an electrical connection 85 is provided between liner and the phase change material in the PCM element 70E.
The liner can be advantageously used to improve readout uniformity by limiting the high-resistance excursion of the cell as it is switched to that state. For example, if the GST resistance values are 100 Ohms for the low resistance state and 1 MegOhm for the high resistance state, it may be beneficial to shunt the 1 MegOhm resistance with a 1 kOhm liner film so that readout electronics can more easily handle the difference between the two states, and so that it is easier to deliver current for heating the element to switch it back to a low resistance state. These advantages were enumerated previously in the Wicker U.S. Patent Application No. 2004/0113135.
The use of such an underlying liner film in this device can help mediate the resistance change to an opportune range of values. It can also assist with bringing the cell resistance into a manageable range for writing (e.g. without requiring high voltage drivers to pass sufficient power into an device such as a 1 MOhm device.) In addition, it can make device readout resistances more uniform. As the current will still be crowded into the thin annular liner region, sufficient local heating will take place to cause the cell to switch state even for reasonably low drive currents.
For either of the devices shown in FIGS. 10A/10B AND 10A′/10B′, a further reduction in the contact area between the annular electrode and the phase change material may be accomplished by patterning the PCM element 70E and upper electrode 80 in the horizontal dimension perpendicular to the plane of the cross-sectional diagram in
An alternative embodiment for the inventive structure is shown in
Step BA is an early stage of an alternative embodiment of the inventive structure and process of
In step BA, at first an interlevel dielectric (ILD) insulator layer 120 having a top surface 120T, which is preferably thicker than layer 20 in
Steps BC and BD
At the point in the process shown in
Electrode 180E can be a jumper (W, TiN, Ta, TaN) to connect between the phase change material 70 and a nearby high-current wire. Alternatively, electrode 180E can be the high-current wire itself (e.g. Damascene copper.) The latter option is enabled by previous patterning of the phase change material.
As in the case of the first embodiment described earlier, this alternative embodiment also supports further reduction of contact area via patterning of the phase change element 70 and upper electrode 180E in the other horizontal dimension.
The foregoing description discloses only exemplary embodiments of the invention. Modifications of the above disclosed apparatus and methods which fall within the scope of the invention will be readily apparent to those of ordinary skill in the art. While this invention has been described in terms of the above specific exemplary embodiment(s), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims, i.e. changes can be made in form and detail, without departing from the spirit and scope of the invention. Accordingly, while the present invention has been disclosed in connection with exemplary embodiments thereof, it should be understood that changes can be made to provide other embodiments which may fall within the spirit and scope of the invention and all such changes come within the purview of the present invention and the invention encompasses the subject matter defined by the following claims.
|Patente citante||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US7598113 *||30 Jun 2006||6 Oct 2009||Industrial Technology Research Institute||Phase change memory device and fabricating method therefor|
|US7619311 *||31 Ene 2008||17 Nov 2009||Macronix International Co., Ltd.||Memory cell device with coplanar electrode surface and method|
|US7868314 *||26 Ago 2009||11 Ene 2011||Industrial Technology Research Institute||Phase change memory device and fabricating method therefor|
|US7883931||6 Feb 2008||8 Feb 2011||Micron Technology, Inc.||Methods of forming memory cells, and methods of forming programmed memory cells|
|US7894254||15 Jul 2009||22 Feb 2011||Macronix International Co., Ltd.||Refresh circuitry for phase change memory|
|US7933139||15 May 2009||26 Abr 2011||Macronix International Co., Ltd.||One-transistor, one-resistor, one-capacitor phase change memory|
|US7972895 *||9 Oct 2009||5 Jul 2011||Macronix International Co., Ltd.||Memory cell device with coplanar electrode surface and method|
|US7981797 *||25 Jun 2008||19 Jul 2011||Hynix Semiconductor Inc.||Phase-change random access memory device and method of manufacturing the same|
|US8097871 *||30 Abr 2009||17 Ene 2012||Macronix International Co., Ltd.||Low operational current phase change memory structures|
|US8119528||19 Ago 2008||21 Feb 2012||International Business Machines Corporation||Nanoscale electrodes for phase change memory devices|
|US8129268||16 Nov 2009||6 Mar 2012||International Business Machines Corporation||Self-aligned lower bottom electrode|
|US8189375||16 Nov 2011||29 May 2012||Micron Technology, Inc.||Methods of forming memory cells and methods of forming programmed memory cells|
|US8233317||16 Nov 2009||31 Jul 2012||International Business Machines Corporation||Phase change memory device suitable for high temperature operation|
|US8283202||28 Ago 2009||9 Oct 2012||International Business Machines Corporation||Single mask adder phase change memory element|
|US8283650||28 Ago 2009||9 Oct 2012||International Business Machines Corporation||Flat lower bottom electrode for phase change memory cell|
|US8320173||3 May 2012||27 Nov 2012||Micron Technology, Inc.||Methods of forming programmed memory cells|
|US8373148 *||26 Abr 2007||12 Feb 2013||Spansion Llc||Memory device with improved performance|
|US8384135||20 Jun 2011||26 Feb 2013||SK Hynix Inc.||Phase-change random access memory device and method of manufacturing the same|
|US8395192||11 Ene 2011||12 Mar 2013||International Business Machines Corporation||Single mask adder phase change memory element|
|US8415653||14 Mar 2012||9 Abr 2013||International Business Machines Corporation||Single mask adder phase change memory element|
|US8471236||16 Jul 2012||25 Jun 2013||International Business Machines Corporation||Flat lower bottom electrode for phase change memory cell|
|US8492194||6 May 2011||23 Jul 2013||International Business Machines Corporation||Chemical mechanical polishing stop layer for fully amorphous phase change memory pore cell|
|US9059394||9 Feb 2012||16 Jun 2015||International Business Machines Corporation||Self-aligned lower bottom electrode|
|Clasificación de EE.UU.||257/2, 257/4, 257/E45.002|
|Clasificación cooperativa||H01L45/06, H01L45/144, H01L45/122, H01L45/126, H01L45/1233, H01L45/1675|
|13 Abr 2006||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ARNOLD, JOHN CHRISTOPHER;CLEVENGER, LAWRENCE ALFRED;DALTON, TIMOTHY JOSEPH;AND OTHERS;REEL/FRAME:018057/0275;SIGNING DATES FROM 20060328 TO 20060407