US 20070262389 A1
Embodiments of the invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication. For one embodiment, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a trench. The trench is then filled with a semiconductor material. The semiconductor material is then planarized with the remainder of the oxide layer and the remainder of the oxide layer is then removed. The semiconductor fins thus exposed are of uniform height to within a specified tolerance.
1. An integrated circuit device comprising:
a substrate; and
a plurality of transistors formed upon the substrate, each transistor of the plurality having a semiconductor body, each semiconductor body having a height (Hsi) of less than 20 nm, the height (Hsi) across the plurality of transistors being uniform to within 5%.
2. The integrated circuit device of
3. The integrated circuit device of
4. The integrated circuit device of
5. The integrated circuit device of
6. The integrated circuit device of
7. The integrated circuit device of
8. An integrated circuit device comprising:
a plurality of transistors on a substrate, each transistor of the plurality having a semiconductor body extending a distance from the substrate, wherein the variation in a transistor body height (HSi) across the plurality is less than the variation in the distance, across the plurality, the semiconductor bodies extend from the substrate.
9. The integrated circuit device of
10. The integrated circuit device of
a gate dielectric on a sidewall of the semiconductor body, wherein the sidewall has a height (HSi) that is less than the distance the semiconductor body extends from the substrate;
a gate electrode on the gate dielectric; and
a source and drain region in the semiconductor body on opposite sides of said gate electrode.
11. The integrated circuit device of
12. The integrated circuit device of
13. The integrated circuit device of
14. The integrated circuit device of
15. An integrated circuit device comprising:
a first tri-gate transistor having a gate dielectric on a sidewall of a first semiconductor body, the first semiconductor body extending from a substrate by a first distance, wherein the sidewall of the first semiconductor body has a first sidewall height that is less than the first distance;
a second tri-gate transistor having the gate dielectric on a sidewall of a second semiconductor body, the second semiconductor body extending from the substrate by a second distance wherein the sidewall of the second semiconductor body has a second sidewall height that is less than the second distance and wherein the second sidewall height is within 5% of the first sidewall height.
16. The integrated circuit device of
17. The integrated circuit device of
18. The integrated circuit device of
19. The integrated circuit device of
20. The integrated circuit device of
This application is a divisional of U.S. patent application Ser. No. 10/760,028 filed Jan. 16, 2004.
Embodiments of the invention relate generally to the field of integrated circuit device fabrication and more specifically to tri-gate transistor fabrication.
The trend toward increasing the number of functions of an integrated circuit device (IC device) is continuing. As the size of transistors decreases, serious drawbacks in current transistor fabrication processes become evident. For example, typical silicon-on-insulator (SOI) transistors are fabricated by coating a substrate with an insulator (e.g., glass or silicon oxide) layer. A second silicon wafer is then bonded to the insulator layer and thinned to a desired thickness (i.e., as determined by the transistor dimensions). This thinning process is very difficult to control with great accuracy.
As shown in
The transfer wafer is then thinned to a desired thickness based upon the transistor dimensions. Typically, this thickness is approximately 50-100 nm. The thinning of the transfer wafer may be accomplished through one of several typical processes. For example, a wet etch and polish process may be used to grind the transfer wafer to the desired thickness. An alternative method for thinning the transfer wafer includes hydrogen implantation of the transfer layer to create a weak section of the transfer wafer. The bonded pair is then heated to effect a high temperature cleave of the hydrogen-doped interface. Subsequently, the transfer wafer surface is polished or treated in other ways to planarize the surface or further reduce the thickness. These methods provide control of the thickness to within approximately several hundred angstroms. As shown in
For typical transistor design architecture, gate length is proportional to HSi, with HSi equal to about one-third of gate length. For typical transistors with gate lengths of approximately 20-100 nm, the desired HSi is greater than approximately 20 nm. Using the current fabrication method, it is possible to create adequate film layers. However, as the gate length, and hence, the desired HSi decreases, current fabrication methods exhibit serious disadvantages.
The HSi value must be uniform across a wafer in order to produce transistors with uniform characteristics. For example, the transistor threshold voltage, which is directly proportional to HSi, should not vary by more than approximately 10%. Therefore, the film layer thickness that determines HSi, should not vary by more than 10%.
The methods of thinning the transfer layer to obtain the film layer are capable of producing a film layer of approximately 20 nm thickness that does not vary by more than approximately 10%. However, these methods fail to produce the required uniformity for thinner film layers. Therefore, current methods of fabricating SOI transistors are incapable of yielding transistors with gate lengths smaller than approximately 50 nm.
Moreover, the process of bonding the carrier wafer and transfer wafer, and the process of thinning the transfer wafer to the desired thickness, are costly and difficult to control.
The invention may be best understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:
In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.
Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Moreover, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention.
At operation 210, selected portions of the trench layer are removed, thus forming trenches. For one embodiment, the trench layer is a material that can be selectively etched using conventional etching processes. For various alternative embodiments, the trench layer may be multiple layers of different materials with each material. In one such embodiment, the multiple layers of the trench layer are susceptible to different etching processes.
At operation 215, the trenches formed by operation 210, are filled with a semiconductor material (e.g., silicon). For one embodiment, the trenches are filled with epitaxial silicon using a selective epitaxial process. In an alternative embodiment, the trenches are filled in some other manner. For example, the trenches may be filled with polysilicon using a blanket deposition process.
At operation 220, the excess semiconductor material is removed. That is, semiconductor material filling the trench that extends above the surface of the remainder of the trench layer is removed. For one embodiment, a chemical-mechanical polish (CMP) is employed to planarize the surface of the semiconductor material.
At operation 225, the remainder of the trench layer is removed exposing semiconductor fins (i.e., the semiconductor material filling the trenches). For one embodiment, the height of the semiconductor fins is uniform to within less than 5%.
Embodiments of the invention include various operations. Many of the methods are described in their most basic form, but operations can be added to or deleted from any of the methods without departing from the basic scope of the invention. For example, the trench layer, described in operation 205 of
As described above, the trenches formed in the trench layer may be filled with silicon in a number of ways including, for example, blanket deposition of polysilicon. For an embodiment in which a blanket deposition of polysilicon is used, an annealing process is employed after deposition to anneal the silicon into a single crystal.
While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.
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