US20070290711A1 - Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control - Google Patents
Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control Download PDFInfo
- Publication number
- US20070290711A1 US20070290711A1 US11/424,535 US42453506A US2007290711A1 US 20070290711 A1 US20070290711 A1 US 20070290711A1 US 42453506 A US42453506 A US 42453506A US 2007290711 A1 US2007290711 A1 US 2007290711A1
- Authority
- US
- United States
- Prior art keywords
- node
- circuit
- slew rate
- bidirectional buffer
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0005—Modifications of input or output impedance
Definitions
- the present invention relates to a bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control.
- Bidirectional buffers are well known devices that allow the transmission of a signal through the buffer. There are many types of buffers, and various combinations of features. For buffers of the type described by the present invention, some conventional buffers are bidirectional, others are unidirectional; some conventional buffers have slew rate control, others do not.
- certain bidirectional buffers also possess the ability to control the slew rate of the signal that is input thereto. Providing for slew rate control can allow one to maintain better overall control of the circuits, as changes in signal that has been buffered have more predictability.
- a bidirectional buffer with slew rate control in at least one direction as well as a method of bidirectionally transmitting signals with slew rate control in at least one direction.
- the present invention is directed to bidirectional buffer with slew rate control in at least one direction.
- the present invention is also directed to a method of bidirectionally transmitting signals with slew rate control in at least one direction.
- FIG. 1 illustrates a block diagram of the buffer according to the present invention.
- FIG. 2 illustrates a detailed circuit diagram of the buffer according to the present invention.
- FIGS. 3A-3C are timing diagrams of various signals input to, outfrom from, and created within the buffer according to the present invention.
- FIG. 1 illustrates a block diagram of the buffer 100 according to the present invention in the boxed out section.
- the buffer 100 is preferably an ASIC, and in one particular embodiment is a circuit that complies with the HDMI specification. With respect to the HDMI implementation, it is relevant that the buffer 100 operates at 3.3 v voltage levels and that the signal, typically a 1 kHz signal, must have a rise time ⁇ 250 us and fall time ⁇ 50 us.
- a 1 kHz signal termed a forward signal herein is input on the IN node, buffered within the buffer 100 , and output as a slew rate controlled 1 kH signal on the OUT node.
- a reverse signal is input on the OUT node, buffered within the buffer 100 , and then output onto the IN node. In the embodiment described herein this reverse signal is not slew rate controlled.
- the reverse signal In this mode of operation, there is not slew rate control. As such, during times in which the 1 Khz forward signal does not exist, there is no forward signal (or one also look at this as the low state of the 1 kHz forward signal). At such times, the reverse signal on the OUT node may be either high or low. The OUT's state will be dictated elsewhere by external circuitry not pertaining to this invention; however, buffer 100 must allow this “high” or “low” signal to be seen on the IN node, preferably at all times.
- FIG. 2 illustrates a detailed circuit diagram of the buffer according to the present invention. Certain of the transistors shown are for simply biasing purposes so they are initially described:
- the OUT's state will be dictated elsewhere by external circuitry not pertaining to this invention; however, it preferably should allow this “high” or “low” signal to be seen on the IN node at all times.
- the pass transistor N 1 will remain “ON” since there is no forward signal on the IN node triggering the time constant R 1 /C 1 .
- the steady state signal on the OUT node will not trigger C 3 /R 5 or C 2 /R 2 so Ipu and Ipd will remain OFF; therefore, the voltage on the OUT node will be allowed to dictate the voltage on the IN node with regards to a logic “low” and “high” state.
- bidirectional slew rate control can be added, which then requires a directional control signal. Other such variations are within the scope of the present invention as defined by the claims.
Abstract
Description
- The present invention relates to a bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control.
- Bidirectional buffers are well known devices that allow the transmission of a signal through the buffer. There are many types of buffers, and various combinations of features. For buffers of the type described by the present invention, some conventional buffers are bidirectional, others are unidirectional; some conventional buffers have slew rate control, others do not.
- As mentioned, certain bidirectional buffers also possess the ability to control the slew rate of the signal that is input thereto. Providing for slew rate control can allow one to maintain better overall control of the circuits, as changes in signal that has been buffered have more predictability.
- Conventional bidirectional circuits that have slew rate control require, however, a directional control input in order to operate properly. While in certain circumstances this works fine, in others it does not.
- What is desired is a bidirectional buffer with slew rate control in at least one direction, as well as a method of bidirectionally transmitting signals with slew rate control in at least one direction.
- The present invention is directed to bidirectional buffer with slew rate control in at least one direction.
- The present invention is also directed to a method of bidirectionally transmitting signals with slew rate control in at least one direction.
- The above and other aspects of the present invention will become readily apparent when reading the following detailed description taken in conjunction with the appended drawings in which:
-
FIG. 1 illustrates a block diagram of the buffer according to the present invention. -
FIG. 2 illustrates a detailed circuit diagram of the buffer according to the present invention. -
FIGS. 3A-3C are timing diagrams of various signals input to, outfrom from, and created within the buffer according to the present invention. -
FIG. 1 illustrates a block diagram of thebuffer 100 according to the present invention in the boxed out section. Thebuffer 100 is preferably an ASIC, and in one particular embodiment is a circuit that complies with the HDMI specification. With respect to the HDMI implementation, it is relevant that thebuffer 100 operates at 3.3 v voltage levels and that the signal, typically a 1 kHz signal, must have a rise time≦250 us and fall time≦50 us. - In one mode of operation, a 1 kHz signal, termed a forward signal herein is input on the IN node, buffered within the
buffer 100, and output as a slew rate controlled 1 kH signal on the OUT node. In another mode of operation, a reverse signal is input on the OUT node, buffered within thebuffer 100, and then output onto the IN node. In the embodiment described herein this reverse signal is not slew rate controlled. - With respect to the circuit elements and blocks shown in
FIG. 1 , some bias must be applied to the “OUT” and “IN” nodes, which is done through resistors Rext,in and Rext,out, as shown. Further, the blocks labeled “IPU”, “IPD”, and “Impedance Control” are blocks with multiple transistors that perform functions as described further herein. - The following general overview of the above referenced circuit will first be provided, in conjunction with reference to the timing diagrams in
FIG. 3 . Thereafter, a more detailed explanation with respect to the circuit diagram ofFIG. 2 will be provided. This particular embodiment is described for a circuit that operates having a 3.3 volt supply voltage and on a 1 kHz signal, although it will be apparent that the present invention can be implemented with other supply voltages and signals. - The following explanation is provided with respect to the forward signal at the transitions of that signal from high to low and low to high, which provide an understanding of how the circuit works.
- HIGH→LOW Transition:
When the 1 kHz forward signal is “HIGH” on thebuffer 100 the “IN” node is pulled to GND quickly. The “Impedance Control” block detects this, as well as, the “IPU” block. The “OUT” node that is being slew rate controlled needs this quick transition to GND offset. To do this the “Impedance Control” signal takes the gate of pass transistor N1 close to GND on the edge of the 1 kHz “HIGH” signal while “IPU” block sources current to keep the voltage on “OUT” at 3.3V. Now the 1 kHz forward signal is a steady state “HIGH” and the gate of N1 is slowly allowed to come back to its nominal voltage allowing current to flow through it to GND through thebuffer 100 from “IPU” block creating a gradual HIGH→LOW transition on the “OUT” node. - LOW→HIGH Transition:
When the 1 kHz forward signal releases from its “HIGH” state on thebuffer 100, the “IN” node is pulled “HIGH” via an external path which in this case is through the external resistor Rext,in. The “Impedance Control” block detects this, as well as the “IPD” block. This time however the “Impedance Control” block allows the gate of transistor N1 to drift slightly higher than nominal but for all intents and purposes transistor N1 is still “ON”. While N1 is “ON” the “IPD” block sinks current to GND so that the “OUT” node is slew rate controlled, thus creating a gradual LOW→HIGH transition on the “OUT” node. - The following explanation is provided with respect to the reverse signal. In this mode of operation, there is not slew rate control. As such, during times in which the 1 Khz forward signal does not exist, there is no forward signal (or one also look at this as the low state of the 1 kHz forward signal). At such times, the reverse signal on the OUT node may be either high or low. The OUT's state will be dictated elsewhere by external circuitry not pertaining to this invention; however,
buffer 100 must allow this “high” or “low” signal to be seen on the IN node, preferably at all times. -
FIG. 2 illustrates a detailed circuit diagram of the buffer according to the present invention. Certain of the transistors shown are for simply biasing purposes so they are initially described: - 1) N2, N3 and P1 provide a current mirror to develop a bias on P2.
- 2) A current source into N4 generates a Vt which is divided by 2 via R3 and R2 to develop a Vt/2 bias on the gate of IPD.
- 3) Similar to (2) N5, N6 and P4 are used as a current mirror to develop a diode drop off of the 3.3V Supply which is resistively divided by R4 and R5 to generate a (3.3-Vt/2) bias on the gate of IPU.
- 4) Transistors N7-N10 take a current source and ratio it up by 5:1, or even more preferably 10:1 so it can be used to bias the “OUT” node via P5 and P6. In a preferred embodiment, the value of this current source is set by the HDMI specification. The current source can be any value taking into account the MAX bus capacitance; which in the HDMI specifrication implementation is 1500 pF for a single CEC bus device. In a preferred implementation according to the present invention, there is used an internal current source of 12 uA, as well as a 10:1 ratio, to obtain the 120 uA value for the current source, per the HDMI specification. The operational description provided herein is similar to that for the forward and reverse signals. Given the further circuit detail, the description is more complex, but the functions are the same.
- For the forward signal, the following description is provided.
- HIGH→LOW Transition:
- When the 1 kHz forward signal is “HIGH” on the
buffer 100 the “IN” node is pulled to GND quickly. C1 “sees” this sudden transition and takes the voltage on P3 (originally at 0V) below GND turning it on hard. This pulls all the current from P2 through P3 to GND so the gate of N1 is at GND isolating the “IN” and “OUT” nodes. This is the case only for a brief time as the RC time constant (R1/C1) gradually allows the gate of P3 to go back to 0V and the gate of N1 to return back to it's nominal voltage of 1.8V. It is noted that while the gate of P3 being at GND does allow current to flow through it continually to GND but it is a very weak transistor so it can't sink all 2.2 uA, therefore, the gate of N1 will still have a bias on it. As the gate of N1 is slowly rising back to its nominal state C3 is “watching” the “OUT” node. As soon as it starts to get pulled down via thebuffer 100, C3 pulls the gate of IPU down turning it on. This allows current to source through N1 through thebuffer 100 to GND keeping the voltage up on “OUT”. Again the RC time constant of C3/R5 gradually shuts off the IPU current source which allows a slow HIGH to LOW transition on the “OUT” node. - LOW→HIGH Transition:
When the 1 kHz forward signal releases from its “HIGH” state on thebuffer 100, the “IN” node is pulled “HIGH” via an external resistor and the “OUT” via the internal current source. However, while this sequence of events is trying to occur, C2 is “watching” the “OUT” node, and as soon as it is pulled high (i.e. +400 mV transition), this is reflected on the gate of IPD so that it turns on and sinks some of the current that's trying to pull-up the “OUT” node. C2/R2 is a time constant as well so the gate of IPD gradually returns back to its normal state of Vt/2 which causes the “OUT” node to rise gradually as well. - For the reverse signal, the following description is provided. The OUT's state will be dictated elsewhere by external circuitry not pertaining to this invention; however, it preferably should allow this “high” or “low” signal to be seen on the IN node at all times. In this case, the pass transistor N1 will remain “ON” since there is no forward signal on the IN node triggering the time constant R1/C1. Furthermore, the steady state signal on the OUT node will not trigger C3/R5 or C2/R2 so Ipu and Ipd will remain OFF; therefore, the voltage on the OUT node will be allowed to dictate the voltage on the IN node with regards to a logic “low” and “high” state. Modifications and variations of the preferred embodiment will be readily apparent to those skilled in the art. For instance, bidirectional slew rate control can be added, which then requires a directional control signal. Other such variations are within the scope of the present invention as defined by the claims.
Claims (14)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/424,535 US7321241B1 (en) | 2006-06-15 | 2006-06-15 | Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control |
PCT/US2007/012884 WO2007145843A2 (en) | 2006-06-15 | 2007-05-31 | Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control |
PCT/US2007/013034 WO2007145864A2 (en) | 2006-06-15 | 2007-05-31 | Apparatus and method that provides active pull-up and logic translation from one signal mode to another signal mode |
EP07795567.2A EP2036129A4 (en) | 2006-06-15 | 2007-05-31 | Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control |
EP07795654.8A EP2039006A4 (en) | 2006-06-15 | 2007-05-31 | Apparatus and method that provides active pull-up and logic translation from one signal mode to another signal mode |
TW096120134A TWI346457B (en) | 2006-06-15 | 2007-06-05 | Apparatus and method that provides active pull-up and logic translation from one signal mode to another signal mode |
TW096120132A TWI448074B (en) | 2006-06-15 | 2007-06-05 | Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/424,535 US7321241B1 (en) | 2006-06-15 | 2006-06-15 | Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control |
Publications (2)
Publication Number | Publication Date |
---|---|
US20070290711A1 true US20070290711A1 (en) | 2007-12-20 |
US7321241B1 US7321241B1 (en) | 2008-01-22 |
Family
ID=38832294
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/424,535 Active 2026-07-01 US7321241B1 (en) | 2006-06-15 | 2006-06-15 | Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control |
Country Status (4)
Country | Link |
---|---|
US (1) | US7321241B1 (en) |
EP (1) | EP2036129A4 (en) |
TW (1) | TWI448074B (en) |
WO (1) | WO2007145843A2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7692450B2 (en) * | 2007-12-17 | 2010-04-06 | Intersil Americas Inc. | Bi-directional buffer with level shifting |
US7737727B2 (en) * | 2007-12-17 | 2010-06-15 | Intersil Americas Inc. | Bi-directional buffer for open-drain or open-collector bus |
US7639045B2 (en) * | 2008-05-23 | 2009-12-29 | Intersil Americas Inc. | Bi-directional buffer and method for bi-directional buffering that reduce glitches due to feedback |
US9183713B2 (en) | 2011-02-22 | 2015-11-10 | Kelly Research Corp. | Perimeter security system |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5517135A (en) * | 1995-07-26 | 1996-05-14 | Xilinx, Inc. | Bidirectional tristate buffer with default input |
US5656950A (en) * | 1995-10-26 | 1997-08-12 | Xilinx, Inc. | Interconnect lines including tri-directional buffer circuits |
US6052325A (en) * | 1998-05-22 | 2000-04-18 | Micron Technology, Inc. | Method and apparatus for translating signals |
US6323722B1 (en) * | 1996-07-29 | 2001-11-27 | Townsend And Townsend And Crew Llp | Apparatus for translating a voltage |
US6329839B1 (en) * | 1996-09-04 | 2001-12-11 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus architecture |
US7239174B2 (en) * | 2002-10-21 | 2007-07-03 | Viciciv Technology | Programmable interconnect structures |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4701720A (en) * | 1986-04-28 | 1987-10-20 | National Semiconductor Corporation | Capacitive feedback to boost amplifier slew rate |
US5084637A (en) * | 1989-05-30 | 1992-01-28 | International Business Machines Corp. | Bidirectional level shifting interface circuit |
JP3251661B2 (en) * | 1991-10-15 | 2002-01-28 | テキサス インスツルメンツ インコーポレイテツド | CMOS buffer circuit with controlled slew rate |
EP0660512B1 (en) * | 1993-12-22 | 1999-12-08 | Philips Composants Et Semiconducteurs | Phase shifter amplifier and its application in a recombiner circuit |
US6066971A (en) * | 1997-10-02 | 2000-05-23 | Motorola, Inc. | Integrated circuit having buffering circuitry with slew rate control |
US6903588B2 (en) * | 2003-04-15 | 2005-06-07 | Broadcom Corporation | Slew rate controlled output buffer |
-
2006
- 2006-06-15 US US11/424,535 patent/US7321241B1/en active Active
-
2007
- 2007-05-31 EP EP07795567.2A patent/EP2036129A4/en not_active Withdrawn
- 2007-05-31 WO PCT/US2007/012884 patent/WO2007145843A2/en active Application Filing
- 2007-06-05 TW TW096120132A patent/TWI448074B/en active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5517135A (en) * | 1995-07-26 | 1996-05-14 | Xilinx, Inc. | Bidirectional tristate buffer with default input |
US5656950A (en) * | 1995-10-26 | 1997-08-12 | Xilinx, Inc. | Interconnect lines including tri-directional buffer circuits |
US6323722B1 (en) * | 1996-07-29 | 2001-11-27 | Townsend And Townsend And Crew Llp | Apparatus for translating a voltage |
US6329839B1 (en) * | 1996-09-04 | 2001-12-11 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus architecture |
US6052325A (en) * | 1998-05-22 | 2000-04-18 | Micron Technology, Inc. | Method and apparatus for translating signals |
US7239174B2 (en) * | 2002-10-21 | 2007-07-03 | Viciciv Technology | Programmable interconnect structures |
Also Published As
Publication number | Publication date |
---|---|
TWI448074B (en) | 2014-08-01 |
EP2036129A4 (en) | 2013-10-09 |
WO2007145843A2 (en) | 2007-12-21 |
WO2007145843A3 (en) | 2008-04-10 |
US7321241B1 (en) | 2008-01-22 |
TW200810356A (en) | 2008-02-16 |
WO2007145843B1 (en) | 2008-06-05 |
EP2036129A2 (en) | 2009-03-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5684415A (en) | 5 volt driver in a 3 volt CMOS process | |
US7495483B2 (en) | Input buffer for CMOS integrated circuits | |
US6429716B1 (en) | Pre-buffer voltage level shifting circuit and method | |
US6281730B1 (en) | Controlled slew rate driver | |
US5880602A (en) | Input and output buffer circuit | |
US8947131B2 (en) | Multi-voltage supplied input buffer | |
US8441301B2 (en) | Cascoded level shifter protection | |
WO2018005115A1 (en) | Edp mipi dsi combination architecture | |
US7876129B2 (en) | Load sense and active noise reduction for I/O circuit | |
US7321241B1 (en) | Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control | |
EP0848498B1 (en) | Output driver circuit in semiconductor device | |
WO1996008871A1 (en) | Controlled slew rate output buffer | |
US6359485B1 (en) | Differential input receiver and method for reducing noise | |
US11296694B2 (en) | Output driving circuit | |
KR100686252B1 (en) | Circuit for reducing switching noise | |
US7466182B2 (en) | Level shift circuit | |
US5903180A (en) | Voltage tolerant bus hold latch | |
US6838915B2 (en) | Input and output circuit of semiconductor device | |
JP2004128162A (en) | Semiconductor device | |
US8686763B2 (en) | Receiver circuit | |
US7446565B2 (en) | Apparatus and method that provides active pull-up and logic translation from one signal mode to another signal mode | |
US10541684B2 (en) | Input/output circuit | |
KR20140086675A (en) | Data output circuit | |
KR20040053370A (en) | Active voltage level bus switch(or pass gate) translator | |
US20060097760A1 (en) | Differential signal generating circuit, differential signal transmitting circuit and differential signal transceiver system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: CALIFORNIA MICRO DEVICES, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MARAK, CHADWICK N.;DUNNIHOO, JEFFREY C.;WHITWORTH, ADAM J.;REEL/FRAME:018199/0806;SIGNING DATES FROM 20060801 TO 20060825 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT,NEW Free format text: SECURITY AGREEMENT;ASSIGNOR:CALIFORNIA MICRO DEVICES CORPORATION;REEL/FRAME:024079/0097 Effective date: 20100225 Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, NE Free format text: SECURITY AGREEMENT;ASSIGNOR:CALIFORNIA MICRO DEVICES CORPORATION;REEL/FRAME:024079/0097 Effective date: 20100225 |
|
AS | Assignment |
Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONA Free format text: MERGER;ASSIGNOR:CALIFORNIA MICRO DEVICES CORPORATION;REEL/FRAME:024879/0135 Effective date: 20100729 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, NEW YORK Free format text: SECURITY INTEREST;ASSIGNOR:SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC;REEL/FRAME:038620/0087 Effective date: 20160415 |
|
AS | Assignment |
Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT;REEL/FRAME:038631/0345 Effective date: 20100511 Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK);REEL/FRAME:038632/0074 Effective date: 20160415 |
|
AS | Assignment |
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC;REEL/FRAME:039853/0001 Effective date: 20160415 Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT, NEW YORK Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC;REEL/FRAME:039853/0001 Effective date: 20160415 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |
|
AS | Assignment |
Owner name: FAIRCHILD SEMICONDUCTOR CORPORATION, ARIZONA Free format text: RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087;ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:064070/0001 Effective date: 20230622 Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONA Free format text: RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087;ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:064070/0001 Effective date: 20230622 |