US20080003791A1 - Method for fabricating recess gate in semiconductor device - Google Patents
Method for fabricating recess gate in semiconductor device Download PDFInfo
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- US20080003791A1 US20080003791A1 US11/644,884 US64488406A US2008003791A1 US 20080003791 A1 US20080003791 A1 US 20080003791A1 US 64488406 A US64488406 A US 64488406A US 2008003791 A1 US2008003791 A1 US 2008003791A1
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 45
- 230000008569 process Effects 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000009413 insulation Methods 0.000 claims abstract description 11
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 44
- 239000007789 gas Substances 0.000 claims description 25
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims description 23
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 21
- 229910018503 SF6 Inorganic materials 0.000 claims description 17
- WRQGPGZATPOHHX-UHFFFAOYSA-N ethyl 2-oxohexanoate Chemical compound CCCCC(=O)C(=O)OCC WRQGPGZATPOHHX-UHFFFAOYSA-N 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000009616 inductively coupled plasma Methods 0.000 claims description 7
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 4
- 239000000460 chlorine Substances 0.000 claims description 4
- 229910052801 chlorine Inorganic materials 0.000 claims description 4
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 claims description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 4
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 claims description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052794 bromium Inorganic materials 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 2
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 2
- 229910052799 carbon Inorganic materials 0.000 claims 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000002955 isolation Methods 0.000 description 9
- 230000003247 decreasing effect Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
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- 230000006866 deterioration Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- YTCQFLFGFXZUSN-BAQGIRSFSA-N microline Chemical compound OC12OC3(C)COC2(O)C(C(/Cl)=C/C)=CC(=O)C21C3C2 YTCQFLFGFXZUSN-BAQGIRSFSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
Definitions
- the present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a recess gate in a semiconductor device.
- a typical planar gate structure includes a gate formed over a plane active area. As the size of a pattern has decreased, a gate channel length has also decreased. Thus, an electric field has increased due to an increased ion doping concentration, causing junction leakage. Accordingly, it has become difficult to maintain a refresh characteristic of the device.
- a three-dimensional recess gate structure has been introduced. Forming the three-dimensional recess gate structure includes forming a gate over a recess after recessing an active region. Such recess gate structure may allow increasing a channel length and decreasing an ion doping concentration. Thus, the refresh characteristic may be improved substantially.
- FIG. 1 illustrates a cross-sectional view showing a typical recess gate structure.
- Device isolation structures 12 defining an active region are formed in a substrate 11 .
- the active region of the substrate 11 is selectively etched to a certain thickness to form recesses 13 .
- Recess gates RG are formed over the recesses 13 .
- Each recess gate RG includes a gate insulation layer 14 , a polysilicon layer 15 for use in a gate electrode, and a metal or metal silicide layer 16 .
- the above-described recess gate has advantages such as an increased gate channel length and a decreased ion implantation doping concentration, improving a refresh characteristic of the device.
- a recess formed by a plasma etching process obtains a ‘V’ shape profile.
- silicon residues referred to as horns are generated between device isolation structures and an active region.
- Such horns cause characteristics of a subsequent gate insulation layer to deteriorate, and consequently, the horns become a stress point and functions as a leakage current source.
- production yield of the device may be reduced.
- FIGS. 2A and 2B illustrate micrographic views showing limitations of the typical method.
- horns are formed between device isolation structures 12 and adjacent recesses 13 when an active region of a substrate is etched to form the recesses 13 .
- a profile of trenches T has a slope formed in a manner that a width of the trenches T become smaller toward a bottom portion.
- recesses also have a profile that provides a width that narrows toward a bottom portion. Accordingly, horns may be generated. Such horns may cause deteriorated characteristics of a subsequent gate insulation layer and may become a stress point to function as a leakage current source.
- Embodiments of the present invention are directed to provide a method for fabricating a recess gate in a semiconductor device, which can reduce deterioration of a gate insulation layer and generation of a leakage current source by reducing generation of horns in recess patterns.
- a method for fabricating a recess gate in a semiconductor device including: etching a substrate to form a first recess; etching the substrate at side portions of the first recess to form a second recess; and forming a gate insulation layer and a gate electrode over the second recess.
- FIG. 1 illustrates a cross-sectional view showing a typical recess gate.
- FIGS. 2A and 2B illustrate micrographic views showing limitations of the typical method.
- FIGS. 3A to 3D illustrate cross-sectional views showing a method for fabricating a recess gate in a semiconductor device according to an embodiment of the present invention.
- FIG. 4 illustrates a cross-sectional view showing a result after a recess etching in accordance with the embodiment of the present invention.
- FIGS. 5A and 5B illustrate micrographic views showing a device fabricated according to the embodiment of the present invention.
- FIGS. 6A and 6B illustrate micrographic views to describe the embodiments of the present invention in detail.
- FIGS. 7A to 7D illustrate graphs to describe the embodiments of the present invention in detail.
- the present invention relates to a method for fabricating a recess gate in a semiconductor device.
- a height of horns generated during a recess formation may be decreased, and thus, deterioration of a gate insulation layer characteristic and a leakage current source caused by concentrated stress may be removed.
- a design rule may be maintained and a process margin may be maximized.
- embodiments of this invention may provide advantages such as a large scale of integration of a semiconductor device including a logic, increased production yield, and reduced production costs.
- FIGS. 3A to 3D illustrate cross-sectional views showing a method for fabricating a recess gate in a semiconductor device according to an embodiment of the present invention.
- device isolations 32 defining an active region and a field region are formed in a substrate 31 .
- the device isolation structures 32 may be formed by employing a shallow trench isolation (STI) process.
- An oxide-based layer 33 for use as a hard mask and a polysilicon layer 34 for use as a hard mask are formed over the substrate 31 .
- An organic bottom anti-reflective coating (BARC) layer 35 is formed over the polysilicon layer 34 .
- a photoresist pattern 36 is formed over the BARC layer 35 .
- the BARC layer 35 and the polysilicon layer 34 are etched using the photoresist pattern 36 as an etch barrier to expose portions of the oxide-based layer 33 .
- the etching of the polysilicon layer 34 includes implanting a chlorine-based plasma in a plasma source of a transformer coupled plasma (TCP) type or an inductivity coupled plasma (ICP) type, and supplying a source power and a bias power. Consequently, a polysilicon hard mask 34 A is formed.
- Reference denotation 35 A refers to a patterned BARC layer.
- the photoresist pattern 36 is removed.
- the patterned BARC layer 35 A is also removed.
- the oxide-based layer 33 and the substrate 31 are etched to form an oxide-based hard mask 33 A and first recesses 37 .
- a line width CD 1 of the first recesses 37 is formed smaller than a line width of intended recesses by approximately 10 nm to approximately 15 nm.
- the etching process for forming the first recesses 37 includes adding a bromine-based plasma to a chlorine-based plasma and supplying a source power and a bias power.
- a bromine-based plasma to a chlorine-based plasma and supplying a source power and a bias power.
- chlorine (Cl 2 )/hydrogen bromide (HBr) plasma is used as a TCP type or an ICP type plasma source.
- a ratio of Cl 2 to HBr ranges approximately 1:5-20.
- the source power ranging from approximately 500 W to approximately 1,500 W and the bias power of approximately 500 W or less are supplied.
- the level of the bias power may be adjusted according to conditions of the process.
- the first recesses 37 are formed by employing the etching process described above.
- the first recesses 37 may be formed using a pressure of approximately 25 mT, a radio frequency (RF) power of approximately 550 W, a bias power of approximately 350 W, and HBr flowing at a rate of approximately 100 sccm.
- RF radio frequency
- an isotropic etching process is performed to enlarge the line width CD 1 of the first recesses 37 , forming second recesses 37 A.
- the second recesses 37 A have an enlarged line width CD 2 .
- the polysilicon hard mask 34 A may be removed during the etching processes for forming the first recesses 37 and the second recesses 37 A.
- the isotropic etching process includes performing the process under a pressure ranging from approximately 20 mT to approximately 100 mT, supplying a source power ranging from approximately 500 W to approximately 1,500 W and a bias power of approximately 50 W or less in a TCP type plasma source.
- the isotropic etching process uses an etch gas comprising a small amount of sulfur hexafluoride (SF 6 )/oxygen (O 2 ) plasma and a large amount of Cl 2 /HBr plasma.
- SF 6 sulfur hexafluoride
- O 2 oxygen
- a ratio of SF 6 to O 2 to Cl 2 to HBr may be approximately 5:3:20:60 in the etch gas.
- the SF 6 gas of the SF 6 /O 2 plasma functions to generate polymers.
- the Cl 2 /HBr plasma is a reaction gas for etching silicon (Si).
- a fluorine-based gas e.g., tetrafluoromethane (CF 4 ) or nitrogen trifluoride (NF 3 ), may be used to generate polymers instead of the SF 6 gas.
- the isotropic etching process may be performed by supplying a source power ranging from approximately 300 W to approximately 2,000 W at an ICP type etch apparatus attached with a faraday shield using an etch gas including SF 6 /O 2 /Cl 2 /HBr.
- the SF 6 /O 2 /Cl 2 /HBr in the etch gas may have a ratio of approximately 5:3:20:60, respectively.
- the isotropic etching process may be performed at an etch apparatus using a plasma source of a microwave down stream (MDS) type, an electron cyclotron resonance (ECR) type, or a helical type.
- MDS microwave down stream
- ECR electron cyclotron resonance
- the isotropic etching process etches substantially the same thickness in most directions due to characteristics of the isotropic etching process.
- the supply of the bias power is minimized to etch sidewall portions of the first recesses 37 more than bottom portions of the first recesses 37 . Accordingly, a width difference W between the first recesses 37 and the second recesses 37 A is larger than a height difference H between the first recesses 37 and the second recesses 37 A.
- the aforementioned isotropic etching process is performed to form the second recesses 37 A having the line width CD 2 enlarged by approximately 10 nm to approximately 15 nm when compared to the line width CD 1 of the first recesses 37 .
- the isotropic etching process may be performed under a pressure of approximately 20 mT, supplying a RF power of approximately 550 W and a bias power of approximately 350 W.
- the isotropic etching process may include flowing SF 6 at a rate of approximately 5 sccm, flowing O 2 at a rate of approximately 5 sccm, flowing Cl 2 at a rate of approximately 20 sccm, and flowing HBr at a rate of approximately 60 sccm.
- the oxide-based hard mask 33 A may be partially etched during the isotropic etching process.
- the remaining oxide-based hard mask is denoted with reference denotation 33 B.
- a gate insulation layer and a gate electrode are formed over the second recesses 37 A after the remaining oxide-based hard mask 33 B is removed.
- the gate electrode may have a stack structure including polysilicon and one of a metal layer and a metal silicide layer.
- FIG. 4 illustrates a cross-sectional view showing a result after the recess etching process in accordance with the embodiment of the present invention.
- Horns formed between the device isolation structures 32 and the second recess 37 A may be removed or partially removed such that chances of generating a deteriorated gate insulation characteristic and forming a stress point that functions as a leakage current source may be reduced. Thus, a production yield may not be decreased.
- FIGS. 5A , 5 B, 6 A, and 6 B illustrate micrographic views showing a recess pattern fabricated according to an embodiment of the present invention.
- a substrate is etched using a polysilicon hard mask as an etch barrier to form first recesses 37 having a micro line width CD 1 .
- an isotropic etching process is performed to form second recesses 37 A having an enlarged line width CD 2 . Horns are reduced between the second recesses 37 A and device isolation structures 32 (refer to ‘A’).
- FIGS. 7A to 7D illustrate graphs to describe the embodiments of the present invention in detail.
- an embodiment of a T66 TIVA device is described.
- Side etch quantities of a silicon layer according to different gases are compared below.
- a horizontal axis represents a flow rate of SF 6 plasma
- a vertical axis represents a side etch quantity of a silicon layer. As the flow rate of the SF 6 plasma increases, the side etch quantity of the silicon layer decreases.
- a horizontal axis represents a flow rate ratio of O 2 plasma
- a vertical axis represents a side etch quantity of a silicon layer. As the flow rate of the O 2 plasma increases, the side etch quantity of the silicon layer decreases.
- a horizontal axis represents a ratio between Cl 2 plasma and HBr plasma
- a vertical axis represents a side etch quantity of a silicon layer.
- a section A represents when the HBr plasma is implanted solely
- a section B represents when the Cl 2 plasma is implanted solely
- a section C represents when the HBr plasma and the Cl 2 plasma are both implanted.
- the side etch quantity of the silicon layer is the largest when the HBr plasma is solely implanted, and is the smallest when the Cl 2 plasma is solely implanted. Implanting both of the HBr plasma and the Cl 2 plasma results in a medium value.
- a horizontal axis represents a TCP RF power
- a vertical axis represents a side etch quantity of a silicon layer.
- a degree of reduction is gentle, as depicted in FIG. 7D .
- the side etch of the silicon layer is most actively performed when using the HBr/Cl 2 plasma with the RF power ranging approximately 400 W to approximately 500 W.
- the deterioration of the gate insulation layer can be reduced by lessening or removing the horns formed between the device isolation structures and the recesses when forming the recess gates.
Abstract
A method for fabricating a recess gate in a semiconductor device includes etching a substrate to form a first recess, etching the substrate at side portions of the first recess to form a second recess, and forming a gate insulation layer and a gate electrode over the second recess, wherein etching the substrate to form the second recess includes performing an isotropic etching process.
Description
- The present invention claims priority of Korean Patent Application Number 10-2006-0060327, filed on Jun. 30, 2006, which is incorporated by reference in its entirety.
- The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a recess gate in a semiconductor device.
- In a fabrication of a semiconductor device, a typical planar gate structure includes a gate formed over a plane active area. As the size of a pattern has decreased, a gate channel length has also decreased. Thus, an electric field has increased due to an increased ion doping concentration, causing junction leakage. Accordingly, it has become difficult to maintain a refresh characteristic of the device. In order to improve the difficulty, a three-dimensional recess gate structure has been introduced. Forming the three-dimensional recess gate structure includes forming a gate over a recess after recessing an active region. Such recess gate structure may allow increasing a channel length and decreasing an ion doping concentration. Thus, the refresh characteristic may be improved substantially.
-
FIG. 1 illustrates a cross-sectional view showing a typical recess gate structure.Device isolation structures 12 defining an active region are formed in asubstrate 11. The active region of thesubstrate 11 is selectively etched to a certain thickness to formrecesses 13. Recess gates RG are formed over therecesses 13. Each recess gate RG includes agate insulation layer 14, apolysilicon layer 15 for use in a gate electrode, and a metal ormetal silicide layer 16. - The above-described recess gate has advantages such as an increased gate channel length and a decreased ion implantation doping concentration, improving a refresh characteristic of the device. However, as devices have become highly integrated, a recess formed by a plasma etching process obtains a ‘V’ shape profile. Thus, silicon residues referred to as horns are generated between device isolation structures and an active region. Such horns cause characteristics of a subsequent gate insulation layer to deteriorate, and consequently, the horns become a stress point and functions as a leakage current source. Thus, production yield of the device may be reduced.
-
FIGS. 2A and 2B illustrate micrographic views showing limitations of the typical method. Referring toFIG. 2A , horns are formed betweendevice isolation structures 12 andadjacent recesses 13 when an active region of a substrate is etched to form therecesses 13. Referring toFIG. 2B , a profile of trenches T has a slope formed in a manner that a width of the trenches T become smaller toward a bottom portion. As described earlier, recesses also have a profile that provides a width that narrows toward a bottom portion. Accordingly, horns may be generated. Such horns may cause deteriorated characteristics of a subsequent gate insulation layer and may become a stress point to function as a leakage current source. - Embodiments of the present invention are directed to provide a method for fabricating a recess gate in a semiconductor device, which can reduce deterioration of a gate insulation layer and generation of a leakage current source by reducing generation of horns in recess patterns.
- In accordance with an aspect of the present invention, there is provided a method for fabricating a recess gate in a semiconductor device, including: etching a substrate to form a first recess; etching the substrate at side portions of the first recess to form a second recess; and forming a gate insulation layer and a gate electrode over the second recess.
-
FIG. 1 illustrates a cross-sectional view showing a typical recess gate. -
FIGS. 2A and 2B illustrate micrographic views showing limitations of the typical method. -
FIGS. 3A to 3D illustrate cross-sectional views showing a method for fabricating a recess gate in a semiconductor device according to an embodiment of the present invention. -
FIG. 4 illustrates a cross-sectional view showing a result after a recess etching in accordance with the embodiment of the present invention. -
FIGS. 5A and 5B illustrate micrographic views showing a device fabricated according to the embodiment of the present invention. -
FIGS. 6A and 6B illustrate micrographic views to describe the embodiments of the present invention in detail. -
FIGS. 7A to 7D illustrate graphs to describe the embodiments of the present invention in detail. - The present invention relates to a method for fabricating a recess gate in a semiconductor device. According to an embodiment of the present invention, a height of horns generated during a recess formation may be decreased, and thus, deterioration of a gate insulation layer characteristic and a leakage current source caused by concentrated stress may be removed. Also, it may be possible to obtain a benefit such as a reduced ion doping concentration according to an embodiment of the present invention, improving a refresh characteristic of the device. Thus, a design rule may be maintained and a process margin may be maximized. Furthermore, embodiments of this invention may provide advantages such as a large scale of integration of a semiconductor device including a logic, increased production yield, and reduced production costs.
-
FIGS. 3A to 3D illustrate cross-sectional views showing a method for fabricating a recess gate in a semiconductor device according to an embodiment of the present invention. - Referring to
FIG. 3A ,device isolations 32 defining an active region and a field region are formed in asubstrate 31. Thedevice isolation structures 32 may be formed by employing a shallow trench isolation (STI) process. An oxide-basedlayer 33 for use as a hard mask and apolysilicon layer 34 for use as a hard mask are formed over thesubstrate 31. An organic bottom anti-reflective coating (BARC)layer 35 is formed over thepolysilicon layer 34. Aphotoresist pattern 36 is formed over the BARClayer 35. - Referring to
FIG. 3B , the BARClayer 35 and thepolysilicon layer 34 are etched using thephotoresist pattern 36 as an etch barrier to expose portions of the oxide-basedlayer 33. The etching of thepolysilicon layer 34 includes implanting a chlorine-based plasma in a plasma source of a transformer coupled plasma (TCP) type or an inductivity coupled plasma (ICP) type, and supplying a source power and a bias power. Consequently, a polysiliconhard mask 34A is formed.Reference denotation 35A refers to a patterned BARC layer. - Referring to
FIG. 3C , thephotoresist pattern 36 is removed. The patternedBARC layer 35A is also removed. The oxide-basedlayer 33 and thesubstrate 31 are etched to form an oxide-basedhard mask 33A and first recesses 37. A line width CD1 of the first recesses 37 is formed smaller than a line width of intended recesses by approximately 10 nm to approximately 15 nm. - The etching process for forming the first recesses 37 includes adding a bromine-based plasma to a chlorine-based plasma and supplying a source power and a bias power. In more detail, chlorine (Cl2)/hydrogen bromide (HBr) plasma is used as a TCP type or an ICP type plasma source. A ratio of Cl2 to HBr ranges approximately 1:5-20. The source power ranging from approximately 500 W to approximately 1,500 W and the bias power of approximately 500 W or less are supplied. The level of the bias power may be adjusted according to conditions of the process.
- The first recesses 37 are formed by employing the etching process described above. The first recesses 37 may be formed using a pressure of approximately 25 mT, a radio frequency (RF) power of approximately 550 W, a bias power of approximately 350 W, and HBr flowing at a rate of approximately 100 sccm.
- Referring to
FIG. 3D , an isotropic etching process is performed to enlarge the line width CD1 of thefirst recesses 37, formingsecond recesses 37A. The second recesses 37A have an enlarged line width CD2. The polysiliconhard mask 34A may be removed during the etching processes for forming thefirst recesses 37 and thesecond recesses 37A. - The isotropic etching process includes performing the process under a pressure ranging from approximately 20 mT to approximately 100 mT, supplying a source power ranging from approximately 500 W to approximately 1,500 W and a bias power of approximately 50 W or less in a TCP type plasma source. The isotropic etching process uses an etch gas comprising a small amount of sulfur hexafluoride (SF6)/oxygen (O2) plasma and a large amount of Cl2/HBr plasma. Although the bias power of approximately 0 W may be supplied, that is, not supplying the bias power, the bias power of approximately 50 W or less is supplied herein because the bias power may be required according to various etch apparatuses.
- A ratio of SF6 to O2 to Cl2 to HBr may be approximately 5:3:20:60 in the etch gas. The SF6 gas of the SF6/O2 plasma functions to generate polymers. The Cl2/HBr plasma is a reaction gas for etching silicon (Si). A fluorine-based gas, e.g., tetrafluoromethane (CF4) or nitrogen trifluoride (NF3), may be used to generate polymers instead of the SF6 gas.
- The isotropic etching process may be performed by supplying a source power ranging from approximately 300 W to approximately 2,000 W at an ICP type etch apparatus attached with a faraday shield using an etch gas including SF6/O2/Cl2/HBr. The SF6/O2/Cl2/HBr in the etch gas may have a ratio of approximately 5:3:20:60, respectively. Furthermore, the isotropic etching process may be performed at an etch apparatus using a plasma source of a microwave down stream (MDS) type, an electron cyclotron resonance (ECR) type, or a helical type.
- The isotropic etching process etches substantially the same thickness in most directions due to characteristics of the isotropic etching process. In this embodiment of the present invention, the supply of the bias power is minimized to etch sidewall portions of the
first recesses 37 more than bottom portions of the first recesses 37. Accordingly, a width difference W between thefirst recesses 37 and thesecond recesses 37A is larger than a height difference H between thefirst recesses 37 and thesecond recesses 37A. - The aforementioned isotropic etching process is performed to form the
second recesses 37A having the line width CD2 enlarged by approximately 10 nm to approximately 15 nm when compared to the line width CD1 of the first recesses 37. The isotropic etching process may be performed under a pressure of approximately 20 mT, supplying a RF power of approximately 550 W and a bias power of approximately 350 W. The isotropic etching process may include flowing SF6 at a rate of approximately 5 sccm, flowing O2 at a rate of approximately 5 sccm, flowing Cl2 at a rate of approximately 20 sccm, and flowing HBr at a rate of approximately 60 sccm. The oxide-basedhard mask 33A may be partially etched during the isotropic etching process. The remaining oxide-based hard mask is denoted withreference denotation 33B. Although not illustrated, a gate insulation layer and a gate electrode are formed over thesecond recesses 37A after the remaining oxide-basedhard mask 33B is removed. The gate electrode may have a stack structure including polysilicon and one of a metal layer and a metal silicide layer. -
FIG. 4 illustrates a cross-sectional view showing a result after the recess etching process in accordance with the embodiment of the present invention. Horns formed between thedevice isolation structures 32 and thesecond recess 37A may be removed or partially removed such that chances of generating a deteriorated gate insulation characteristic and forming a stress point that functions as a leakage current source may be reduced. Thus, a production yield may not be decreased. -
FIGS. 5A , 5B, 6A, and 6B illustrate micrographic views showing a recess pattern fabricated according to an embodiment of the present invention. Referring toFIGS. 5A and 6A , a substrate is etched using a polysilicon hard mask as an etch barrier to form first recesses 37 having a micro line width CD1. Referring toFIGS. 5B and 6B , an isotropic etching process is performed to formsecond recesses 37A having an enlarged line width CD2. Horns are reduced between thesecond recesses 37A and device isolation structures 32 (refer to ‘A’). -
FIGS. 7A to 7D illustrate graphs to describe the embodiments of the present invention in detail. In particular, an embodiment of a T66 TIVA device is described. Side etch quantities of a silicon layer according to different gases are compared below. - Referring to
FIG. 7A , a horizontal axis represents a flow rate of SF6 plasma, and a vertical axis represents a side etch quantity of a silicon layer. As the flow rate of the SF6 plasma increases, the side etch quantity of the silicon layer decreases. - Referring to
FIG. 7B , a horizontal axis represents a flow rate ratio of O2 plasma, and a vertical axis represents a side etch quantity of a silicon layer. As the flow rate of the O2 plasma increases, the side etch quantity of the silicon layer decreases. - Referring to
FIG. 7C , a horizontal axis represents a ratio between Cl2 plasma and HBr plasma, and a vertical axis represents a side etch quantity of a silicon layer. A section A represents when the HBr plasma is implanted solely, a section B represents when the Cl2 plasma is implanted solely, and a section C represents when the HBr plasma and the Cl2 plasma are both implanted. The side etch quantity of the silicon layer is the largest when the HBr plasma is solely implanted, and is the smallest when the Cl2 plasma is solely implanted. Implanting both of the HBr plasma and the Cl2 plasma results in a medium value. - Referring to
FIG. 7D , a horizontal axis represents a TCP RF power, and a vertical axis represents a side etch quantity of a silicon layer. As the TCP RF power increases, the side etch quantity of the silicon layer decreases. A degree of reduction is gentle, as depicted inFIG. 7D . - Referring to the
FIGS. 7A to 7D , the side etch of the silicon layer is most actively performed when using the HBr/Cl2 plasma with the RF power ranging approximately 400 W to approximately 500 W. - In accordance with the embodiments of the present invention, the deterioration of the gate insulation layer can be reduced by lessening or removing the horns formed between the device isolation structures and the recesses when forming the recess gates.
- While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Claims (20)
1. A method for fabricating a recess gate in a semiconductor device, comprising:
etching a substrate to form a first recess;
etching sidewalls and a bottom of the first recess to form a second recess; and
forming a gate insulation layer and a gate electrode over the second recess.
2. The method of claim 1 , wherein etching the sidewalls and the bottom of the first recess to form the second recess comprises performing an isotropic etching process.
3. The method of claim 2 , wherein the isotropic etching process comprises using one of nitrogen trifluoride (NF3) and sulfur hexafluoride (SF6).
4. The method of claim 2 , wherein the isotropic etching process comprises using an etch gas including a fluorine-based gas and a bromine-based gas.
5. The method of claim 2 , wherein the isotropic etching process comprises using a gas mixture including an etch gas composed of a fluorine-based gas and a bromine-based gas, oxygen (O2), and chlorine (Cl2).
6. The method of claim 5 , wherein the gas mixture comprises SF6/O2/Cl2/hydrogen bromide (HBr).
7. The method of claim 6 , wherein an amount of the SF6/O2 is smaller than an amount of the Cl2/HBr in the gas mixture.
8. The method of claim 6 , wherein a ratio of the SF6 to the O2 to the Cl2 to the HBr in the gas mixture is approximately 5:3:20:60.
9. The method of claim 1 , wherein etching the sidewalls and the bottom of the first recess to form the second recess comprises using a plasma etch apparatus.
10. The method of claim 9 , wherein etching the sidewalls and the bottom of the first recess to form the second recess comprises using a pressure ranging from approximately 20 mT to approximately 100 mT, a source power ranging from approximately 500 W to approximately 1,500 W, and a bias power of approximately 50 W or less.
11. The method of claim 9 , wherein etching the sidewalls and the bottom of the first recess to form the second recess comprises performing the etching at a transformer coupled plasma (TCP) type apparatus using a pressure ranging from approximately 20 mT to approximately 100 mT and a source power ranging from approximately 500 W to approximately 1,500 W, without supplying a bias power.
12. The method of claim 2 , wherein the isotropic etching process comprises using a gas mixture including an etch gas composed of a carbon-based gas and HBr, O2, and Cl2.
13. The method of claim 12 , wherein the carbon-based gas comprises tetrafluoromethane (CF4).
14. The method of claim 1 , wherein etching the sidewalls and the bottom of the first recess to form the second recess comprises performing the etching at an inductivity coupled plasma (ICP) type apparatus attached with a faraday shield using a power ranging from approximately 300 W to approximately 2,000 W.
15. The method of claim 14 , wherein etching the sidewalls and the bottom of the first recess to form the second recess comprises using an etch gas including SF6/O2/Cl2/HBr mixed at a ratio of approximately 5:3:20:60.
16. The method of claim 1 , wherein etching the sidewalls and the bottom of the first recess to form the second recess comprises performing the etching at an etch apparatus using a plasma source selected from a group consisting of a microwave down stream (MDS) type, an electron cyclotron resonance (ECR) type, and a helical type.
17. The method of claim 1 , wherein a line width of the second recess is larger than a line width of the first recess by approximately 10 nm to approximately 15 nm.
18. The method of claim 1 , wherein etching a substrate to form the first recess comprises:
forming an oxide-based layer and a polysilicon layer over the substrate;
patterning the polysilicon layer; and
etching the oxide-based layer and the substrate using the patterned polysilicon layer.
19. The method of claim 18 , wherein etching a substrate to form the first recess comprises using a plasma source of a TCP type or an ICP type, a mixed gas including Cl2/HBr, and a power ranging from approximately 500 W to approximately 1,500 W.
20. The method of claim 19 , wherein a ratio of the Cl2 to the HBr in the mixed gas including Cl2/HBr ranges approximately 1:5-20.
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KR1020060060327A KR100792365B1 (en) | 2006-06-30 | 2006-06-30 | Method for fabricating recess gate in semiconductor device |
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US20100255649A1 (en) * | 2009-04-06 | 2010-10-07 | Samsung Electronics Co., Ltd. | Methods of fabricating recessed channel metal oxide semiconductor (mos) transistors |
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US9395374B2 (en) | 2008-04-16 | 2016-07-19 | Momenta Pharmaceuticals, Inc. | Analysis of amino acid copolymer compositions |
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JP2009259863A (en) * | 2008-04-11 | 2009-11-05 | Tokyo Electron Ltd | Dry etching processing device, and dry etching method |
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JP2001237218A (en) | 2000-02-21 | 2001-08-31 | Nec Corp | Method of manufacturing semiconductor device |
KR20060062326A (en) * | 2004-12-03 | 2006-06-12 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
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2006
- 2006-06-30 KR KR1020060060327A patent/KR100792365B1/en not_active IP Right Cessation
- 2006-12-26 US US11/644,884 patent/US20080003791A1/en not_active Abandoned
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US20040194890A1 (en) * | 2001-09-28 | 2004-10-07 | Tokyo Electron Limited | Hybrid plasma processing apparatus |
US20050003240A1 (en) * | 2002-03-21 | 2005-01-06 | Lam Research Corporation | Low contamination components for semiconductor processing apparatus and methods for making components |
US6844591B1 (en) * | 2003-09-17 | 2005-01-18 | Micron Technology, Inc. | Method of forming DRAM access transistors |
US20060049455A1 (en) * | 2004-09-09 | 2006-03-09 | Se-Myeong Jang | Semiconductor devices with local recess channel transistors and methods of manufacturing the same |
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US9395374B2 (en) | 2008-04-16 | 2016-07-19 | Momenta Pharmaceuticals, Inc. | Analysis of amino acid copolymer compositions |
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US8859489B2 (en) | 2009-04-03 | 2014-10-14 | Momenta Pharmaceuticals, Inc. | Water-mediated control of depolymerization step of glatiramer acetate synthesis |
US20100255649A1 (en) * | 2009-04-06 | 2010-10-07 | Samsung Electronics Co., Ltd. | Methods of fabricating recessed channel metal oxide semiconductor (mos) transistors |
US8058128B2 (en) | 2009-04-06 | 2011-11-15 | Samsung Electronics Co., Ltd. | Methods of fabricating recessed channel metal oxide semiconductor (MOS) transistors |
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