US20080067639A1 - Integrated circuit package system with encapsulation lock - Google Patents
Integrated circuit package system with encapsulation lock Download PDFInfo
- Publication number
- US20080067639A1 US20080067639A1 US11/532,508 US53250806A US2008067639A1 US 20080067639 A1 US20080067639 A1 US 20080067639A1 US 53250806 A US53250806 A US 53250806A US 2008067639 A1 US2008067639 A1 US 2008067639A1
- Authority
- US
- United States
- Prior art keywords
- paddle
- lead body
- top surface
- recess
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present application contains subject matter related to a concurrently filed U.S. Patent Application by Byung Tai Do and Sung Uk Yang entitled “Integrated Circuit Package System with Encapsulation Lock”.
- the related application is assigned to STATS ChipPAC Ltd and is identified by docket number 27-291.
- the present application also contains subject matter related to a concurrently filed U.S. Patent Application by Byung Tai Do and Sung Uk Yang entitled “Integrated Circuit Package System with Encapsulation Lock”.
- the related application is assigned to STATS ChipPAC Ltd and is identified by docket number 27-299.
- the present invention relates generally to integrated circuit packages and more particularly to molded integrated circuit packages.
- Modern electronics such as smart phones, personal digital assistants, location based services devices, enterprise class servers, or enterprise class storage arrays, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost.
- Contemporary electronics expose integrated circuits and packages to more demanding and sometimes new environmental conditions, such as cold, heat, and humidity requiring integrated circuit packages to provide robust structures.
- EMC epoxy mold compound
- a variation of existing technologies uses mature package technologies with lead fingers made from lead frames. However, lead frame packages typically use bond wires electrically connecting the lead fingers to the integrated circuit. Another variation of existing technologies uses solder bumps on the integrated circuit with a flip chip mounting. Yet another variation combines flip chip style mounting with lead frame packages.
- the lead design of integrated circuit packages such as quad flat nonleaded (QFN) packages, generally has a lug feature to provide locking between lead and mold compound. But, it adversely reduces metal-to-metal space and disturbs mold compound flow. This impact is bigger than other types of lead frame packages due to its inherently small size of the package. As a result, it causes reliability problem such as delamination between lead, tie-bar or paddle and mold compound or internal void. When it comes to the Flip Chip packages, die area covers more space above the paddle and some portion of leads as well and the problem tends to be more serious or more frequent.
- the present invention provides an integrated circuit package system including forming a paddle having a depression from a paddle top surface and an external interconnect, forming a lead tip and a lead body of the external interconnect, connecting a device over the paddle top surface and the external interconnect, and filling a substantially electrically nonconductive material in the depression.
- FIG. 1 is a plan view of an integrated circuit package system in an embodiment of the present invention
- FIG. 2 is a cross-sectional view of the integrated circuit package system of FIG. 1 ;
- FIG. 3 is a plan view of an integrated circuit package system in an alternative embodiment of the present invention.
- FIG. 4 is a cross-sectional view of the integrated circuit package system of FIG. 3 ;
- FIG. 5 is a plan view of an integrated circuit package system in another alternative embodiment of the present invention.
- FIG. 6 is a cross-sectional view of the integrated circuit package system of FIG. 5 ;
- FIG. 7 is a more detailed plan view of a portion of the external interconnects of FIG. 5 ;
- FIG. 8 is a cross-sectional view of the portion of the external interconnects of FIG. 7 ;
- FIG. 9 is a different cross-sectional view of the portion of the external interconnects of FIG. 7 ;
- FIG. 10 is a cross-sectional view of an integrated circuit package system in yet another alternative embodiment of the present invention.
- FIG. 11 is a cross-sectional view of an integrated circuit package system in yet another alternative embodiment of the present invention.
- FIG. 12 is a cross-sectional view of an integrated circuit package system in yet another alternative embodiment of the present invention.
- FIG. 13 is a plan view of an integrated circuit package system in yet another embodiment of the present invention.
- FIG. 14 is a cross-sectional view of the integrated circuit package system of FIG. 13 ;
- FIG. 15 is a flow chart of an integrated circuit package system for manufacture of the integrated circuit package system in an embodiment of the present invention.
- horizontal as used herein is defined as a plane parallel to the conventional integrated circuit surface, regardless of its orientation.
- vertical refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane.
- on means there is direct contact among elements.
- processing includes deposition of material, patterning, exposure, development, etching, cleaning, molding, and/or removal of the material or as required in forming a described structure.
- the integrated circuit package system 100 includes a device 102 , such as an integrated circuit die, over a paddle 104 , such as die-attach paddle.
- the paddle 104 includes a depression 105 , such as an array of dimples, a moat, or a depression in a geometric shape of an x-mark.
- the device 102 extends over a portion of external interconnects 106 , such as leads, and tie bars 108 .
- the tie bars 108 connect to the corners of the paddle 104 .
- An encapsulation 118 such as an epoxy mold compound, covers the device 102 , the paddle 104 , the tie bars 108 , and the external interconnects 106 .
- the encapsulation 118 fills the depression 105 , wherein the encapsulation 118 is a substantially electrically nonconductive material such as an epoxy mold compound (EMC).
- EMC epoxy mold compound
- FIG. 2 therein is shown a cross-sectional view of the integrated circuit package system 100 of FIG. 1 .
- the cross-sectional view is along segment 2 - 2 in FIG. 1 .
- Each of the external interconnects 106 has a lead tip 202 and a lead body 204 .
- the lead tip 202 may be formed by any number of processes, such as half etching the external interconnects 106 .
- the formation for the lead tip 202 also forms the lead body 204 .
- the lead tip 202 has a lead tip top surface 206 to a lead tip bottom surface 208 .
- the paddle 104 is between the external interconnects 106 .
- a paddle bottom surface 210 of the paddle 104 is in substantially the same horizontal plane as a lead body bottom surface 212 .
- the paddle 104 may be formed by any number of processes, such as by half etching.
- the depression 105 is from a paddle top surface 214 of the paddle 104 .
- the paddle top surface 214 is below the lead tip top surface 206 .
- the paddle 104 may serve multiple functions, such as thermal dissipation or ground connection.
- the encapsulation 118 fills the depression 105 in the paddle 104 providing improved adhesion between the encapsulation 118 and the paddle 104 .
- the improved adhesion improves performance in moisture sensitivity level (MSL) test.
- the depression 105 may be formed by any number of processes such as etching or half-etching the paddle 104 .
- the device 102 does not contact the paddle 104 .
- the depression 105 is shown from the paddle top surface 214 and not extending to the paddle bottom surface 210 , although it is understood that the depression 105 or a portion of the depression 105 may traverse through the paddle 104 .
- the paddle top surface 214 is described as below the same horizontal plane as the lead tip top surface 206 , although it is understood that the paddle top surface 214 may not be below the lead tip top surface 206 .
- the paddle bottom surface 210 is described as in substantially the same horizontal plane as the lead body bottom surface 212 , although it is understood that the paddle bottom surface 210 and the lead body bottom surface 212 may not be in substantially the same horizontal plane.
- the device 102 has a non-active side 216 and an active side 218 .
- the device 102 is over the paddle 104 and connect to the lead tip 202 with an internal interconnect 220 , such as a solder bump.
- the internal interconnect 220 is on the active side 218 .
- the integrated circuit package system 300 includes a device 302 , such as an integrated circuit die, over a paddle 304 , such as die-attach paddle.
- the paddle 304 includes a depression 305 , such as an array of dimples, a moat, or a depression in a geometric shape of an x-mark.
- the device 302 extends over a portion of external interconnects 306 , such as leads, and tie bars 308 .
- the tie bars 308 connect to the corners of the paddle 304 .
- the external interconnects 306 have holes 320 , such as through holes.
- the holes 320 are located towards the interior portion, to the integrated circuit package system 300 , of the external interconnects 306 relative.
- the tie bars 308 have slots 322 .
- An encapsulation 318 such as an epoxy mold compound, covers the device 302 , the paddle 304 , the tie bars 308 , and the external interconnects 306 .
- the encapsulation 318 flows through and fills the holes 320 in the external interconnects 306 as well as the slots 322 of the tie bars 308 forming mold locks.
- the mold locks form structural reinforcement holding the encapsulation 318 in place.
- the mold locks help resist delamination of the encapsulation and improves performance in moisture sensitivity level (MSL) test.
- the encapsulation 318 also fills the depression 305 in the paddle 304 , wherein the encapsulation 318 is a substantially electrically nonconductive material such as an epoxy mold compound (EMC).
- EMC epoxy mold compound
- the tie bars 308 are shown having two instances of the slots 322 , although it is understood that the number of the slots 322 may differ. Also for illustrative purposes, the slots 322 are shown as a substantially the same, although it is understood that the slots 322 may differ from one another.
- FIG. 4 therein is shown a cross-sectional view of the integrated circuit package system 300 of FIG. 3 .
- the cross-sectional view is along segment 4 - 4 in FIG. 3 .
- Each of the external interconnects 306 has a lead tip 402 and a lead body 404 .
- the lead tip 402 may be formed by any number of processes, such as half etching the external interconnects 306 .
- the formation for the lead tip 402 also forms the lead body 404 .
- the lead tip 402 has the holes 320 from a lead tip top surface 406 to a lead tip bottom surface 408 .
- the paddle 304 is between the external interconnects 306 .
- a paddle bottom surface 410 of the paddle 304 is in substantially the same horizontal plane as a lead body bottom surface 412 .
- the paddle 304 may be formed by any number of processes, such as by half etching.
- the depression 305 is from a paddle top surface 414 of the paddle 304 .
- the paddle top surface 414 is below the lead tip top surface 406 .
- the paddle 304 may serve multiple functions, such as thermal dissipation or ground connection.
- the encapsulation 318 fills the depression 305 in the paddle 304 providing improved adhesion between the encapsulation 318 and the paddle 304 .
- the improved adhesion improves performance in moisture sensitivity level (MSL) test.
- the depression 305 may be formed by any number of processes such as etching or half-etching the paddle 304 .
- the device 302 does not contact the paddle 304 .
- the depression 305 is shown from the paddle top surface 414 and not extending to the paddle bottom surface 410 , although it is understood that the depression 305 or a portion of the depression 305 may traverse through the paddle 304 .
- the paddle top surface 414 is described as below the same horizontal plane as the lead tip top surface 406 , although it is understood that the paddle top surface 414 may not be below the lead tip top surface 406 .
- the paddle bottom surface 410 is described as in substantially the same horizontal plane as the lead body bottom surface 412 , although it is understood that the paddle bottom surface 410 and the lead body bottom surface 412 may not be in substantially the same horizontal plane.
- the device 302 has a non-active side 416 and an active side 418 .
- the device 302 is over the paddle 304 and connect to the lead tip 402 with an internal interconnect 420 , such as a solder bump.
- the internal interconnect 420 is on the active side 418 .
- the connection of the internal interconnect 420 do not fill the holes 320 .
- the encapsulation 318 fills the holes 320 to provide mold locks for the integrated circuit package system 300 .
- the integrated circuit package system 500 includes a device 502 , such as an integrated circuit die, over a paddle 504 , such as die-attach paddle.
- the paddle 504 includes a depression 505 , such as an array of dimples, a moat, or a depression in a geometric shape of an x-mark.
- the device 502 extends over a portion of external interconnects 506 , such as leads, and tie bars 508 .
- the tie bars 508 connect to the corners of the paddle 504 .
- Each of the external interconnects 506 has a recess 510 , such as an intersecting recess segments.
- the recess 510 is located towards an edge of the integrated circuit package system 500 .
- the recess 510 has a first recess segment 512 and a second recess segment 514 .
- the first recess segment 512 is along a length-wise dimension 516 of the external interconnects 506 .
- the second recess segment 514 is perpendicular to the first recess segment 512 .
- the recess 510 has the first recess segment 512 and three instances of the second recess segment 514 .
- the recess 510 areas shown has one instance of the first recess segment 512 and three instances of the second recess segment 514 , although it is understood that the number of the first recess segment 512 and the second recess segment 514 may differ.
- the configuration of the recess 510 has the first recess segment 512 orthogonal with the second recess segment 514 , although it is understood that the first recess segment 512 and the second recess segment 514 may be in a different configuration.
- the recess 510 is shown having both the first recess segment 512 and the second recess segment 514 , although it is understood that the recess 510 may not have both the first recess segment 512 and the second recess segment 514 .
- An encapsulation 518 covers the device 502 , the paddle 504 , the tie bars 508 , and the external interconnects 506 .
- the encapsulation 518 fills the recess 510 in the external interconnects 506 forming mold locks.
- the tie bars 508 and the paddle 504 also provide mold locks.
- the mold locks form structural reinforcement holding the encapsulation 518 in place.
- the mold locks help resist delamination of the encapsulation and improves performance in moisture sensitivity level (MSL) test.
- the encapsulation 518 also fills the depression 505 in the paddle 504 , wherein the encapsulation 518 is a substantially electrically nonconductive material such as an epoxy mold compound (EMC).
- EMC epoxy mold compound
- FIG. 6 therein is shown a cross-sectional view of the integrated circuit package system 500 of FIG. 5 .
- the cross-sectional view is along segment 6 - 6 in FIG. 5 .
- Each of the external interconnects 506 has a lead tip 602 and a lead body 604 .
- the lead tip 602 may be formed by any number of processes, such as half etching the external interconnects 506 .
- the formation for the lead tip 602 also forms the lead body 604 .
- the lead body 604 has the recess 510 from a lead body top surface 606 of the lead body 604 .
- a lead body bottom surface 608 of the lead body 604 is used for connections to the next system level (not shown), such as a printed circuit board or another integrated circuit package system.
- the paddle 504 is between the external interconnects 506 .
- a paddle bottom surface 610 of the paddle 504 is in substantially the same horizontal plane as the lead body bottom surface 608 .
- the paddle 504 may be formed by any number of processes, such as by half etching.
- a paddle top surface 612 of the paddle 504 is below the lead body top surface 606 .
- the paddle 504 may serve multiple functions, such as thermal dissipation or ground connection.
- the encapsulation 518 fills the depression 505 in the paddle 504 providing improved adhesion between the encapsulation 518 and the paddle 504 .
- the improved adhesion improves performance in moisture sensitivity level (MSL) test.
- the depression 505 may be formed by any number of processes such as etching or half-etching the paddle 504 .
- the device 502 does not contact the paddle 504 .
- the depression 505 is shown from the paddle top surface 612 and not extending to the paddle bottom surface 610 , although it is understood that the depression 505 or a portion of the depression 505 may traverse through the paddle 504 .
- the paddle top surface 612 is described as not in substantially the same horizontal plane as the lead body top surface 606 , although it is understood that the paddle top surface 612 and the lead body top surface 606 may be in substantially the same horizontal plane.
- the paddle bottom surface 610 is described as in substantially the same horizontal plane as the lead body bottom surface 608 , although it is understood that the paddle bottom surface 610 and the lead body bottom surface 608 may not be in substantially the same horizontal plane.
- the device 502 has a non-active side 614 and an active side 616 .
- the device 502 is over the paddle 504 and connect to the lead tip 602 with an internal interconnect 618 , such as a solder bump.
- the internal interconnect 618 is on the active side 616 . The connection of the internal interconnect 618 do not fill the recess 5 10 .
- FIG. 7 therein is shown a more detailed plan view of a portion of the external interconnects 506 of FIG. 7 .
- This view depicts the portion of the external interconnects 506 , such as a first external interconnect 702 and a second external interconnect 704 .
- the first external interconnect 702 has a first lead body 706 and a first lead tip 708 .
- the first lead tip 708 is shown as a substantially straight segment extending from the first lead body 706 .
- One instance of the recess 510 is in the first lead body 706 .
- the second external interconnect 704 has a second lead body 710 and a second lead tip 712 The second lead tip 712 extends from the second lead body 710 with a displacement portion such that a tip end of the second lead tip 712 does not extend substantially straight from a body end of the second lead tip 712 next to the second lead body 710 .
- the first recess segment 512 has an orientation substantially parallel to the length-wise dimension 516 of the first lead body 706 .
- the second recess segment 514 is perpendicular to and intersects the first recess segment 512 in the first lead body 706 .
- one instance of the recess 510 is also part of the second lead body 710 .
- the first recess segment 512 and the second recess segment 514 are in a similar configuration in the second external interconnect 704 as in the first external interconnect 702 .
- the encapsulation 518 of FIG. 5 fills in the recess 510 , such as the first recess segment 512 and the second recess segment 514 , to form a mold lock from the top of the lead body 604 , such as the first lead body 706 and the second lead body 710 .
- the recess 510 with the intersecting pattern, is part of the mold lock in the horizontal dimensions of the integrated circuit package system 500 of FIG. 5 .
- FIG. 8 therein is shown a cross-sectional view of the portion of the external interconnects 506 of FIG. 7 .
- the cross-sectional view is along the segment 8 - 8 in FIG. 7 showing the cross sections of the first lead body 706 and the second lead body 710 .
- the first lead body 706 has the second recess segment 514 in a curve shape from the lead body top surface 606 .
- the first recess segment 512 is shown as another recess to the second intersecting recess segment and at a bottom portion of the second recess segment 514 .
- the first recess segment 512 and the second recess segment 514 do not extend through the lead body bottom surface 608 of both the first lead body 706 and the second lead body 710 .
- the encapsulation 518 fills the first recess segment 512 and the second recess segment 514 .
- FIG. 9 therein is shown a different cross-sectional view of the portion of the external interconnects 506 of FIG. 7 .
- the cross-sectional view is along the segment 9 - 9 in FIG. 7 showing the cross section of the second external interconnect 704 and may represent a similar cross section of any of the external interconnects 506 of FIG. 5 .
- This cross section shows the second lead tip 712 and the second lead body 710 .
- An outline of the first recess segment 512 is shown as having a curve shape at the ends and flat in the middle.
- the first recess segment 512 is shown from the lead body top surface 606 and within the second lead body 710 while not part of the second lead tip 712 . As mentioned earlier, the first recess segment 512 does not extend to the lead body bottom surface 608 .
- the encapsulation 518 fills in the recess 510 .
- the recess 510 with the paddle 504 of FIG. 5 and the lead tip 602 of FIG. 6 , are also part of the mold lock in the vertical dimensions of the integrated circuit package system 300 of FIG. 5 .
- FIG. 10 therein is shown a cross-sectional view of an integrated circuit package system 1000 in yet another alternative embodiment of the present invention.
- This cross-sectional view may represent the cross section of the integrated circuit package system 500 along segment 6 - 6 in FIG. 5 .
- Each of external interconnects 1006 has a lead tip 1020 and a lead body 1022 .
- the lead tip 1020 may be formed by any number of processes, such as half etching the external interconnects 1006 .
- the formation for the lead tip 1020 also forms the lead body 1022 .
- the lead body 1022 has a recess 1010 from a lead body top surface 1024 of the lead body 1022 .
- a lead body bottom surface 1026 of the lead body 1022 is used for connections to the next system level (not shown), such as a printed circuit board or another integrated circuit package system.
- a paddle 1004 is between the external interconnects 1006 .
- a paddle bottom surface 1028 of the paddle 1004 is in substantially the same horizontal plane as the lead body bottom surface 1026 .
- the paddle 1004 may be formed by any number of processes, such as by punch or stamp of a lead frame (not shown).
- a paddle top surface 1030 of the paddle 1004 is in substantially the same horizontal plane as the lead body top surface 1024 .
- the paddle 1004 from the paddle top surface 1030 has a depression 1005 .
- a device 1002 does not contact the paddle 1004 .
- the paddle 1004 may serve multiple functions, such as thermal dissipation or ground connection.
- the paddle top surface 1030 is described as in substantially the same horizontal plane as the lead body top surface 1024 , although it is understood that the paddle top surface 1030 and the lead body top surface 1024 may not be in substantially the same horizontal plane.
- the paddle bottom surface 1028 is described as in substantially the same horizontal plane as the lead body bottom surface 1026 , although it is understood that the paddle bottom surface 1028 and the lead body bottom surface 1026 may not be in substantially the same horizontal plane.
- the device 1002 such as an integrated circuit die, has a non-active side 1032 and an active side 1034 .
- the device 1002 is over the paddle 1004 and connect to the lead tip 1020 with an internal interconnect 1036 , such as a solder bump.
- the internal interconnect 1036 is on the active side 1034 .
- the connection of the internal interconnect 1036 do not fill the recess 1010 .
- An encapsulation 1018 such as a substantially electrically nonconductive material or an epoxy mold compound (EMC), fills the recess 1010 to provide mold locks for the integrated circuit package system 1000 .
- the encapsulation 1018 also fills the depression 1005 in the paddle 1004 providing improved adhesion between the encapsulation 1018 and the paddle 1004 .
- Each of external interconnects 1106 has a lead tip 1120 and a lead body 1122 .
- the lead tip 1120 may be formed by any number of processes, such as half etching the external interconnects 1 106 .
- the formation for the lead tip 1120 also forms the lead body 1122 .
- the lead body 1122 has a recess 1110 from a lead body top surface 1124 of the lead body 1122 .
- a lead body bottom surface 1126 of the lead body 1122 is used for connections to the next system level (not shown), such as a printed circuit board or another integrated circuit package system.
- a paddle 1104 is between the external interconnects 1106 .
- a paddle bottom surface 1128 of the paddle 1104 is in substantially the same horizontal plane as the lead body bottom surface 1126 .
- the paddle 1104 may be formed by any number of processes, such as by half etching.
- a paddle top surface 1130 of the paddle 1104 is below the lead body top surface 1124 .
- the paddle 1104 from the paddle top surface 1130 has a depression 1105 .
- the paddle 1104 may serve multiple functions, such as thermal dissipation or ground connection.
- the paddle top surface 1130 is described as not in substantially the same horizontal plane as the lead body top surface 1124 , although it is understood that the paddle top surface 1130 and the lead body top surface 1124 may be in substantially the same horizontal plane.
- the paddle bottom surface 1128 is described as in substantially the same horizontal plane as the lead body bottom surface 1126 , although it is understood that the paddle bottom surface 1128 and the lead body bottom surface 1126 may not be in substantially the same horizontal plane.
- a device 1102 such as an integrated circuit die, has a non-active side 1132 and an active side 1134 .
- the device 1102 is attached on the paddle 1104 with an adhesive 1136 , such as a substantially electrically nonconductive material or a die attach adhesive.
- the active side 1134 connect to the lead tip 1120 with an internal interconnect 1138 , such as bond wires.
- An encapsulation 1118 fills the recess 1110 to provide mold locks for the integrated circuit package system 1100 .
- the encapsulation 1118 also fills the depression 1105 not covered by the device 1102 or the adhesive 1136 providing improved adhesion between the encapsulation 1118 and the paddle 1104 .
- the adhesive 1136 such as a substantially electrically nonconductive material or an epoxy mold compound (EMC), may also fill the depression 1105 reducing the delamination of the device 1102 with the paddle 1104 .
- Each of external interconnects 1206 has a lead tip 1220 and a lead body 1222 .
- the lead tip 1220 may be formed by any number of processes, such as half etching the external interconnects 1206 .
- the formation for the lead tip 1220 also forms the lead body 1222 .
- the lead body 1222 has a recess 1210 from a lead body top surface 1224 of the lead body 1222 .
- a lead body bottom surface 1226 of the lead body 1222 is used for connections to the next system level (not shown), such as a printed circuit board or another integrated circuit package system.
- a paddle 1204 is between the external interconnects 1206 .
- a paddle bottom surface 1228 of the paddle 1204 is in substantially the same horizontal plane as the lead body bottom surface 1226 .
- the paddle 1204 may be formed by any number of processes, such as by punch or stamp of a lead frame (not shown).
- a paddle top surface 1230 of the paddle 1204 is in substantially the same horizontal plane as the lead body top surface 1224 .
- the paddle 1204 from the paddle top surface 1230 has a depression 1205 .
- the paddle 1204 may serve multiple functions, such as thermal dissipation or ground connection.
- the paddle top surface 1230 is described as in substantially the same horizontal plane as the lead body top surface 1224 , although it is understood that the paddle top surface 1230 and the lead body top surface 1224 may not be in substantially the same horizontal plane.
- the paddle bottom surface 1228 is described as in substantially the same horizontal plane as the lead body bottom surface 1226 , although it is understood that the paddle bottom surface 1228 and the lead body bottom surface 1226 may not be in substantially the same horizontal plane.
- a device 1202 such as an integrated circuit die, has a non-active side 1232 and an active side 1234 .
- the device 1202 is attached on the paddle 1204 with an adhesive 1236 , such as a substantially electrically nonconductive material or a die attach adhesive.
- the active side 1234 connect to the lead tip 1220 with an internal interconnect 1238 , such as bond wires.
- An encapsulation 1218 fills the recess 1210 to provide mold locks for the integrated circuit package system 1200 .
- the encapsulation 1218 also fills the depression 1205 not covered by the device 1202 or the adhesive 1236 providing improved adhesion between the encapsulation 1218 and the paddle 1204 .
- the adhesive 1236 may also fill the depression 1205 reducing the delamination of the device 1202 with the paddle 1204 .
- the integrated circuit package system 1300 includes a device 1302 , such as an integrated circuit die, over a paddle 1304 , such as die-attach paddle.
- the paddle 1304 includes a depression 1305 , such as an array of dimples, a moat, or a depression in a geometric shape of an x-mark.
- the device 1302 extends over a portion of external interconnects 1306 , such as leads, and tie bars 1308 .
- the tie bars 1308 connect to the corners of the paddle 1304 .
- Each of the external interconnects 1306 has a recess 1310 , such as an intersecting recess segments.
- the recess 1310 is located towards an edge of the integrated circuit package system 1300 .
- the recess 1310 has a first recess segment 1312 and a second recess segment 1314 .
- the first recess segment 1312 is along a length-wise dimension 1316 of the external interconnects 1306 .
- the second recess segment 1314 is perpendicular to the first recess segment 1312 .
- the recess 1310 has the first recess segment 1312 and three instances of the second recess segment 1314 .
- the recess 1310 areas shown has one instance of the first recess segment 1312 and three instances of the second recess segment 1314 , although it is understood that the number of the first recess segment 1312 and the second recess segment 1314 may differ.
- the configuration of the recess 1310 has the first recess segment 1312 orthogonal with the second recess segment 1314 , although it is understood that the first recess segment 1312 and the second recess segment 1314 may be in a different configuration.
- the external interconnects 1306 also have holes 1320 , such as through holes.
- the holes 1320 are located towards the interior portion, to the integrated circuit package system 1300 , of the external interconnects 1306 relative.
- the tie bars 1308 have slots 1322 .
- An encapsulation 1318 such as an epoxy mold compound, covers the device 1302 , the paddle 1304 , the tie bars 1308 , and the external interconnects 1306 .
- the encapsulation 1318 fills the recess 1310 in the external interconnects 1306 forming mold locks.
- the encapsulation 1318 also flows through and fills the holes 1320 in the external interconnects 1306 as well as the slots 1322 of the tie bars 1308 forming additional mold locks.
- the mold locks form structural reinforcement holding the encapsulation 1318 in place.
- the mold locks help resist delamination of the encapsulation and improves performance in moisture sensitivity level (MSL) test.
- MSL moisture sensitivity level
- the encapsulation 1318 such as substantially electrically nonconductive material or an epoxy mold compound (EMC), fills the depression 1305 in the paddle 1304 providing improved adhesion between the encapsulation 1318 and the paddle 1304 .
- the improved adhesion improves performance in moisture sensitivity level (MSL) test.
- the depression 1305 may be formed by any number of processes such as etching or half-etching the paddle 1304 .
- the device 1302 does not contact the paddle 1304 .
- FIG. 14 therein is shown a cross-sectional view of the integrated circuit package system 1300 of FIG. 13 .
- the cross-sectional view is along segment 14 - 14 in FIG. 13 .
- Each of the external interconnects 1306 has a lead tip 1402 and a lead body 1404 .
- the lead tip 1402 may be formed by any number of processes, such as half etching the external interconnects 1306 .
- the lead tip 1402 has the holes 1320 from a lead tip top surface 1406 to a lead tip bottom surface 1408 .
- the encapsulation 1318 fills the holes 1320 as well as the slots 1322 of FIG. 13 forming mold locks for the integrated circuit package system 1300 .
- the formation for the lead tip 1402 also forms the lead body 1404 .
- the lead body 1404 has the recess 1310 from a lead body top surface 1422 of the lead body 1404 .
- a lead body bottom surface 1412 of the lead body 1404 is used for connections to the next system level (not shown), such as a printed circuit board or another integrated circuit package system.
- the encapsulation 1318 also fills the recess 1310 to provide additional mold locks for the integrated circuit package system 1300 .
- the encapsulation 1318 further fills the depression 1305 in the paddle 1304 providing improved adhesion between the encapsulation 1318 and the paddle 1304 .
- the paddle 1304 is between the external interconnects 1306 .
- a paddle bottom surface 1410 of the paddle 1304 is in substantially the same horizontal plane as the lead body bottom surface 1412 .
- the paddle 1304 may be formed by any number of processes, such as by half etching.
- a paddle top surface 1414 of the paddle 1304 is below the lead body top surface 1422 .
- the paddle 1304 from the paddle top surface 1414 has the depression 1305 .
- the device 1302 does not contact the paddle 1304 .
- the paddle 1304 may serve multiple functions, such as thermal dissipation or ground connection.
- the paddle top surface 1414 is described as not in substantially the same horizontal plane as the lead body top surface 1422 , although it is understood that the paddle top surface 1414 and the lead body top surface 1422 may be in substantially the same horizontal plane.
- the paddle bottom surface 1410 is described as in substantially the same horizontal plane as the lead body bottom surface 1412 , although it is understood that the paddle bottom surface 1410 and the lead body bottom surface 1412 may not be in substantially the same horizontal plane.
- the device 1302 has a non-active side 1416 and an active side 1418 .
- the device 1302 is over the paddle 1304 and connect to the lead tip 1402 with an internal interconnect 1420 , such as a solder bump.
- the internal interconnect 1420 is on the active side 1418 .
- the connection of the internal interconnect 1420 do not fill the recess 1310 .
- the system 1500 includes forming a paddle having a depression from a paddle top surface and an external interconnect in a block 1502 ; forming a lead tip and a lead body of the external interconnect in a block 1504 ; connecting a device over the paddle top surface and the external interconnect in a block 1506 ; and filling a substantially electrically nonconductive material in the depression in a block 1508 .
- the present invention provides an integrated circuit package system with improved yield and reliability.
- the various mold lock features require less space, improves moldability, reduces delamination, and improves performance on reliability tests, such as moisture level sensitivity (MSL) test.
- MSL moisture level sensitivity
- An aspect is that the present invention provides increased metal to metal spacing for improved molding compound flow to form the encapsulation.
- the depression in the paddle, intersecting recess segments, the holes in the lead tips, or the slots in the tie bars do not require additional structure, such as a lug between the external leads, to form mold locks.
- Another aspect of the present invention provides depressions of various patterns in the paddle.
- the encapsulation fills the depression providing improved adhesion between the encapsulation and the paddle. This improved adhesion improves performance in moisture sensitivity level (MSL) test.
- MSL moisture sensitivity level
- Yet another aspect of the present invention provides depressions of various structures such that some depressions may be through the paddle while others may not.
- the die-attach adhesive may also fill the depressions or a portion of the depressions reducing the delamination of the device and the paddle.
- Yet another aspect of the present invention provides multiple mold lock features for a distributed and multi-dimensional locking structure support.
- the intersecting recess segments, the holes in the lead tips, and the slots in the tie bars as well as the paddle forms mold locks distributed throughout the integrated circuit package system.
- the distribution of mold locks provides support in all three dimensions of the integrated circuit package system package.
- Yet another aspect of the present invention provides structures for the mold lock features with improved adhesion between the leads as well as the tie bars and the encapsulation.
- Yet another aspect of the present invention provides mold lock features improves reliability performance.
- the distributed, multi-dimensional mold locks reduces delamination of the encapsulation and improves performance in moisture sensitivity level (MSL) tests.
- MSL moisture sensitivity level
- Yet another aspect of the present invention provides flexibility to select various mold locks locations in the possible locations provided by the distributed, multi-dimensional mold locks.
- the intersecting recess segments in the external interconnects, the slots in the tie bars, the holes in the external interconnects may be used individually or any combination thereof.
- Yet another important aspect of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.
- the integrated circuit package system method of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for improving reliability in systems.
- the resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile and effective, can be implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing integrated circuit package devices.
Abstract
Description
- The present application contains subject matter related to a concurrently filed U.S. Patent Application by Byung Tai Do and Sung Uk Yang entitled “Integrated Circuit Package System with Encapsulation Lock”. The related application is assigned to STATS ChipPAC Ltd and is identified by docket number 27-291.
- The present application also contains subject matter related to a concurrently filed U.S. Patent Application by Byung Tai Do and Sung Uk Yang entitled “Integrated Circuit Package System with Encapsulation Lock”. The related application is assigned to STATS ChipPAC Ltd and is identified by docket number 27-299.
- The present invention relates generally to integrated circuit packages and more particularly to molded integrated circuit packages.
- Modern electronics, such as smart phones, personal digital assistants, location based services devices, enterprise class servers, or enterprise class storage arrays, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. Contemporary electronics expose integrated circuits and packages to more demanding and sometimes new environmental conditions, such as cold, heat, and humidity requiring integrated circuit packages to provide robust structures.
- Numerous technologies have been developed to meet these requirements. Some of the research and development strategies focus on new technologies while others focus on improving the existing and mature technologies. Research and development in the existing technologies may take a myriad of different directions.
- One proven way to reduce cost is to use mature package technologies with existing manufacturing methods and equipments. Existing packaging technologies struggle to cost effectively meet the ever demanding thermal, reliability, and structural requirements of today's integrated circuits and packages.
- Most integrated circuit devices use molded plastic epoxy as an epoxy mold compound (EMC) for protecting package. But the poor heat dissipation property of EMC sometimes leads to device malfunctions. Some integrated circuit devices are large and/or very thin such that they become susceptible to warpage. Both heat and warpage may lead to delamination of the molding compound. The encapsulation delamination may also pose other problems, such as poor performance in moisture level sensitivity (MSL) tests.
- A variation of existing technologies uses mature package technologies with lead fingers made from lead frames. However, lead frame packages typically use bond wires electrically connecting the lead fingers to the integrated circuit. Another variation of existing technologies uses solder bumps on the integrated circuit with a flip chip mounting. Yet another variation combines flip chip style mounting with lead frame packages.
- The lead design of integrated circuit packages, such as quad flat nonleaded (QFN) packages, generally has a lug feature to provide locking between lead and mold compound. But, it adversely reduces metal-to-metal space and disturbs mold compound flow. This impact is bigger than other types of lead frame packages due to its inherently small size of the package. As a result, it causes reliability problem such as delamination between lead, tie-bar or paddle and mold compound or internal void. When it comes to the Flip Chip packages, die area covers more space above the paddle and some portion of leads as well and the problem tends to be more serious or more frequent.
- Thus, a need still remains for an integrated circuit package system providing low cost manufacturing and improved reliability for the integrated circuit package. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
- Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
- The present invention provides an integrated circuit package system including forming a paddle having a depression from a paddle top surface and an external interconnect, forming a lead tip and a lead body of the external interconnect, connecting a device over the paddle top surface and the external interconnect, and filling a substantially electrically nonconductive material in the depression.
- Certain embodiments of the invention have other aspects in addition to or in place of those mentioned or obvious from the above. The aspects will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.
-
FIG. 1 is a plan view of an integrated circuit package system in an embodiment of the present invention; -
FIG. 2 is a cross-sectional view of the integrated circuit package system ofFIG. 1 ; -
FIG. 3 is a plan view of an integrated circuit package system in an alternative embodiment of the present invention; -
FIG. 4 is a cross-sectional view of the integrated circuit package system ofFIG. 3 ; -
FIG. 5 is a plan view of an integrated circuit package system in another alternative embodiment of the present invention; -
FIG. 6 is a cross-sectional view of the integrated circuit package system ofFIG. 5 ; -
FIG. 7 is a more detailed plan view of a portion of the external interconnects ofFIG. 5 ; -
FIG. 8 is a cross-sectional view of the portion of the external interconnects ofFIG. 7 ; -
FIG. 9 is a different cross-sectional view of the portion of the external interconnects ofFIG. 7 ; -
FIG. 10 is a cross-sectional view of an integrated circuit package system in yet another alternative embodiment of the present invention; -
FIG. 11 is a cross-sectional view of an integrated circuit package system in yet another alternative embodiment of the present invention; -
FIG. 12 is a cross-sectional view of an integrated circuit package system in yet another alternative embodiment of the present invention; -
FIG. 13 is a plan view of an integrated circuit package system in yet another embodiment of the present invention; -
FIG. 14 is a cross-sectional view of the integrated circuit package system ofFIG. 13 ; and -
FIG. 15 is a flow chart of an integrated circuit package system for manufacture of the integrated circuit package system in an embodiment of the present invention. - In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the apparatus are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the figures. In addition, where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with like reference numerals.
- The term “horizontal” as used herein is defined as a plane parallel to the conventional integrated circuit surface, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means there is direct contact among elements.
- The term “processing” as used herein includes deposition of material, patterning, exposure, development, etching, cleaning, molding, and/or removal of the material or as required in forming a described structure.
- Referring now to
FIG. 1 , therein is shown a plan view of an integratedcircuit package system 100 in an embodiment of the present invention. The integratedcircuit package system 100 includes adevice 102, such as an integrated circuit die, over apaddle 104, such as die-attach paddle. Thepaddle 104 includes adepression 105, such as an array of dimples, a moat, or a depression in a geometric shape of an x-mark. Thedevice 102 extends over a portion ofexternal interconnects 106, such as leads, and tie bars 108. The tie bars 108 connect to the corners of thepaddle 104. - An
encapsulation 118, such as an epoxy mold compound, covers thedevice 102, thepaddle 104, the tie bars 108, and theexternal interconnects 106. Theencapsulation 118 fills thedepression 105, wherein theencapsulation 118 is a substantially electrically nonconductive material such as an epoxy mold compound (EMC). - Referring now to
FIG. 2 , therein is shown a cross-sectional view of the integratedcircuit package system 100 ofFIG. 1 . The cross-sectional view is along segment 2-2 inFIG. 1 . Each of theexternal interconnects 106 has alead tip 202 and alead body 204. Thelead tip 202 may be formed by any number of processes, such as half etching theexternal interconnects 106. The formation for thelead tip 202 also forms thelead body 204. Thelead tip 202 has a lead tiptop surface 206 to a lead tipbottom surface 208. - The
paddle 104 is between theexternal interconnects 106. Apaddle bottom surface 210 of thepaddle 104 is in substantially the same horizontal plane as a lead bodybottom surface 212. Thepaddle 104 may be formed by any number of processes, such as by half etching. Thedepression 105 is from a paddletop surface 214 of thepaddle 104. The paddletop surface 214 is below the lead tiptop surface 206. Thepaddle 104 may serve multiple functions, such as thermal dissipation or ground connection. - The
encapsulation 118 fills thedepression 105 in thepaddle 104 providing improved adhesion between theencapsulation 118 and thepaddle 104. The improved adhesion improves performance in moisture sensitivity level (MSL) test. Thedepression 105 may be formed by any number of processes such as etching or half-etching thepaddle 104. Thedevice 102 does not contact thepaddle 104. - For illustrative purposes, the
depression 105 is shown from the paddletop surface 214 and not extending to the paddlebottom surface 210, although it is understood that thedepression 105 or a portion of thedepression 105 may traverse through thepaddle 104. Also for illustrative purposes, the paddletop surface 214 is described as below the same horizontal plane as the lead tiptop surface 206, although it is understood that the paddletop surface 214 may not be below the lead tiptop surface 206. Further for illustrative purposes, the paddlebottom surface 210 is described as in substantially the same horizontal plane as the lead bodybottom surface 212, although it is understood that the paddlebottom surface 210 and the lead bodybottom surface 212 may not be in substantially the same horizontal plane. - The
device 102 has anon-active side 216 and anactive side 218. Thedevice 102 is over thepaddle 104 and connect to thelead tip 202 with aninternal interconnect 220, such as a solder bump. Theinternal interconnect 220 is on theactive side 218. - Referring now to
FIG. 3 , therein is shown a plan view of an integratedcircuit package system 300 in an alternative embodiment of the present invention. The integratedcircuit package system 300 includes adevice 302, such as an integrated circuit die, over apaddle 304, such as die-attach paddle. Thepaddle 304 includes adepression 305, such as an array of dimples, a moat, or a depression in a geometric shape of an x-mark. Thedevice 302 extends over a portion ofexternal interconnects 306, such as leads, and tie bars 308. The tie bars 308 connect to the corners of thepaddle 304. - The
external interconnects 306 haveholes 320, such as through holes. Theholes 320 are located towards the interior portion, to the integratedcircuit package system 300, of theexternal interconnects 306 relative. The tie bars 308 haveslots 322. - An
encapsulation 318, such as an epoxy mold compound, covers thedevice 302, thepaddle 304, the tie bars 308, and theexternal interconnects 306. Theencapsulation 318 flows through and fills theholes 320 in theexternal interconnects 306 as well as theslots 322 of the tie bars 308 forming mold locks. The mold locks form structural reinforcement holding theencapsulation 318 in place. The mold locks help resist delamination of the encapsulation and improves performance in moisture sensitivity level (MSL) test. Theencapsulation 318 also fills thedepression 305 in thepaddle 304, wherein theencapsulation 318 is a substantially electrically nonconductive material such as an epoxy mold compound (EMC). - For illustrative purpose, the tie bars 308 are shown having two instances of the
slots 322, although it is understood that the number of theslots 322 may differ. Also for illustrative purposes, theslots 322 are shown as a substantially the same, although it is understood that theslots 322 may differ from one another. - Referring now to
FIG. 4 , therein is shown a cross-sectional view of the integratedcircuit package system 300 ofFIG. 3 . The cross-sectional view is along segment 4-4 inFIG. 3 . Each of theexternal interconnects 306 has alead tip 402 and alead body 404. Thelead tip 402 may be formed by any number of processes, such as half etching theexternal interconnects 306. The formation for thelead tip 402 also forms thelead body 404. Thelead tip 402 has theholes 320 from a lead tiptop surface 406 to a lead tipbottom surface 408. - The
paddle 304 is between theexternal interconnects 306. Apaddle bottom surface 410 of thepaddle 304 is in substantially the same horizontal plane as a lead bodybottom surface 412. Thepaddle 304 may be formed by any number of processes, such as by half etching. Thedepression 305 is from a paddletop surface 414 of thepaddle 304. The paddletop surface 414 is below the lead tiptop surface 406. Thepaddle 304 may serve multiple functions, such as thermal dissipation or ground connection. - The
encapsulation 318 fills thedepression 305 in thepaddle 304 providing improved adhesion between theencapsulation 318 and thepaddle 304. The improved adhesion improves performance in moisture sensitivity level (MSL) test. Thedepression 305 may be formed by any number of processes such as etching or half-etching thepaddle 304. Thedevice 302 does not contact thepaddle 304. - For illustrative purpose, the
depression 305 is shown from the paddletop surface 414 and not extending to the paddlebottom surface 410, although it is understood that thedepression 305 or a portion of thedepression 305 may traverse through thepaddle 304. Also for illustrative purpose, the paddletop surface 414 is described as below the same horizontal plane as the lead tiptop surface 406, although it is understood that the paddletop surface 414 may not be below the lead tiptop surface 406. Further for illustrative purposes, the paddlebottom surface 410 is described as in substantially the same horizontal plane as the lead bodybottom surface 412, although it is understood that the paddlebottom surface 410 and the lead bodybottom surface 412 may not be in substantially the same horizontal plane. - The
device 302 has anon-active side 416 and anactive side 418. Thedevice 302 is over thepaddle 304 and connect to thelead tip 402 with aninternal interconnect 420, such as a solder bump. Theinternal interconnect 420 is on theactive side 418. The connection of theinternal interconnect 420 do not fill theholes 320. Theencapsulation 318 fills theholes 320 to provide mold locks for the integratedcircuit package system 300. - Referring now to
FIG. 5 , therein is shown a plan view of an integratedcircuit package system 500 in another alternative embodiment of the present invention. The integratedcircuit package system 500 includes adevice 502, such as an integrated circuit die, over apaddle 504, such as die-attach paddle. Thepaddle 504 includes adepression 505, such as an array of dimples, a moat, or a depression in a geometric shape of an x-mark. Thedevice 502 extends over a portion ofexternal interconnects 506, such as leads, and tie bars 508. The tie bars 508 connect to the corners of thepaddle 504. - Each of the
external interconnects 506 has arecess 510, such as an intersecting recess segments. Therecess 510 is located towards an edge of the integratedcircuit package system 500. Therecess 510 has afirst recess segment 512 and asecond recess segment 514. Thefirst recess segment 512 is along alength-wise dimension 516 of theexternal interconnects 506. Thesecond recess segment 514 is perpendicular to thefirst recess segment 512. Therecess 510 has thefirst recess segment 512 and three instances of thesecond recess segment 514. - For illustrative purposes, the
recess 510 areas shown has one instance of thefirst recess segment 512 and three instances of thesecond recess segment 514, although it is understood that the number of thefirst recess segment 512 and thesecond recess segment 514 may differ. Also for illustrative purposes, the configuration of therecess 510 has thefirst recess segment 512 orthogonal with thesecond recess segment 514, although it is understood that thefirst recess segment 512 and thesecond recess segment 514 may be in a different configuration. Further, for illustrative purposes, therecess 510 is shown having both thefirst recess segment 512 and thesecond recess segment 514, although it is understood that therecess 510 may not have both thefirst recess segment 512 and thesecond recess segment 514. - An
encapsulation 518, such as an epoxy mold compound, covers thedevice 502, thepaddle 504, the tie bars 508, and theexternal interconnects 506. Theencapsulation 518 fills therecess 510 in theexternal interconnects 506 forming mold locks. The tie bars 508 and thepaddle 504 also provide mold locks. The mold locks form structural reinforcement holding theencapsulation 518 in place. The mold locks help resist delamination of the encapsulation and improves performance in moisture sensitivity level (MSL) test. Theencapsulation 518 also fills thedepression 505 in thepaddle 504, wherein theencapsulation 518 is a substantially electrically nonconductive material such as an epoxy mold compound (EMC). - Referring now to
FIG. 6 , therein is shown a cross-sectional view of the integratedcircuit package system 500 ofFIG. 5 . The cross-sectional view is along segment 6-6 inFIG. 5 . Each of theexternal interconnects 506 has alead tip 602 and alead body 604. Thelead tip 602 may be formed by any number of processes, such as half etching theexternal interconnects 506. - The formation for the
lead tip 602 also forms thelead body 604. Thelead body 604 has therecess 510 from a lead bodytop surface 606 of thelead body 604. A lead bodybottom surface 608 of thelead body 604 is used for connections to the next system level (not shown), such as a printed circuit board or another integrated circuit package system. - The
paddle 504 is between theexternal interconnects 506. Apaddle bottom surface 610 of thepaddle 504 is in substantially the same horizontal plane as the lead bodybottom surface 608. Thepaddle 504 may be formed by any number of processes, such as by half etching. A paddletop surface 612 of thepaddle 504 is below the lead bodytop surface 606. Thepaddle 504 may serve multiple functions, such as thermal dissipation or ground connection. - The
encapsulation 518 fills thedepression 505 in thepaddle 504 providing improved adhesion between theencapsulation 518 and thepaddle 504. The improved adhesion improves performance in moisture sensitivity level (MSL) test. Thedepression 505 may be formed by any number of processes such as etching or half-etching thepaddle 504. Thedevice 502 does not contact thepaddle 504. - For illustrative purposes, the
depression 505 is shown from the paddletop surface 612 and not extending to the paddlebottom surface 610, although it is understood that thedepression 505 or a portion of thedepression 505 may traverse through thepaddle 504. Also for illustrative purposes, the paddletop surface 612 is described as not in substantially the same horizontal plane as the lead bodytop surface 606, although it is understood that the paddletop surface 612 and the lead bodytop surface 606 may be in substantially the same horizontal plane. Further for illustrative purposes, the paddlebottom surface 610 is described as in substantially the same horizontal plane as the lead bodybottom surface 608, although it is understood that the paddlebottom surface 610 and the lead bodybottom surface 608 may not be in substantially the same horizontal plane. - The
device 502 has anon-active side 614 and anactive side 616. Thedevice 502 is over thepaddle 504 and connect to thelead tip 602 with aninternal interconnect 618, such as a solder bump. Theinternal interconnect 618 is on theactive side 616. The connection of theinternal interconnect 618 do not fill the recess 5 10. - Referring now to
FIG. 7 , therein is shown a more detailed plan view of a portion of theexternal interconnects 506 ofFIG. 7 . This view depicts the portion of theexternal interconnects 506, such as a firstexternal interconnect 702 and a secondexternal interconnect 704. - The first
external interconnect 702 has a firstlead body 706 and afirst lead tip 708. Thefirst lead tip 708 is shown as a substantially straight segment extending from the firstlead body 706. One instance of therecess 510 is in the firstlead body 706. The secondexternal interconnect 704 has a secondlead body 710 and asecond lead tip 712 Thesecond lead tip 712 extends from the secondlead body 710 with a displacement portion such that a tip end of thesecond lead tip 712 does not extend substantially straight from a body end of thesecond lead tip 712 next to the secondlead body 710. - The
first recess segment 512 has an orientation substantially parallel to thelength-wise dimension 516 of the firstlead body 706. Thesecond recess segment 514 is perpendicular to and intersects thefirst recess segment 512 in the firstlead body 706. Similarly, one instance of therecess 510 is also part of the secondlead body 710. Thefirst recess segment 512 and thesecond recess segment 514 are in a similar configuration in the secondexternal interconnect 704 as in the firstexternal interconnect 702. - The
encapsulation 518 ofFIG. 5 fills in therecess 510, such as thefirst recess segment 512 and thesecond recess segment 514, to form a mold lock from the top of thelead body 604, such as the firstlead body 706 and the secondlead body 710. Therecess 510, with the intersecting pattern, is part of the mold lock in the horizontal dimensions of the integratedcircuit package system 500 ofFIG. 5 . - Referring now to
FIG. 8 , therein is shown a cross-sectional view of the portion of theexternal interconnects 506 ofFIG. 7 . The cross-sectional view is along the segment 8-8 inFIG. 7 showing the cross sections of the firstlead body 706 and the secondlead body 710. - The first
lead body 706 has thesecond recess segment 514 in a curve shape from the lead bodytop surface 606. Thefirst recess segment 512 is shown as another recess to the second intersecting recess segment and at a bottom portion of thesecond recess segment 514. Thefirst recess segment 512 and thesecond recess segment 514 do not extend through the lead bodybottom surface 608 of both the firstlead body 706 and the secondlead body 710. Theencapsulation 518 fills thefirst recess segment 512 and thesecond recess segment 514. - Referring now to
FIG. 9 , therein is shown a different cross-sectional view of the portion of theexternal interconnects 506 ofFIG. 7 . The cross-sectional view is along the segment 9-9 inFIG. 7 showing the cross section of the secondexternal interconnect 704 and may represent a similar cross section of any of theexternal interconnects 506 ofFIG. 5 . - This cross section shows the
second lead tip 712 and the secondlead body 710. An outline of thefirst recess segment 512 is shown as having a curve shape at the ends and flat in the middle. Thefirst recess segment 512 is shown from the lead bodytop surface 606 and within the secondlead body 710 while not part of thesecond lead tip 712. As mentioned earlier, thefirst recess segment 512 does not extend to the lead bodybottom surface 608. - As mentioned earlier, the
encapsulation 518 fills in therecess 510. Therecess 510, with thepaddle 504 ofFIG. 5 and thelead tip 602 ofFIG. 6 , are also part of the mold lock in the vertical dimensions of the integratedcircuit package system 300 ofFIG. 5 . - Referring now to
FIG. 10 , therein is shown a cross-sectional view of an integratedcircuit package system 1000 in yet another alternative embodiment of the present invention. This cross-sectional view may represent the cross section of the integratedcircuit package system 500 along segment 6-6 inFIG. 5 . Each ofexternal interconnects 1006 has alead tip 1020 and alead body 1022. Thelead tip 1020 may be formed by any number of processes, such as half etching theexternal interconnects 1006. - The formation for the
lead tip 1020 also forms thelead body 1022. Thelead body 1022 has arecess 1010 from a leadbody top surface 1024 of thelead body 1022. A leadbody bottom surface 1026 of thelead body 1022 is used for connections to the next system level (not shown), such as a printed circuit board or another integrated circuit package system. - A
paddle 1004 is between theexternal interconnects 1006. Apaddle bottom surface 1028 of thepaddle 1004 is in substantially the same horizontal plane as the leadbody bottom surface 1026. Thepaddle 1004 may be formed by any number of processes, such as by punch or stamp of a lead frame (not shown). Apaddle top surface 1030 of thepaddle 1004 is in substantially the same horizontal plane as the leadbody top surface 1024. Thepaddle 1004 from thepaddle top surface 1030 has adepression 1005. Adevice 1002 does not contact thepaddle 1004. Thepaddle 1004 may serve multiple functions, such as thermal dissipation or ground connection. - For illustrative purpose, the
paddle top surface 1030 is described as in substantially the same horizontal plane as the leadbody top surface 1024, although it is understood that thepaddle top surface 1030 and the leadbody top surface 1024 may not be in substantially the same horizontal plane. Also for illustrative purposes, thepaddle bottom surface 1028 is described as in substantially the same horizontal plane as the leadbody bottom surface 1026, although it is understood that thepaddle bottom surface 1028 and the leadbody bottom surface 1026 may not be in substantially the same horizontal plane. - The
device 1002, such as an integrated circuit die, has anon-active side 1032 and anactive side 1034. Thedevice 1002 is over thepaddle 1004 and connect to thelead tip 1020 with aninternal interconnect 1036, such as a solder bump. Theinternal interconnect 1036 is on theactive side 1034. The connection of theinternal interconnect 1036 do not fill therecess 1010. - An
encapsulation 1018, such as a substantially electrically nonconductive material or an epoxy mold compound (EMC), fills therecess 1010 to provide mold locks for the integratedcircuit package system 1000. Theencapsulation 1018 also fills thedepression 1005 in thepaddle 1004 providing improved adhesion between theencapsulation 1018 and thepaddle 1004. - Referring now to
FIG. 11 , therein is shown a cross-sectional view of an integratedcircuit package system 1100 in yet another alternative embodiment of the present invention. Each ofexternal interconnects 1106 has alead tip 1120 and alead body 1122. Thelead tip 1120 may be formed by any number of processes, such as half etching the external interconnects 1 106. - The formation for the
lead tip 1120 also forms thelead body 1122. Thelead body 1122 has arecess 1110 from a leadbody top surface 1124 of thelead body 1122. A leadbody bottom surface 1126 of thelead body 1122 is used for connections to the next system level (not shown), such as a printed circuit board or another integrated circuit package system. - A
paddle 1104 is between theexternal interconnects 1106. Apaddle bottom surface 1128 of thepaddle 1104 is in substantially the same horizontal plane as the leadbody bottom surface 1126. Thepaddle 1104 may be formed by any number of processes, such as by half etching. Apaddle top surface 1130 of thepaddle 1104 is below the leadbody top surface 1124. Thepaddle 1104 from thepaddle top surface 1130 has adepression 1105. Thepaddle 1104 may serve multiple functions, such as thermal dissipation or ground connection. - For illustrative purpose, the
paddle top surface 1130 is described as not in substantially the same horizontal plane as the leadbody top surface 1124, although it is understood that thepaddle top surface 1130 and the leadbody top surface 1124 may be in substantially the same horizontal plane. Also for illustrative purposes, thepaddle bottom surface 1128 is described as in substantially the same horizontal plane as the leadbody bottom surface 1126, although it is understood that thepaddle bottom surface 1128 and the leadbody bottom surface 1126 may not be in substantially the same horizontal plane. - A
device 1102, such as an integrated circuit die, has anon-active side 1132 and anactive side 1134. Thedevice 1102 is attached on thepaddle 1104 with an adhesive 1136, such as a substantially electrically nonconductive material or a die attach adhesive. Theactive side 1134 connect to thelead tip 1120 with aninternal interconnect 1138, such as bond wires. - An
encapsulation 1118 fills therecess 1110 to provide mold locks for the integratedcircuit package system 1100. Theencapsulation 1118 also fills thedepression 1105 not covered by thedevice 1102 or the adhesive 1136 providing improved adhesion between theencapsulation 1118 and thepaddle 1104. The adhesive 1136, such as a substantially electrically nonconductive material or an epoxy mold compound (EMC), may also fill thedepression 1105 reducing the delamination of thedevice 1102 with thepaddle 1104. - Referring now to
FIG. 12 , therein is shown a cross-sectional view of an integratedcircuit package system 1200 in yet another alternative embodiment of the present invention. Each ofexternal interconnects 1206 has alead tip 1220 and alead body 1222. Thelead tip 1220 may be formed by any number of processes, such as half etching theexternal interconnects 1206. - The formation for the
lead tip 1220 also forms thelead body 1222. Thelead body 1222 has arecess 1210 from a leadbody top surface 1224 of thelead body 1222. A leadbody bottom surface 1226 of thelead body 1222 is used for connections to the next system level (not shown), such as a printed circuit board or another integrated circuit package system. - A
paddle 1204 is between theexternal interconnects 1206. Apaddle bottom surface 1228 of thepaddle 1204 is in substantially the same horizontal plane as the leadbody bottom surface 1226. Thepaddle 1204 may be formed by any number of processes, such as by punch or stamp of a lead frame (not shown). Apaddle top surface 1230 of thepaddle 1204 is in substantially the same horizontal plane as the leadbody top surface 1224. Thepaddle 1204 from thepaddle top surface 1230 has adepression 1205. Thepaddle 1204 may serve multiple functions, such as thermal dissipation or ground connection. - For illustrative purpose, the
paddle top surface 1230 is described as in substantially the same horizontal plane as the leadbody top surface 1224, although it is understood that thepaddle top surface 1230 and the leadbody top surface 1224 may not be in substantially the same horizontal plane. Also for illustrative purposes, thepaddle bottom surface 1228 is described as in substantially the same horizontal plane as the leadbody bottom surface 1226, although it is understood that thepaddle bottom surface 1228 and the leadbody bottom surface 1226 may not be in substantially the same horizontal plane. - A
device 1202, such as an integrated circuit die, has anon-active side 1232 and anactive side 1234. Thedevice 1202 is attached on thepaddle 1204 with an adhesive 1236, such as a substantially electrically nonconductive material or a die attach adhesive. Theactive side 1234 connect to thelead tip 1220 with aninternal interconnect 1238, such as bond wires. - An
encapsulation 1218 fills therecess 1210 to provide mold locks for the integratedcircuit package system 1200. Theencapsulation 1218 also fills thedepression 1205 not covered by thedevice 1202 or the adhesive 1236 providing improved adhesion between theencapsulation 1218 and thepaddle 1204. The adhesive 1236 may also fill thedepression 1205 reducing the delamination of thedevice 1202 with thepaddle 1204. - Referring now to
FIG. 13 , therein is shown a plan view of an integratedcircuit package system 1300 in yet another embodiment of the present invention. The integratedcircuit package system 1300 includes adevice 1302, such as an integrated circuit die, over apaddle 1304, such as die-attach paddle. Thepaddle 1304 includes adepression 1305, such as an array of dimples, a moat, or a depression in a geometric shape of an x-mark. Thedevice 1302 extends over a portion ofexternal interconnects 1306, such as leads, and tie bars 1308. The tie bars 1308 connect to the corners of thepaddle 1304. - Each of the
external interconnects 1306 has arecess 1310, such as an intersecting recess segments. Therecess 1310 is located towards an edge of the integratedcircuit package system 1300. Therecess 1310 has a first recess segment 1312 and a second recess segment 1314. The first recess segment 1312 is along alength-wise dimension 1316 of theexternal interconnects 1306. The second recess segment 1314 is perpendicular to the first recess segment 1312. Therecess 1310 has the first recess segment 1312 and three instances of the second recess segment 1314. - For illustrative purposes, the
recess 1310 areas shown has one instance of the first recess segment 1312 and three instances of the second recess segment 1314, although it is understood that the number of the first recess segment 1312 and the second recess segment 1314 may differ. Also for illustrative purposes, the configuration of therecess 1310 has the first recess segment 1312 orthogonal with the second recess segment 1314, although it is understood that the first recess segment 1312 and the second recess segment 1314 may be in a different configuration. - The
external interconnects 1306 also haveholes 1320, such as through holes. Theholes 1320 are located towards the interior portion, to the integratedcircuit package system 1300, of theexternal interconnects 1306 relative. The tie bars 1308 haveslots 1322. - An
encapsulation 1318, such as an epoxy mold compound, covers thedevice 1302, thepaddle 1304, the tie bars 1308, and theexternal interconnects 1306. Theencapsulation 1318 fills therecess 1310 in theexternal interconnects 1306 forming mold locks. Theencapsulation 1318 also flows through and fills theholes 1320 in theexternal interconnects 1306 as well as theslots 1322 of the tie bars 1308 forming additional mold locks. The mold locks form structural reinforcement holding theencapsulation 1318 in place. The mold locks help resist delamination of the encapsulation and improves performance in moisture sensitivity level (MSL) test. - The
encapsulation 1318, such as substantially electrically nonconductive material or an epoxy mold compound (EMC), fills thedepression 1305 in thepaddle 1304 providing improved adhesion between theencapsulation 1318 and thepaddle 1304. The improved adhesion improves performance in moisture sensitivity level (MSL) test. Thedepression 1305 may be formed by any number of processes such as etching or half-etching thepaddle 1304. Thedevice 1302 does not contact thepaddle 1304. - Referring now to
FIG. 14 , therein is shown a cross-sectional view of the integratedcircuit package system 1300 ofFIG. 13 . The cross-sectional view is along segment 14-14 inFIG. 13 . Each of theexternal interconnects 1306 has alead tip 1402 and alead body 1404. Thelead tip 1402 may be formed by any number of processes, such as half etching theexternal interconnects 1306. Thelead tip 1402 has theholes 1320 from a leadtip top surface 1406 to a leadtip bottom surface 1408. Theencapsulation 1318 fills theholes 1320 as well as theslots 1322 ofFIG. 13 forming mold locks for the integratedcircuit package system 1300. - The formation for the
lead tip 1402 also forms thelead body 1404. Thelead body 1404 has therecess 1310 from a leadbody top surface 1422 of thelead body 1404. A leadbody bottom surface 1412 of thelead body 1404 is used for connections to the next system level (not shown), such as a printed circuit board or another integrated circuit package system. Theencapsulation 1318 also fills therecess 1310 to provide additional mold locks for the integratedcircuit package system 1300. Theencapsulation 1318 further fills thedepression 1305 in thepaddle 1304 providing improved adhesion between theencapsulation 1318 and thepaddle 1304. - The
paddle 1304 is between theexternal interconnects 1306. Apaddle bottom surface 1410 of thepaddle 1304 is in substantially the same horizontal plane as the leadbody bottom surface 1412. Thepaddle 1304 may be formed by any number of processes, such as by half etching. Apaddle top surface 1414 of thepaddle 1304 is below the leadbody top surface 1422. Thepaddle 1304 from thepaddle top surface 1414 has thedepression 1305. Thedevice 1302 does not contact thepaddle 1304. Thepaddle 1304 may serve multiple functions, such as thermal dissipation or ground connection. - For illustrative purpose, the
paddle top surface 1414 is described as not in substantially the same horizontal plane as the leadbody top surface 1422, although it is understood that thepaddle top surface 1414 and the leadbody top surface 1422 may be in substantially the same horizontal plane. Also for illustrative purposes, thepaddle bottom surface 1410 is described as in substantially the same horizontal plane as the leadbody bottom surface 1412, although it is understood that thepaddle bottom surface 1410 and the leadbody bottom surface 1412 may not be in substantially the same horizontal plane. - The
device 1302 has anon-active side 1416 and anactive side 1418. Thedevice 1302 is over thepaddle 1304 and connect to thelead tip 1402 with aninternal interconnect 1420, such as a solder bump. Theinternal interconnect 1420 is on theactive side 1418. The connection of theinternal interconnect 1420 do not fill therecess 1310. - Referring now to
FIG. 15 , therein is shown a flow chart of an integratedcircuit package system 1500 for manufacture of the integratedcircuit package system 100 in an embodiment of the present invention. Thesystem 1500 includes forming a paddle having a depression from a paddle top surface and an external interconnect in ablock 1502; forming a lead tip and a lead body of the external interconnect in ablock 1504; connecting a device over the paddle top surface and the external interconnect in ablock 1506; and filling a substantially electrically nonconductive material in the depression in ablock 1508. - It has been discovered that the present invention thus has numerous aspects.
- It has been discovered that the present invention provides an integrated circuit package system with improved yield and reliability. The various mold lock features require less space, improves moldability, reduces delamination, and improves performance on reliability tests, such as moisture level sensitivity (MSL) test.
- An aspect is that the present invention provides increased metal to metal spacing for improved molding compound flow to form the encapsulation. The depression in the paddle, intersecting recess segments, the holes in the lead tips, or the slots in the tie bars do not require additional structure, such as a lug between the external leads, to form mold locks.
- Another aspect of the present invention provides depressions of various patterns in the paddle. The encapsulation fills the depression providing improved adhesion between the encapsulation and the paddle. This improved adhesion improves performance in moisture sensitivity level (MSL) test.
- Yet another aspect of the present invention provides depressions of various structures such that some depressions may be through the paddle while others may not. The die-attach adhesive may also fill the depressions or a portion of the depressions reducing the delamination of the device and the paddle.
- Yet another aspect of the present invention provides multiple mold lock features for a distributed and multi-dimensional locking structure support. The intersecting recess segments, the holes in the lead tips, and the slots in the tie bars as well as the paddle forms mold locks distributed throughout the integrated circuit package system. The distribution of mold locks provides support in all three dimensions of the integrated circuit package system package.
- Yet another aspect of the present invention provides structures for the mold lock features with improved adhesion between the leads as well as the tie bars and the encapsulation.
- Yet another aspect of the present invention provides mold lock features improves reliability performance. The distributed, multi-dimensional mold locks reduces delamination of the encapsulation and improves performance in moisture sensitivity level (MSL) tests.
- Yet another aspect of the present invention provides flexibility to select various mold locks locations in the possible locations provided by the distributed, multi-dimensional mold locks. The intersecting recess segments in the external interconnects, the slots in the tie bars, the holes in the external interconnects may be used individually or any combination thereof.
- Yet another important aspect of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.
- These and other valuable aspects of the present invention consequently further the state of the technology to at least the next level.
- Thus, it has been discovered that the integrated circuit package system method of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for improving reliability in systems. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile and effective, can be implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing integrated circuit package devices.
- While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters hithertofore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.
Claims (20)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/532,508 US20080067639A1 (en) | 2006-09-15 | 2006-09-15 | Integrated circuit package system with encapsulation lock |
US12/690,092 US7919838B2 (en) | 2006-09-15 | 2010-01-19 | Integrated circuit package system with encapsulation lock and method of manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/532,508 US20080067639A1 (en) | 2006-09-15 | 2006-09-15 | Integrated circuit package system with encapsulation lock |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/690,092 Continuation US7919838B2 (en) | 2006-09-15 | 2010-01-19 | Integrated circuit package system with encapsulation lock and method of manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080067639A1 true US20080067639A1 (en) | 2008-03-20 |
Family
ID=39187709
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/532,508 Abandoned US20080067639A1 (en) | 2006-09-15 | 2006-09-15 | Integrated circuit package system with encapsulation lock |
US12/690,092 Active US7919838B2 (en) | 2006-09-15 | 2010-01-19 | Integrated circuit package system with encapsulation lock and method of manufacture thereof |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/690,092 Active US7919838B2 (en) | 2006-09-15 | 2010-01-19 | Integrated circuit package system with encapsulation lock and method of manufacture thereof |
Country Status (1)
Country | Link |
---|---|
US (2) | US20080067639A1 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080067698A1 (en) * | 2006-09-15 | 2008-03-20 | Stats Chippac Ltd. | Integrated circuit package system with encapsulation lock |
US20080067640A1 (en) * | 2006-09-15 | 2008-03-20 | Stats Chippac Ltd. | Integrated circuit package system with encapsulation lock |
US20090152694A1 (en) * | 2007-12-12 | 2009-06-18 | Infineon Technologies Ag | Electronic device |
US20110248393A1 (en) * | 2010-04-09 | 2011-10-13 | Freescale Semiconductor, Inc | Lead frame for semiconductor device |
US20130069214A1 (en) * | 2011-09-21 | 2013-03-21 | Renesas Electronics Corporation | Lead frame, semiconductor device, method of manufacturing lead frame, and method of manufacturing semiconductor device |
US8604596B2 (en) | 2011-03-24 | 2013-12-10 | Stats Chippac Ltd. | Integrated circuit packaging system with locking interconnects and method of manufacture thereof |
WO2021107769A1 (en) * | 2019-11-29 | 2021-06-03 | Ampleon Netherlands B.V. | Lead frame based molded radio frequency package |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7923846B2 (en) * | 2007-11-16 | 2011-04-12 | Stats Chippac Ltd. | Integrated circuit package-in-package system with wire-in-film encapsulant |
US8710636B1 (en) * | 2013-02-04 | 2014-04-29 | Freescale Semiconductor, Inc. | Lead frame array package with flip chip die attach |
MY184608A (en) * | 2013-12-10 | 2021-04-07 | Carsem M Sdn Bhd | Pre-molded integrated circuit packages |
Citations (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5753969A (en) * | 1995-08-15 | 1998-05-19 | Kabushiki Kaisha Toshiba | Resin sealed semiconductor device including a die pad uniformly having heat conducting paths and circulating holes for fluid resin |
US5973388A (en) * | 1998-01-26 | 1999-10-26 | Motorola, Inc. | Leadframe, method of manufacturing a leadframe, and method of packaging an electronic component utilizing the leadframe |
US6127206A (en) * | 1997-03-24 | 2000-10-03 | Seiko Epson Corporation | Semiconductor device substrate, lead frame, semiconductor device and method of making the same, circuit board, and electronic apparatus |
US6166430A (en) * | 1998-05-27 | 2000-12-26 | Matsushita Electronics Corporation | Lead frame, method for manufacturing the frame, resin-molded semiconductor device and method for manufacturing the device |
US6197615B1 (en) * | 1997-04-04 | 2001-03-06 | Samsung Electronics Co., Ltd. | Method of producing lead frame having uneven surfaces |
US20020079561A1 (en) * | 2000-12-21 | 2002-06-27 | Shoshi Yasunaga | Lead frame for a semiconductor device, a semiconductor device made from the lead frame, and a method of making a semiconductor device |
US6483178B1 (en) * | 2000-07-14 | 2002-11-19 | Siliconware Precision Industries Co., Ltd. | Semiconductor device package structure |
US6639306B2 (en) * | 1998-07-30 | 2003-10-28 | Siliconware Precision Industries, Co., Ltd. | Semiconductor package having a die pad with downward-extended tabs |
US6661083B2 (en) * | 2001-02-27 | 2003-12-09 | Chippac, Inc | Plastic semiconductor package |
US20040084757A1 (en) * | 2002-10-29 | 2004-05-06 | Signetics Korea Co., Ltd. | Micro leadframe package having oblique etching |
US20040227217A1 (en) * | 1999-10-15 | 2004-11-18 | Jang Sung Sik | Semiconductor package having improved adhesiveness and ground bonding |
US20050051876A1 (en) * | 2003-09-08 | 2005-03-10 | United Test And Assembly Test Center, Ltd. | Integrated circuit package with leadframe enhancement and method of manufacturing the same |
US20050242417A1 (en) * | 2004-04-29 | 2005-11-03 | Cheul-Joong Youn | Semiconductor chip package and method for manufacturing the same |
US20050258521A1 (en) * | 2004-05-24 | 2005-11-24 | Advanced Semiconductor Engineering Inc. | Leadless leadframe with an improved die pad for mold locking |
US7042071B2 (en) * | 2002-10-24 | 2006-05-09 | Matsushita Electric Industrial Co., Ltd. | Leadframe, plastic-encapsulated semiconductor device, and method for fabricating the same |
US7060536B2 (en) * | 2004-05-13 | 2006-06-13 | St Assembly Test Services Ltd. | Dual row leadframe and fabrication method |
US7060535B1 (en) * | 2003-10-29 | 2006-06-13 | Ns Electronics Bangkok (1993) Ltd. | Flat no-lead semiconductor die package including stud terminals |
US7115978B2 (en) * | 2004-06-30 | 2006-10-03 | Orient Semiconductor Electronics, Ltd. | Package Structure |
US7221045B2 (en) * | 2004-09-04 | 2007-05-22 | Samsung Techwin Co., Ltd. | Flat chip semiconductor device and manufacturing method thereof |
US20070170559A1 (en) * | 2006-01-24 | 2007-07-26 | Stats Chippac Ltd. | Integrated circuit package system |
US7361531B2 (en) * | 2005-11-01 | 2008-04-22 | Allegro Microsystems, Inc. | Methods and apparatus for Flip-Chip-On-Lead semiconductor package |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4862246A (en) | 1984-09-26 | 1989-08-29 | Hitachi, Ltd. | Semiconductor device lead frame with etched through holes |
JPH05291467A (en) * | 1992-04-08 | 1993-11-05 | Hitachi Ltd | Lead frame and semiconductor device |
JP2912134B2 (en) | 1993-09-20 | 1999-06-28 | 日本電気株式会社 | Semiconductor device |
FR2741191B1 (en) | 1995-11-14 | 1998-01-09 | Sgs Thomson Microelectronics | PROCESS FOR MANUFACTURING A MICROMODULE, PARTICULARLY FOR CHIP CARDS |
US6448633B1 (en) * | 1998-11-20 | 2002-09-10 | Amkor Technology, Inc. | Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant |
KR20010037254A (en) * | 1999-10-15 | 2001-05-07 | 마이클 디. 오브라이언 | Semiconductor package |
JP4308528B2 (en) * | 2001-01-31 | 2009-08-05 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
US6794738B2 (en) | 2002-09-23 | 2004-09-21 | Texas Instruments Incorporated | Leadframe-to-plastic lock for IC package |
TW567598B (en) | 2002-11-13 | 2003-12-21 | Advanced Semiconductor Eng | Flip chip semiconductor package |
US20040262781A1 (en) * | 2003-06-27 | 2004-12-30 | Semiconductor Components Industries, Llc | Method for forming an encapsulated device and structure |
US8067271B2 (en) | 2006-09-15 | 2011-11-29 | Stats Chippac Ltd. | Integrated circuit package system with encapsulation lock |
US8093693B2 (en) | 2006-09-15 | 2012-01-10 | Stats Chippac Ltd. | Integrated circuit package system with encapsulation lock |
-
2006
- 2006-09-15 US US11/532,508 patent/US20080067639A1/en not_active Abandoned
-
2010
- 2010-01-19 US US12/690,092 patent/US7919838B2/en active Active
Patent Citations (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5753969A (en) * | 1995-08-15 | 1998-05-19 | Kabushiki Kaisha Toshiba | Resin sealed semiconductor device including a die pad uniformly having heat conducting paths and circulating holes for fluid resin |
US6127206A (en) * | 1997-03-24 | 2000-10-03 | Seiko Epson Corporation | Semiconductor device substrate, lead frame, semiconductor device and method of making the same, circuit board, and electronic apparatus |
US6197615B1 (en) * | 1997-04-04 | 2001-03-06 | Samsung Electronics Co., Ltd. | Method of producing lead frame having uneven surfaces |
US5973388A (en) * | 1998-01-26 | 1999-10-26 | Motorola, Inc. | Leadframe, method of manufacturing a leadframe, and method of packaging an electronic component utilizing the leadframe |
US6166430A (en) * | 1998-05-27 | 2000-12-26 | Matsushita Electronics Corporation | Lead frame, method for manufacturing the frame, resin-molded semiconductor device and method for manufacturing the device |
US6639306B2 (en) * | 1998-07-30 | 2003-10-28 | Siliconware Precision Industries, Co., Ltd. | Semiconductor package having a die pad with downward-extended tabs |
US20040227217A1 (en) * | 1999-10-15 | 2004-11-18 | Jang Sung Sik | Semiconductor package having improved adhesiveness and ground bonding |
US6483178B1 (en) * | 2000-07-14 | 2002-11-19 | Siliconware Precision Industries Co., Ltd. | Semiconductor device package structure |
US20020079561A1 (en) * | 2000-12-21 | 2002-06-27 | Shoshi Yasunaga | Lead frame for a semiconductor device, a semiconductor device made from the lead frame, and a method of making a semiconductor device |
US6661083B2 (en) * | 2001-02-27 | 2003-12-09 | Chippac, Inc | Plastic semiconductor package |
US7042071B2 (en) * | 2002-10-24 | 2006-05-09 | Matsushita Electric Industrial Co., Ltd. | Leadframe, plastic-encapsulated semiconductor device, and method for fabricating the same |
US20040084757A1 (en) * | 2002-10-29 | 2004-05-06 | Signetics Korea Co., Ltd. | Micro leadframe package having oblique etching |
US20050051876A1 (en) * | 2003-09-08 | 2005-03-10 | United Test And Assembly Test Center, Ltd. | Integrated circuit package with leadframe enhancement and method of manufacturing the same |
US7060535B1 (en) * | 2003-10-29 | 2006-06-13 | Ns Electronics Bangkok (1993) Ltd. | Flat no-lead semiconductor die package including stud terminals |
US20050242417A1 (en) * | 2004-04-29 | 2005-11-03 | Cheul-Joong Youn | Semiconductor chip package and method for manufacturing the same |
US7060536B2 (en) * | 2004-05-13 | 2006-06-13 | St Assembly Test Services Ltd. | Dual row leadframe and fabrication method |
US20050258521A1 (en) * | 2004-05-24 | 2005-11-24 | Advanced Semiconductor Engineering Inc. | Leadless leadframe with an improved die pad for mold locking |
US7115978B2 (en) * | 2004-06-30 | 2006-10-03 | Orient Semiconductor Electronics, Ltd. | Package Structure |
US7221045B2 (en) * | 2004-09-04 | 2007-05-22 | Samsung Techwin Co., Ltd. | Flat chip semiconductor device and manufacturing method thereof |
US7361531B2 (en) * | 2005-11-01 | 2008-04-22 | Allegro Microsystems, Inc. | Methods and apparatus for Flip-Chip-On-Lead semiconductor package |
US20070170559A1 (en) * | 2006-01-24 | 2007-07-26 | Stats Chippac Ltd. | Integrated circuit package system |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8779568B2 (en) | 2006-09-15 | 2014-07-15 | Stats Chippac Ltd. | Integrated circuit package system with encapsulation lock |
US20080067640A1 (en) * | 2006-09-15 | 2008-03-20 | Stats Chippac Ltd. | Integrated circuit package system with encapsulation lock |
US20080067698A1 (en) * | 2006-09-15 | 2008-03-20 | Stats Chippac Ltd. | Integrated circuit package system with encapsulation lock |
US8067271B2 (en) | 2006-09-15 | 2011-11-29 | Stats Chippac Ltd. | Integrated circuit package system with encapsulation lock |
US8093693B2 (en) | 2006-09-15 | 2012-01-10 | Stats Chippac Ltd. | Integrated circuit package system with encapsulation lock |
US20090152694A1 (en) * | 2007-12-12 | 2009-06-18 | Infineon Technologies Ag | Electronic device |
US7737537B2 (en) * | 2007-12-12 | 2010-06-15 | Infineon Technologies Ag | Electronic device |
US20100213587A1 (en) * | 2007-12-12 | 2010-08-26 | Infineon Technologies Ag | Electronic device |
US8030741B2 (en) | 2007-12-12 | 2011-10-04 | Infineon Technologies Ag | Electronic device |
US20110248393A1 (en) * | 2010-04-09 | 2011-10-13 | Freescale Semiconductor, Inc | Lead frame for semiconductor device |
US8115288B2 (en) * | 2010-04-09 | 2012-02-14 | Freescale Semiconductor, Inc. | Lead frame for semiconductor device |
US8604596B2 (en) | 2011-03-24 | 2013-12-10 | Stats Chippac Ltd. | Integrated circuit packaging system with locking interconnects and method of manufacture thereof |
US20130069214A1 (en) * | 2011-09-21 | 2013-03-21 | Renesas Electronics Corporation | Lead frame, semiconductor device, method of manufacturing lead frame, and method of manufacturing semiconductor device |
US8552542B2 (en) * | 2011-09-21 | 2013-10-08 | Renesas Electronics Corporation | Lead frame, semiconductor device, method of manufacturing lead frame, and method of manufacturing semiconductor device |
WO2021107769A1 (en) * | 2019-11-29 | 2021-06-03 | Ampleon Netherlands B.V. | Lead frame based molded radio frequency package |
Also Published As
Publication number | Publication date |
---|---|
US7919838B2 (en) | 2011-04-05 |
US20100117205A1 (en) | 2010-05-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8067271B2 (en) | Integrated circuit package system with encapsulation lock | |
US7919838B2 (en) | Integrated circuit package system with encapsulation lock and method of manufacture thereof | |
US7298037B2 (en) | Stacked integrated circuit package-in-package system with recessed spacer | |
US7400049B2 (en) | Integrated circuit package system with heat sink | |
US8779568B2 (en) | Integrated circuit package system with encapsulation lock | |
US7772683B2 (en) | Stacked integrated circuit package-in-package system | |
US7420269B2 (en) | Stacked integrated circuit package-in-package system | |
US7556987B2 (en) | Method of fabricating an integrated circuit with etched ring and die paddle | |
US8541872B2 (en) | Integrated circuit package system with package stacking and method of manufacture thereof | |
US20070241441A1 (en) | Multichip package system | |
US7843047B2 (en) | Encapsulant interposer system with integrated passive devices and manufacturing method therefor | |
US7479692B2 (en) | Integrated circuit package system with heat sink | |
US8723324B2 (en) | Integrated circuit packaging system with pad connection and method of manufacture thereof | |
US8124451B2 (en) | Integrated circuit packaging system with interposer | |
US7871863B2 (en) | Integrated circuit package system with multiple molding | |
US8193037B1 (en) | Integrated circuit packaging system with pad connection and method of manufacture thereof | |
US8633063B2 (en) | Integrated circuit packaging system with pad connection and method of manufacture thereof | |
US7521297B2 (en) | Multichip package system | |
US8581382B2 (en) | Integrated circuit packaging system with leadframe and method of manufacture thereof | |
US7928540B2 (en) | Integrated circuit package system | |
US7582957B2 (en) | Integrated circuit package system with encapsulation lock | |
US8410587B2 (en) | Integrated circuit package system | |
US20070109750A1 (en) | Integrated circuit package system | |
US20080284038A1 (en) | Integrated circuit package system with perimeter paddle |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: STATS CHIPPAC LTD., SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DO, BYUNG TAI;YANG, SUNG UK;REEL/FRAME:018266/0795 Effective date: 20060907 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT, HONG KONG Free format text: SECURITY INTEREST;ASSIGNORS:STATS CHIPPAC, INC.;STATS CHIPPAC LTD.;REEL/FRAME:036288/0748 Effective date: 20150806 Owner name: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY Free format text: SECURITY INTEREST;ASSIGNORS:STATS CHIPPAC, INC.;STATS CHIPPAC LTD.;REEL/FRAME:036288/0748 Effective date: 20150806 |
|
AS | Assignment |
Owner name: STATS CHIPPAC PTE. LTE., SINGAPORE Free format text: CHANGE OF NAME;ASSIGNOR:STATS CHIPPAC LD.;REEL/FRAME:038378/0442 Effective date: 20160329 |
|
AS | Assignment |
Owner name: STATS CHIPPAC PTE. LTE., SINGAPORE Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED ON REEL 038378 FRAME 0442. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME;ASSIGNOR:STATS CHIPPAC LTD.;REEL/FRAME:039514/0451 Effective date: 20160329 |
|
AS | Assignment |
Owner name: STATS CHIPPAC PTE. LTD., SINGAPORE Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 039514 FRAME: 0451. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME;ASSIGNOR:STATS CHIPPAC LTD.;REEL/FRAME:039980/0838 Effective date: 20160329 |
|
AS | Assignment |
Owner name: STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD., SINGAPORE Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT;REEL/FRAME:053476/0094 Effective date: 20190503 Owner name: STATS CHIPPAC, INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT;REEL/FRAME:053476/0094 Effective date: 20190503 |