US20080089123A1 - Method for Programming a Multi-Level Non-Volatile Memory Device - Google Patents
Method for Programming a Multi-Level Non-Volatile Memory Device Download PDFInfo
- Publication number
- US20080089123A1 US20080089123A1 US11/848,014 US84801407A US2008089123A1 US 20080089123 A1 US20080089123 A1 US 20080089123A1 US 84801407 A US84801407 A US 84801407A US 2008089123 A1 US2008089123 A1 US 2008089123A1
- Authority
- US
- United States
- Prior art keywords
- voltage
- cell
- programmed
- programming
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5646—Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"
Definitions
- the present disclosure relates to a non-volatile memory device and, more specifically, to a method for programming a multi-level non-volatile memory device.
- Flash memory is a form of computer memory that can retain data without having to consume power and is thus characterized as non-volatile. Flash memory may be programmed and erased in blocks.
- Flash memory stores data in an array of floating gate transistors called cells.
- single-level flash memory one bit of data may be stored in each cell.
- multi-level flash memory more than one bit of data may be stored in each cell by differentiating between several levels of charge that may be stored in the floating gate of the cell.
- FIG. 1 is a schematic diagram showing a single cell 10 of flash memory.
- Flash memory is comprised of a p-type semiconductor substrate 11 that may be doped, for example with boron ions.
- An n-type source region 12 and an n-type drain region 13 may be formed within the substrate 11 by droping, for example, with phosphorus arsenic, or antimony ions.
- a floating gate 14 may be formed above the substrate 11 and may be insulated from the substrate.
- a control gate 15 may be formed above the floating gate 14 and may be insulated from the floating gate 14 . Because the floating gate 14 is completely insulated, charge that may be stored within the floating gate is trapped and thus data may persist in the floating gate without the consumption of electricity.
- Flash memory may be either NOR memory or NAND memory. Each form of flash memory has its own set of characteristics. For example, NOR flash utilizes a process called hot electron injection to trap charge within the floating gate and relies on quantum tunneling to discharge the floating gate. NAND flash utilizes quantum tunneling both to trap charge and discharge.
- a NAND flash memory device may be organized into strings.
- FIG. 2 shows an example of a string of NAND flash memory.
- the illustrated string is depicted physically 200 A and in terms of its analogous electrical schematic 200 B.
- Each string is a group of cells connected in series.
- Each string may comprise, for example, 16 or 32 cells.
- Each string may have a bit line with a bit tine contact 210 and one or more gates for controlling the string.
- each string may have a select gate 220 and a control gate 230 .
- the string may also have a floating gate 240 and a cell source line 250 .
- FIG. 3 shows an example of a flash memory block.
- the flash memory 100 has an X-Decoder 130 that controls voltages of the word lines (WL), the string select line (SSL) and the ground source line (GSL).
- the flash memory 100 also has a page buffer circuit 150 for controlling voltages of the bit lines (BL).
- the flash memory 100 is organized as a block 110 made up of strings.
- strings 110 _ 1 , 110 _ 2 , and 110 _M are shown, however, it is to be understood that there may be any number of strings between 110 _ 2 and 110 _M .
- string 110 _ 1 has a bit line “BLe”
- string 110 _ 2 has a bit line “BLo”.
- the flash memory 100 is also organized into pages.
- An example of a page is shown as 110 p.
- Each string may be connected to a string selection line (SSL), a ground selection line (GSL), a series of word lines (WL) numbered WL ⁇ N ⁇ 1> through WL ⁇ 0>, and a common source line (CSL), and each string may have a string selection transistor (SST), a ground select transistor (GST) and a series of memory cell transistors (MCT) numbered MCT ⁇ N ⁇ 1> through MCT ⁇ 0>.
- SST string selection transistor
- GST ground select transistor
- MCT memory cell transistors
- the presence and degree of charge within the floating gate affects the threshold voltage of the cell.
- the threshold voltage of the cell may be understood to be the minimum voltage that need be applied to the control gate before current may begin to flow between the source and drain. Accordingly, the cell may be read by applying a predetermined voltage to the control gate and determining whether current may flow between the source and drain. In practice sense amplifiers may be used to detect and amplify observed current flow.
- a multi-level flash multiple discrete levels of charge may be stored within the floating gate of the cell.
- multiple discrete levels of charge may be stored within the floating gate of the cell.
- the cell may exhibit one of four distinct threshold voltages depending on the level of charge trapped in the floating gate.
- the level of charge stored in the cell, and hence the stored data value may be determined by applying a test voltage to the control gate and determining whether current flows.
- Multi-level flash may have more than 2-bits.
- a multi-level flash may have 3 or more bits.
- a 3-bit flash would have 8 (2 3 ) states per cell
- a 4-bit flash would have 16 (2 4 ) states per cell
- a 5-bit flash would have 32 (2 5 ) states per cell, etc.
- the operative threshold levels of such multi-level flash would have to be set over the range of possible values and adjacent threshold ranges may be separated by margins. Accordingly, flash having higher number of bits must be able to set charge levels within narrower ranges and have narrower margins. To accommodate these narrower ranges and margins, charge must be added to cells with increased precision. The process of adding charge to cells is referred to as “programming.” Accordingly, programming for multi-level flash requires increased precision.
- a method for programming multi-level non-volatile memory A plurality of multi-bit storage cells capable of storing different levels of charge usable to represent data represented by least significant bits (LSBs) and most significant bits (MSBs) are programmed first with LSBs and then with MSBs.
- Each of the programmed storage cells has a threshold voltage lower than a voltage VR 1 when it is desired that the storage cell store a first value.
- Each of the cells has a threshold voltage greater than the voltage VR 1 and lower than a voltage VR 2 when it is desired that the storage cell store a second value.
- Each of the cells has a threshold voltage greater than the voltage VR 2 and lower than a voltage VR 3 when it is desired that the storage cell store a third value.
- Each of the cells has a threshold voltage greater than a voltage VR 3 when it is desired that the storage cell store a fourth value.
- the voltage VR 1 is less than VR 2 which is less than VR 3 .
- the flag cell is programmed to have a threshold voltage greater than the voltage VR 3 to indicate that the MSBs have been programmed.
- a controller for controlling memory according to a method for programming multi-level non -volatile memory comprising at least one flag cell and a plurality of multi-bit storage cells.
- Each of the plurality of multi-bit storage cells is capable of storing different levels of charge usable to represent data.
- the data is represented by least significant bits (LSBs) and a most significant bits (MSBs).
- the method includes programming the storage cells first with LSBs and then with MSB data.
- Each of the programmed storage cells has a threshold voltage lower than a voltage VR 1 when it is desired that the storage cell store a first value.
- Each of the cells has a threshold voltage greater than the voltage VR 1 and lower than a voltage VR 2 when it is desired that the storage cell store a second value.
- Each of the cells has a threshold voltage greater than the voltage VR 2 and lower than a voltage VR 3 when it is desired that the storage cell store a third value.
- Each of the cells has a threshold voltage greater than a voltage VR 3 when it is desired that the storage cell store a fourth value.
- the voltage VR 1 is less than VR 2 which is less than VR 3 .
- the flag cell is programmed to have a threshold voltage greater than the voltage VR 3 to indicate that the MSB data have been programmed.
- a method for programming a multi-level non-volatile memory comprising at least one flag cell and a plurality of multi-bit storage cells.
- Each of the plurality of multi-bit storage cells is capable of storing different levels of charge usable to represent data.
- the data is represented by a plurality of data pages.
- the method includes sequentially programming one or more of the plurality of data pages such that each of the programmed storage cells has a threshold voltage within one of a plurality of threshold voltage ranges comprising a first range and a plurality of subsequent ranges.
- Each of the plurality of subsequent ranges is defined as being equal to or greater than a respective verify voltage.
- Each of the plurality of subsequent ranges is read at a respective read voltage.
- the respective read voltage is less than the respective verify voltage by a margin M.
- the at least one flag cell is programmed to a threshold voltage within a threshold voltage range indicative of the number of data pages that have been programmed.
- the flag cell threshold voltage range is defined as being equal to or greater than a flag cell verify voltage.
- the flag cell is read at a flag cell read voltage.
- the flag cell read voltage is less than the flag cell verify voltage by an enhanced margin M enhanced that is larger than the margin M.
- a controller for controlling memory according to a method for programming multi-level non-volatile memory comprising at least one flag cell and a plurality of multi-bit storage cells.
- Each of the plurality of multi-bit storage cells is capable of storing different levels of charge usable to represent data.
- the data is represented by a plurality of data pages.
- the method includes sequentially programming one or more of the plurality of data pages such that each of the programmed storage cells has a threshold voltage within one of a plurality of threshold voltage ranges comprising a first range and a plurality of subsequent ranges.
- Each of the plurality of subsequent ranges is defined as being equal to or greater than a respective verify voltage.
- Each of the plurality of subsequent ranges is read at a respective read voltage.
- the respective read voltage is less than the respective verify voltage by a margin M.
- the at least one flag cell is programmed to a threshold voltage within a threshold voltage range indicative of the number of data pages that have been programmed.
- the flag cell threshold voltage range is defined as being equal to or greater than a flag cell verify voltage.
- the flag cell is read at a flag cell read voltage.
- the flag cell read voltage is less than the flag cell verify voltage by an enhanced margin M enhanced that is larger than the margin M.
- FIG. 1 is a schematic diagram showing a single cell of flash memory
- FIG. 2 shows an example of a string of NAND flash memory
- FIG. 3 shows an example of a flash memory block
- FIG. 4 illustrates the four states of a 2-bit multi-level flash according to an exemplary embodiment of the present invention
- FIG. 5 illustrates an exemplary electrical signal used as part of a method of ISPP ention
- FIG. 6 illustrates an electrical signal used as part of a method of ISPP according to another exemplary embodiment of the present invention
- FIG. 7 illustrates the four possible states of a 2-bit memory according to an exemplary embodiment of the present invention
- FIG. 8 illustrates a method for programming data in a cell according to an exemplary embodiment of the present invention
- FIG. 9 illustrates a method for programming a multi-level non-volatile memory device according to an exemplary embodiment of the present invention.
- FIG. 10 illustrates a method for programming a multi-level non-volatile memory device according to an exemplary embodiment of the present invention
- FIG. 11 illustrates a method for programming a multi-level non-volatile memory device according to an exemplary embodiment of the present invention
- FIGS. 12A-12B show a three-bit memory device according to an exemplary embodiment of the present invention.
- FIGS. 12C-12D show a three-bit memory device according to an exemplary embodiment of the present invention.
- FIG. 13 is a table showing bias conditions for controlling a two-bit multi-level non-volatile memory device according to an exemplary embodiment of the present invention
- FIG. 14 is a schematic representation of a memory page according to an exemplary embodiment of the present invention.
- FIG. 15 shows a memory system including flash memory according to an exemplary embodiment of the present invention.
- Embodiments of the present invention may allow for high-precision programming of cells within a multi-level non-volatile memory device, for example, a flash memory having two or more bits.
- FIG. 4 illustrates the four states of a 2-bit multi-level flash.
- the x-axis represents threshold voltage while the y-axis represents the probability distribution for the threshold voltage of a particular programmed cell.
- the threshold voltage of the cell is represented as a probability distribution and thus the cell's charge states are represented as a curve showing the likelihood that the cell programmed according to a particular state would have a particular threshold value.
- a given cell may have one of the four possible threshold voltage probability curves 410 , 420 , 430 , 440 representative of a first state, a second state, a third state and a fourth state respectively.
- a cell having the threshold voltage probability curve 410 will not register a current at any of test voltages VR 1 , VR 2 , and VR 3 .
- a cell having the threshold voltage probability curve 420 will register a current at VR 1 but not at VR 2 or VR 3 .
- a cell having the threshold voltage curve 430 will register a current at VR 1 and VR 2 but not at VR 3 .
- a cell having the threshold voltage curve 440 will register a current at all test voltages VR 1 , VR 2 , and VR 3 . Accordingly, in the ideal case, it is possible to distinguish between four states by reading the cell at each of 3 voltages VR 1 , VR 2 , and VR 3 .
- margins may also be desirable to leave a margin between the threshold voltage ranges 420 , 430 , and 440 and the measurement voltages VR 1 , VR 2 , and VR 3 respectively. These margins are shown as the distance M and extend from the measurement voltage and the adjacent verify voltage VF 1 , VF 2 , and VF 3 which indicates the start of the threshold voltage ranges 420 , 430 , and 440 .
- the states of the cell may be set according to any voltage scale.
- the first state 410 may be represented by a cell having a threshold voltage less than approximately ⁇ 2 Volts.
- the second state 420 may be represented by a cell having a threshold voltage within the range of 0.3 to 0.7 Volts.
- the third state 430 may be represented by a cell having a threshold voltage within the range of 1.3 to 1.7 Volts.
- the fourth state 440 may be represented by a cell having a threshold voltage within the range of 2.3 to 2.7 Volts.
- FIG. 5 shows an exemplary wave form useable for ISPP.
- FIG. 6 shows a waveform for ISPP according to an exemplary embodiment of the present invention.
- the electrical signal 600 comprises a series of pulses with each pulse extending for a length of time constituting a program period 620 .
- Each pulse may be separated by a length of time constituting a verify period 640 .
- the voltage of each successive pulse may increase, for example, by a voltage 630 ( ⁇ Vpgm), which may be, for example, 0.5V.
- the voltage of the first pulse 610 may be 15V.
- Each successive pulse may increase up to and including a maximum voltage 650 which may be, for example, 19V.
- the threshold voltage of the cell may be tested, for example, between each pulse or periodically, for example, every 3 pulses, to see if the proper threshold voltage has been achieved. If it has not been achieved, additional pulses may be applied.
- the cell may be read to verify that the cell has been properly programmed. For example, the threshold voltage may be tested to see if it has been set sufficiently high. If it has not been, additional pulses may be applied until the threshold voltage is sufficiently high.
- a set of verification test voltages may be used to verify the programmed threshold voltages.
- the verification voltages (VF) may be different than the test voltages used to read the cells (VR).
- the verification voltages VF 1 , VF 2 , VF 3 may each be greater than the corresponding read voltages VR 1 , VR 2 , VR 3 by the amount of the margin M discussed above.
- Each cell state of a multi-bit memory device may be represented by a number.
- each of the four possible states may be expressed by a 2-bit binary number.
- the first unprogrammed state may be expressed as “11”
- the second state may be expressed as “01
- the third state may be expressed as “10”
- the fourth state may be expressed as “00.”
- FIG. 7 illustrates the four possible states of a 2-bit memory according to an embodiment of the present invention. It should be understood that the nomenclature may be arbitrary and the present nomenclature is offered as an example.
- the threshold voltage probability distribution 700 for each of the four states is shown. It is to be understood that a given cell may only have one threshold voltage at a time and the threshold voltage may be within one of the 4 states, with the exact threshold voltage falling within the distribution for that state in accordance with the probability curve.
- Each 2-bit binary number may be said to include a most significant bit (MSB) and a least significant bit (LSB).
- MSB most significant bit
- LSB least significant bit
- data may be stored in each cell by trapping a level of charge in the floating gate necessary to achieve a threshold voltage within a desired range, with each range representing a state. Accordingly, data may be stored in the cell by programming the cell and in the case of a 2-bit memory, 2-bits of data may be stored in each cell.
- 2-bit memory cells may be programmed with only a single bit of data.
- a cell programmed with only a first bit of data may be later programmed with a second bit of data.
- the cell is said to contain only LSB data.
- 2-bits of data are programmed in a cell, the cell is said to contain both LSB data and MSB data.
- LSB cells may be programmed one page at a time. Accordingly, the LSB cells of a physical page may be considered an LSB logical page and the MSB cells of the physical page may be considered an MSB logical page wherein the process of programming a physical page includes first programming (and verifying) the LSB logical page and next programming (and verifying) the MSB logical page.
- FIG. 8 illustrates a method for programming data in a cell according to an exemplary embodiment of the present invention.
- Lin 800 A represents a cell where only LSB data has been programmed. The unprogrammed state of LSB data is “1.” When it is desired that a “0” be stored, the cell is programmed until the threshold voltage is verified to be within the appropriate range of the “0” state (greater than VF 2 *). Such a programming step is illustrated as P 1 .
- the cell When only LSB data is stored in a cell, the cell may be read at a single voltage, here shown as VR 1 . If at voltage VR 1 , current can be observed, then the cell is determined to be in the unprogrammed “1” state. If at voltage VR 1 , no current can be observed, then the cell is determined to be in the “0” state.
- Line 800 B represents the cell where only LSB data has been programmed and the threshold voltage probability curve has widened by an amount D 1 .
- the “1” LSB data state of line 800 B may remain as the “11” data state of line 800 C or may be programmed until the threshold voltage is verified to be within the appropriate range of the “01” state of line 800 C (greater than VF 1 ) through a programming step shown as P 2 .
- the “0” data state of line 800 B may be programmed until the threshold voltage is verified to be within the appropriate range of the “10” state of line 800 C (greater than VF 2 ) through a programming step shown as P 3 or it may be programmed until the threshold voltage is verified to be within the appropriate range of the “00” data state of line 800 C (greater than VF 3 ) through a programming step shown as P 4 .
- Each programming step may utilize an ISPP process, for example, the ISPP processes described above.
- the “0” state of LSB data may include threshold voltages on either side of the VR 2 voltage.
- VF 1 is greater than VR 1 by a margin M.
- VF 2 is greater than VR 2 by a margin M and VF 3 is greater than VR 3 by a margin M. All margins M may be the same; however, this is not required. Allowing a margin may improve read accuracy.
- Embodiments of the present invention may utilize a cell referred to as an MSB flag to indicate whether MSB data has been stored.
- a cell of a storage device is dedicated as an MSB flag cell, the remaining cells may be referred to as data storage cells.
- the MSB flag cell may be read to allow for an accurate interpretation of the stored data regardless of whether only LSB data have been stored or whether both LSB and MSB data have been stored.
- Line 800 D illustrates an MSB flag cell in the unprogrammed “1” state. This state may be used to indicate that MSB data has not been programmed.
- Line 800 E illustrates an MSB flag cell in the “0” state. This state may be used to indicate that MSB data has been programmed. The MSB flag may begin in the “1” state and may be programmed until the threshold voltage is verified to be in the “0” state (greater than VF 3 ) by a programming step P 5 to indicate that MSB data has been programmed.
- the “0” state of the MSB flag may be programmed until the threshold voltage of the MSB flag cell is greater than VF 3 . While the threshold voltage of this state is greater than VR 3 by the margin M, the MSB flag is read from VR 2 to provide an enhanced margin. This enhanced margin is illustrated as M Enhanced .
- a phenomenon referred to as charge loss may occur as charge unintentionally escapes from the floating gate of a cell. Charge may unintentionally escape due to defects in the insulation layer or some other factor. Loss of charge may result in the possibility that the threshold voltage can become lower than is desired. This possibility may be represented by a spreading of the probability curve in the lower-voltage direction.
- charge loss may occur at any cell, storage cells tend to have a greater level of error correction measures than the MSB flag cell. Additionally, charge loss in one storage cell may render only the affected cell unreadable, while charge loss in the MSB flag cell may render an entire page unreadable. Accordingly charge loss in the MSB flag cell may be especially problematic.
- the enhanced margin M Enhanced may be great enough to allow for an accurate read of the MSB flag cell even if charge is lost from the floating gate of the MSB flag cell.
- the distance M Enhanced may be sufficient to place the “0” state of the MSB flag at the same distribution curve as the “00” state of the storage cell (shown as “00” on line 800 C). By defining the “0” state of the MSB flag cell accordingly, the MSB flag cell may be accurately read even in less-than ideal conditions.
- FIG. 9 illustrates a method for programming a multi-level non-volatile memory device according to an exemplary embodiment of the present invention.
- the LSB data of the storage cells may be programmed (Step S 910 ).
- the LSB logical page may be programmed by employing an ISPP process until the threshold voltage is verified as being greater than VF 2 * where a ‘0’ state is desired. If the ‘1’ state is desired than no programming is necessary at this step.
- Next MSB data may be used to program the “00” state, where desired, (Step S 920 A) by employing the ISPP process until the threshold voltage is verified as being greater than VF 3 .
- This programming step may include implementing an ISPP process to add additional charge to the “0” LSB state.
- the MSB flag cell may be programmed from the non-programmed state “1” to the programmed state “0” (Step S 920 B) to indicate that MSB data has been programmed.
- This programming step may include implementing an ISPP process to add additional charge to the “1” state to achieve the “0” state.
- the “0” state for the MSB flag cell may be programmed until the threshold voltage is verified as being greater than VR 3 .
- Steps S 920 A and S 920 B may be simultaneously executed as they may both use the same VR 3 verification voltage.
- the MSB data may be used to program the “01” and “10” states (Step S 390 ) where desired.
- This programming step may include implementing an ISPP process to add additional charge to the “1” and “0” states to achieve the “01” and “10” states respectively by programming the threshold voltage is verified as being greater than VF 1 and VF 2 respectively.
- the “11” state may be achieved by leaving the cell in its unprogrammed “1” state.
- Step S 920 A the programming of the MSB flag cell
- Step S 920 B the programming of the MSB flag cell
- Exemplary embodiments of the present invention discussed below concern both approaches to programming main memory cells and approaches to programming flag cells when programming main memory cells. It is to be understood that the approaches to programming main memory cells discussed below and the approaches to programming flag cells discussed below are not interdependent and do not require that the specific approaches be combined in the manner shown. Particularly, the approaches to programming main memory cells discussed below may be combined with other approaches to programming flag cells not discussed below but known in the art while the approaches to programming flag cells discussed below may be combined with other approaches to programming main memory cells not discussed below but known in the art.
- FIGS. 10 and 11 illustrate an alternative method for programming a multi-level non-volatile memory device according to another exemplary embodiment of the present invention.
- LSB data may be programmed in the manner discussed above (Step S 1010 ) (Line 1100 A).
- the ‘0’ state may be advanced to the advanced state “A” by programming the cell until the threshold voltage is verified as being greater than VF 2 (Step S 1020 ) (Line 1100 B).
- the state defined by programming to VF 2 is also defined as the ‘10’ state, however, this step may be performed when either the ‘10’ state or the ‘00’ state is desired.
- the MSB flag cell may remain unprogrammed at this step ( 1110 B).
- the ‘00’ state may be programmed, if desired, by programming the A state until the threshold voltage is verified as being greater than VF 3 or where the ‘10’ state is desired, no additional programming need occur (Step S 1030 A) (Line 1100 C).
- the MSB flag may be programmed at this point by programming the MSB flag cell until the threshold voltage is verified as being greater than VF 3 (Step S 1030 B) (Line 1100 C), Steps S 1030 A and S 1030 B may be executed simultaneously or near simultaneously as they both involve programming to the VF 3 verification voltage.
- the “01” state may be programmed where desired by programming the “1” state until the threshold voltage is verified as being greater than VF 1 (Step S 1040 ) (Line 1100 D).
- a three-bit multi-level non-volatile memory device may be used.
- the three-bit device would have 8 available memory states for each cell. These memory states may be called “111,” “011,” “101,” “001,” “110,” “010,” “100,” and “000” respectively.
- the three-bit memory device instead of having an LSB page and a MSB page, would have a first logical page, a second logical page and a third logical page.
- first flag cell indicating when the second page has been programmed
- second flag cell indicating when the third page has been programmed
- a single flag cell may be used having multiple memory states to indicate when the second page has been programmed and when the third page has been programmed.
- the flag cell may initially be set to an unprogrammed ‘111’ state indicating that neither second nor third data pages have been programmed, the flag cell may be programmed to a ‘010’ state to indicate that the second data page has been loaded and the flag cell may be programmed to a ‘000’ state to indicate that the third data page has been loaded.
- the first flag cell may be programmed to the ‘0’ state to indicate that the second data page has been programmed and the second flag cell may be programmed to the ‘0’ state to indicate that the third data page has been programmed. While embodiments of the present invention utilize either approach, the exemplary embodiments of the present invention are discussed in terms of the first approach for simplicity.
- FIGS. 12A-12D show a three-bit memory device according to exemplary embodiments of the present invention. Many of the details as to how to program the various cells may be understood to be analogous to the exemplary embodiments discussed herein. It should be understood that the features of these examples may be extrapolated to provide multi-bit memory devices of greater than three bits.
- the storage cells are not advanced prior to second page and third page programming.
- FIGS. 12A and 12B illustrate such an embodiment.
- the first page may be programmed (line 1417 , step S 1423 ).
- the flag cell may originate in the unwritten ‘111’ state (line 1418 ).
- the second page data may be programmed (line 1419 , step S 1424 ) and the flag cell may be programmed to a level indicating that second data page has been programmed (line 1420 , Step S 1425 ).
- the flag cell may be programmed to the ‘010’ state.
- the two steps S 1424 and S 1425 may occur simultaneously or nearly simultaneously.
- the third page data may then be programmed (line 1421 , step S 1426 ) and the flag cell may be programmed to a level indicating that the third data page has been programmed (line 1422 , step S 1427 ).
- the flag cell may be programmed to the ‘000’ state.
- the two steps S 1426 and S 1427 may occur simultaneously or nearly simultaneously.
- the first page may be programmed (line 1430 , step S 1440 ).
- the flag cell may originate in the unwritten ‘111’ state (line 1431 ).
- the ‘0’ bit may then be advanced (line 1432 , step S 1441 ) so that the first page data may be protected from data corruption in the event of an unanticipated interruption.
- the flag cell may remain in the ‘111’ state (line 1433 ).
- the second page data may be programmed (line 1434 , step S 1442 ) and the flag cell may be programmed to a level indicating that second data page has been programmed (line 1435 , Step S 1443 ).
- the flag cell may be programmed to the ‘000’ state.
- the two steps S 1442 and S 1443 may occur simultaneously or nearly simultaneously.
- the second page data states ‘01,’ ‘10,’ and ‘00’ may then be advanced (line 1446 , step S 1444 ) so that the second page data may be protected from data corruption in the event of an unanticipated interruption.
- the flag cell may also be advanced from the ‘000’ state to the ‘100’ state (line 1437 , step S 1445 ).
- the third page data may then be programmed (line 1438 , step S 1446 ) and the flag cell may be programmed to a level indicating that the third data page has been programmed (line 1439 , step S 1447 ). For example, the flag cell may be programmed to the ‘000’ state.
- the two steps S 1446 and S 1447 may occur simultaneously or nearly simultaneously.
- FIG. 13 is a table showing bias conditions for controlling a two-bit multi-level non-volatile memory device according to an exemplary embodiment of the present invention. This table shows examples of signals that may be used to erase, program, inhibit, read and verify the storage cells and flag cell according to an exemplary embodiment of the present invention.
- the table in FIG. 13 summarizes voltages applied to operate the memory cell array according to an exemplary embodiment of the present invention.
- the top row of the table defines a set of possible memory functions that may be performed. These functions include erasing memory, programming memory, inhibiting the programming of memory, and reading LSB, MSB and flag cell data.
- the first column labels each line that may receive a voltage in the execution of the desired function.
- the remaining rows and columns of the table define the set of voltages that are to be applied to each of the lines listed on the first column to perform the desired function listed on the top row.
- the voltages may be specified in terms of a specific voltage such as 0 V or 20 V.
- the voltages may alternatively be specified in terms of a signal such as Vcc or Vpgm that have been described in detail above.
- the term “Floating” indicates that the line is not set to a particular voltage. “H or L” indicates that the line may be sent a high signal or a low signal. Vread is applied to unselected WLs when reading data, and Vpass is applied to unselected WLs when programming.
- FIG. 4 is a schematic representation of a memory page according to an exemplary embodiment of the present invention.
- the memory page 1600 shows multiple data storage cells on multiple data storage bit lines.
- the data storage bit lines are controlled by a set of data storage circuits 1620 , 1630 , and 1640 that comprise the page buffer circuit along with the flag storage data circuit 1650 that controls bit lines associated with the flag cell 1605 .
- the data storage cells and the flag cell comprise a data block 1610 .
- FIG. 15 shows a memory system including flash memory according to an exemplary embodiment of the present invention.
- Memory systems may include a flash memory 1500 and a memory controller 1510 .
- the memory controller 1510 may control the operation of the flash memory 1500 .
Abstract
Description
- The present application claims priority to Korean Patent Application 10-2006-0085880, filed Sep. 6, 2006, the entire contents of which are herein incorporated by reference.
- The present disclosure relates to a non-volatile memory device and, more specifically, to a method for programming a multi-level non-volatile memory device.
- Flash memory is a form of computer memory that can retain data without having to consume power and is thus characterized as non-volatile. Flash memory may be programmed and erased in blocks.
- Flash memory stores data in an array of floating gate transistors called cells. In single-level flash memory, one bit of data may be stored in each cell. In multi-level flash memory, more than one bit of data may be stored in each cell by differentiating between several levels of charge that may be stored in the floating gate of the cell.
-
FIG. 1 is a schematic diagram showing asingle cell 10 of flash memory. Flash memory is comprised of a p-type semiconductor substrate 11 that may be doped, for example with boron ions. An n-type source region 12 and an n-type drain region 13 may be formed within the substrate 11 by droping, for example, with phosphorus arsenic, or antimony ions. Afloating gate 14 may be formed above the substrate 11 and may be insulated from the substrate. Acontrol gate 15 may be formed above thefloating gate 14 and may be insulated from thefloating gate 14. Because thefloating gate 14 is completely insulated, charge that may be stored within the floating gate is trapped and thus data may persist in the floating gate without the consumption of electricity. - Flash memory may be either NOR memory or NAND memory. Each form of flash memory has its own set of characteristics. For example, NOR flash utilizes a process called hot electron injection to trap charge within the floating gate and relies on quantum tunneling to discharge the floating gate. NAND flash utilizes quantum tunneling both to trap charge and discharge.
- A NAND flash memory device may be organized into strings.
FIG. 2 shows an example of a string of NAND flash memory. The illustrated string is depicted physically 200A and in terms of its analogous electrical schematic 200B. Each string is a group of cells connected in series. Each string may comprise, for example, 16 or 32 cells. Each string may have a bit line with abit tine contact 210 and one or more gates for controlling the string. For example, each string may have a select gate 220 and acontrol gate 230. The string may also have afloating gate 240 and acell source line 250. - Multiple strings may be connected to form a page. Word lines may connect analogous cells in each string of the page. Multiple pages may be organized into blocks.
FIG. 3 shows an example of a flash memory block. Theflash memory 100 has anX-Decoder 130 that controls voltages of the word lines (WL), the string select line (SSL) and the ground source line (GSL). Theflash memory 100 also has apage buffer circuit 150 for controlling voltages of the bit lines (BL). Theflash memory 100 is organized as ablock 110 made up of strings. InFIG. 3 , strings 110_1, 110_2, and 110_M are shown, however, it is to be understood that there may be any number of strings between 110_2 and 110_M . Here, string 110_1 has a bit line “BLe” and string 110_2 has a bit line “BLo”. Theflash memory 100 is also organized into pages. An example of a page is shown as 110 p. - Each string may be connected to a string selection line (SSL), a ground selection line (GSL), a series of word lines (WL) numbered WL<N−1> through WL<0>, and a common source line (CSL), and each string may have a string selection transistor (SST), a ground select transistor (GST) and a series of memory cell transistors (MCT) numbered MCT<N−1> through MCT<0>.
- In the flash memory device, the presence and degree of charge within the floating gate affects the threshold voltage of the cell. The threshold voltage of the cell may be understood to be the minimum voltage that need be applied to the control gate before current may begin to flow between the source and drain. Accordingly, the cell may be read by applying a predetermined voltage to the control gate and determining whether current may flow between the source and drain. In practice sense amplifiers may be used to detect and amplify observed current flow.
- In a multi-level flash, multiple discrete levels of charge may be stored within the floating gate of the cell. For example, in a 2-bit multi-level flash, there may be four discrete levels of charge that may be stored within the floating gate of the cell. In this case, the cell may exhibit one of four distinct threshold voltages depending on the level of charge trapped in the floating gate. The level of charge stored in the cell, and hence the stored data value, may be determined by applying a test voltage to the control gate and determining whether current flows. For a 2-bit multi-level flash, it may be necessary to test whether current flows at up to 3 discrete read voltages to determine the state of the cell.
- Multi-level flash may have more than 2-bits. For examples a multi-level flash may have 3 or more bits. A 3-bit flash would have 8 (23) states per cell, a 4-bit flash would have 16 (24) states per cell, a 5-bit flash would have 32 (25) states per cell, etc. The operative threshold levels of such multi-level flash would have to be set over the range of possible values and adjacent threshold ranges may be separated by margins. Accordingly, flash having higher number of bits must be able to set charge levels within narrower ranges and have narrower margins. To accommodate these narrower ranges and margins, charge must be added to cells with increased precision. The process of adding charge to cells is referred to as “programming.” Accordingly, programming for multi-level flash requires increased precision.
- A method for programming multi-level non-volatile memory. A plurality of multi-bit storage cells capable of storing different levels of charge usable to represent data represented by least significant bits (LSBs) and most significant bits (MSBs) are programmed first with LSBs and then with MSBs. Each of the programmed storage cells has a threshold voltage lower than a voltage VR1 when it is desired that the storage cell store a first value. Each of the cells has a threshold voltage greater than the voltage VR1 and lower than a voltage VR2 when it is desired that the storage cell store a second value. Each of the cells has a threshold voltage greater than the voltage VR2 and lower than a voltage VR3 when it is desired that the storage cell store a third value. Each of the cells has a threshold voltage greater than a voltage VR3 when it is desired that the storage cell store a fourth value. The voltage VR1 is less than VR2 which is less than VR3. The flag cell is programmed to have a threshold voltage greater than the voltage VR3 to indicate that the MSBs have been programmed.
- A controller for controlling memory according to a method for programming multi-level non -volatile memory comprising at least one flag cell and a plurality of multi-bit storage cells. Each of the plurality of multi-bit storage cells is capable of storing different levels of charge usable to represent data. The data is represented by least significant bits (LSBs) and a most significant bits (MSBs). The method includes programming the storage cells first with LSBs and then with MSB data. Each of the programmed storage cells has a threshold voltage lower than a voltage VR1 when it is desired that the storage cell store a first value. Each of the cells has a threshold voltage greater than the voltage VR1 and lower than a voltage VR2 when it is desired that the storage cell store a second value. Each of the cells has a threshold voltage greater than the voltage VR2 and lower than a voltage VR3 when it is desired that the storage cell store a third value. Each of the cells has a threshold voltage greater than a voltage VR3 when it is desired that the storage cell store a fourth value. The voltage VR1 is less than VR2 which is less than VR3. The flag cell is programmed to have a threshold voltage greater than the voltage VR3 to indicate that the MSB data have been programmed.
- A method for programming a multi-level non-volatile memory comprising at least one flag cell and a plurality of multi-bit storage cells. Each of the plurality of multi-bit storage cells is capable of storing different levels of charge usable to represent data. The data is represented by a plurality of data pages. The method includes sequentially programming one or more of the plurality of data pages such that each of the programmed storage cells has a threshold voltage within one of a plurality of threshold voltage ranges comprising a first range and a plurality of subsequent ranges. Each of the plurality of subsequent ranges is defined as being equal to or greater than a respective verify voltage. Each of the plurality of subsequent ranges is read at a respective read voltage. For each given subsequent range, the respective read voltage is less than the respective verify voltage by a margin M. The at least one flag cell is programmed to a threshold voltage within a threshold voltage range indicative of the number of data pages that have been programmed. The flag cell threshold voltage range is defined as being equal to or greater than a flag cell verify voltage. The flag cell is read at a flag cell read voltage. The flag cell read voltage is less than the flag cell verify voltage by an enhanced margin Menhanced that is larger than the margin M.
- A controller for controlling memory according to a method for programming multi-level non-volatile memory comprising at least one flag cell and a plurality of multi-bit storage cells. Each of the plurality of multi-bit storage cells is capable of storing different levels of charge usable to represent data. The data is represented by a plurality of data pages. The method includes sequentially programming one or more of the plurality of data pages such that each of the programmed storage cells has a threshold voltage within one of a plurality of threshold voltage ranges comprising a first range and a plurality of subsequent ranges. Each of the plurality of subsequent ranges is defined as being equal to or greater than a respective verify voltage. Each of the plurality of subsequent ranges is read at a respective read voltage. For each given subsequent range, the respective read voltage is less than the respective verify voltage by a margin M. The at least one flag cell is programmed to a threshold voltage within a threshold voltage range indicative of the number of data pages that have been programmed. The flag cell threshold voltage range is defined as being equal to or greater than a flag cell verify voltage. The flag cell is read at a flag cell read voltage. The flag cell read voltage is less than the flag cell verify voltage by an enhanced margin Menhanced that is larger than the margin M.
- A more complete appreciation of the present disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
-
FIG. 1 is a schematic diagram showing a single cell of flash memory; -
FIG. 2 shows an example of a string of NAND flash memory; -
FIG. 3 shows an example of a flash memory block; -
FIG. 4 illustrates the four states of a 2-bit multi-level flash according to an exemplary embodiment of the present invention; -
FIG. 5 illustrates an exemplary electrical signal used as part of a method of ISPP ention; -
FIG. 6 illustrates an electrical signal used as part of a method of ISPP according to another exemplary embodiment of the present invention; -
FIG. 7 illustrates the four possible states of a 2-bit memory according to an exemplary embodiment of the present invention; -
FIG. 8 illustrates a method for programming data in a cell according to an exemplary embodiment of the present invention; -
FIG. 9 illustrates a method for programming a multi-level non-volatile memory device according to an exemplary embodiment of the present invention; -
FIG. 10 illustrates a method for programming a multi-level non-volatile memory device according to an exemplary embodiment of the present invention; -
FIG. 11 illustrates a method for programming a multi-level non-volatile memory device according to an exemplary embodiment of the present invention; -
FIGS. 12A-12B show a three-bit memory device according to an exemplary embodiment of the present invention; -
FIGS. 12C-12D show a three-bit memory device according to an exemplary embodiment of the present invention; -
FIG. 13 is a table showing bias conditions for controlling a two-bit multi-level non-volatile memory device according to an exemplary embodiment of the present invention; -
FIG. 14 is a schematic representation of a memory page according to an exemplary embodiment of the present invention; and -
FIG. 15 shows a memory system including flash memory according to an exemplary embodiment of the present invention. - In describing the preferred embodiments of the present disclosure illustrated in the drawings, specific terminology is employed for sake of clarity. However, the present disclosure is not intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents which operate in a similar manner.
- Embodiments of the present invention may allow for high-precision programming of cells within a multi-level non-volatile memory device, for example, a flash memory having two or more bits.
-
FIG. 4 illustrates the four states of a 2-bit multi-level flash. In thisgraph 400, the x-axis represents threshold voltage while the y-axis represents the probability distribution for the threshold voltage of a particular programmed cell. The threshold voltage of the cell is represented as a probability distribution and thus the cell's charge states are represented as a curve showing the likelihood that the cell programmed according to a particular state would have a particular threshold value. - A given cell may have one of the four possible threshold voltage probability curves 410, 420, 430, 440 representative of a first state, a second state, a third state and a fourth state respectively. In the ideal case, a cell having the threshold
voltage probability curve 410 will not register a current at any of test voltages VR1, VR2, and VR3. A cell having the thresholdvoltage probability curve 420 will register a current at VR1 but not at VR2 or VR3. A cell having thethreshold voltage curve 430 will register a current at VR1 and VR2 but not at VR3. A cell having thethreshold voltage curve 440 will register a current at all test voltages VR1, VR2, and VR3. Accordingly, in the ideal case, it is possible to distinguish between four states by reading the cell at each of 3 voltages VR1, VR2, and VR3. - It may also be desirable to leave a margin between the threshold voltage ranges 420, 430, and 440 and the measurement voltages VR1, VR2, and VR3 respectively. These margins are shown as the distance M and extend from the measurement voltage and the adjacent verify voltage VF1, VF2, and VF3 which indicates the start of the threshold voltage ranges 420, 430, and 440.
- While the exact threshold voltage ranges may be selected according to design and manufacturing constraints, specific voltages may be provided herein solely as an example, and it is contemplated that the states of the cell may be set according to any voltage scale. For example, the
first state 410 may be represented by a cell having a threshold voltage less than approximately −2 Volts. Thesecond state 420 may be represented by a cell having a threshold voltage within the range of 0.3 to 0.7 Volts. Thethird state 430 may be represented by a cell having a threshold voltage within the range of 1.3 to 1.7 Volts. Thefourth state 440 may be represented by a cell having a threshold voltage within the range of 2.3 to 2.7 Volts. - As discussed above, as the number of possible memory states of a cell increases, the ranges of threshold voltages that correspond to a given state become more narrow as do the margins that separate the threshold voltages from the measurement voltages. Accordingly, it is increasingly important to program each cell with a high degree of precision.
- One method for increasing programming precision is Incremental Step Pulse Programming (ISIPP).
FIG. 5 shows an exemplary wave form useable for ISPP. -
FIG. 6 shows a waveform for ISPP according to an exemplary embodiment of the present invention. The use of the waveform shown inFIG. 6 facilitates smaller cell threshold voltage variations than the use of the waveform shown inFIG. 5 . Here, the electrical signal 600 (Vpgm) comprises a series of pulses with each pulse extending for a length of time constituting aprogram period 620. Each pulse may be separated by a length of time constituting a verifyperiod 640. The voltage of each successive pulse may increase, for example, by a voltage 630 (ΔVpgm), which may be, for example, 0.5V. For example, the voltage of thefirst pulse 610 may be 15V. Each successive pulse may increase up to and including amaximum voltage 650 which may be, for example, 19V. The threshold voltage of the cell may be tested, for example, between each pulse or periodically, for example, every 3 pulses, to see if the proper threshold voltage has been achieved. If it has not been achieved, additional pulses may be applied. - After the cell has been programmed, the cell may be read to verify that the cell has been properly programmed. For example, the threshold voltage may be tested to see if it has been set sufficiently high. If it has not been, additional pulses may be applied until the threshold voltage is sufficiently high.
- A set of verification test voltages may be used to verify the programmed threshold voltages. The verification voltages (VF) may be different than the test voltages used to read the cells (VR). For example, the verification voltages VF1, VF2, VF3 may each be greater than the corresponding read voltages VR1, VR2, VR3 by the amount of the margin M discussed above.
- Each cell state of a multi-bit memory device may be represented by a number. For example, where a 2-bit flash is used, each of the four possible states may be expressed by a 2-bit binary number. For example, the first unprogrammed state may be expressed as “11,” the second state may be expressed as “01, ” the third state may be expressed as “10,” and the fourth state may be expressed as “00.”
FIG. 7 illustrates the four possible states of a 2-bit memory according to an embodiment of the present invention. It should be understood that the nomenclature may be arbitrary and the present nomenclature is offered as an example. Here, the thresholdvoltage probability distribution 700 for each of the four states is shown. It is to be understood that a given cell may only have one threshold voltage at a time and the threshold voltage may be within one of the 4 states, with the exact threshold voltage falling within the distribution for that state in accordance with the probability curve. - Each 2-bit binary number may be said to include a most significant bit (MSB) and a least significant bit (LSB). In the first unprogrammed state 710, the MSB 712 is “1” and the LSB 718 is “1.” In the second state 720, the MSB 722 is “0” and the LSB 728 is “1.” In the third state 730, the MSB 732 is “1” and the MSB 738 is “0.” In the fourth state 740, the MSB 742 is “0” and the LSB 748 is “0.”
- As discussed above, data may be stored in each cell by trapping a level of charge in the floating gate necessary to achieve a threshold voltage within a desired range, with each range representing a state. Accordingly, data may be stored in the cell by programming the cell and in the case of a 2-bit memory, 2-bits of data may be stored in each cell. When desired, 2-bit memory cells may be programmed with only a single bit of data. Similarly, a cell programmed with only a first bit of data may be later programmed with a second bit of data. When only a single bit of data is programmed in a cell, the cell is said to contain only LSB data. When 2-bits of data are programmed in a cell, the cell is said to contain both LSB data and MSB data. It may be desirable, and in some cases necessary, to first program (and verify) LSB data within a cell and then to program (and verify) MSB data within the cell. It should be understood that in NAND flash memory, cells may be programmed one page at a time. Accordingly, the LSB cells of a physical page may be considered an LSB logical page and the MSB cells of the physical page may be considered an MSB logical page wherein the process of programming a physical page includes first programming (and verifying) the LSB logical page and next programming (and verifying) the MSB logical page.
-
FIG. 8 illustrates a method for programming data in a cell according to an exemplary embodiment of the present invention.Lin 800A represents a cell where only LSB data has been programmed. The unprogrammed state of LSB data is “1.” When it is desired that a “0” be stored, the cell is programmed until the threshold voltage is verified to be within the appropriate range of the “0” state (greater than VF2*). Such a programming step is illustrated as P1. - When only LSB data is stored in a cell, the cell may be read at a single voltage, here shown as VR1. If at voltage VR1, current can be observed, then the cell is determined to be in the unprogrammed “1” state. If at voltage VR1, no current can be observed, then the cell is determined to be in the “0” state.
- At least partly because of the close proximity of adjacent cells, the programming of adjacent cells may affect the threshold voltage for a given cell in a phenomenon identified as the coupling effect. Because of this potential for change in threshold voltage of the affected cell, the probability curve may widen.
Line 800B represents the cell where only LSB data has been programmed and the threshold voltage probability curve has widened by an amount D1. - When the MSB page is programmed after the LSB page is programmed, as is the case with some exemplary embodiments of the present invention, the “1” LSB data state of
line 800B may remain as the “11” data state ofline 800C or may be programmed until the threshold voltage is verified to be within the appropriate range of the “01” state ofline 800C (greater than VF1) through a programming step shown as P2. Similarly, the “0” data state ofline 800B may be programmed until the threshold voltage is verified to be within the appropriate range of the “10” state ofline 800C (greater than VF2) through a programming step shown as P3 or it may be programmed until the threshold voltage is verified to be within the appropriate range of the “00” data state ofline 800C (greater than VF3) through a programming step shown as P4. Each programming step may utilize an ISPP process, for example, the ISPP processes described above. - When reading data from the memory device, it may be necessary to know whether only LSB data have been stored or whether both LSB data and MSB data have been stored. There are many reasons why this information should be known. For example, reading only LSB data only requires reading at one voltage (VR1) while reading LSB and MSB data requires reading at three voltages (VR1, VR2, and VR3) as discussed above. Additionally, as shown in
line 800B, the “0” state of LSB data may include threshold voltages on either side of the VR2 voltage. - VF1 is greater than VR1 by a margin M. Similarly, VF2 is greater than VR2 by a margin M and VF3 is greater than VR3 by a margin M. All margins M may be the same; however, this is not required. Allowing a margin may improve read accuracy.
- Embodiments of the present invention may utilize a cell referred to as an MSB flag to indicate whether MSB data has been stored. Where a cell of a storage device is dedicated as an MSB flag cell, the remaining cells may be referred to as data storage cells. At a later point when reading of the stored data is desired, the MSB flag cell may be read to allow for an accurate interpretation of the stored data regardless of whether only LSB data have been stored or whether both LSB and MSB data have been stored. There may be at least one MSB flag cell for each page indicating whether MSB data has been stored to that page.
- Line 800D illustrates an MSB flag cell in the unprogrammed “1” state. This state may be used to indicate that MSB data has not been programmed.
Line 800E illustrates an MSB flag cell in the “0” state. This state may be used to indicate that MSB data has been programmed. The MSB flag may begin in the “1” state and may be programmed until the threshold voltage is verified to be in the “0” state (greater than VF3) by a programming step P5 to indicate that MSB data has been programmed. - As discussed above, the “0” state of the MSB flag may be programmed until the threshold voltage of the MSB flag cell is greater than VF3. While the threshold voltage of this state is greater than VR3 by the margin M, the MSB flag is read from VR2 to provide an enhanced margin. This enhanced margin is illustrated as MEnhanced.
- A phenomenon referred to as charge loss may occur as charge unintentionally escapes from the floating gate of a cell. Charge may unintentionally escape due to defects in the insulation layer or some other factor. Loss of charge may result in the possibility that the threshold voltage can become lower than is desired. This possibility may be represented by a spreading of the probability curve in the lower-voltage direction.
- While charge loss may occur at any cell, storage cells tend to have a greater level of error correction measures than the MSB flag cell. Additionally, charge loss in one storage cell may render only the affected cell unreadable, while charge loss in the MSB flag cell may render an entire page unreadable. Accordingly charge loss in the MSB flag cell may be especially problematic.
- For at least this reason, the enhanced margin MEnhanced may be great enough to allow for an accurate read of the MSB flag cell even if charge is lost from the floating gate of the MSB flag cell. According to one embodiment of the present invention, the distance MEnhanced may be sufficient to place the “0” state of the MSB flag at the same distribution curve as the “00” state of the storage cell (shown as “00” on
line 800C). By defining the “0” state of the MSB flag cell accordingly, the MSB flag cell may be accurately read even in less-than ideal conditions. -
FIG. 9 illustrates a method for programming a multi-level non-volatile memory device according to an exemplary embodiment of the present invention. First, the LSB data of the storage cells may be programmed (Step S910). As discussed above, the LSB logical page may be programmed by employing an ISPP process until the threshold voltage is verified as being greater than VF2* where a ‘0’ state is desired. If the ‘1’ state is desired than no programming is necessary at this step. Next MSB data may be used to program the “00” state, where desired, (Step S920A) by employing the ISPP process until the threshold voltage is verified as being greater than VF3. This programming step may include implementing an ISPP process to add additional charge to the “0” LSB state. The MSB flag cell may be programmed from the non-programmed state “1” to the programmed state “0” (Step S920B) to indicate that MSB data has been programmed. This programming step may include implementing an ISPP process to add additional charge to the “1” state to achieve the “0” state. As described above, the “0” state for the MSB flag cell may be programmed until the threshold voltage is verified as being greater than VR3. Steps S920A and S920B may be simultaneously executed as they may both use the same VR3 verification voltage. Next, the MSB data may be used to program the “01” and “10” states (Step S390) where desired. This programming step may include implementing an ISPP process to add additional charge to the “1” and “0” states to achieve the “01” and “10” states respectively by programming the threshold voltage is verified as being greater than VF1 and VF2 respectively. The “11” state may be achieved by leaving the cell in its unprogrammed “1” state. - However, a problem may arise if the above writing process is prematurely ended, for example, if power is interrupted during the programming of the “00” state with MSB data (Step S920A) and the programming of the MSB flag cell (Step S920B). In such an event, while LSB data may be potentially readable, MSB data would not be readable and yet the state of the MSB flag cell may not be clearly identifiable. Because of the ambiguous state of the MSB flag cell, the LSB data may be rendered unreadable.
- Exemplary embodiments of the present invention discussed below concern both approaches to programming main memory cells and approaches to programming flag cells when programming main memory cells. It is to be understood that the approaches to programming main memory cells discussed below and the approaches to programming flag cells discussed below are not interdependent and do not require that the specific approaches be combined in the manner shown. Particularly, the approaches to programming main memory cells discussed below may be combined with other approaches to programming flag cells not discussed below but known in the art while the approaches to programming flag cells discussed below may be combined with other approaches to programming main memory cells not discussed below but known in the art.
- Accordingly,
FIGS. 10 and 11 illustrate an alternative method for programming a multi-level non-volatile memory device according to another exemplary embodiment of the present invention. First, LSB data may be programmed in the manner discussed above (Step S1010) (Line 1100A). Next, the ‘0’ state may be advanced to the advanced state “A” by programming the cell until the threshold voltage is verified as being greater than VF2 (Step S1020) (Line 1100B). The state defined by programming to VF2 is also defined as the ‘10’ state, however, this step may be performed when either the ‘10’ state or the ‘00’ state is desired. The MSB flag cell may remain unprogrammed at this step (1110B). Next, the ‘00’ state may be programmed, if desired, by programming the A state until the threshold voltage is verified as being greater than VF3 or where the ‘10’ state is desired, no additional programming need occur (Step S1030A) (Line 1100C). The MSB flag may be programmed at this point by programming the MSB flag cell until the threshold voltage is verified as being greater than VF3 (Step S1030B) (Line 1100C), Steps S1030A and S1030B may be executed simultaneously or near simultaneously as they both involve programming to the VF3 verification voltage. Finally, the “01” state may be programmed where desired by programming the “1” state until the threshold voltage is verified as being greater than VF1 (Step S1040) (Line 1100D). - While the exemplary embodiments discussed above describe a two-bit multi-level non-volatile memory device, it is to be understood that the exemplary embodiments of the present invention may be applied to a multi-level non-volatile memory device with any number of bits. For example, a three-bit multi-level non-volatile memory device may be used. The three-bit device would have 8 available memory states for each cell. These memory states may be called “111,” “011,” “101,” “001,” “110,” “010,” “100,” and “000” respectively. The three-bit memory device, instead of having an LSB page and a MSB page, would have a first logical page, a second logical page and a third logical page. There may also be a first flag cell indicating when the second page has been programmed and a second flag cell indicating when the third page has been programmed. Alternatively, a single flag cell may be used having multiple memory states to indicate when the second page has been programmed and when the third page has been programmed. For example, the flag cell may initially be set to an unprogrammed ‘111’ state indicating that neither second nor third data pages have been programmed, the flag cell may be programmed to a ‘010’ state to indicate that the second data page has been loaded and the flag cell may be programmed to a ‘000’ state to indicate that the third data page has been loaded. For embodiments where two flag cells are used, the first flag cell may be programmed to the ‘0’ state to indicate that the second data page has been programmed and the second flag cell may be programmed to the ‘0’ state to indicate that the third data page has been programmed. While embodiments of the present invention utilize either approach, the exemplary embodiments of the present invention are discussed in terms of the first approach for simplicity.
- For embodiments where there are more than three-bits, there may be more than 8 available memory states and more than three flag cells or more than three states on a single flag cell.
-
FIGS. 12A-12D show a three-bit memory device according to exemplary embodiments of the present invention. Many of the details as to how to program the various cells may be understood to be analogous to the exemplary embodiments discussed herein. It should be understood that the features of these examples may be extrapolated to provide multi-bit memory devices of greater than three bits. - According to some exemplary embodiments of the present invention, the storage cells are not advanced prior to second page and third page programming.
FIGS. 12A and 12B illustrate such an embodiment. With respect toFIGS. 12A and 12B , the first page may be programmed (line 1417, step S1423). The flag cell may originate in the unwritten ‘111’ state (line 1418). Then, the second page data may be programmed (line 1419, step S1424) and the flag cell may be programmed to a level indicating that second data page has been programmed (line 1420, Step S1425). For example, the flag cell may be programmed to the ‘010’ state. The two steps S1424 and S1425 may occur simultaneously or nearly simultaneously. The third page data may then be programmed (line 1421, step S1426) and the flag cell may be programmed to a level indicating that the third data page has been programmed (line 1422, step S1427). For example, the flag cell may be programmed to the ‘000’ state. The two steps S1426 and S1427 may occur simultaneously or nearly simultaneously. - With respect to
FIGS. 12A and 12D , the first page may be programmed (line 1430, step S1440). The flag cell may originate in the unwritten ‘111’ state (line 1431). The ‘0’ bit may then be advanced (line 1432, step S1441) so that the first page data may be protected from data corruption in the event of an unanticipated interruption. The flag cell may remain in the ‘111’ state (line 1433). Then, the second page data may be programmed (line 1434, step S1442) and the flag cell may be programmed to a level indicating that second data page has been programmed (line 1435, Step S1443). For example, the flag cell may be programmed to the ‘000’ state. The two steps S1442 and S1443 may occur simultaneously or nearly simultaneously. The second page data states ‘01,’ ‘10,’ and ‘00’ may then be advanced (line 1446, step S1444) so that the second page data may be protected from data corruption in the event of an unanticipated interruption. The flag cell may also be advanced from the ‘000’ state to the ‘100’ state (line 1437, step S1445). The third page data may then be programmed (line 1438, step S1446) and the flag cell may be programmed to a level indicating that the third data page has been programmed (line 1439, step S1447). For example, the flag cell may be programmed to the ‘000’ state. The two steps S1446 and S1447 may occur simultaneously or nearly simultaneously. - While multi-level non-volatile memory devices may use any conceivable scheme for the programming of data cells,
FIG. 13 is a table showing bias conditions for controlling a two-bit multi-level non-volatile memory device according to an exemplary embodiment of the present invention. This table shows examples of signals that may be used to erase, program, inhibit, read and verify the storage cells and flag cell according to an exemplary embodiment of the present invention. - The table in
FIG. 13 summarizes voltages applied to operate the memory cell array according to an exemplary embodiment of the present invention. The top row of the table defines a set of possible memory functions that may be performed. These functions include erasing memory, programming memory, inhibiting the programming of memory, and reading LSB, MSB and flag cell data. For each desired function, the first column labels each line that may receive a voltage in the execution of the desired function. The remaining rows and columns of the table define the set of voltages that are to be applied to each of the lines listed on the first column to perform the desired function listed on the top row. The voltages may be specified in terms of a specific voltage such as 0 V or 20 V. The voltages may alternatively be specified in terms of a signal such as Vcc or Vpgm that have been described in detail above. The term “Floating” indicates that the line is not set to a particular voltage. “H or L” indicates that the line may be sent a high signal or a low signal. Vread is applied to unselected WLs when reading data, and Vpass is applied to unselected WLs when programming. -
FIG. 4 is a schematic representation of a memory page according to an exemplary embodiment of the present invention. Thememory page 1600 shows multiple data storage cells on multiple data storage bit lines. The data storage bit lines are controlled by a set ofdata storage circuits data block 1610. -
FIG. 15 shows a memory system including flash memory according to an exemplary embodiment of the present invention. Memory systems may include aflash memory 1500 and amemory controller 1510. Thememory controller 1510 may control the operation of theflash memory 1500. - It is to be understood that while many of the figures show a cell having multiple threshold voltage curves, these multiple threshold voltage curves are shown for the purposes of illustrating all of the possible states and it is to be understood that any one given cell will only have one threshold voltage range at a given time. Moreover, when the disclosure discusses programming a state, it is to be understood that programming is only executed to the extent desired. Accordingly, when a process step describes programming a cell, for example, to the ‘00’ state, this programming step is only executed when such a state is desired. It is to be understood that once the desired state has already been achieved, the cell will not be programmed to another state.
- The above specific embodiments are illustrative and many variations can be introduced on these embodiments without departing from the spirit of the disclosure or from the scope of the appended claims. For example, elements and/or features of different illustrative embodiments may be combined with each other and/or substituted for each other within the scope of this disclosure and appended claims.
Claims (28)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007230423A JP2008065978A (en) | 2006-09-06 | 2007-09-05 | Program method for multi-level non-volatile memory device |
CN2007103061929A CN101197190B (en) | 2006-09-06 | 2007-09-06 | Programming method for multi-level non-volatile memory device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020060085880A KR100771883B1 (en) | 2006-09-06 | 2006-09-06 | Multi-level non-volatile memory device and program method thereof |
KR10-2006-0085880 | 2006-09-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20080089123A1 true US20080089123A1 (en) | 2008-04-17 |
US7596022B2 US7596022B2 (en) | 2009-09-29 |
Family
ID=39060398
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/848,014 Active 2027-09-14 US7596022B2 (en) | 2006-09-06 | 2007-08-30 | Method for programming a multi-level non-volatile memory device |
Country Status (3)
Country | Link |
---|---|
US (1) | US7596022B2 (en) |
KR (1) | KR100771883B1 (en) |
CN (1) | CN101197190B (en) |
Cited By (76)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080080237A1 (en) * | 2006-09-29 | 2008-04-03 | Hynix Semiconductor Inc. | Method of programming a multi level cell |
US20080084739A1 (en) * | 2006-09-06 | 2008-04-10 | Dong Hyuk Chae | Method for Programming a Multi-Level Non-Volatile Memory Device |
US20080126686A1 (en) * | 2006-11-28 | 2008-05-29 | Anobit Technologies Ltd. | Memory power and performance management |
US20080144380A1 (en) * | 2006-12-13 | 2008-06-19 | Dong-Kyu Youn | Nonvolatile memory device having flag cells for storing MSB program state |
US20080189478A1 (en) * | 2007-02-06 | 2008-08-07 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device with advanced multi-page program operation |
US20090213654A1 (en) * | 2008-02-24 | 2009-08-27 | Anobit Technologies Ltd | Programming analog memory cells for reduced variance after retention |
US20090296467A1 (en) * | 2008-06-03 | 2009-12-03 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of driving the same |
US20090313423A1 (en) * | 2008-06-17 | 2009-12-17 | Samsung Electronics Co., Ltd. | Multi-bit flash memory device and method of analyzing flag cells of the same |
US20100131827A1 (en) * | 2007-05-12 | 2010-05-27 | Anobit Technologies Ltd | Memory device with internal signap processing unit |
US20100165730A1 (en) * | 2006-10-30 | 2010-07-01 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
CN101872642A (en) * | 2009-04-23 | 2010-10-27 | 无锡华润上华半导体有限公司 | Storing and reading method for random access memory |
US7881107B2 (en) | 2007-01-24 | 2011-02-01 | Anobit Technologies Ltd. | Memory device with negative thresholds |
US7900102B2 (en) | 2006-12-17 | 2011-03-01 | Anobit Technologies Ltd. | High-speed programming of memory devices |
US7924613B1 (en) * | 2008-08-05 | 2011-04-12 | Anobit Technologies Ltd. | Data storage in analog memory cells with protection against programming interruption |
US7925936B1 (en) | 2007-07-13 | 2011-04-12 | Anobit Technologies Ltd. | Memory device with non-uniform programming levels |
US7924587B2 (en) | 2008-02-21 | 2011-04-12 | Anobit Technologies Ltd. | Programming of analog memory cells using a single programming pulse per state transition |
US7995388B1 (en) | 2008-08-05 | 2011-08-09 | Anobit Technologies Ltd. | Data storage using modified voltages |
US8000141B1 (en) | 2007-10-19 | 2011-08-16 | Anobit Technologies Ltd. | Compensation for voltage drifts in analog memory cells |
US8001320B2 (en) | 2007-04-22 | 2011-08-16 | Anobit Technologies Ltd. | Command interface for memory devices |
US8000135B1 (en) | 2008-09-14 | 2011-08-16 | Anobit Technologies Ltd. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8050086B2 (en) | 2006-05-12 | 2011-11-01 | Anobit Technologies Ltd. | Distortion estimation and cancellation in memory devices |
US8060806B2 (en) | 2006-08-27 | 2011-11-15 | Anobit Technologies Ltd. | Estimation of non-linear distortion in memory devices |
US8059457B2 (en) | 2008-03-18 | 2011-11-15 | Anobit Technologies Ltd. | Memory device with multiple-accuracy read commands |
US8068360B2 (en) | 2007-10-19 | 2011-11-29 | Anobit Technologies Ltd. | Reading analog memory cells using built-in multi-threshold commands |
US8085586B2 (en) | 2007-12-27 | 2011-12-27 | Anobit Technologies Ltd. | Wear level estimation in analog memory cells |
US8151166B2 (en) | 2007-01-24 | 2012-04-03 | Anobit Technologies Ltd. | Reduction of back pattern dependency effects in memory devices |
US8151163B2 (en) | 2006-12-03 | 2012-04-03 | Anobit Technologies Ltd. | Automatic defect management in memory devices |
US8156403B2 (en) | 2006-05-12 | 2012-04-10 | Anobit Technologies Ltd. | Combined distortion estimation and error correction coding for memory devices |
US8156398B2 (en) | 2008-02-05 | 2012-04-10 | Anobit Technologies Ltd. | Parameter estimation based on error correction code parity check equations |
US8169825B1 (en) | 2008-09-02 | 2012-05-01 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells subjected to long retention periods |
US8174857B1 (en) | 2008-12-31 | 2012-05-08 | Anobit Technologies Ltd. | Efficient readout schemes for analog memory cell devices using multiple read threshold sets |
US8174905B2 (en) | 2007-09-19 | 2012-05-08 | Anobit Technologies Ltd. | Programming orders for reducing distortion in arrays of multi-level analog memory cells |
US20120147669A1 (en) * | 2010-12-14 | 2012-06-14 | Dae-Seok Byeon | Non-volatile memory device and a method for operating the device |
US8208304B2 (en) | 2008-11-16 | 2012-06-26 | Anobit Technologies Ltd. | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
US8209588B2 (en) | 2007-12-12 | 2012-06-26 | Anobit Technologies Ltd. | Efficient interference cancellation in analog memory cell arrays |
US20120175953A1 (en) * | 2009-09-28 | 2012-07-12 | Hitachi, Ltd. | Battery System |
US8225181B2 (en) | 2007-11-30 | 2012-07-17 | Apple Inc. | Efficient re-read operations from memory devices |
US8230300B2 (en) | 2008-03-07 | 2012-07-24 | Apple Inc. | Efficient readout from analog memory cells using data compression |
US8228701B2 (en) | 2009-03-01 | 2012-07-24 | Apple Inc. | Selective activation of programming schemes in analog memory cell arrays |
US8234545B2 (en) | 2007-05-12 | 2012-07-31 | Apple Inc. | Data storage with incremental redundancy |
US8239734B1 (en) | 2008-10-15 | 2012-08-07 | Apple Inc. | Efficient data storage in storage device arrays |
US8239735B2 (en) | 2006-05-12 | 2012-08-07 | Apple Inc. | Memory Device with adaptive capacity |
US8238157B1 (en) | 2009-04-12 | 2012-08-07 | Apple Inc. | Selective re-programming of analog memory cells |
US8248831B2 (en) | 2008-12-31 | 2012-08-21 | Apple Inc. | Rejuvenation of analog memory cells |
US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
US8261159B1 (en) | 2008-10-30 | 2012-09-04 | Apple, Inc. | Data scrambling schemes for memory devices |
US8259497B2 (en) | 2007-08-06 | 2012-09-04 | Apple Inc. | Programming schemes for multi-level analog memory cells |
US8270246B2 (en) | 2007-11-13 | 2012-09-18 | Apple Inc. | Optimized selection of memory chips in multi-chips memory devices |
US8369141B2 (en) | 2007-03-12 | 2013-02-05 | Apple Inc. | Adaptive estimation of memory cell read thresholds |
US8400858B2 (en) | 2008-03-18 | 2013-03-19 | Apple Inc. | Memory device with reduced sense time readout |
US8479080B1 (en) | 2009-07-12 | 2013-07-02 | Apple Inc. | Adaptive over-provisioning in memory systems |
US8482978B1 (en) | 2008-09-14 | 2013-07-09 | Apple Inc. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8495465B1 (en) | 2009-10-15 | 2013-07-23 | Apple Inc. | Error correction coding over multiple memory pages |
US8527819B2 (en) | 2007-10-19 | 2013-09-03 | Apple Inc. | Data storage in analog memory cell arrays having erase failures |
US8572423B1 (en) | 2010-06-22 | 2013-10-29 | Apple Inc. | Reducing peak current in memory systems |
US8572311B1 (en) | 2010-01-11 | 2013-10-29 | Apple Inc. | Redundant data storage in multi-die memory systems |
US8595591B1 (en) | 2010-07-11 | 2013-11-26 | Apple Inc. | Interference-aware assignment of programming levels in analog memory cells |
US8645794B1 (en) | 2010-07-31 | 2014-02-04 | Apple Inc. | Data storage in analog memory cells using a non-integer number of bits per cell |
US8677054B1 (en) | 2009-12-16 | 2014-03-18 | Apple Inc. | Memory management schemes for non-volatile memory devices |
US8694853B1 (en) | 2010-05-04 | 2014-04-08 | Apple Inc. | Read commands for reading interfering memory cells |
US8694854B1 (en) | 2010-08-17 | 2014-04-08 | Apple Inc. | Read threshold setting based on soft readout statistics |
US8694814B1 (en) | 2010-01-10 | 2014-04-08 | Apple Inc. | Reuse of host hibernation storage space by memory controller |
US8832354B2 (en) | 2009-03-25 | 2014-09-09 | Apple Inc. | Use of host system resources by memory controller |
US8856475B1 (en) | 2010-08-01 | 2014-10-07 | Apple Inc. | Efficient selection of memory blocks for compaction |
US8924661B1 (en) | 2009-01-18 | 2014-12-30 | Apple Inc. | Memory system including a controller and processors associated with memory devices |
US8949684B1 (en) | 2008-09-02 | 2015-02-03 | Apple Inc. | Segmented data storage |
KR101495795B1 (en) | 2008-06-13 | 2015-02-27 | 삼성전자주식회사 | Nonvolatile memory device and programming method thereof |
US9021181B1 (en) | 2010-09-27 | 2015-04-28 | Apple Inc. | Memory management for unifying memory cell conditions by using maximum time intervals |
US9104580B1 (en) | 2010-07-27 | 2015-08-11 | Apple Inc. | Cache memory for hybrid disk drives |
TWI501241B (en) * | 2008-07-01 | 2015-09-21 | Seagate Technology Llc | Methods and apparatus for soft demapping and intercell interference mitigation in flash memories |
TWI566250B (en) * | 2014-10-13 | 2017-01-11 | 力旺電子股份有限公司 | Nonvolatile memory having memory array with differential cells |
US9696918B2 (en) | 2014-07-13 | 2017-07-04 | Apple Inc. | Protection and recovery from sudden power failure in non-volatile memory devices |
US20190156904A1 (en) * | 2017-09-11 | 2019-05-23 | SK Hynix Inc. | Semiconductor memory device and method of operating the same |
US10923186B2 (en) * | 2019-03-22 | 2021-02-16 | Toshiba Memory Corporation | Semiconductor memory device to hold 5-bits of data per memory cell |
US11556416B2 (en) | 2021-05-05 | 2023-01-17 | Apple Inc. | Controlling memory readout reliability and throughput by adjusting distance between read thresholds |
US11847342B2 (en) | 2021-07-28 | 2023-12-19 | Apple Inc. | Efficient transfer of hard data and confidence levels in reading a nonvolatile memory |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8027194B2 (en) | 1988-06-13 | 2011-09-27 | Samsung Electronics Co., Ltd. | Memory system and method of accessing a semiconductor memory device |
KR100948468B1 (en) * | 2007-12-24 | 2010-03-17 | 주식회사 하이닉스반도체 | The method for flag satus deterimining of non volatile memory device |
KR100933852B1 (en) * | 2007-12-28 | 2009-12-24 | 주식회사 하이닉스반도체 | Nonvolatile Memory Device and Operation Method |
KR101512199B1 (en) * | 2009-06-29 | 2015-04-14 | 에스케이하이닉스 주식회사 | Method of operating a non volatile memory device |
KR101616097B1 (en) * | 2009-11-11 | 2016-04-28 | 삼성전자주식회사 | Programing method of nonvolatile memory device |
US8406051B2 (en) | 2010-05-17 | 2013-03-26 | Seagate Technology Llc | Iterative demodulation and decoding for multi-page memory architecture |
US8254167B2 (en) | 2010-05-17 | 2012-08-28 | Seagate Technologies Llc | Joint encoding of logical pages in multi-page memory architecture |
US8451662B2 (en) | 2011-03-03 | 2013-05-28 | Micron Technology, Inc. | Reading memory cell history during program operation for adaptive programming |
CN102543147A (en) * | 2012-01-18 | 2012-07-04 | 北京大学 | Reading circuit and reading method of multilevel storage circuit |
KR101916192B1 (en) | 2012-04-19 | 2018-11-07 | 삼성전자주식회사 | Nonvolatile memory device comprising flag cell and user device comprising the same |
CN104571933B (en) * | 2013-10-18 | 2017-10-13 | 光宝科技股份有限公司 | Have the electronic installation and its corresponding control methods of solid-state storage element |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5299162A (en) * | 1992-02-21 | 1994-03-29 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device and an optimizing programming method thereof |
US5831900A (en) * | 1995-09-13 | 1998-11-03 | Kabushiki Kaisha Toshiba | Nonvolatile multi-level semiconductor memory device with registers |
US6456528B1 (en) * | 2001-09-17 | 2002-09-24 | Sandisk Corporation | Selective operation of a multi-state non-volatile memory system in a binary mode |
US6859397B2 (en) * | 2003-03-05 | 2005-02-22 | Sandisk Corporation | Source side self boosting technique for non-volatile memory |
US6958934B2 (en) * | 2002-01-17 | 2005-10-25 | Macronix International Co., Ltd. | Method of programming and erasing multi-level flash memory |
US7120052B2 (en) * | 2002-11-29 | 2006-10-10 | Kabushiki Kaisha Toshiba | Semiconductor memory device for storing multivalued data |
US20080084739A1 (en) * | 2006-09-06 | 2008-04-10 | Dong Hyuk Chae | Method for Programming a Multi-Level Non-Volatile Memory Device |
US20080144380A1 (en) * | 2006-12-13 | 2008-06-19 | Dong-Kyu Youn | Nonvolatile memory device having flag cells for storing MSB program state |
US20080189473A1 (en) * | 2007-02-07 | 2008-08-07 | Micron Technology, Inc | Mlc selected multi-program for system management |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6522580B2 (en) | 2001-06-27 | 2003-02-18 | Sandisk Corporation | Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states |
JP4170952B2 (en) * | 2004-01-30 | 2008-10-22 | 株式会社東芝 | Semiconductor memory device |
US8019928B2 (en) | 2004-02-15 | 2011-09-13 | Sandisk Il Ltd. | Method of managing a multi-bit-cell flash memory |
KR100525004B1 (en) * | 2004-02-26 | 2005-10-31 | 삼성전자주식회사 | Multi-level cell flash memory device and program method thereof |
US7092290B2 (en) | 2004-11-16 | 2006-08-15 | Sandisk Corporation | High speed programming system with reduced over programming |
-
2006
- 2006-09-06 KR KR1020060085880A patent/KR100771883B1/en active IP Right Grant
-
2007
- 2007-08-30 US US11/848,014 patent/US7596022B2/en active Active
- 2007-09-06 CN CN2007103061929A patent/CN101197190B/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5299162A (en) * | 1992-02-21 | 1994-03-29 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device and an optimizing programming method thereof |
US5831900A (en) * | 1995-09-13 | 1998-11-03 | Kabushiki Kaisha Toshiba | Nonvolatile multi-level semiconductor memory device with registers |
US6414893B1 (en) * | 1995-09-13 | 2002-07-02 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of using the same |
US6456528B1 (en) * | 2001-09-17 | 2002-09-24 | Sandisk Corporation | Selective operation of a multi-state non-volatile memory system in a binary mode |
US6958934B2 (en) * | 2002-01-17 | 2005-10-25 | Macronix International Co., Ltd. | Method of programming and erasing multi-level flash memory |
US7120052B2 (en) * | 2002-11-29 | 2006-10-10 | Kabushiki Kaisha Toshiba | Semiconductor memory device for storing multivalued data |
US6859397B2 (en) * | 2003-03-05 | 2005-02-22 | Sandisk Corporation | Source side self boosting technique for non-volatile memory |
US20080084739A1 (en) * | 2006-09-06 | 2008-04-10 | Dong Hyuk Chae | Method for Programming a Multi-Level Non-Volatile Memory Device |
US20080144380A1 (en) * | 2006-12-13 | 2008-06-19 | Dong-Kyu Youn | Nonvolatile memory device having flag cells for storing MSB program state |
US20080189473A1 (en) * | 2007-02-07 | 2008-08-07 | Micron Technology, Inc | Mlc selected multi-program for system management |
Cited By (102)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8599611B2 (en) | 2006-05-12 | 2013-12-03 | Apple Inc. | Distortion estimation and cancellation in memory devices |
US8156403B2 (en) | 2006-05-12 | 2012-04-10 | Anobit Technologies Ltd. | Combined distortion estimation and error correction coding for memory devices |
US8239735B2 (en) | 2006-05-12 | 2012-08-07 | Apple Inc. | Memory Device with adaptive capacity |
US8050086B2 (en) | 2006-05-12 | 2011-11-01 | Anobit Technologies Ltd. | Distortion estimation and cancellation in memory devices |
US8570804B2 (en) | 2006-05-12 | 2013-10-29 | Apple Inc. | Distortion estimation and cancellation in memory devices |
US8060806B2 (en) | 2006-08-27 | 2011-11-15 | Anobit Technologies Ltd. | Estimation of non-linear distortion in memory devices |
US20080084739A1 (en) * | 2006-09-06 | 2008-04-10 | Dong Hyuk Chae | Method for Programming a Multi-Level Non-Volatile Memory Device |
US7508705B2 (en) * | 2006-09-06 | 2009-03-24 | Samsung Electronics Co., Ltd. | Method for programming a multi-level non-volatile memory device |
US7609548B2 (en) * | 2006-09-29 | 2009-10-27 | Hynix Semiconductor Inc. | Method of programming a multi level cell |
US20080080237A1 (en) * | 2006-09-29 | 2008-04-03 | Hynix Semiconductor Inc. | Method of programming a multi level cell |
USRE46346E1 (en) | 2006-10-30 | 2017-03-21 | Apple Inc. | Reading memory cells using multiple thresholds |
US8145984B2 (en) | 2006-10-30 | 2012-03-27 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
US20100165730A1 (en) * | 2006-10-30 | 2010-07-01 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
US7975192B2 (en) | 2006-10-30 | 2011-07-05 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
US7924648B2 (en) | 2006-11-28 | 2011-04-12 | Anobit Technologies Ltd. | Memory power and performance management |
US20080126686A1 (en) * | 2006-11-28 | 2008-05-29 | Anobit Technologies Ltd. | Memory power and performance management |
US8151163B2 (en) | 2006-12-03 | 2012-04-03 | Anobit Technologies Ltd. | Automatic defect management in memory devices |
US7532495B2 (en) * | 2006-12-13 | 2009-05-12 | Samsung Electronics Co., Ltd. | Nonvolatile memory device having flag cells for storing MSB program state |
US20080144380A1 (en) * | 2006-12-13 | 2008-06-19 | Dong-Kyu Youn | Nonvolatile memory device having flag cells for storing MSB program state |
US7900102B2 (en) | 2006-12-17 | 2011-03-01 | Anobit Technologies Ltd. | High-speed programming of memory devices |
US7881107B2 (en) | 2007-01-24 | 2011-02-01 | Anobit Technologies Ltd. | Memory device with negative thresholds |
US8151166B2 (en) | 2007-01-24 | 2012-04-03 | Anobit Technologies Ltd. | Reduction of back pattern dependency effects in memory devices |
US8234440B2 (en) | 2007-02-06 | 2012-07-31 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device with advanced multi-page program operation |
US8539144B2 (en) | 2007-02-06 | 2013-09-17 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device with advanced multi-page program operation |
US20080189478A1 (en) * | 2007-02-06 | 2008-08-07 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device with advanced multi-page program operation |
US8046525B2 (en) * | 2007-02-06 | 2011-10-25 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device with advanced multi-page program operation |
US8369141B2 (en) | 2007-03-12 | 2013-02-05 | Apple Inc. | Adaptive estimation of memory cell read thresholds |
US8001320B2 (en) | 2007-04-22 | 2011-08-16 | Anobit Technologies Ltd. | Command interface for memory devices |
US20100131827A1 (en) * | 2007-05-12 | 2010-05-27 | Anobit Technologies Ltd | Memory device with internal signap processing unit |
US8234545B2 (en) | 2007-05-12 | 2012-07-31 | Apple Inc. | Data storage with incremental redundancy |
US8429493B2 (en) | 2007-05-12 | 2013-04-23 | Apple Inc. | Memory device with internal signap processing unit |
US7925936B1 (en) | 2007-07-13 | 2011-04-12 | Anobit Technologies Ltd. | Memory device with non-uniform programming levels |
US8259497B2 (en) | 2007-08-06 | 2012-09-04 | Apple Inc. | Programming schemes for multi-level analog memory cells |
US8174905B2 (en) | 2007-09-19 | 2012-05-08 | Anobit Technologies Ltd. | Programming orders for reducing distortion in arrays of multi-level analog memory cells |
US8068360B2 (en) | 2007-10-19 | 2011-11-29 | Anobit Technologies Ltd. | Reading analog memory cells using built-in multi-threshold commands |
US8000141B1 (en) | 2007-10-19 | 2011-08-16 | Anobit Technologies Ltd. | Compensation for voltage drifts in analog memory cells |
US8527819B2 (en) | 2007-10-19 | 2013-09-03 | Apple Inc. | Data storage in analog memory cell arrays having erase failures |
US8270246B2 (en) | 2007-11-13 | 2012-09-18 | Apple Inc. | Optimized selection of memory chips in multi-chips memory devices |
US8225181B2 (en) | 2007-11-30 | 2012-07-17 | Apple Inc. | Efficient re-read operations from memory devices |
US8209588B2 (en) | 2007-12-12 | 2012-06-26 | Anobit Technologies Ltd. | Efficient interference cancellation in analog memory cell arrays |
US8085586B2 (en) | 2007-12-27 | 2011-12-27 | Anobit Technologies Ltd. | Wear level estimation in analog memory cells |
US8156398B2 (en) | 2008-02-05 | 2012-04-10 | Anobit Technologies Ltd. | Parameter estimation based on error correction code parity check equations |
US7924587B2 (en) | 2008-02-21 | 2011-04-12 | Anobit Technologies Ltd. | Programming of analog memory cells using a single programming pulse per state transition |
US20090213654A1 (en) * | 2008-02-24 | 2009-08-27 | Anobit Technologies Ltd | Programming analog memory cells for reduced variance after retention |
US7864573B2 (en) | 2008-02-24 | 2011-01-04 | Anobit Technologies Ltd. | Programming analog memory cells for reduced variance after retention |
US8230300B2 (en) | 2008-03-07 | 2012-07-24 | Apple Inc. | Efficient readout from analog memory cells using data compression |
US8400858B2 (en) | 2008-03-18 | 2013-03-19 | Apple Inc. | Memory device with reduced sense time readout |
US8059457B2 (en) | 2008-03-18 | 2011-11-15 | Anobit Technologies Ltd. | Memory device with multiple-accuracy read commands |
US20090296467A1 (en) * | 2008-06-03 | 2009-12-03 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of driving the same |
US8325517B2 (en) * | 2008-06-03 | 2012-12-04 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of driving the same |
KR101495795B1 (en) | 2008-06-13 | 2015-02-27 | 삼성전자주식회사 | Nonvolatile memory device and programming method thereof |
US20090313423A1 (en) * | 2008-06-17 | 2009-12-17 | Samsung Electronics Co., Ltd. | Multi-bit flash memory device and method of analyzing flag cells of the same |
US8218371B2 (en) * | 2008-06-17 | 2012-07-10 | Samsung Electronics Co., Ltd. | Multi-bit flash memory device and method of analyzing flag cells of the same |
KR101456592B1 (en) * | 2008-06-17 | 2014-10-31 | 삼성전자주식회사 | Multi-bit flash memory device and analysis method of flag cells for the same |
TWI501241B (en) * | 2008-07-01 | 2015-09-21 | Seagate Technology Llc | Methods and apparatus for soft demapping and intercell interference mitigation in flash memories |
US7995388B1 (en) | 2008-08-05 | 2011-08-09 | Anobit Technologies Ltd. | Data storage using modified voltages |
US7924613B1 (en) * | 2008-08-05 | 2011-04-12 | Anobit Technologies Ltd. | Data storage in analog memory cells with protection against programming interruption |
US8498151B1 (en) | 2008-08-05 | 2013-07-30 | Apple Inc. | Data storage in analog memory cells using modified pass voltages |
US8949684B1 (en) | 2008-09-02 | 2015-02-03 | Apple Inc. | Segmented data storage |
US8169825B1 (en) | 2008-09-02 | 2012-05-01 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells subjected to long retention periods |
US8000135B1 (en) | 2008-09-14 | 2011-08-16 | Anobit Technologies Ltd. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8482978B1 (en) | 2008-09-14 | 2013-07-09 | Apple Inc. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8239734B1 (en) | 2008-10-15 | 2012-08-07 | Apple Inc. | Efficient data storage in storage device arrays |
US8713330B1 (en) | 2008-10-30 | 2014-04-29 | Apple Inc. | Data scrambling in memory devices |
US8261159B1 (en) | 2008-10-30 | 2012-09-04 | Apple, Inc. | Data scrambling schemes for memory devices |
US8208304B2 (en) | 2008-11-16 | 2012-06-26 | Anobit Technologies Ltd. | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
US8397131B1 (en) | 2008-12-31 | 2013-03-12 | Apple Inc. | Efficient readout schemes for analog memory cell devices |
US8174857B1 (en) | 2008-12-31 | 2012-05-08 | Anobit Technologies Ltd. | Efficient readout schemes for analog memory cell devices using multiple read threshold sets |
US8248831B2 (en) | 2008-12-31 | 2012-08-21 | Apple Inc. | Rejuvenation of analog memory cells |
US8924661B1 (en) | 2009-01-18 | 2014-12-30 | Apple Inc. | Memory system including a controller and processors associated with memory devices |
US8228701B2 (en) | 2009-03-01 | 2012-07-24 | Apple Inc. | Selective activation of programming schemes in analog memory cell arrays |
US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
US8832354B2 (en) | 2009-03-25 | 2014-09-09 | Apple Inc. | Use of host system resources by memory controller |
US8238157B1 (en) | 2009-04-12 | 2012-08-07 | Apple Inc. | Selective re-programming of analog memory cells |
CN101872642A (en) * | 2009-04-23 | 2010-10-27 | 无锡华润上华半导体有限公司 | Storing and reading method for random access memory |
US8479080B1 (en) | 2009-07-12 | 2013-07-02 | Apple Inc. | Adaptive over-provisioning in memory systems |
US9203248B2 (en) * | 2009-09-28 | 2015-12-01 | Hitachi, Ltd. | Battery management system using non-volatile memory |
US20120175953A1 (en) * | 2009-09-28 | 2012-07-12 | Hitachi, Ltd. | Battery System |
US8495465B1 (en) | 2009-10-15 | 2013-07-23 | Apple Inc. | Error correction coding over multiple memory pages |
US8677054B1 (en) | 2009-12-16 | 2014-03-18 | Apple Inc. | Memory management schemes for non-volatile memory devices |
US8694814B1 (en) | 2010-01-10 | 2014-04-08 | Apple Inc. | Reuse of host hibernation storage space by memory controller |
US8572311B1 (en) | 2010-01-11 | 2013-10-29 | Apple Inc. | Redundant data storage in multi-die memory systems |
US8677203B1 (en) | 2010-01-11 | 2014-03-18 | Apple Inc. | Redundant data storage schemes for multi-die memory systems |
US8694853B1 (en) | 2010-05-04 | 2014-04-08 | Apple Inc. | Read commands for reading interfering memory cells |
US8572423B1 (en) | 2010-06-22 | 2013-10-29 | Apple Inc. | Reducing peak current in memory systems |
US8595591B1 (en) | 2010-07-11 | 2013-11-26 | Apple Inc. | Interference-aware assignment of programming levels in analog memory cells |
US9104580B1 (en) | 2010-07-27 | 2015-08-11 | Apple Inc. | Cache memory for hybrid disk drives |
US8645794B1 (en) | 2010-07-31 | 2014-02-04 | Apple Inc. | Data storage in analog memory cells using a non-integer number of bits per cell |
US8767459B1 (en) | 2010-07-31 | 2014-07-01 | Apple Inc. | Data storage in analog memory cells across word lines using a non-integer number of bits per cell |
US8856475B1 (en) | 2010-08-01 | 2014-10-07 | Apple Inc. | Efficient selection of memory blocks for compaction |
US8694854B1 (en) | 2010-08-17 | 2014-04-08 | Apple Inc. | Read threshold setting based on soft readout statistics |
US9021181B1 (en) | 2010-09-27 | 2015-04-28 | Apple Inc. | Memory management for unifying memory cell conditions by using maximum time intervals |
US20120147669A1 (en) * | 2010-12-14 | 2012-06-14 | Dae-Seok Byeon | Non-volatile memory device and a method for operating the device |
US9696918B2 (en) | 2014-07-13 | 2017-07-04 | Apple Inc. | Protection and recovery from sudden power failure in non-volatile memory devices |
TWI566250B (en) * | 2014-10-13 | 2017-01-11 | 力旺電子股份有限公司 | Nonvolatile memory having memory array with differential cells |
US20190156904A1 (en) * | 2017-09-11 | 2019-05-23 | SK Hynix Inc. | Semiconductor memory device and method of operating the same |
US10839925B2 (en) * | 2017-09-11 | 2020-11-17 | SK Hynix Inc. | Semiconductor memory device and method of operating the same |
US10923186B2 (en) * | 2019-03-22 | 2021-02-16 | Toshiba Memory Corporation | Semiconductor memory device to hold 5-bits of data per memory cell |
US11361820B2 (en) | 2019-03-22 | 2022-06-14 | Kioxia Corporation | Semiconductor memory device to hold 5-bits of data per memory cell |
US11699486B2 (en) | 2019-03-22 | 2023-07-11 | Kioxia Corporation | Semiconductor memory device to hold 5-bits of data per memory cell |
US11556416B2 (en) | 2021-05-05 | 2023-01-17 | Apple Inc. | Controlling memory readout reliability and throughput by adjusting distance between read thresholds |
US11847342B2 (en) | 2021-07-28 | 2023-12-19 | Apple Inc. | Efficient transfer of hard data and confidence levels in reading a nonvolatile memory |
Also Published As
Publication number | Publication date |
---|---|
US7596022B2 (en) | 2009-09-29 |
KR100771883B1 (en) | 2007-11-01 |
CN101197190B (en) | 2012-05-09 |
CN101197190A (en) | 2008-06-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7596022B2 (en) | Method for programming a multi-level non-volatile memory device | |
US7508705B2 (en) | Method for programming a multi-level non-volatile memory device | |
US11915756B2 (en) | Nonvolatile semiconductor memory device | |
JP4856138B2 (en) | Nonvolatile semiconductor memory device | |
US7800946B2 (en) | Flash memory device and operating method thereof | |
US8717821B2 (en) | Nonvolatile memory device and method of programming the same | |
US9818477B2 (en) | Methods of programming memory cells in non-volatile memory devices | |
US7773427B2 (en) | Non-volatile memory device and method of operating | |
JP2007533055A (en) | Variable programming of non-volatile memory | |
JP2014225310A (en) | Nonvolatile semiconductor memory device | |
JP2008117471A (en) | Nonvolatile semiconductor storage device and nonvolatile memory system | |
JP2009541910A (en) | Detecting individual size margin in nonvolatile memory read operation improvement and detection by compensation in selected state | |
US8456907B2 (en) | Semiconductor memory device and method of operating the same | |
JP2011150749A (en) | Nonvolatile semiconductor memory device | |
US9349481B2 (en) | Semiconductor memory device and method of operating the same | |
JP2013069363A (en) | Nonvolatile semiconductor memory device | |
JP2008065978A (en) | Program method for multi-level non-volatile memory device | |
KR20100059422A (en) | Method of operating a flash memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SAMSUNG ELECTRONICS CO., LTD, KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHAE, DONG HYUK;BYEON, DAE SEOK;REEL/FRAME:019770/0099 Effective date: 20070824 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |