US20080096314A1 - Ball grid array package and method thereof - Google Patents

Ball grid array package and method thereof Download PDF

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Publication number
US20080096314A1
US20080096314A1 US11/984,159 US98415907A US2008096314A1 US 20080096314 A1 US20080096314 A1 US 20080096314A1 US 98415907 A US98415907 A US 98415907A US 2008096314 A1 US2008096314 A1 US 2008096314A1
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Prior art keywords
substrate
pads
chip
solder balls
disposed
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US11/984,159
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Sheng Liu
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to US11/984,159 priority Critical patent/US20080096314A1/en
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC. reassignment ADVANCED SEMICONDUCTOR ENGINEERING, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIU, SHENG TSUNG
Publication of US20080096314A1 publication Critical patent/US20080096314A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0588—Second resist used as pattern over first resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Definitions

  • This invention generally relates to a ball grid array package, and more particularly to a ball grid array package having a plurality of partitioning walls for keeping solder balls in proper position.
  • BGA ball grid array
  • FIG. 1 it shows a conventional ball grid array (BGA) package 10 using wire bonding technique and being disposed on a main board 30 .
  • the BGA package 10 includes a substrate 20 , a chip 11 , and a plurality of solder balls 40 .
  • the substrate 20 has an upper surface 22 , a lower surface 24 opposite to the upper surface 22 , and a plurality of metal wirings (not shown).
  • the chip 11 is disposed on the upper surface 22 of the substrate 20 and electrically connected to the metal wirings of the substrate 20 by a plurality of bonding wires 12 .
  • the solder balls 40 are disposed on the lower surface 24 of the substrate 20 and electrically connected to the chip 11 through the metal wrings and the bonding wires 12 .
  • a solder mask 26 is provided on the lower surface 24 of the substrate 20 and a plurality of pads 50 are exposed therefrom.
  • a plurality of flux units 60 are applied to the pads 50 .
  • the solder balls 40 are disposed on the flux units 60 and adhered to the pads 50 (as shown in FIG. 3 ) by a reflow process.
  • solder bridge formed between two pads 50 as shown in FIG. 3 might be occurred due to the spread of the flux units 60 .
  • the solder balls 40 may also be shifted due to the occurrence of a shake, a vibration and so on such that the implantation yield of the solder balls 40 is reduced.
  • U.S. Pat. No. 5,636,104 discloses a BGA package using wire bonding technique, which is incorporated herein by reference.
  • the substrate of such a BGA package comprises a plurality of groove mounting pads for carrying a plurality of solder balls, thereby improving the strength and the positioning capability of the solder balls on the substrate.
  • the plurality of groove mounting pads will increase the manufacturing processes and cost.
  • BGA ball grid array
  • the present invention provides a BGA package including a substrate, a chip, a plurality of pads, a solder mask, a plurality of partitioning walls, and a plurality of solder balls.
  • the substrate has an upper surface and a lower surface opposite to the upper surface.
  • the chip is disposed on the upper surface of the substrate.
  • the pads are disposed on the lower surface of the substrate and electrically connected to the chip.
  • the solder mask is disposed on the lower surface of the substrate.
  • the partitioning walls are disposed on the solder mask and each between the adjacent pads.
  • the solder balls are respectively disposed on the pads.
  • the plurality of partitioning walls can prevent the flux from spreading and therefore avoid the solder bridge being formed between two solder balls. Furthermore, the plurality of partitioning walls can also prevent the solder balls from being shifted and therefore increase the implantation yield of the solder balls.
  • FIG. 1 is a cross-sectional view of a conventional BGA package using wire bonding technique and being disposed on a main substrate.
  • FIG. 2 is an enlarged view of the area A shown in FIG. 1 .
  • FIG. 3 illustrates that the solder balls of FIG. 2 are adhered to the pads through a reflow process.
  • FIG. 4 is a bottom view of a BGA package according to one embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of the BGA package taken along line 5 - 5 of FIG. 4 .
  • FIGS. 4 and 5 show a ball grid array (BGA) package 100 according to one embodiment of the present invention.
  • the BGA package 100 includes a substrate 120 and a chip 111 .
  • the substrate 120 has an upper surface 122 , a lower surface 124 opposite to the upper surface, and a plurality of wirings (not shown).
  • the chip 111 is disposed on the upper surface 122 of the substrate 120 and electrically connected to the wirings of the substrate through bonding wires, that is, the chip 111 is electrically connected to the substrate by wire bonding technique.
  • a package body is formed over the chip 111 and a portion of the upper surface 122 of the substrate 120 . It should be understood by a skilled person in art that the chip 111 can be replaced by a flip chip.
  • a plurality of pads 150 are disposed on the lower surface 124 of the substrate 120 and electrically connected to the chip 111 through the wirings.
  • a plurality of solder balls 140 are respectively disposed on the plurality of pads 150 .
  • a solder mask 126 is applied over the lower surface 124 of the substrate 120 while the plurality of pads 150 are exposed therefrom.
  • the substrate 120 further has a plurality of partitioning walls 128 , which are disposed on and extend from the solder mask 126 , for partitioning the plurality of pads 150 and accurately positioning the solder balls 140 in place.
  • the plurality of partitioning walls 128 can be made in many different patterns.
  • the plurality of partitioning walls 128 can be made in a continuous pattern, e.g. a lattice pattern as shown in FIG. 4 .
  • the plurality of partitioning walls 128 can be made in a plurality of discontinuous or independent patterns, such as a plurality of ring-shaped, C-shaped or line-shaped patterns (not shown), for respectively partitioning the adjacent pads 150 .
  • a plurality of preflux or flux units 160 such as solder paste, can be respectively disposed on the plurality of pads 150 for facilitating the adherence of the solder balls 140 to the substrate 120 .
  • each partitioning wall 128 of the BGA package 100 is determined by the heights of the pad 150 , the flux unit 160 and the solder ball 140 .
  • the width of the partitioning wall 128 is determined by the dispositions of the pad 150 , the flux unit 160 and the solder ball 140 .
  • each partitioning wall 128 is substantially about 0.025 mm to 0.08 mm in height and encloses each pad 150 so as to form a lattice arrangement.
  • the material of the partitioning wall 128 is generally the same with that of the solder mask 126 , such as epoxy resin, such that the partitioning wall 128 is similar to the substrate 120 in chemical and physical characteristics thereby avoiding incompatibility between both of them.
  • a substrate 120 having an upper surface 122 and a lower surface 124 is first provided. Then, a chip 111 is disposed on the upper surface 122 of the substrate 120 and electrically connected to the substrate 120 by wire bonding technique. Then, a package body is molded for encapsulating the chip 111 and a portion of the upper surface 122 of the substrate 120 . It should be understood by a skilled person in art that the chip 111 can also be electrically connected to the substrate 120 by flip chip technique. A solder mask 126 is applied to the lower surface 124 of the substrate 120 and a plurality of pads 150 are defined.
  • a plurality of partitioning walls 128 are formed on the solder mask 126 by printed process or photolithography and etching processes and used for respectively partitioning the plurality of pads 150 .
  • a plurality of flux units 160 can be further applied to the plurality of pads 150 .
  • a plurality of solder balls 140 are respectively disposed on the flux units 160 and finally soldered to the pads 150 through a reflow process so as to form the BGA package 100 .
  • the BGA package 100 has the plurality of partitioning walls 128 for preventing the flux units 160 from spreading and therefore further preventing the solder bridge formed between the pads 150 .
  • the plurality of partitioning walls 128 can also prevent the plurality of solder balls 140 from being shifted and therefore increase the implantation yield of the solder balls 140 .

Abstract

A ball grid array package includes a substrate, a chip, a plurality of pads, a solder mask, a plurality of partitioning walls, and a plurality of solder balls. The substrate has an upper surface and a lower surface opposite to the upper surface. The chip is disposed on the upper surface of the substrate. The pads are disposed on the lower surface of the substrate and electrically connected to the chip. The solder mask is disposed on the lower surface of the substrate. The partitioning walls are disposed on the solder mask and between the adjacent pads. The solder balls are respectively disposed on the pads.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a Divisional application of U.S. application Ser. No. 10/974,936 filed Oct. 28, 2004. Priority is claimed based on U.S. application Ser. No. 10/974,936 filed Oct. 28, 2004, which claims the priority date of Taiwan Patent Application Serial Number 092129954, filed Oct. 28, 2003, the full disclosure of which is incorporated herein by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • This invention generally relates to a ball grid array package, and more particularly to a ball grid array package having a plurality of partitioning walls for keeping solder balls in proper position.
  • 2. Description of the Related Art
  • Miniaturization of semiconductor device size has been an important topic in the art, when the device requires more I/O pins along with the increase of device density. Relatively, the ball grid array (BGA) package is an efficient packaging technology since it can provide more I/O pins.
  • Referring to FIG. 1, it shows a conventional ball grid array (BGA) package 10 using wire bonding technique and being disposed on a main board 30. The BGA package 10 includes a substrate 20, a chip 11, and a plurality of solder balls 40. The substrate 20 has an upper surface 22, a lower surface 24 opposite to the upper surface 22, and a plurality of metal wirings (not shown). The chip 11 is disposed on the upper surface 22 of the substrate 20 and electrically connected to the metal wirings of the substrate 20 by a plurality of bonding wires 12. The solder balls 40 are disposed on the lower surface 24 of the substrate 20 and electrically connected to the chip 11 through the metal wrings and the bonding wires 12.
  • Referring to FIGS. 2 and 3, in manufacturing processes of the BGA package 10, a solder mask 26 is provided on the lower surface 24 of the substrate 20 and a plurality of pads 50 are exposed therefrom. A plurality of flux units 60 are applied to the pads 50. Then, the solder balls 40 are disposed on the flux units 60 and adhered to the pads 50 (as shown in FIG. 3) by a reflow process.
  • After the solder balls 40 pass through the reflow process, a solder bridge formed between two pads 50 as shown in FIG. 3 might be occurred due to the spread of the flux units 60. Further, in manufacturing and/or transporting processes, the solder balls 40 may also be shifted due to the occurrence of a shake, a vibration and so on such that the implantation yield of the solder balls 40 is reduced.
  • For example, U.S. Pat. No. 5,636,104 discloses a BGA package using wire bonding technique, which is incorporated herein by reference. The substrate of such a BGA package comprises a plurality of groove mounting pads for carrying a plurality of solder balls, thereby improving the strength and the positioning capability of the solder balls on the substrate. However, the plurality of groove mounting pads will increase the manufacturing processes and cost.
  • Accordingly, there exists a need to provide a BGA package which can improve the positioning capability and increase the implantation yield of the solder balls.
    • SUMMARY OF THE INVENTION
  • It is an object of the present invention to provide a ball grid array (BGA) package, which can avoid the shift problem of the solder balls and thus improve the positioning accuracy of the solder balls on the substrate.
  • In order to achieve the above object, the present invention provides a BGA package including a substrate, a chip, a plurality of pads, a solder mask, a plurality of partitioning walls, and a plurality of solder balls. The substrate has an upper surface and a lower surface opposite to the upper surface. The chip is disposed on the upper surface of the substrate. The pads are disposed on the lower surface of the substrate and electrically connected to the chip. The solder mask is disposed on the lower surface of the substrate. The partitioning walls are disposed on the solder mask and each between the adjacent pads. The solder balls are respectively disposed on the pads.
  • According to the BGA package of the present invention, the plurality of partitioning walls can prevent the flux from spreading and therefore avoid the solder bridge being formed between two solder balls. Furthermore, the plurality of partitioning walls can also prevent the solder balls from being shifted and therefore increase the implantation yield of the solder balls.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other objects, advantages, and novel features of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
  • FIG. 1 is a cross-sectional view of a conventional BGA package using wire bonding technique and being disposed on a main substrate.
  • FIG. 2 is an enlarged view of the area A shown in FIG. 1.
  • FIG. 3 illustrates that the solder balls of FIG. 2 are adhered to the pads through a reflow process.
  • FIG. 4 is a bottom view of a BGA package according to one embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of the BGA package taken along line 5-5 of FIG. 4.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • FIGS. 4 and 5 show a ball grid array (BGA) package 100 according to one embodiment of the present invention. The BGA package 100 includes a substrate 120 and a chip 111. The substrate 120 has an upper surface 122, a lower surface 124 opposite to the upper surface, and a plurality of wirings (not shown). The chip 111 is disposed on the upper surface 122 of the substrate 120 and electrically connected to the wirings of the substrate through bonding wires, that is, the chip 111 is electrically connected to the substrate by wire bonding technique. A package body is formed over the chip 111 and a portion of the upper surface 122 of the substrate 120. It should be understood by a skilled person in art that the chip 111 can be replaced by a flip chip.
  • A plurality of pads 150 are disposed on the lower surface 124 of the substrate 120 and electrically connected to the chip 111 through the wirings. A plurality of solder balls 140 are respectively disposed on the plurality of pads 150. A solder mask 126 is applied over the lower surface 124 of the substrate 120 while the plurality of pads 150 are exposed therefrom. The substrate 120 further has a plurality of partitioning walls 128, which are disposed on and extend from the solder mask 126, for partitioning the plurality of pads 150 and accurately positioning the solder balls 140 in place.
  • The plurality of partitioning walls 128 can be made in many different patterns. For example, the plurality of partitioning walls 128 can be made in a continuous pattern, e.g. a lattice pattern as shown in FIG. 4. Alternatively, the plurality of partitioning walls 128 can be made in a plurality of discontinuous or independent patterns, such as a plurality of ring-shaped, C-shaped or line-shaped patterns (not shown), for respectively partitioning the adjacent pads 150.
  • It should be understood by a skilled person in art that a plurality of preflux or flux units 160, such as solder paste, can be respectively disposed on the plurality of pads 150 for facilitating the adherence of the solder balls 140 to the substrate 120.
  • The height of the partitioning wall 128 of the BGA package 100 is determined by the heights of the pad 150, the flux unit 160 and the solder ball 140. The width of the partitioning wall 128 is determined by the dispositions of the pad 150, the flux unit 160 and the solder ball 140. In one specific embodiment of the present invention, each partitioning wall 128 is substantially about 0.025 mm to 0.08 mm in height and encloses each pad 150 so as to form a lattice arrangement.
  • The material of the partitioning wall 128 is generally the same with that of the solder mask 126, such as epoxy resin, such that the partitioning wall 128 is similar to the substrate 120 in chemical and physical characteristics thereby avoiding incompatibility between both of them.
  • In the manufacturing process of the BGA package 100, a substrate 120 having an upper surface 122 and a lower surface 124 is first provided. Then, a chip 111 is disposed on the upper surface 122 of the substrate 120 and electrically connected to the substrate 120 by wire bonding technique. Then, a package body is molded for encapsulating the chip 111 and a portion of the upper surface 122 of the substrate 120. It should be understood by a skilled person in art that the chip 111 can also be electrically connected to the substrate 120 by flip chip technique. A solder mask 126 is applied to the lower surface 124 of the substrate 120 and a plurality of pads 150 are defined. Then, a plurality of partitioning walls 128 are formed on the solder mask 126 by printed process or photolithography and etching processes and used for respectively partitioning the plurality of pads 150. A plurality of flux units 160 can be further applied to the plurality of pads 150. Next, a plurality of solder balls 140 are respectively disposed on the flux units 160 and finally soldered to the pads 150 through a reflow process so as to form the BGA package 100.
  • Accordingly, the BGA package 100 according to the present invention has the plurality of partitioning walls 128 for preventing the flux units 160 from spreading and therefore further preventing the solder bridge formed between the pads 150. In addition, the plurality of partitioning walls 128 can also prevent the plurality of solder balls 140 from being shifted and therefore increase the implantation yield of the solder balls 140.
  • Although the invention has been explained in relation to its preferred embodiment, it is not used to limit the invention. It is to be understood that many other possible modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention as hereinafter claimed.

Claims (10)

1. A method for manufacturing a BGA package comprising the following steps:
providing a substrate having an upper surface and a lower surface opposite to the upper surface;
providing a chip disposed on and electrically connected to the upper surface of the substrate;
applying a solder mask to the lower surface of the substrate and defining a plurality of pads; and
forming a plurality of partitioning walls on the solder mask wherein each partitioning wall is positioned between two adjacent pads.
2. The method as claimed in claim 1 further comprising a step of forming a plurality of flux units on the pads.
3. The method as claimed in claim 2 further comprising following steps:
providing a plurality of solder balls respectively positioned on the pads; and
reflowing the solder balls.
4. The method as claimed in claim 1, wherein the chip is electrically connected to the substrate by a wire bonding technique.
5. The method as claimed in claim 1, wherein the chip is electrically connected to the substrate by a flip chip technique.
6. The method as claimed in claim 4 further comprising a step of molding a package body for encapsulating the chip and a portion of the upper surface of the substrate.
7. The method as claimed in claim 1, wherein the material of the partitioning walls is the same with that of the solder mask.
8. The method as claimed in claim 1, wherein the partitioning walls are formed by a printed process.
9. The method as claimed in claim 1, wherein the partitioning walls are formed by photolithography and etching processes.
10. The method as claimed in claim 5, further comprising a step of molding a package body for encapsulating the chip and a portion of the upper surface of the substrate.
US11/984,159 2003-10-28 2007-11-14 Ball grid array package and method thereof Abandoned US20080096314A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/984,159 US20080096314A1 (en) 2003-10-28 2007-11-14 Ball grid array package and method thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
TW092129954A TWI233677B (en) 2003-10-28 2003-10-28 Ball grid array package and method thereof
TW092129954 2003-10-28
US10/974,936 US7315085B2 (en) 2003-10-28 2004-10-28 Ball grid array package and method thereof
US11/984,159 US20080096314A1 (en) 2003-10-28 2007-11-14 Ball grid array package and method thereof

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US10/974,936 Division US7315085B2 (en) 2003-10-28 2004-10-28 Ball grid array package and method thereof

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US20080096314A1 true US20080096314A1 (en) 2008-04-24

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