US20080116577A1 - Semiconductor device and production method therefor - Google Patents
Semiconductor device and production method therefor Download PDFInfo
- Publication number
- US20080116577A1 US20080116577A1 US12/005,383 US538307A US2008116577A1 US 20080116577 A1 US20080116577 A1 US 20080116577A1 US 538307 A US538307 A US 538307A US 2008116577 A1 US2008116577 A1 US 2008116577A1
- Authority
- US
- United States
- Prior art keywords
- layer
- film
- interconnection layer
- interlevel
- interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
- H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device having a plurality of interconnection layers and to a production method for the semiconductor device.
- Semiconductor devices generally include a semiconductor substrate, a functional device provided in a surface of the semiconductor substrate, and a multi-level interconnection structure provided on the semiconductor substrate.
- the multi-level interconnection structure typically includes a plurality of interconnection layers stacked with the intervention of interlevel insulation films, and connection between the interconnection layers is achieved through contact holes formed in the interlevel insulating films.
- Aluminum is conventionally employed as an interconnection material, but has a limitation in reduction of the resistance of the interconnection. As the sectional area of the interconnection is reduced with microminiaturization of the semiconductor device, a problem associated with the resistance of the interconnection arises. As a result, particularly, there is a demand for reduction of the resistances of a ground line and a power line.
- a barrier layer of a titanium thin film is disposed between an aluminum interconnection layer and the uppermost gold interconnection layer electrically connected to each other through a contact hole, so that migration of aluminum is prevented by the barrier layer.
- gold is a highly diffusible material.
- the semiconductor device is allowed to stand at a high temperature for a long period of time (e.g., at 400° C. for 30 minutes to 1 hour) in an alloying process, for example, gold easily diffuses into the aluminum interconnection layer.
- the titanium thin film has virtually no function as the barrier layer, but merely functions as an adhesive layer to contribute to the bonding between the interlevel insulation film and the gold layer and the bonding between the aluminum interconnection layer and the gold layer.
- TiW thin film is conceivably usable as the barrier layer.
- the TiW film has virtually no function for prevention of mutual diffusion between the gold layer and the aluminum interconnection layer, but merely functions as an adhesive layer.
- the barrier layer Although electrically conductive materials having a barrier effect should be employed for the formation of the barrier layer, such materials have difficulty in forming a barrier layer having a uniform thickness. More specifically, the barrier layer is liable to have a reduced thickness on the bottom (especially, at a corner of the bottom) of the contact hole formed in the interlevel insulation film, resulting in poor coverage. Therefore, the barrier layer fails to provide a sufficient barrier effect in a heat treatment at a high temperature.
- a semiconductor device comprises: a first interconnection layer provided on a semiconductor substrate; an interlevel insulation film provided over the first interconnection layer; a barrier layer provided between the first interconnection layer and the interlevel insulation film on a region of the first interconnection layer including an interlevel connection opening region where an interlevel connection opening is formed in the interlevel insulation film, the region of the first interconnection layer having a greater area than the interlevel connection opening region; and a second interconnection layer of gold provided as an uppermost interconnection layer on the interlevel insulation film and electrically connected to the first interconnection layer via the barrier layer in the interlevel connection opening.
- the barrier layer is provided on the region of the first interconnection layer having a greater area than the interlevel connection opening.
- the barrier layer is not provided on the interlevel insulation film, but provided between the first interconnection layer and the interlevel insulation film. Therefore, the barrier layer is free from the poor coverage in the interlevel connection opening formed in the interlevel insulation film, and advantageously has a uniform thickness everywhere on the first interconnection layer.
- the diffusion of the materials between the first interconnection layer and the second interconnection gold layer can effectively be suppressed or prevented by the barrier layer having a uniform thickness.
- the semiconductor device preferably further comprises an adhesive layer of an electrically conductive material provided between the interlevel insulation film and the second interconnection layer and between the barrier layer and the second interconnection layer in the interlevel connection opening to bond the second interconnection layer to the interlevel insulation film and the barrier layer.
- the second interconnection layer is electrically connected to the barrier layer and, at the same time, properly bonded to the interlevel insulation film and the barrier layer by the adhesive layer of the electrically conductive material.
- the barrier layer preferably comprises a nitride film.
- the barrier layer may have a single layer structure consisting of the nitride film, or a laminate structure comprising the nitride film and any other electrically conductive material film.
- the nitride film include a TiN film and a TaN film.
- An electrically conductive material such as silicon may also be employed as a material for the barrier layer.
- the first interconnection layer is an aluminum interconnection layer (composed of metal aluminum or an aluminum alloy such as an Al—Si alloy or an Al—Cu alloy).
- the nitride film constituting the barrier layer is preferably a film having an anti-reflection property. With this arrangement, the nitride film constituting the barrier layer functions as an anti-reflection film in a photolithography process for patterning the first interconnection layer.
- the anti-reflection film formation apparatus may be employed for the formation of the nitride film constituting the barrier layer. Therefore, the existing production system can be employed for the production of the semiconductor device of the present invention.
- the barrier layer is preferably configured to be conformal to the first interconnection layer with at least a part thereof adjacent to the interlevel connection opening region being planar (or flat).
- the nitride film included in the barrier layer may have such a configuration.
- the barrier layer preferably has a thickness in a range from 200 ⁇ to 1000 ⁇ (more preferably from 500 ⁇ to 1000 ⁇ ).
- the nitride film having a thickness within this range can assuredly prevent the diffusion of gold from the second interconnection layer in the heat treatment process, and is free from penetration when being etched for the formation of the interlevel connection opening.
- the nitride film serving as the anti-reflection film generally has a thickness of not greater than 300 ⁇ , the nitride film preferably has a thickness within the aforesaid range for prevention of the diffusion of gold.
- a semiconductor device production method comprises the steps of: forming a first interconnection layer on a semiconductor substrate; forming an interlevel insulation film which covers the first interconnection layer; forming an interlevel connection opening at a predetermined position in the interlevel insulation film to expose a part of the first interconnection layer; forming a barrier layer on a region of the first interconnection layer after the formation of the first interconnection layer but before the formation of the interlevel insulation film, the region of the first interconnection layer including an interlevel connection opening region where the interlevel connection opening is formed in the interlevel insulation film, and having a greater area than the interlevel connection opening region; and forming a second interconnection layer of gold as an uppermost interconnection layer on the interlevel insulation film so as to electrically connect the second interconnection layer to the first interconnection layer via the barrier layer in the interlevel connection opening.
- the barrier layer is formed on the great area region of the first interconnection layer, and the interlevel insulation film is formed over the barrier layer.
- the barrier layer is exposed from the interlevel connection opening formed in the interlevel insulation film. Therefore, the barrier layer is free from the problem associated with the coverage around the interlevel connection opening, so that the barrier layer can be formed as having a uniform thickness to provide an excellent barrier effect with respect to the second interconnection gold layer.
- the aforesaid method preferably further comprises the step of forming an adhesive layer of an electrically conductive material on the interlevel insulation film and in the interlevel connection opening in contact with the interlevel insulation film and the barrier layer exposed in the opening to bond the second interconnection layer to the interlevel insulation film and the barrier layer after the formation of the interlevel insulation film but before the formation of the second interconnection layer.
- the first interconnection layer forming step and the barrier layer forming step preferably comprises the steps of: forming a metal material film for the first interconnection layer on the semiconductor substrate; forming the barrier layer on the metal material film; forming a resist pattern film having a pattern corresponding to the first interconnection layer on the barrier layer; and etching the metal material film and the barrier layer by employing the resist pattern film as a common mask to form the first interconnection layer and pattern the barrier layer so as to cover the first interconnection layer with the barrier layer.
- the first interconnection layer and the barrier layer are patterned by the etching employing the resist pattern film as the common mask, whereby the barrier layer is formed as covering the entire first interconnection layer.
- the barrier layer thus formed has a uniform thickness, and has an excellent barrier effect with respect to the second interconnection layer.
- the resist pattern film forming step preferably comprises the steps of forming a resist film to cover the entire barrier layer, and exposing the resist film to light so as to allow the resist film to have a pattern corresponding to the first interconnection layer.
- the barrier layer forming step preferably comprises the step of forming the barrier layer from a nitride material having an anti-reflection function for blocking light reflected from the first interconnection layer in the exposure step.
- the nitride film formed as covering the first interconnection layer serves as an anti-reflection film, so that a resist pattern film can properly be formed.
- FIG. 1 is a sectional view illustrating the construction of a semiconductor device according to one embodiment of the present invention
- FIGS. 2 ( a ) to 2 ( g ) are sectional views illustrating a process sequence for production of the semiconductor device.
- FIG. 3 is a sectional view illustrating the construction of a semiconductor device according to another embodiment of the present invention.
- FIG. 1 is a sectional view illustrating the construction of a semiconductor device according to one embodiment of the present invention.
- the semiconductor device has a polysilicon interconnection 15 provided on a silicon substrate 11 formed with a field oxide film 12 .
- An interlevel insulation film 13 entirely covers the field oxide film 12 and the polysilicon interconnection 15 .
- An aluminum interconnection layer 14 is provided as a first interconnection layer on the interlevel insulation film 13 .
- a TiN (titanium nitride) film 30 (barrier layer) is provided as an electrically conductive nitride film to cover a surface of the aluminum interconnection layer 14 .
- the TiN film 30 has the same pattern as the aluminum interconnection layer 14 , and covers the entire surface of the aluminum interconnection layer 14 .
- the TiN film 30 and the interlevel insulation film 13 are entirely covered with an interlevel insulation film 16 of a laminate structure which includes a USG (undoped silicate glass) layer 16 U and a silicon nitride film 16 S covering the entire surface of the USG layer 16 U. That is, the TiN film 30 is disposed below the interlevel insulation film 16 , and intervenes between the aluminum interconnection layer 14 and the interlevel insulation film 16 .
- an interlevel insulation film 16 of a laminate structure which includes a USG (undoped silicate glass) layer 16 U and a silicon nitride film 16 S covering the entire surface of the USG layer 16 U. That is, the TiN film 30 is disposed below the interlevel insulation film 16 , and intervenes between the aluminum interconnection layer 14 and the interlevel insulation film 16 .
- a gold interconnection layer (interconnection layer of gold) 19 is provided as a second interconnection layer (uppermost interconnection layer) on the interlevel insulation film 16 .
- the gold interconnection layer 19 and the interlevel insulation film 16 are entirely covered with a polyimide resin film 18 , which has a planar surface.
- the interlevel insulation film 16 has a contact hole H formed therein at a predetermined position to expose a part of the TiN film 30 underlying the interlevel insulation film 16 .
- the aluminum interconnection layer 14 and the gold interconnection layer 19 are electrically connected to each other via the TiN film 30 through the contact hole H.
- the TiN film 30 functions as the barrier layer for preventing the diffusion of gold which is a material metal for the gold interconnection layer 19 .
- the TiN film 30 is flatly (or planarly) provided on a region of the aluminum interconnection layer 14 which includes a region of the contact hole H and has a greater area than the contact hole region. Therefore, the TiN film 30 is free from the problem associated with the coverage in the contact hole H and, hence, advantageously has a uniform thickness.
- FIG. 1 shows that the surface of the interlevel insulation film 16 is generally or substantially parallel to the flat TiN film 30 , and that the interlevel insulation film 16 therefore has a substantially flat surface in the region of the TiN film 30 .
- the interlevel insulation film 16 surface does not comprise two portions of different heights or different shapes.
- the phrase “substantially flat” does not relate to surface roughness but to overall or geometrical shape.
- a TiW film 20 functioning as an electrically conductive adhesive layer for bonding the gold interconnection layer 19 to the TiN film 30 and the interlevel insulation film 16 is provided between the gold interconnection layer 19 and the TiN film 30 and between the gold interconnection layer 19 and the interlevel insulation film 16 .
- the TiN film 30 can effectively prevent gold of the gold interconnection layer 19 from diffusing into the aluminum interconnection layer 14 even if the semiconductor device is allowed to stand in a high temperature environment in an alloying process after the production of the semiconductor device. Further, the TiN film 30 , which is one type of the nitride film, is excellent in corrosion resistance, and exhibits a high corrosion resistance even in a pressure cocker test environment.
- the thickness of the TiN film 30 is preferably 200 ⁇ to 1000 ⁇ , more preferably 500 ⁇ to 1000 ⁇ .
- FIGS. 2 ( a ) to 2 ( g ) are sectional views illustrating a process sequence for production of the aforesaid semiconductor device.
- a device isolation film 12 is first formed in a surface of a silicon substrate 11 to define a device region, and an interconnection 15 of a polysilicon film is formed in the device region on the silicon substrate 11 .
- an interlevel insulation film 13 of a BPSG film is formed over the resulting substrate, and an aluminum interconnection material film 140 which is connected to the polysilicon interconnection 15 through a contact hole not shown is formed over the entire resulting substrate.
- a TiN film 30 having a thickness of 500 ⁇ to 1000 ⁇ is formed over the aluminum interconnection material film 140 to entirely cover the aluminum interconnection material film 140 .
- the formation of the aluminum interconnection material film 140 and the TiN film 30 is achieved by a sputtering method. For example, the aluminum interconnection material film 140 is first formed by sputtering, and then the TiN film 30 is formed on the aluminum interconnection material film 140 by sputtering with the substrate 11 kept in vacuum.
- a resist 40 is applied onto the TiN film 30 , and exposed to light with the use of a mask 41 having a pattern corresponding to a pattern of the aluminum interconnection layer 14 .
- the TiN film 30 functions as an anti-reflection film to block light reflected from the aluminum interconnection material film 140 for prevention of unwanted exposure of the resist 40 to the reflected light.
- the exposure of the resist 40 can advantageously be achieved. Therefore, the resist 40 can be patterned into a desired pattern in a subsequent developing process.
- the TiN film 30 and the aluminum interconnection layer 14 are patterned by etching with the use of the patterned resist 40 as a common mask. As a result, the TiN film 30 having the same pattern as the aluminum interconnection layer 14 is provided as covering the entire surface of the aluminum interconnection layer 14 .
- a USG (undoped silicate glass) is deposited on the resulting substrate by a CVD (chemical vapor deposition) method or the like to form a USG layer 16 U, and further a silicon nitride film 16 S is formed over the USG layer 16 U by a plasma CVD method.
- a contact hole H is formed at a predetermined position in the interlevel insulation film 16 by dry etching.
- the contact holes preferably have a uniform diameter on the order of not greater than 3 ⁇ m.
- TiW film 20 is formed over the entire resulting substrate, for example, by a sputtering method as illustrated on a greater scale in FIG. 2 ( f ).
- a gold seed layer 19 S is formed over the entire resulting substrate.
- the formation of the seed layer 19 S may be achieved through a sequential sputtering method by switching a target from TiW to gold in a treatment chamber employed for the formation of the TiW film 20 .
- a resist 24 is formed as covering the entire seed layer 19 S.
- An opening 24 a corresponding to a gold interconnection layer 19 is formed in the resist 24 .
- a gold electrolytic plating process is performed, whereby the gold interconnection layer 19 grows in the opening 24 a.
- the resist 24 is removed, and a part of the seed layer 19 S and a part of the TiW film 20 not covered with the gold interconnection layer 19 are etched away. Then, for example, a 2 ⁇ m thick polyimide resin film 18 is formed as a passivation film by coating.
- a semiconductor device having a construction as shown in FIG. 1 is provided.
- openings may be formed at predetermined positions in the polyimide resin film 18 above the gold interconnection layer 19 for connection between the gold interconnection layer 19 and external connection terminals (not shown) by bonding wires.
- FIG. 3 is a sectional view illustrating the construction of a semiconductor device according to another embodiment of the present invention.
- components corresponding to those shown in FIG. 1 will be denoted by the same reference characters as in FIG. 1 .
- a silicon nitride film 25 is provided instead of the polyimide resin film 18 as the passivation film. That is, after the resist 24 is removed and unnecessary portions of the seed layer 19 S and the TIW film 20 are etched away in the state shown in FIG. 2 ( g ), the silicon nitride film 25 is formed over the entire resulting substrate, for example, by a plasma CVD method. Thus, a semiconductor device as shown in FIG. 3 is provided.
- the corrosion resistance of the semiconductor device can further be improved, because the silicon nitride film 25 herein employed is highly dense and has a high passivation effect.
- the silicon nitride film 25 is formed by the plasma CVD method, the semiconductor device is allowed to stand in a high temperature environment. Even in this case, the TiN film 30 prevents the diffusion of gold into the aluminum interconnection layer 14 from the gold interconnection layer 19 .
- the invention may be embodied in other ways.
- the polyimide resin film 18 is employed as the passivation film in the embodiment shown in FIG. 1
- the silicon nitride film 25 is employed as the passivation film in the embodiment shown in FIG. 3
- neither the polyimide resin film 18 nor the silicon nitride film 25 may be provided, that is, no passivation film may be provided.
- the gold interconnection layer 19 exposed to a surface of the semiconductor device has a sufficient corrosion resistance
- the surface of the interlevel insulation film 16 is constituted by the silicon nitride film 16 S having a high passivation effect.
- the TiN film 30 is excellent in corrosion resistance. Therefore, the semiconductor device totally has a sufficient corrosion resistance.
- a PSG film (a silicon oxide film doped with phosphorus) or a USG film may be employed as the interlevel insulation film 13 .
- an organic insulative silicon compound which permits easy formation of a thicker film may be applied on the deposited USG film 16 U as filling a recess in an upper surface of the USG layer 16 U by an SOG (spin on glass) method to form an organic SOG layer 26 (see FIGS. 1 and 3 ), and then the silicon nitride film 16 S may be formed by a high density plasma CVD method.
Abstract
Description
- This is a Divisional of U.S. application Ser. No. 10/919,385, filed Aug. 17, 2004, and allowed on Oct. 1, 2007, the subject matter of which is incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a semiconductor device having a plurality of interconnection layers and to a production method for the semiconductor device.
- 2. Description of Related Art
- Semiconductor devices generally include a semiconductor substrate, a functional device provided in a surface of the semiconductor substrate, and a multi-level interconnection structure provided on the semiconductor substrate. The multi-level interconnection structure typically includes a plurality of interconnection layers stacked with the intervention of interlevel insulation films, and connection between the interconnection layers is achieved through contact holes formed in the interlevel insulating films.
- Aluminum is conventionally employed as an interconnection material, but has a limitation in reduction of the resistance of the interconnection. As the sectional area of the interconnection is reduced with microminiaturization of the semiconductor device, a problem associated with the resistance of the interconnection arises. As a result, particularly, there is a demand for reduction of the resistances of a ground line and a power line.
- In this connection, the inventor of the present invention, for example, has proposed in US2002-132392A1 that a gold layer is employed as an uppermost interconnection layer for the reduction of the resistance of the interconnection.
- In this prior art, a barrier layer of a titanium thin film is disposed between an aluminum interconnection layer and the uppermost gold interconnection layer electrically connected to each other through a contact hole, so that migration of aluminum is prevented by the barrier layer.
- However, gold is a highly diffusible material. Where the semiconductor device is allowed to stand at a high temperature for a long period of time (e.g., at 400° C. for 30 minutes to 1 hour) in an alloying process, for example, gold easily diffuses into the aluminum interconnection layer.
- In practice, the titanium thin film has virtually no function as the barrier layer, but merely functions as an adhesive layer to contribute to the bonding between the interlevel insulation film and the gold layer and the bonding between the aluminum interconnection layer and the gold layer.
- Besides the titanium thin film, a TiW thin film is conceivably usable as the barrier layer. However, like the titanium thin film, the TiW film has virtually no function for prevention of mutual diffusion between the gold layer and the aluminum interconnection layer, but merely functions as an adhesive layer.
- Although electrically conductive materials having a barrier effect should be employed for the formation of the barrier layer, such materials have difficulty in forming a barrier layer having a uniform thickness. More specifically, the barrier layer is liable to have a reduced thickness on the bottom (especially, at a corner of the bottom) of the contact hole formed in the interlevel insulation film, resulting in poor coverage. Therefore, the barrier layer fails to provide a sufficient barrier effect in a heat treatment at a high temperature.
- It is an object of the present invention to provide a semiconductor device and a production method therefor, which employ a gold interconnection layer and yet effectively suppress or prevent diffusion of gold.
- A semiconductor device according to the present invention comprises: a first interconnection layer provided on a semiconductor substrate; an interlevel insulation film provided over the first interconnection layer; a barrier layer provided between the first interconnection layer and the interlevel insulation film on a region of the first interconnection layer including an interlevel connection opening region where an interlevel connection opening is formed in the interlevel insulation film, the region of the first interconnection layer having a greater area than the interlevel connection opening region; and a second interconnection layer of gold provided as an uppermost interconnection layer on the interlevel insulation film and electrically connected to the first interconnection layer via the barrier layer in the interlevel connection opening.
- With the aforesaid arrangement, the barrier layer is provided on the region of the first interconnection layer having a greater area than the interlevel connection opening. The barrier layer is not provided on the interlevel insulation film, but provided between the first interconnection layer and the interlevel insulation film. Therefore, the barrier layer is free from the poor coverage in the interlevel connection opening formed in the interlevel insulation film, and advantageously has a uniform thickness everywhere on the first interconnection layer.
- Thus, the diffusion of the materials between the first interconnection layer and the second interconnection gold layer can effectively be suppressed or prevented by the barrier layer having a uniform thickness.
- The semiconductor device preferably further comprises an adhesive layer of an electrically conductive material provided between the interlevel insulation film and the second interconnection layer and between the barrier layer and the second interconnection layer in the interlevel connection opening to bond the second interconnection layer to the interlevel insulation film and the barrier layer. With this arrangement, the second interconnection layer is electrically connected to the barrier layer and, at the same time, properly bonded to the interlevel insulation film and the barrier layer by the adhesive layer of the electrically conductive material.
- The barrier layer preferably comprises a nitride film. In this case, the barrier layer may have a single layer structure consisting of the nitride film, or a laminate structure comprising the nitride film and any other electrically conductive material film. Examples of the nitride film include a TiN film and a TaN film. An electrically conductive material such as silicon may also be employed as a material for the barrier layer.
- An example of the first interconnection layer is an aluminum interconnection layer (composed of metal aluminum or an aluminum alloy such as an Al—Si alloy or an Al—Cu alloy).
- The nitride film constituting the barrier layer is preferably a film having an anti-reflection property. With this arrangement, the nitride film constituting the barrier layer functions as an anti-reflection film in a photolithography process for patterning the first interconnection layer.
- Since an apparatus for the formation of the anti-reflection film is generally incorporated in a semiconductor device production system, the anti-reflection film formation apparatus may be employed for the formation of the nitride film constituting the barrier layer. Therefore, the existing production system can be employed for the production of the semiconductor device of the present invention.
- The barrier layer is preferably configured to be conformal to the first interconnection layer with at least a part thereof adjacent to the interlevel connection opening region being planar (or flat). The nitride film included in the barrier layer may have such a configuration.
- The barrier layer preferably has a thickness in a range from 200 Å to 1000 Å (more preferably from 500 Å to 1000 Å). The nitride film having a thickness within this range can assuredly prevent the diffusion of gold from the second interconnection layer in the heat treatment process, and is free from penetration when being etched for the formation of the interlevel connection opening.
- Although the nitride film serving as the anti-reflection film generally has a thickness of not greater than 300 Å, the nitride film preferably has a thickness within the aforesaid range for prevention of the diffusion of gold.
- A semiconductor device production method according to the present invention comprises the steps of: forming a first interconnection layer on a semiconductor substrate; forming an interlevel insulation film which covers the first interconnection layer; forming an interlevel connection opening at a predetermined position in the interlevel insulation film to expose a part of the first interconnection layer; forming a barrier layer on a region of the first interconnection layer after the formation of the first interconnection layer but before the formation of the interlevel insulation film, the region of the first interconnection layer including an interlevel connection opening region where the interlevel connection opening is formed in the interlevel insulation film, and having a greater area than the interlevel connection opening region; and forming a second interconnection layer of gold as an uppermost interconnection layer on the interlevel insulation film so as to electrically connect the second interconnection layer to the first interconnection layer via the barrier layer in the interlevel connection opening.
- In this method, the barrier layer is formed on the great area region of the first interconnection layer, and the interlevel insulation film is formed over the barrier layer. The barrier layer is exposed from the interlevel connection opening formed in the interlevel insulation film. Therefore, the barrier layer is free from the problem associated with the coverage around the interlevel connection opening, so that the barrier layer can be formed as having a uniform thickness to provide an excellent barrier effect with respect to the second interconnection gold layer.
- The aforesaid method preferably further comprises the step of forming an adhesive layer of an electrically conductive material on the interlevel insulation film and in the interlevel connection opening in contact with the interlevel insulation film and the barrier layer exposed in the opening to bond the second interconnection layer to the interlevel insulation film and the barrier layer after the formation of the interlevel insulation film but before the formation of the second interconnection layer.
- The first interconnection layer forming step and the barrier layer forming step preferably comprises the steps of: forming a metal material film for the first interconnection layer on the semiconductor substrate; forming the barrier layer on the metal material film; forming a resist pattern film having a pattern corresponding to the first interconnection layer on the barrier layer; and etching the metal material film and the barrier layer by employing the resist pattern film as a common mask to form the first interconnection layer and pattern the barrier layer so as to cover the first interconnection layer with the barrier layer.
- In this method, the first interconnection layer and the barrier layer are patterned by the etching employing the resist pattern film as the common mask, whereby the barrier layer is formed as covering the entire first interconnection layer. The barrier layer thus formed has a uniform thickness, and has an excellent barrier effect with respect to the second interconnection layer.
- The resist pattern film forming step preferably comprises the steps of forming a resist film to cover the entire barrier layer, and exposing the resist film to light so as to allow the resist film to have a pattern corresponding to the first interconnection layer. The barrier layer forming step preferably comprises the step of forming the barrier layer from a nitride material having an anti-reflection function for blocking light reflected from the first interconnection layer in the exposure step.
- In this method, the nitride film formed as covering the first interconnection layer serves as an anti-reflection film, so that a resist pattern film can properly be formed.
- The foregoing and other objects, features and effects of the present invention will become more apparent from the following description of the preferred embodiments with reference to the attached drawings.
-
FIG. 1 is a sectional view illustrating the construction of a semiconductor device according to one embodiment of the present invention; - FIGS. 2(a) to 2(g) are sectional views illustrating a process sequence for production of the semiconductor device; and
-
FIG. 3 is a sectional view illustrating the construction of a semiconductor device according to another embodiment of the present invention. -
FIG. 1 is a sectional view illustrating the construction of a semiconductor device according to one embodiment of the present invention. The semiconductor device has apolysilicon interconnection 15 provided on asilicon substrate 11 formed with afield oxide film 12. - An
interlevel insulation film 13 entirely covers thefield oxide film 12 and thepolysilicon interconnection 15. Analuminum interconnection layer 14 is provided as a first interconnection layer on theinterlevel insulation film 13. A TiN (titanium nitride) film 30 (barrier layer) is provided as an electrically conductive nitride film to cover a surface of thealuminum interconnection layer 14. In this embodiment, theTiN film 30 has the same pattern as thealuminum interconnection layer 14, and covers the entire surface of thealuminum interconnection layer 14. - The
TiN film 30 and theinterlevel insulation film 13 are entirely covered with aninterlevel insulation film 16 of a laminate structure which includes a USG (undoped silicate glass)layer 16U and asilicon nitride film 16S covering the entire surface of theUSG layer 16U. That is, theTiN film 30 is disposed below theinterlevel insulation film 16, and intervenes between thealuminum interconnection layer 14 and theinterlevel insulation film 16. - A gold interconnection layer (interconnection layer of gold) 19 is provided as a second interconnection layer (uppermost interconnection layer) on the
interlevel insulation film 16. Thegold interconnection layer 19 and theinterlevel insulation film 16 are entirely covered with apolyimide resin film 18, which has a planar surface. - The
interlevel insulation film 16 has a contact hole H formed therein at a predetermined position to expose a part of theTiN film 30 underlying theinterlevel insulation film 16. Thealuminum interconnection layer 14 and thegold interconnection layer 19 are electrically connected to each other via theTiN film 30 through the contact hole H. In this case, theTiN film 30 functions as the barrier layer for preventing the diffusion of gold which is a material metal for thegold interconnection layer 19. TheTiN film 30 is flatly (or planarly) provided on a region of thealuminum interconnection layer 14 which includes a region of the contact hole H and has a greater area than the contact hole region. Therefore, theTiN film 30 is free from the problem associated with the coverage in the contact hole H and, hence, advantageously has a uniform thickness.FIG. 1 shows that the surface of theinterlevel insulation film 16 is generally or substantially parallel to theflat TiN film 30, and that theinterlevel insulation film 16 therefore has a substantially flat surface in the region of theTiN film 30. For example, theinterlevel insulation film 16 surface does not comprise two portions of different heights or different shapes. Here, the phrase “substantially flat” does not relate to surface roughness but to overall or geometrical shape. - A
TiW film 20 functioning as an electrically conductive adhesive layer for bonding thegold interconnection layer 19 to theTiN film 30 and theinterlevel insulation film 16 is provided between thegold interconnection layer 19 and theTiN film 30 and between thegold interconnection layer 19 and theinterlevel insulation film 16. - With this arrangement, the
TiN film 30 can effectively prevent gold of thegold interconnection layer 19 from diffusing into thealuminum interconnection layer 14 even if the semiconductor device is allowed to stand in a high temperature environment in an alloying process after the production of the semiconductor device. Further, theTiN film 30, which is one type of the nitride film, is excellent in corrosion resistance, and exhibits a high corrosion resistance even in a pressure cocker test environment. - To ensure the higher barrier effect of the
TiN film 30 and prevent the contact hole H from penetrating through theTiN film 30 in the etching for the formation of the contact hole H, the thickness of theTiN film 30 is preferably 200 Å to 1000 Å, more preferably 500 Å to 1000 Å. - FIGS. 2(a) to 2(g) are sectional views illustrating a process sequence for production of the aforesaid semiconductor device. As shown in
FIG. 2 (a), adevice isolation film 12 is first formed in a surface of asilicon substrate 11 to define a device region, and aninterconnection 15 of a polysilicon film is formed in the device region on thesilicon substrate 11. - Then, as shown in
FIG. 2 (b), aninterlevel insulation film 13 of a BPSG film is formed over the resulting substrate, and an aluminuminterconnection material film 140 which is connected to thepolysilicon interconnection 15 through a contact hole not shown is formed over the entire resulting substrate. Further, aTiN film 30 having a thickness of 500 Å to 1000 Å is formed over the aluminuminterconnection material film 140 to entirely cover the aluminuminterconnection material film 140. The formation of the aluminuminterconnection material film 140 and theTiN film 30 is achieved by a sputtering method. For example, the aluminuminterconnection material film 140 is first formed by sputtering, and then theTiN film 30 is formed on the aluminuminterconnection material film 140 by sputtering with thesubstrate 11 kept in vacuum. - Further, as shown in
FIG. 2 (c), a resist 40 is applied onto theTiN film 30, and exposed to light with the use of amask 41 having a pattern corresponding to a pattern of thealuminum interconnection layer 14. At this time, theTiN film 30 functions as an anti-reflection film to block light reflected from the aluminuminterconnection material film 140 for prevention of unwanted exposure of the resist 40 to the reflected light. Thus, the exposure of the resist 40 can advantageously be achieved. Therefore, the resist 40 can be patterned into a desired pattern in a subsequent developing process. - Then, as shown in
FIG. 2 (d), theTiN film 30 and thealuminum interconnection layer 14 are patterned by etching with the use of the patterned resist 40 as a common mask. As a result, theTiN film 30 having the same pattern as thealuminum interconnection layer 14 is provided as covering the entire surface of thealuminum interconnection layer 14. - Thereafter, as shown in
FIG. 2 (e), a USG (undoped silicate glass) is deposited on the resulting substrate by a CVD (chemical vapor deposition) method or the like to form aUSG layer 16U, and further asilicon nitride film 16S is formed over theUSG layer 16U by a plasma CVD method. Thus, aninterlevel insulation film 16 is formed. A contact hole H is formed at a predetermined position in theinterlevel insulation film 16 by dry etching. Where a plurality of contact holes H are formed on thesilicon substrate 11, the contact holes preferably have a uniform diameter on the order of not greater than 3 μm. Thus, the etching rate over thesubstrate 11 can be made uniform, and the selectivity ratio of thesilicon nitride film 16S to theTiN film 30 can be increased. - Thereafter, a
TiW film 20 is formed over the entire resulting substrate, for example, by a sputtering method as illustrated on a greater scale inFIG. 2 (f). - In turn, as shown in
FIG. 2 (g), agold seed layer 19S is formed over the entire resulting substrate. The formation of theseed layer 19S may be achieved through a sequential sputtering method by switching a target from TiW to gold in a treatment chamber employed for the formation of theTiW film 20. - Then, a resist 24 is formed as covering the
entire seed layer 19S. Anopening 24 a corresponding to agold interconnection layer 19 is formed in the resist 24. In this state, a gold electrolytic plating process is performed, whereby thegold interconnection layer 19 grows in theopening 24 a. - Thereafter, the resist 24 is removed, and a part of the
seed layer 19S and a part of theTiW film 20 not covered with thegold interconnection layer 19 are etched away. Then, for example, a 2 μm thickpolyimide resin film 18 is formed as a passivation film by coating. Thus, a semiconductor device having a construction as shown inFIG. 1 is provided. - Further, openings may be formed at predetermined positions in the
polyimide resin film 18 above thegold interconnection layer 19 for connection between thegold interconnection layer 19 and external connection terminals (not shown) by bonding wires. -
FIG. 3 is a sectional view illustrating the construction of a semiconductor device according to another embodiment of the present invention. InFIG. 3 , components corresponding to those shown inFIG. 1 will be denoted by the same reference characters as inFIG. 1 . - In this embodiment, a
silicon nitride film 25 is provided instead of thepolyimide resin film 18 as the passivation film. That is, after the resist 24 is removed and unnecessary portions of theseed layer 19S and theTIW film 20 are etched away in the state shown inFIG. 2 (g), thesilicon nitride film 25 is formed over the entire resulting substrate, for example, by a plasma CVD method. Thus, a semiconductor device as shown inFIG. 3 is provided. - With this arrangement, the corrosion resistance of the semiconductor device can further be improved, because the
silicon nitride film 25 herein employed is highly dense and has a high passivation effect. When thesilicon nitride film 25 is formed by the plasma CVD method, the semiconductor device is allowed to stand in a high temperature environment. Even in this case, theTiN film 30 prevents the diffusion of gold into thealuminum interconnection layer 14 from thegold interconnection layer 19. - While the two embodiments of the present invention have thus been described, the invention may be embodied in other ways. Although the
polyimide resin film 18 is employed as the passivation film in the embodiment shown inFIG. 1 , and thesilicon nitride film 25 is employed as the passivation film in the embodiment shown inFIG. 3 , neither thepolyimide resin film 18 nor thesilicon nitride film 25 may be provided, that is, no passivation film may be provided. Even in this case, thegold interconnection layer 19 exposed to a surface of the semiconductor device has a sufficient corrosion resistance, and the surface of theinterlevel insulation film 16 is constituted by thesilicon nitride film 16S having a high passivation effect. Further, theTiN film 30 is excellent in corrosion resistance. Therefore, the semiconductor device totally has a sufficient corrosion resistance. - Besides the BPSG film, a PSG film (a silicon oxide film doped with phosphorus) or a USG film may be employed as the
interlevel insulation film 13. - Further, an organic insulative silicon compound (organic SOG) which permits easy formation of a thicker film may be applied on the deposited
USG film 16U as filling a recess in an upper surface of theUSG layer 16U by an SOG (spin on glass) method to form an organic SOG layer 26 (seeFIGS. 1 and 3 ), and then thesilicon nitride film 16S may be formed by a high density plasma CVD method. - While the present invention has been described in detail by way of the embodiments thereof, it should be understood that the foregoing disclosure is merely illustrative of the technical principles of the present invention but not limitative of the same. The spirit and scope of the present invention are to be limited only by the appended claims.
- This application corresponds to Japanese Patent Application No. 2003-314240 filed with the Japanese Patent Office on Sep. 5, 2003, the disclosure of which is incorporated herein by reference.
Claims (12)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/005,383 US7662713B2 (en) | 2003-09-05 | 2007-12-27 | Semiconductor device production method that includes forming a gold interconnection layer |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003-314240 | 2003-09-05 | ||
JP2003314240A JP2005085884A (en) | 2003-09-05 | 2003-09-05 | Semiconductor device and method of manufacturing the same |
US10/919,385 US7335989B2 (en) | 2003-09-05 | 2004-08-17 | Semiconductor device and production method therefor |
US12/005,383 US7662713B2 (en) | 2003-09-05 | 2007-12-27 | Semiconductor device production method that includes forming a gold interconnection layer |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/919,385 Division US7335989B2 (en) | 2003-09-05 | 2004-08-17 | Semiconductor device and production method therefor |
Publications (2)
Publication Number | Publication Date |
---|---|
US20080116577A1 true US20080116577A1 (en) | 2008-05-22 |
US7662713B2 US7662713B2 (en) | 2010-02-16 |
Family
ID=34225163
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/919,385 Expired - Fee Related US7335989B2 (en) | 2003-09-05 | 2004-08-17 | Semiconductor device and production method therefor |
US12/005,383 Active 2024-11-19 US7662713B2 (en) | 2003-09-05 | 2007-12-27 | Semiconductor device production method that includes forming a gold interconnection layer |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/919,385 Expired - Fee Related US7335989B2 (en) | 2003-09-05 | 2004-08-17 | Semiconductor device and production method therefor |
Country Status (5)
Country | Link |
---|---|
US (2) | US7335989B2 (en) |
JP (1) | JP2005085884A (en) |
KR (1) | KR20050025240A (en) |
CN (1) | CN100452384C (en) |
TW (1) | TWI332247B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100032837A1 (en) * | 2006-10-12 | 2010-02-11 | Rohm Co., Ltd | Semiconductor device and semiconductor device manufacturing method |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3954998B2 (en) * | 2003-08-11 | 2007-08-08 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
US7566607B2 (en) * | 2004-09-30 | 2009-07-28 | Ricoh Company, Ltd. | Semiconductor device and fabrication process thereof |
KR101616044B1 (en) * | 2009-07-03 | 2016-04-28 | 삼성전자주식회사 | Semiconductor device comprising landing pad formed by electroless plating |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6037664A (en) * | 1997-08-20 | 2000-03-14 | Sematech Inc | Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer |
US6143646A (en) * | 1997-06-03 | 2000-11-07 | Motorola Inc. | Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation |
US6255226B1 (en) * | 1998-12-01 | 2001-07-03 | Philips Semiconductor, Inc. | Optimized metal etch process to enable the use of aluminum plugs |
US6271127B1 (en) * | 1999-06-10 | 2001-08-07 | Conexant Systems, Inc. | Method for dual damascene process using electron beam and ion implantation cure methods for low dielectric constant materials |
US20020132392A1 (en) * | 2001-01-15 | 2002-09-19 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing the same |
US6475836B1 (en) * | 1999-03-29 | 2002-11-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US6495879B1 (en) * | 1998-11-30 | 2002-12-17 | Nec Corporation | Ferroelectric memory device having a protective layer |
US6548900B1 (en) * | 1999-04-27 | 2003-04-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and fabrication method thereof |
US20030111735A1 (en) * | 2001-12-13 | 2003-06-19 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods for fabricating the same |
US6586347B1 (en) * | 2001-10-16 | 2003-07-01 | Taiwan Semiconductor Manufacturing Company | Method and structure to improve the reliability of multilayer structures of FSG (F-doped SiO2) dielectric layers and metal layers in semiconductor integrated circuits |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04196251A (en) | 1990-11-27 | 1992-07-16 | Mitsubishi Electric Corp | Semiconductor device |
JPH07183377A (en) | 1993-12-24 | 1995-07-21 | Nec Corp | Semiconductor device |
JPH07263555A (en) * | 1994-03-24 | 1995-10-13 | Nec Corp | Production process of semiconductor device |
JP4260334B2 (en) | 1999-03-29 | 2009-04-30 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
-
2003
- 2003-09-05 JP JP2003314240A patent/JP2005085884A/en active Pending
-
2004
- 2004-07-07 TW TW093120319A patent/TWI332247B/en not_active IP Right Cessation
- 2004-07-20 KR KR1020040056527A patent/KR20050025240A/en not_active Application Discontinuation
- 2004-07-30 CN CNB2004100559322A patent/CN100452384C/en not_active Expired - Fee Related
- 2004-08-17 US US10/919,385 patent/US7335989B2/en not_active Expired - Fee Related
-
2007
- 2007-12-27 US US12/005,383 patent/US7662713B2/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6143646A (en) * | 1997-06-03 | 2000-11-07 | Motorola Inc. | Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation |
US6037664A (en) * | 1997-08-20 | 2000-03-14 | Sematech Inc | Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer |
US6495879B1 (en) * | 1998-11-30 | 2002-12-17 | Nec Corporation | Ferroelectric memory device having a protective layer |
US6255226B1 (en) * | 1998-12-01 | 2001-07-03 | Philips Semiconductor, Inc. | Optimized metal etch process to enable the use of aluminum plugs |
US6475836B1 (en) * | 1999-03-29 | 2002-11-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US6548900B1 (en) * | 1999-04-27 | 2003-04-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and fabrication method thereof |
US6271127B1 (en) * | 1999-06-10 | 2001-08-07 | Conexant Systems, Inc. | Method for dual damascene process using electron beam and ion implantation cure methods for low dielectric constant materials |
US20020132392A1 (en) * | 2001-01-15 | 2002-09-19 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing the same |
US6586347B1 (en) * | 2001-10-16 | 2003-07-01 | Taiwan Semiconductor Manufacturing Company | Method and structure to improve the reliability of multilayer structures of FSG (F-doped SiO2) dielectric layers and metal layers in semiconductor integrated circuits |
US20030111735A1 (en) * | 2001-12-13 | 2003-06-19 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods for fabricating the same |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100032837A1 (en) * | 2006-10-12 | 2010-02-11 | Rohm Co., Ltd | Semiconductor device and semiconductor device manufacturing method |
US8125084B2 (en) | 2006-10-12 | 2012-02-28 | Rohm Co., Ltd. | Semiconductor device and semiconductor device manufacturing method |
Also Published As
Publication number | Publication date |
---|---|
TWI332247B (en) | 2010-10-21 |
JP2005085884A (en) | 2005-03-31 |
KR20050025240A (en) | 2005-03-14 |
US7335989B2 (en) | 2008-02-26 |
TW200511499A (en) | 2005-03-16 |
US7662713B2 (en) | 2010-02-16 |
CN100452384C (en) | 2009-01-14 |
US20050051899A1 (en) | 2005-03-10 |
CN1591857A (en) | 2005-03-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6472763B2 (en) | Semiconductor device with bumps for pads | |
JP2518435B2 (en) | Multilayer wiring formation method | |
US20110186962A1 (en) | Semiconductor device and method of manufacturing the same | |
US7943506B2 (en) | Semiconductor device and production method therefor | |
TW200405552A (en) | Semiconductor device | |
US6127715A (en) | Photodetector element containing circuit element and manufacturing method thereof | |
US8164160B2 (en) | Semiconductor device | |
US7662713B2 (en) | Semiconductor device production method that includes forming a gold interconnection layer | |
US8324731B2 (en) | Integrated circuit device | |
US8013442B2 (en) | Semiconductor device and manufacturing method thereof | |
US20080296772A1 (en) | Semicondutor device | |
US6313037B1 (en) | Semiconductor device and method for manufacturing the same | |
US20080237853A1 (en) | Semiconductor device and manufacturing method of the same | |
US7670948B2 (en) | Semiconductor device having diffusion barriers and a method of preventing diffusion of copper in a metal interconnection of a semiconductor device | |
KR100771549B1 (en) | Method for forming metal contact in semiconductor device | |
US6417568B1 (en) | Semiconductor device | |
US20080258301A1 (en) | Semiconductor device and manufacturing method of the same | |
JP3111466B2 (en) | Method of manufacturing semiconductor device having plated wiring layer | |
JP4986721B2 (en) | Semiconductor device and manufacturing method thereof | |
JP3745460B2 (en) | Wiring formation method of semiconductor device | |
JP2000068274A (en) | Wiring structure and forming method thereof | |
JPH11214513A (en) | Wiring structure of integrated circuit, and wiring formation method | |
KR0172525B1 (en) | Fabrication method of semiconductor device | |
JP2004273593A (en) | Semiconductor device and its fabricating process | |
KR100846993B1 (en) | A manufacturing method for wires of semiconductor devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ROHM CO., LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NAKATANI, GORO;TAMURA, HITOSHI;REEL/FRAME:020342/0282 Effective date: 20040706 Owner name: ROHM CO., LTD.,JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NAKATANI, GORO;TAMURA, HITOSHI;REEL/FRAME:020342/0282 Effective date: 20040706 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |