US20080122671A1

US20080122671A1 - Digital-to-analog converter

Info

Publication number: US20080122671A1
Application number: US11/563,321
Authority: US
Inventors: Ling Yun WANG; Ming-Cheng Chiu
Original assignee: Himax Technologies Ltd
Current assignee: Himax Technologies Ltd
Priority date: 2006-11-27
Filing date: 2006-11-27
Publication date: 2008-05-29
Anticipated expiration: 2026-11-27
Also published as: CN101192831B; TW200824301A; US20080122672A1; TW200824300A; US7375670B1; CN101192831A; TWI339512B; TWI330469B; US7511650B2

Abstract

A DAC is provided to convert an input word into dual output voltages, and the input word includes a least significant bit and remaining bits. The DAC includes an R-string DAC section and a selecting section. The R-string DAC section is capable of providing an nth and (n+2)th voltage levels according to the remaining bits. The selecting section includes a first multiplexer and a second multiplexer. The first multiplexer is coupled to the R-string DAC section to provide a first output voltage according to a panel polarity signal. The second multiplexer is coupled to the R-string DAC section to provide a second output voltage according to the LSB bit of the N-bit input word. The DAC may further include an operational amplifier to average the dual output voltages for producing an analog output signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. application Ser. No. 11/168,334, filed on Jun. 29, 2005, which is hereby incorporated by reference in its entirety.

BACKGROUND

1. Field of Invention
The present invention relates to digital-to-analog converters. More particularly, the present invention relates to a digital-to-analog converter having two sections for processing an input word.
2. Description of Related Art
There are many different types of digital-to-analog converters (DAC) available, such as a resistor string (R-string) DAC. FIG. 1 illustrates a conventional R-string DAC. An R-string DAC 100 includes a resistor string of resistors 110 and a selector 120. The selector 120 includes selecting lines 124 each of which is composed of switching elements 122. Each switching element 122 is controlled by one of the bits of an input word.
The resistor string is connected between a high reference voltage (V_H) and a low reference voltage (V_L). Each of the selecting lines 124 is connected to one of the nodes in the resistor string. Only one of the selecting lines 124 has switches all turned on by the input word and couples the voltage on the corresponding node in the resistor string to the output node Vo.
For N-bit digital-to-analog conversion, the R-string DAC 100 requires 2^Nselecting lines. Moreover, each of the selected lines 124 requires N switching elements. Therefore, 2^N×N switching elements are required for the N-bit R-string DAC 100. The number of switching elements dramatically increases when the bits of the input word are increased, which results in a larger layout area. This is disadvantageous for chip shrinkage and cost reduction.

SUMMARY

It is therefore an aspect of the present invention to provide a DAC, of which the circuit loading is lowered and the layout area is decreased.
According to one embodiment of the present invention, the DAC is provided to convert an input word into dual output voltages, and the input word includes a least significant bit (LSB) and remaining bits. The DAC includes an R-string DAC section and a selecting section. The R-string DAC section is capable of providing an nth and (n+2)th voltage levels according to the remaining bits.
The selecting section includes a first multiplexer and a second multiplexer. The first multiplexer is coupled to the R-string DAC section to provide a first output voltage according to a panel polarity signal. The second multiplexer is coupled to the R-string DAC section to provide a second output voltage according to the LSB bit of the N-bit input word.
The DAC may further include an operational amplifier to average the dual output voltages for producing an analog output signal.
In conclusion, an input word includes an LSB bit and remaining bits. A R-string DAC section is capable of providing an nth and (n+2)th voltage levels according to the remaining bits, which has one less switching element for each of the selected lines results in fewer switching elements needed compared to the conventional N-bit R-string DAC. Therefore, the circuit loading of the DAC is effectively lowered and the layout area is decreased. Further, a selecting section is coupled to the R-string DAC section to provide dual output voltages according to the LSB bit and a panel polarity signal. An operational amplifier may be adopted to average the dual output voltages to produce an analog output signal.
It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:

FIG. 1 illustrates a conventional R-string DAC;

FIG. 2 illustrates one embodiment of the present invention; and

FIG. 3 illustrates one embodiment of the R-string DAC section;

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
FIG. 2 illustrates one embodiment of the present invention. A DAC 200 converts an input word into dual output voltages V_O1and V_O2. An input word includes a least significant bit (LSB) and remaining bits. An 8-bit input word B₇B₆B₅B₄B₃B₂B₁B₀includes an LSB bit B₀and remaining bits B₇B₆B₅B₄B₃B₂B₁. The DAC 200 includes an R-string DAC section 202 and a selecting section 204. The R-string DAC section 202 is capable of providing an nth and (n+2)th voltage levels according to the remaining bits of the input word. The selection section 204 provides dual output voltages V_O1and V_O2. The selection section 204 includes a first multiplexer 208 and a second multiplexer 210. The first multiplexer 208 is coupled to the R-string DAC section 202. The first multiplexer 208 provides a first output voltage V_O1according to a panel polarity signal (e.g. an MREV signal). The second mutliplexer 210 is coupled to the R-string DAC section 202. The second multiplexer 210 provides a second output voltage V_O2according to the LSB bit of the input word.
The DAC 200 may include an operational amplifier 206. The operation amplifier 206 is coupled to the selecting section 204, and averages the dual output voltages V_O1and V_O2to produce an analog output signal V_O.
FIG. 3 illustrates one embodiment of the R-string DAC section. An R-string DAC section 300 includes a voltage generator and a 2-of-N selector 302. The voltage generator is capable of providing voltage levels V₀, V₂, . . . , V₂₅₄, V₂₅₆. The voltage levels V₀, V₂, . . . V₂₅₆are the even-numbered discrete analog voltages for digital-to-analog conversion of an 8-bit input word. The voltage generator includes resistors 308 electrically connected in series between a high reference voltage (V_H) and a low reference voltage (V_L) to provide voltage levels V₀, V₂, . . . , V₂₅₄, V₂₅₆. The 2-of-N selector 302 is coupled to the voltage generator, and selects an nth voltage level and an (n+2)th voltage level [for example, (V₀and V₂) or (V₂₅₂and V₂₅₄) voltage levels] according to the remaining bits.
More particularly, the 2-of-N selector 302 has selecting lines 304 correspondingly coupled to the voltage generator and selects the nth voltage level and the (n+2)th voltage level. For the 8-bit DAC, each of the selecting lines 304 includes 7 switching elements 306 [(total number bits of the input word−1) of switching elements], and each of the switching elements 306 (D₇D₆D₅D₄D₃D₂D₁) is controlled by one of the remaining bits (B₇B₆B₅B₄B₃B₂B₁). The switching elements 306 comprise PMOS and NMOS transistors. These transistors are arranged so that two adjacent voltage levels V_nand V_n+2are respectively output to the nodes V_in1and V_in2when the remaining bits (B₇B₆B₅B₄B₃B₂B₁) are received, where n is an integer between 0 and 254. More specifically, when the remaining bits 0000000 are received, the voltage levels V₀and V₂are respectively output as the voltages V_in1and V_in2. When the remaining bits 1111111 are received, the voltage levels V₂₅₄and V₂₅₆are respectively output as the voltages V_in1and V_in2.
Referring to FIG. 2, the first input terminal (1) of the first multiplexer 208 and the second input terminal (0) of the second multiplexer 210 are coupled to V_in1voltage level, the second input terminal (0) of the first multiplexer 208 and the first input terminal (1) of the second multiplexer 210 are coupled to the V_in2voltage level.
The first multiplexer 208 selects one of the voltages V_in1and V_in2as the first output voltage V_O1according to the panel polarity signal MREV signal, and the second multiplexer 210 selects one of the voltages V_in1and V_in2as the second output voltage V_O2according to the LSB bit of the input word. More particularly, the first multiplexer 208 selects the voltage V_in1as the first output voltage V_O1while the panel polarity signal has a high logic level, and the first multiplexer 208 selects the voltage V_in2as the first output voltage V_O1while the panel polarity signal has a low logic level. The second multiplexer 210 selects the voltage V_in2as the second output voltage V_O2while the LSB bit of the input word has a high logic level, the second multiplexer 210 selects the voltage V_in1as the second output voltage V_O2while the LSB bit of the input word has a low logic level.
For clarity, Table 1 shows the voltage levels of the signals V_in1, V_in2, V_O1, V_O2and V_Ofor different input words and logic levels of the signal MREV.

TABLE 1

	Input word	V_in1	V_in2	V_O1	V_O2	V_O

MREV = 1	00,000,000	V0	V2	V0	V0	V0
MREV = 0	11,111,111	V254	V256	V256	V256	V256
MREV = 1	00,000,001	V0	V2	V0	V2	V1
MREV = 0	11,111,110	V254	V256	V256	V254	V255

Those skilled in the art will appreciate that the MREV signal is the panel polarity signal for data inversion. The MREV signal may be used for the flat display of the mobile phone. Referring to row 2 of Table 1, when the input word is 00,000,000, the V_in1is equal to V0, and the V_in2is equal to V2. The MREV signal has a high logic level so that V0 is selected as the first output voltage V_O1. V0 is selected as the second output voltage V_O2since the LSB of the input word is 0.
Referring to row 3 of Table 1, when the input word is 11,111,111, the V_in1is equal to V254, and the V_in2is equal to V256. The MREV signal has a low logic level so that V256 is selected as the first output voltage V_O1. V256 is also selected as the second output voltage V_O2since the LSB of the input word is 1.
The operation amplifier 206 is coupled to the selecting section 204, and is capable of averaging the dual output voltages V_O1and V_O2to produce an analog output signal V_O, i.e., the analog output signal V_Ois equal to (V_O1+V_O2)/2. For the input word “00000000”, both the voltages V_O1and V_O2are V0 so that V_O=(V0+V0)/2=V0. For the input word “00000001”, the voltages V_O1and V_O2are respectively V0 and V2 so that V_O=(V0+V2)/2=V1
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims

1. A digital-to-analog converter (DAC), for converting an input word into dual output voltages, wherein the input word comprises a least significant bit (LSB) and remaining bits, the DAC comprising:

an R-string DAC section for providing an nth and (n+2)th voltage levels according to the remaining bits; and

a selecting section, comprising:

a first multiplexer, coupled to the R-string DAC section to provide a first output voltage according to a panel polarity signal; and

a second multiplexer, coupled to the R-string DAC section to provide a second output voltage according to the LSB bit of the input word, wherein the first multiplexer selects one of the nth and (n+2)th voltage levels to be the first output voltage, and the second multiplexer selects one of the nth and (n+2)th voltage levels to be the second output voltage.

2. The DAC as claimed in claim 1, wherein the R-string DAC section further comprises:

a voltage generator, capable of generating a plurality of voltage levels; and

a 2-of-N selector having a plurality of selecting lines correspondingly coupled to the voltage generator to provide the corresponding voltage levels, and each of the selecting lines comprises (total number bits of the input word-1) series-connected switching elements,

wherein each of the switching elements is switchedby one of the remaining bits.

3. The DAC as claimed in claim 2, wherein the voltage generator comprises a plurality of resistors electrically connected in series to provide the voltage levels.

4. (canceled)

5. The DAC as claimed in claim 4, wherein the first multiplexer selects the nth voltage level to be the first output voltage while the panel polarity signal is high, the first multiplexer selects the (n+2)th voltage level to be the first output voltage while the panel polarity signal is low.

6. The DAC as claimed in claim 4, wherein the second multiplexer selects the (n+2)th voltage level to be the second output voltage while the LSB bit of the input word is high, the second multiplexer selects the nth voltage level to be the second output voltage while the LSB bit of the input word is low.

7. The DAC as claimed in claim 1, wherein the voltage levels are grayscale voltages.

8. A digital-to-analog converter (DAC), for converting an input word into an analog output signal, wherein the input word comprises a least significant bit (LSB) and remaining bits, the DAC comprising:

a selecting section for providing dual output voltages, comprising:

a second multiplexer, coupled to the R-string DAC section to provide a second output voltage according to the LSB bit of the N-bit input word; and

an operational amplifier, coupled to the dual output voltages, is capable of averaging the dual output voltages to generate the analog output signal.

9. The DAC as claimed in claim 8, wherein the R-string DAC section further comprises:

a voltage generator, capable of generating a plurality of voltage levels; and

wherein each of the switching elements is switched by one of the remaining bits.

10. The DAC as claimed in claim 9, wherein the voltage generator comprises a plurality of resistors electrically connected in series to provide the voltage levels.

11. The DAC as claimed in claim 8, wherein the first multiplexer selects one of the nth and (n+2)th voltage levels to be the first output voltage, and the second multiplexer selects one of the nth and (n+2)th voltage levels to be the second output voltage.

12. The DAC as claimed in claim 11, wherein the first multiplexer selects the nth voltage level to be the first output voltage while the panel polarity signal is high, the first multiplexer selects the (n+2)th voltage level to be the first output voltage while the panel polarity signal is low.

13. The DAC as claimed in claim 11, wherein the second multiplexer selects the (n+2)th voltage level to be the second output voltage while the LSB bit of the input word is high, the second multiplexer selects the nth voltage level to be the second output voltage while the LSB bit of the input word is low.

14. The DAC as claimed in claim 8, wherein the voltage levels are grayscale voltages.