US20080142994A1 - Contact Pad And Bump Pad Arrangement for High-Lead Or Lead-Free Bumps - Google Patents
Contact Pad And Bump Pad Arrangement for High-Lead Or Lead-Free Bumps Download PDFInfo
- Publication number
- US20080142994A1 US20080142994A1 US12/036,928 US3692808A US2008142994A1 US 20080142994 A1 US20080142994 A1 US 20080142994A1 US 3692808 A US3692808 A US 3692808A US 2008142994 A1 US2008142994 A1 US 2008142994A1
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- Prior art keywords
- bump
- lead
- linear dimension
- bumps
- conductive pad
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Definitions
- This invention relates generally to integrated circuit packaging, more particularly to a method of forming electrically conductive bumps for flip chip packages.
- a flip chip microelectronic assembly includes a direct electrical connection of facing-down (that is, “flipped”) electronic components onto substrates, such as ceramic substrates, circuit boards, or carriers using conductive bump bond pads of the chip.
- Flip chip technology is quickly replacing older wire bonding technology that uses facing-up chips with a wire connected to each pad on the chip.
- flip chip components used in flip chip microelectronic assemblies are predominantly semiconductor devices, however, components such as passive filters, detector arrays, and memory devices are also being used in flip chip form.
- Flip chips are advantageous because of their high-speed electrical performance when compared to other assembly methods. Eliminating bond wires reduces the delay in inductance and capacitance of the connection, and substantially shortens the current path, resulting in a high-speed off-chip interconnection.
- Flip chips also provide the most rugged mechanical interconnection. When underfilled with an adhesive such as an epoxy, flip chips can withstand the most rugged durability testing. Additionally, flip chips can be the lowest cost interconnection for high-volume automated production.
- Flip chips are typically made by placing solder bumps on a silicon chip, and the solder bump flip chip process typically includes four sequential steps: 1) preparing the chip for solder bumping; 2) forming or placing the solder bumps on the chip; 3) attaching the solder bumped chip to a board, substrate or carrier; and 4) completing the assembly with an adhesive underfill.
- the bumps of the flip chip assembly serve several functions.
- the bumps provide electrical conductive paths from the chip (or die) to the substrate on which the chip is mounted.
- a thermally conductive path is also provided by the bumps to carry heat from the chip to the substrate.
- the bumps also provide part of the mechanical mounting of the chip to the substrate.
- the bumps act as a short lead to relieve mechanical strain between the chip and the substrate.
- Eutectic solder material containing lead (Pb) and tin (Sn) is typically used for solder bumps.
- a commonly used lead containing eutectic solder has about 63% tin (Sb) and 37% lead (Pb). This combination gives the solder material suitable melting point and low electrical resistivity.
- Lead is a toxic material. Legislation and industry requirements have demanded lead-free solder bumps. Companies in the supply chain of the electronics interconnection industry are actively seeking to replace Sn—Pb solder. However, the commonly known lead-free solder, such as Sn—Ag, Sn—Ag—Cu and their inter-metallic components are too brittle, therefore, suffering cracking. On the other hand, high-lead bumps are also preferred by the industry for applying in high electro-migration performance. Addition of lead provides increased corrosion resistance, lowers the reflow temperature of pure tin, and lowers the surface tension of pure tin. High-lead bumps are also brittle and each prone to cracking.
- Bump cracking is typically generated by stress.
- the coefficient of thermal expansion (CTE) mismatch between materials in the package assembly is one of the main reasons causing stress.
- silicon substrate typically has a CTE of higher than about 3 ppm/C
- low-k dielectric has a CTE of higher than about 20 ppm/C
- the package substrate has a CTE of higher than about 17 ppm/C.
- the significant difference of CTEs introduces stress to the structure when thermal change occurs.
- One solution to this problem is through the underfill process in which a liquid epoxy is dispensed along one or two sides of a chip to fill the gap between the chip and a substrate. Epoxy underfill helps spread the stress and protect the solder bumps.
- both lead-free and high-lead bumps need to be protected, preferably without using high strength underfill.
- Conventional solutions for the bump cracking problem have been concentrated on materials. Exploring a solution from a view of the structure therefore becomes valuable.
- the preferred embodiment of the present invention provides a solution with a modified structure.
- a semiconductor package assembly comprises a contact pad (first conductive pad) or an under bump metallurgy (UBM) on a semiconductor substrate, a bump underlying the contact pad and overlying a package substrate, which has a bump pad (second conductive pad) in contact with the bump.
- a top interface exists between the contact pad/UBM and the bump, and a bottom interface exists between the bump and a bump pad of the package substrate.
- the sizes of the top and bottom interfaces are substantially comparable.
- the balanced structure reduces stress applied to the bump, the inter-metallic component and neighboring materials. The reliability of the resulting assembly is significantly improved.
- the preferred embodiment of the present invention has presented a packaging solution that solves the cracking problem for lead-free and high-lead-containing bumps.
- the solution is compatible with the present packaging process. There is no extra effort or cost introduced. Also there is no requirement of using high strength underfills to protect bumps, therefore, damage to low-k materials in the chip is avoided.
- FIG. 1 illustrates a chip having a solder bump
- FIG. 2 illustrates a package substrate
- FIGS. 3 and 4 illustrate package assemblies with a chip and a package substrate integrated.
- the preferred embodiment of the present invention presents a package assembly structure that uses lead-free or high-lead-containing bumps.
- the preferred embodiments are illustrated in FIGS. 1 through 4 wherein like reference numbers are used to designate like elements throughout the various views and illustrative embodiments of the present invention.
- solder bumps are formed on chips, which contain integrated circuits. In other embodiments, the solder bumps are formed on package substrates.
- FIG. 1 illustrates a semiconductor substrate 2 having a solder bump 10 formed on a conductive pad, which is typically referred to as an under bump metallurgy (UBM) 8 .
- the semiconductor substrate 2 is sometimes referred to as chip 2 .
- the semiconductor substrate 2 preferably comprises low-k dielectrics that typically have low strength. Preferably, at least one low-k dielectric layer having a k value of less than about 3.3 is included in the semiconductor substrate 2 .
- a passivation layer 4 which is preferably formed of dielectric materials such as nitride, oxide, polyimide, and the like, is formed on the surface of chip 2 .
- a contact pad 6 is electrically coupled to the integrated circuit (not shown) in the semiconductor substrate 2 and is preferably formed of copper, aluminum, or alloys thereof and the like.
- An under bump metallurgy (UBM) 8 also referred to as under bump metallization layer, which is a conductive pad, is preferably formed on the contact pad 6 .
- UBM 8 provides good adhesion between the contact pad 6 and the bump 10 . It typically has a composite structure comprising multiple layers and serves as a diffusion barrier, a solder wettable layer, and an oxidation barrier.
- UBM 8 can be formed by sputtering, evaporation, electro plating or alternative methods. The multiple layers of UBM 8 are deposited sequentially, and the wettable layer, which is the outmost layer of UBM 8 , is typically formed of a conductive material comprising copper, nickel, palladium, or alloys thereof.
- UBM 8 preferably has the shape of a square or a rectangle having substantially equal length and width. The longest distance that can be found between any two points, also referred to as the linear dimension W 1 of UBM 8 , is preferably between about 30 ⁇ m and about 200 ⁇ m, more preferably about 100 ⁇ m.
- linear dimension indicates that the shapes of bump pads or UBMs are not limited to a square and a rectangle, and can be an arbitrary shape.
- a linear dimension is the diameter of a circle.
- a chip typically comprises multiple contact pads and multiple bumps.
- the pitch, or the distance between bumps 8 is preferably between about 100 ⁇ m and 300 ⁇ m, more preferably about 150 ⁇ m and 250 ⁇ m.
- solder bump 10 is formed on the UBM 8 .
- Solder bump 10 can be formed by commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc.
- a lead-free bump 10 comprises tin, silver, and, optionally, copper.
- the lead-free bump 10 comprises about 95% to about 97% tin, about 3% to about 4% silver, and about 0.5% to about 1.5% copper.
- a high-lead bump preferably comprises between about 95% to about 97% lead, about 3% and about 5% tin, more preferably about 95% lead and 5% tin.
- FIG. 2 illustrates a package substrate 12 .
- the package substrate 12 is preferably formed of a material such as polymer, ceramic, and print circuit.
- Bump pad 16 preferably comprises copper, aluminum, and alloys thereof.
- a solder resistance layer 14 is formed on package substrate 12 preventing solder from adhering to undesired parts of the package substrate 12 .
- a solder resistance opening (SRO) 24 exposing bump pad 16 is formed through the solder resistance layer 14 .
- SRO 24 is preferably a square or a rectangle having substantially equal length and width. The longest length, or the linear dimension W 2 of the SRO 24 , is preferably between about 30 ⁇ m and about 200 ⁇ m, more preferably about 100 ⁇ m.
- a protecting layer 18 which is a conductive pad, is optionally formed on the bump pad 16 .
- the protecting layer 18 preferably has a thickness of between about 100 ⁇ to about 10,000 ⁇ and is formed of a conductive material such as nickel, gold, or alloys thereof.
- Conductive line 22 electrically couples the bump pad 16 and another bump pad 20 . The function of the bump pad 20 will be discussed in subsequent paragraphs.
- Semiconductor substrate 2 as referred to in FIG. 1 and package substrate 12 as referred to in FIG. 2 are integrated to form a semiconductor package assembly 23 , as illustrated in FIG. 3 .
- Semiconductor substrate 2 is assembled facing down. Flux is applied either on the semiconductor substrate 2 or on the package substrate 12 prior to placing them together. Solder bumps 10 reflow to form a bond between two conductive pads 8 and 16 .
- the conductive pads 8 and 16 are UBM 8 and bump pad 16 , respectively (perhaps through another conductive pad, which is referred to as the protecting layer 18 ).
- bump 10 is re-shaped, it is preferred that the linear dimension W m of the bump is between about 100 ⁇ m and about 300 ⁇ m.
- the ratio of the height H to the greatest width W m is preferably between about 0.5 and about 1.0.
- the size of the top interface 26 which is the interface between bump 10 and UBM 8 , is typically defined by the size of UBM 8 .
- the size of the bottom interface 28 which is the interface between bump 10 and protecting layer 18 , is typically defined by the size of SRO 24 .
- a bump is considered unbalanced if the size of top interface 26 and bottom interface 28 are substantially different.
- Unbalanced bump 10 has a high stress at the end with smaller size (either the top interface 26 or the bottom interface 28 ), causing it to be more prone to cracking. Therefore, it is preferred that UBM 8 is balanced, which means the size W 1 of UBM 8 is substantially close to the size W 2 of SRO 24 . Preferably the ratio of W 1 /W 2 is between about 0.7 and about 1.7, more preferably between about 0.8 and about 1.5, even more preferably between about 0.9 and about 1.3.
- IMC inter-metallic components
- a pre-solder layer is preferably formed.
- FIG. 4 illustrates another preferred embodiment wherein a pre-solder layer 36 is formed between the bump 10 and the bump pad 16 .
- the pre-solder layer 36 is preferably formed of eutectic materials such as an alloy comprising 63% tin and 37% lead, and the like.
- the bottom interface size of the bump 10 is, therefore, typically defined by the size of the pre-solder layer 36 .
- the linear dimension W 2 of the pre-solder layer 36 is preferably between about 30 ⁇ m and about 200 ⁇ m, more preferably about 100 ⁇ m.
- the ratio of W 1 /W 2 is preferably between about 0.7 and about 1.7, more preferably between about 0.8 and about 1.5, even more preferably between about 0.9 and about 1.3.
- the package substrate 12 typically has a layered structure.
- bump 10 is electrically connected to one of the ball grid array (BGA) balls 30 .
- BGA balls 30 are formed under package substrate 12 and used for electrically coupling the integrated circuit (not shown) on substrate 2 to an external component such as a print circuit board 40 .
- BGA balls 30 are substantially lead-free and comprise a solder material having a lead concentration of less than about 5%.
- BGA balls 30 comprise a eutectic alloy comprising lead and tin.
- Low-k materials are widely used in integrated circuits as inter-metal dielectrics.
- Low-k dielectrics typically have lower strength and are sometimes porous, and therefore they are easier to be damaged or delaminated, especially when used together with high strength materials.
- the use of low-k dielectrics in chip 2 limits the usage of high strength underfill material, which in turn limits the protection bump 10 receives from the underfill. Without the protection, lead-free and high-lead bumps and their IMCs are more prone to cracking. Tests have been conducted regarding the reliability of lead-free and high-lead materials. It has been found that a significant number of samples failed during thermal cycle tests if the bumps are unbalanced. Cracks are typically formed close to the end having smaller interface size. If inappropriate underfill materials are used, failures may also occur due to low-k dielectric de-lamination or underfill de-lamination. When tests are performed on samples with substantially balanced bumps, significant improvements are found. None of the samples failed during the thermal cycle test.
- the preferred embodiment of the present invention has presented a packaging solution that solves the cracking problem for lead-free and high-lead bumps. Contrary to prior teachings that the lead-free and high-lead bumps are prone to cracking, the results have demonstrated that lead-free and high lead bumps are not prone to cracking, providing the size balancing requirements specified in the preferred embodiments of the present invention are met.
- the current solution is fully inline with the existing packaging process and no extra effort or cost is introduced. High strength underfill material is not required for protecting bumps so that damage to low-k dielectrics is avoided.
Abstract
A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with the first conductive pad, the first interface having a first linear dimension; the bump has a second interface with the second conductive pad, the second interface having a second linear dimension; and wherein the ratio of the first linear dimension and the second linear dimension is between about 0.7 and about 1.7.
Description
- This application is a divisional of patent application Ser. No. 11/082,298, entitled “Reducing Cracking of High-Lead Or Lead-Free Bumps by Matching Sizes of Contact Pads and Bump Pads,” filed on Mar. 17, 2005, which application is incorporated herein by reference.
- This invention relates generally to integrated circuit packaging, more particularly to a method of forming electrically conductive bumps for flip chip packages.
- A flip chip microelectronic assembly includes a direct electrical connection of facing-down (that is, “flipped”) electronic components onto substrates, such as ceramic substrates, circuit boards, or carriers using conductive bump bond pads of the chip. Flip chip technology is quickly replacing older wire bonding technology that uses facing-up chips with a wire connected to each pad on the chip.
- The flip chip components used in flip chip microelectronic assemblies are predominantly semiconductor devices, however, components such as passive filters, detector arrays, and memory devices are also being used in flip chip form. Flip chips are advantageous because of their high-speed electrical performance when compared to other assembly methods. Eliminating bond wires reduces the delay in inductance and capacitance of the connection, and substantially shortens the current path, resulting in a high-speed off-chip interconnection.
- Flip chips also provide the most rugged mechanical interconnection. When underfilled with an adhesive such as an epoxy, flip chips can withstand the most rugged durability testing. Additionally, flip chips can be the lowest cost interconnection for high-volume automated production.
- Flip chips are typically made by placing solder bumps on a silicon chip, and the solder bump flip chip process typically includes four sequential steps: 1) preparing the chip for solder bumping; 2) forming or placing the solder bumps on the chip; 3) attaching the solder bumped chip to a board, substrate or carrier; and 4) completing the assembly with an adhesive underfill. The bumps of the flip chip assembly serve several functions. The bumps provide electrical conductive paths from the chip (or die) to the substrate on which the chip is mounted. A thermally conductive path is also provided by the bumps to carry heat from the chip to the substrate. The bumps also provide part of the mechanical mounting of the chip to the substrate. Finally, the bumps act as a short lead to relieve mechanical strain between the chip and the substrate.
- Eutectic solder material containing lead (Pb) and tin (Sn) is typically used for solder bumps. A commonly used lead containing eutectic solder has about 63% tin (Sb) and 37% lead (Pb). This combination gives the solder material suitable melting point and low electrical resistivity.
- Lead is a toxic material. Legislation and industry requirements have demanded lead-free solder bumps. Companies in the supply chain of the electronics interconnection industry are actively seeking to replace Sn—Pb solder. However, the commonly known lead-free solder, such as Sn—Ag, Sn—Ag—Cu and their inter-metallic components are too brittle, therefore, suffering cracking. On the other hand, high-lead bumps are also preferred by the industry for applying in high electro-migration performance. Addition of lead provides increased corrosion resistance, lowers the reflow temperature of pure tin, and lowers the surface tension of pure tin. High-lead bumps are also brittle and each prone to cracking.
- Bump cracking is typically generated by stress. The coefficient of thermal expansion (CTE) mismatch between materials in the package assembly is one of the main reasons causing stress. For example, silicon substrate typically has a CTE of higher than about 3 ppm/C, low-k dielectric has a CTE of higher than about 20 ppm/C, while the package substrate has a CTE of higher than about 17 ppm/C. The significant difference of CTEs introduces stress to the structure when thermal change occurs. One solution to this problem is through the underfill process in which a liquid epoxy is dispensed along one or two sides of a chip to fill the gap between the chip and a substrate. Epoxy underfill helps spread the stress and protect the solder bumps.
- With low-k dielectrics widely used in the integrated circuit, a dilemma exists between the protection of bumps and low-k dielectrics. The protection of brittle bumps demands high strength underfills. However, the low-k dielectrics may be harmed by high strength underfill material and problems such as delaminating occur.
- Therefore, with low-k dielectrics used, both lead-free and high-lead bumps need to be protected, preferably without using high strength underfill. Conventional solutions for the bump cracking problem have been concentrated on materials. Exploring a solution from a view of the structure therefore becomes valuable. The preferred embodiment of the present invention provides a solution with a modified structure.
- In accordance with one aspect of the present invention, a semiconductor package assembly comprises a contact pad (first conductive pad) or an under bump metallurgy (UBM) on a semiconductor substrate, a bump underlying the contact pad and overlying a package substrate, which has a bump pad (second conductive pad) in contact with the bump. A top interface exists between the contact pad/UBM and the bump, and a bottom interface exists between the bump and a bump pad of the package substrate. The sizes of the top and bottom interfaces are substantially comparable. The balanced structure reduces stress applied to the bump, the inter-metallic component and neighboring materials. The reliability of the resulting assembly is significantly improved.
- The preferred embodiment of the present invention has presented a packaging solution that solves the cracking problem for lead-free and high-lead-containing bumps. The solution is compatible with the present packaging process. There is no extra effort or cost introduced. Also there is no requirement of using high strength underfills to protect bumps, therefore, damage to low-k materials in the chip is avoided.
- For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 illustrates a chip having a solder bump; -
FIG. 2 illustrates a package substrate; and -
FIGS. 3 and 4 illustrate package assemblies with a chip and a package substrate integrated. - The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
- The preferred embodiment of the present invention presents a package assembly structure that uses lead-free or high-lead-containing bumps. The preferred embodiments are illustrated in
FIGS. 1 through 4 wherein like reference numbers are used to designate like elements throughout the various views and illustrative embodiments of the present invention. - In the preferred embodiment, solder bumps are formed on chips, which contain integrated circuits. In other embodiments, the solder bumps are formed on package substrates.
FIG. 1 illustrates asemiconductor substrate 2 having asolder bump 10 formed on a conductive pad, which is typically referred to as an under bump metallurgy (UBM) 8. Thesemiconductor substrate 2 is sometimes referred to aschip 2. Thesemiconductor substrate 2 preferably comprises low-k dielectrics that typically have low strength. Preferably, at least one low-k dielectric layer having a k value of less than about 3.3 is included in thesemiconductor substrate 2. Apassivation layer 4, which is preferably formed of dielectric materials such as nitride, oxide, polyimide, and the like, is formed on the surface ofchip 2. Acontact pad 6 is electrically coupled to the integrated circuit (not shown) in thesemiconductor substrate 2 and is preferably formed of copper, aluminum, or alloys thereof and the like. An under bump metallurgy (UBM) 8, also referred to as under bump metallization layer, which is a conductive pad, is preferably formed on thecontact pad 6.UBM 8 provides good adhesion between thecontact pad 6 and thebump 10. It typically has a composite structure comprising multiple layers and serves as a diffusion barrier, a solder wettable layer, and an oxidation barrier.UBM 8 can be formed by sputtering, evaporation, electro plating or alternative methods. The multiple layers ofUBM 8 are deposited sequentially, and the wettable layer, which is the outmost layer ofUBM 8, is typically formed of a conductive material comprising copper, nickel, palladium, or alloys thereof.UBM 8 preferably has the shape of a square or a rectangle having substantially equal length and width. The longest distance that can be found between any two points, also referred to as the linear dimension W1 ofUBM 8, is preferably between about 30 μm and about 200 μm, more preferably about 100 μm. When linear dimension is used, it indicates that the shapes of bump pads or UBMs are not limited to a square and a rectangle, and can be an arbitrary shape. A linear dimension is the diameter of a circle. A chip typically comprises multiple contact pads and multiple bumps. The pitch, or the distance betweenbumps 8, is preferably between about 100 μm and 300 μm, more preferably about 150 μm and 250 μm. - After
UBM 8 deposition, asolder bump 10 is formed on theUBM 8.Solder bump 10 can be formed by commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. In one preferred embodiment, a lead-free bump 10 comprises tin, silver, and, optionally, copper. In an exemplary embodiment, the lead-free bump 10 comprises about 95% to about 97% tin, about 3% to about 4% silver, and about 0.5% to about 1.5% copper. A high-lead bump preferably comprises between about 95% to about 97% lead, about 3% and about 5% tin, more preferably about 95% lead and 5% tin. -
FIG. 2 illustrates apackage substrate 12. Thepackage substrate 12 is preferably formed of a material such as polymer, ceramic, and print circuit.Bump pad 16 preferably comprises copper, aluminum, and alloys thereof. Asolder resistance layer 14 is formed onpackage substrate 12 preventing solder from adhering to undesired parts of thepackage substrate 12. A solder resistance opening (SRO) 24 exposingbump pad 16 is formed through thesolder resistance layer 14.SRO 24 is preferably a square or a rectangle having substantially equal length and width. The longest length, or the linear dimension W2 of theSRO 24, is preferably between about 30 μm and about 200 μm, more preferably about 100 μm. A protectinglayer 18, which is a conductive pad, is optionally formed on thebump pad 16. The protectinglayer 18 preferably has a thickness of between about 100 Å to about 10,000 Å and is formed of a conductive material such as nickel, gold, or alloys thereof.Conductive line 22 electrically couples thebump pad 16 and anotherbump pad 20. The function of thebump pad 20 will be discussed in subsequent paragraphs. -
Semiconductor substrate 2 as referred to inFIG. 1 andpackage substrate 12 as referred to inFIG. 2 are integrated to form asemiconductor package assembly 23, as illustrated inFIG. 3 .Semiconductor substrate 2 is assembled facing down. Flux is applied either on thesemiconductor substrate 2 or on thepackage substrate 12 prior to placing them together. Solder bumps 10 reflow to form a bond between twoconductive pads conductive pads UBM 8 andbump pad 16, respectively (perhaps through another conductive pad, which is referred to as the protecting layer 18). - After reflowing, bump 10 is re-shaped, it is preferred that the linear dimension Wm of the bump is between about 100 μm and about 300 μm. The ratio of the height H to the greatest width Wm is preferably between about 0.5 and about 1.0. The size of the
top interface 26, which is the interface betweenbump 10 andUBM 8, is typically defined by the size ofUBM 8. The size of thebottom interface 28, which is the interface betweenbump 10 and protectinglayer 18, is typically defined by the size ofSRO 24. A bump is considered unbalanced if the size oftop interface 26 andbottom interface 28 are substantially different.Unbalanced bump 10 has a high stress at the end with smaller size (either thetop interface 26 or the bottom interface 28), causing it to be more prone to cracking. Therefore, it is preferred thatUBM 8 is balanced, which means the size W1 ofUBM 8 is substantially close to the size W2 ofSRO 24. Preferably the ratio of W1/W2 is between about 0.7 and about 1.7, more preferably between about 0.8 and about 1.5, even more preferably between about 0.9 and about 1.3. After bumps reflow, inter-metallic components (IMC) (not shown) are formed atinterfaces - For a high-lead bump assembly to be formed using an organic substrate, a pre-solder layer is preferably formed.
FIG. 4 illustrates another preferred embodiment wherein apre-solder layer 36 is formed between thebump 10 and thebump pad 16. Thepre-solder layer 36 is preferably formed of eutectic materials such as an alloy comprising 63% tin and 37% lead, and the like. The bottom interface size of thebump 10 is, therefore, typically defined by the size of thepre-solder layer 36. Similar to the previously discussed embodiment, the linear dimension W2 of thepre-solder layer 36 is preferably between about 30 μm and about 200 μm, more preferably about 100 μm. In order to balance the bump and, thus, reduce stress at thetop interface 26 orbottom interface 28, the ratio of W1/W2 is preferably between about 0.7 and about 1.7, more preferably between about 0.8 and about 1.5, even more preferably between about 0.9 and about 1.3. - Referring back to
FIG. 3 , thepackage substrate 12 typically has a layered structure. Through ametal line 22, which is routed inpackage substrate 12,bump 10 is electrically connected to one of the ball grid array (BGA)balls 30.BGA balls 30 are formed underpackage substrate 12 and used for electrically coupling the integrated circuit (not shown) onsubstrate 2 to an external component such as aprint circuit board 40. In the preferred embodiment,BGA balls 30 are substantially lead-free and comprise a solder material having a lead concentration of less than about 5%. In alternative embodiments,BGA balls 30 comprise a eutectic alloy comprising lead and tin. - Low-k materials are widely used in integrated circuits as inter-metal dielectrics. Low-k dielectrics typically have lower strength and are sometimes porous, and therefore they are easier to be damaged or delaminated, especially when used together with high strength materials. The use of low-k dielectrics in
chip 2 limits the usage of high strength underfill material, which in turn limits theprotection bump 10 receives from the underfill. Without the protection, lead-free and high-lead bumps and their IMCs are more prone to cracking. Tests have been conducted regarding the reliability of lead-free and high-lead materials. It has been found that a significant number of samples failed during thermal cycle tests if the bumps are unbalanced. Cracks are typically formed close to the end having smaller interface size. If inappropriate underfill materials are used, failures may also occur due to low-k dielectric de-lamination or underfill de-lamination. When tests are performed on samples with substantially balanced bumps, significant improvements are found. None of the samples failed during the thermal cycle test. - The preferred embodiment of the present invention has presented a packaging solution that solves the cracking problem for lead-free and high-lead bumps. Contrary to prior teachings that the lead-free and high-lead bumps are prone to cracking, the results have demonstrated that lead-free and high lead bumps are not prone to cracking, providing the size balancing requirements specified in the preferred embodiments of the present invention are met. The current solution is fully inline with the existing packaging process and no extra effort or cost is introduced. High strength underfill material is not required for protecting bumps so that damage to low-k dielectrics is avoided.
- Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (8)
1. A semiconductor package assembly comprising:
a first conductive pad on a semiconductor substrate;
a second conductive pad on a package substrate;
a substantially high-lead-containing bump physically coupled between the semiconductor substrate and the package substrate;
wherein the bump has a first interface with the first conductive pad, the first interface having a first linear dimension;
wherein the bump has a second interface with the second conductive pad, the second interface having a second linear dimension; and
wherein the first linear dimension and the second linear dimension has a ratio of between about 0.7 and about 1.7.
2. The semiconductor package assembly of claim 1 wherein the semiconductor substrate comprises at least one low-k dielectric layer having a k value of less than about 3.3.
3. The semiconductor package assembly of claim 1 wherein the bump comprises greater than about 80 percent lead.
4. The semiconductor package assembly of claim 1 wherein the ratio of the first linear dimension and the second linear dimension is between about 0.8 and about 1.5.
5. The semiconductor package assembly of claim 4 wherein the ratio of the first linear dimension and the second linear dimension is between about 0.9 and about 1.3.
6. The semiconductor package assembly of claim 1 wherein the second conductive pad comprises a material selected from the group consisting essentially of copper, aluminum, and combinations thereof.
7. The semiconductor package assembly of claim 1 wherein the first and second linear dimensions are between about 30 μm and 200 μm, respectively.
8. The semiconductor package assembly of claim 1 wherein the bump has a height of between about 30 μm and about 200 μm, wherein the height and the first linear dimension has a ratio of between about 0.5 and about 1.0, and wherein the height and the second linear dimension has a ratio of between about 0.5 and about 1.0.
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US12/036,928 US20080142994A1 (en) | 2005-03-17 | 2008-02-25 | Contact Pad And Bump Pad Arrangement for High-Lead Or Lead-Free Bumps |
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US11/082,298 US7361990B2 (en) | 2005-03-17 | 2005-03-17 | Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads |
US12/036,928 US20080142994A1 (en) | 2005-03-17 | 2008-02-25 | Contact Pad And Bump Pad Arrangement for High-Lead Or Lead-Free Bumps |
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US11/082,298 Division US7361990B2 (en) | 2005-03-17 | 2005-03-17 | Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads |
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US12/036,928 Abandoned US20080142994A1 (en) | 2005-03-17 | 2008-02-25 | Contact Pad And Bump Pad Arrangement for High-Lead Or Lead-Free Bumps |
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110101519A1 (en) * | 2009-10-29 | 2011-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Robust Joint Structure for Flip-Chip Bonding |
US20110101526A1 (en) * | 2009-10-29 | 2011-05-05 | Ching-Wen Hsiao | Copper Bump Joint Structures with Improved Crack Resistance |
US20130087892A1 (en) * | 2011-10-07 | 2013-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd | Electrical Connection for Chip Scale Packaging |
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EP3940771A1 (en) * | 2020-07-15 | 2022-01-19 | Renesas Electronics Corporation | Semiconductor device |
Families Citing this family (109)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8350384B2 (en) | 2009-11-24 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
USRE47600E1 (en) | 2003-11-10 | 2019-09-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
US8129841B2 (en) | 2006-12-14 | 2012-03-06 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
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US8674500B2 (en) * | 2003-12-31 | 2014-03-18 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
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US8216930B2 (en) | 2006-12-14 | 2012-07-10 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
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US8841779B2 (en) | 2005-03-25 | 2014-09-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate |
US20070029669A1 (en) * | 2005-08-05 | 2007-02-08 | Frank Stepniak | Integrated circuit with low-stress under-bump metallurgy |
DE102005055280B3 (en) * | 2005-11-17 | 2007-04-12 | Infineon Technologies Ag | Connecting elements for semiconductor components have mushroom shape with first metal area filling out indentations on top of insulating layer and with second metal area on containing refractory inter-metallic phases of metals of solder |
JP2007317979A (en) * | 2006-05-29 | 2007-12-06 | Toshiba Corp | Method for manufacturing semiconductor device |
JP5078500B2 (en) * | 2006-08-30 | 2012-11-21 | 三洋電機株式会社 | Device mounting substrate, semiconductor module, and portable device |
US8081484B2 (en) | 2006-11-30 | 2011-12-20 | Cisco Technology, Inc. | Method and apparatus for supporting a computer chip on a printed circuit board assembly |
GB2444775B (en) * | 2006-12-13 | 2011-06-08 | Cambridge Silicon Radio Ltd | Chip mounting |
JP4980709B2 (en) * | 2006-12-25 | 2012-07-18 | ローム株式会社 | Semiconductor device |
TWI331797B (en) * | 2007-04-18 | 2010-10-11 | Unimicron Technology Corp | Surface structure of a packaging substrate and a fabricating method thereof |
US7615865B2 (en) * | 2007-05-21 | 2009-11-10 | Stats Chippac, Ltd. | Standoff height improvement for bumping technology using solder resist |
DE102009012139B4 (en) * | 2009-03-06 | 2012-02-23 | Epcos Ag | Module substrate and method of manufacture |
TWI445147B (en) | 2009-10-14 | 2014-07-11 | Advanced Semiconductor Eng | Semiconductor device |
TWI502706B (en) * | 2009-10-29 | 2015-10-01 | Taiwan Semiconductor Mfg Co Ltd | Robust joint structure for flip-chip bonding |
KR101290045B1 (en) * | 2009-10-29 | 2013-07-30 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Robust Joint Structure for Flip-Chip Bonding |
JP5357784B2 (en) * | 2010-01-05 | 2013-12-04 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
US8642448B2 (en) | 2010-06-22 | 2014-02-04 | Applied Materials, Inc. | Wafer dicing using femtosecond-based laser and plasma etch |
KR101692702B1 (en) * | 2010-07-01 | 2017-01-18 | 삼성전자주식회사 | Semiconductor package and Method of fabricating the same |
TWI478303B (en) | 2010-09-27 | 2015-03-21 | Advanced Semiconductor Eng | Chip having metal pillar and package having the same |
CN102064135B (en) * | 2010-10-21 | 2015-07-22 | 日月光半导体制造股份有限公司 | Chip with metal post and encapsulating structure of chip with metal post |
TWI451546B (en) | 2010-10-29 | 2014-09-01 | Advanced Semiconductor Eng | Stacked semiconductor package, semiconductor package thereof and method for making a semiconductor package |
US8693203B2 (en) | 2011-01-14 | 2014-04-08 | Harris Corporation | Method of making an electronic device having a liquid crystal polymer solder mask laminated to an interconnect layer stack and related devices |
US8912077B2 (en) | 2011-06-15 | 2014-12-16 | Applied Materials, Inc. | Hybrid laser and plasma etch wafer dicing using substrate carrier |
US9029242B2 (en) | 2011-06-15 | 2015-05-12 | Applied Materials, Inc. | Damage isolation by shaped beam delivery in laser scribing process |
US20120322235A1 (en) * | 2011-06-15 | 2012-12-20 | Wei-Sheng Lei | Wafer dicing using hybrid galvanic laser scribing process with plasma etch |
US8703581B2 (en) | 2011-06-15 | 2014-04-22 | Applied Materials, Inc. | Water soluble mask for substrate dicing by laser and plasma etch |
US8557683B2 (en) | 2011-06-15 | 2013-10-15 | Applied Materials, Inc. | Multi-step and asymmetrically shaped laser beam scribing |
US9129904B2 (en) | 2011-06-15 | 2015-09-08 | Applied Materials, Inc. | Wafer dicing using pulse train laser with multiple-pulse bursts and plasma etch |
US8507363B2 (en) * | 2011-06-15 | 2013-08-13 | Applied Materials, Inc. | Laser and plasma etch wafer dicing using water-soluble die attach film |
US8759197B2 (en) | 2011-06-15 | 2014-06-24 | Applied Materials, Inc. | Multi-step and asymmetrically shaped laser beam scribing |
WO2013101241A1 (en) | 2011-12-31 | 2013-07-04 | Intel Corporation | Organic thin film passivation of metal interconnections |
WO2013101243A1 (en) | 2011-12-31 | 2013-07-04 | Intel Corporation | High density package interconnects |
US8946057B2 (en) | 2012-04-24 | 2015-02-03 | Applied Materials, Inc. | Laser and plasma etch wafer dicing using UV-curable adhesive film |
US8884443B2 (en) | 2012-07-05 | 2014-11-11 | Advanced Semiconductor Engineering, Inc. | Substrate for semiconductor package and process for manufacturing |
US9048309B2 (en) | 2012-07-10 | 2015-06-02 | Applied Materials, Inc. | Uniform masking for wafer dicing using laser and plasma etch |
US8859397B2 (en) | 2012-07-13 | 2014-10-14 | Applied Materials, Inc. | Method of coating water soluble mask for laser scribing and plasma etch |
US8940619B2 (en) | 2012-07-13 | 2015-01-27 | Applied Materials, Inc. | Method of diced wafer transportation |
US9159687B2 (en) | 2012-07-31 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Solder bump for ball grid array |
US8686568B2 (en) | 2012-09-27 | 2014-04-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor package substrates having layered circuit segments, and related methods |
US9252057B2 (en) | 2012-10-17 | 2016-02-02 | Applied Materials, Inc. | Laser and plasma etch wafer dicing with partial pre-curing of UV release dicing tape for film frame wafer application |
US8975162B2 (en) | 2012-12-20 | 2015-03-10 | Applied Materials, Inc. | Wafer dicing from wafer backside |
US9236305B2 (en) | 2013-01-25 | 2016-01-12 | Applied Materials, Inc. | Wafer dicing with etch chamber shield ring for film frame wafer applications |
US9773724B2 (en) * | 2013-01-29 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices, methods of manufacture thereof, and semiconductor device packages |
TWI619165B (en) | 2013-03-14 | 2018-03-21 | 應用材料股份有限公司 | Multi-layer mask including non-photodefinable laser energy absorbing layer for substrate dicing by laser and plasma etch |
US9105710B2 (en) | 2013-08-30 | 2015-08-11 | Applied Materials, Inc. | Wafer dicing method for improving die packaging quality |
US9224650B2 (en) | 2013-09-19 | 2015-12-29 | Applied Materials, Inc. | Wafer dicing from wafer backside and front side |
US9460966B2 (en) | 2013-10-10 | 2016-10-04 | Applied Materials, Inc. | Method and apparatus for dicing wafers having thick passivation polymer layer |
US9041198B2 (en) | 2013-10-22 | 2015-05-26 | Applied Materials, Inc. | Maskless hybrid laser scribing and plasma etching wafer dicing process |
US9312177B2 (en) | 2013-12-06 | 2016-04-12 | Applied Materials, Inc. | Screen print mask for laser scribe and plasma etch wafer dicing process |
US9299614B2 (en) | 2013-12-10 | 2016-03-29 | Applied Materials, Inc. | Method and carrier for dicing a wafer |
US9293304B2 (en) | 2013-12-17 | 2016-03-22 | Applied Materials, Inc. | Plasma thermal shield for heat dissipation in plasma chamber |
US9018079B1 (en) | 2014-01-29 | 2015-04-28 | Applied Materials, Inc. | Wafer dicing using hybrid laser scribing and plasma etch approach with intermediate reactive post mask-opening clean |
US9299611B2 (en) | 2014-01-29 | 2016-03-29 | Applied Materials, Inc. | Method of wafer dicing using hybrid laser scribing and plasma etch approach with mask plasma treatment for improved mask etch resistance |
US8991329B1 (en) | 2014-01-31 | 2015-03-31 | Applied Materials, Inc. | Wafer coating |
US9236284B2 (en) | 2014-01-31 | 2016-01-12 | Applied Materials, Inc. | Cooled tape frame lift and low contact shadow ring for plasma heat isolation |
US9275902B2 (en) | 2014-03-26 | 2016-03-01 | Applied Materials, Inc. | Dicing processes for thin wafers with bumps on wafer backside |
US9076860B1 (en) | 2014-04-04 | 2015-07-07 | Applied Materials, Inc. | Residue removal from singulated die sidewall |
US8975163B1 (en) | 2014-04-10 | 2015-03-10 | Applied Materials, Inc. | Laser-dominated laser scribing and plasma etch hybrid wafer dicing |
US8932939B1 (en) | 2014-04-14 | 2015-01-13 | Applied Materials, Inc. | Water soluble mask formation by dry film lamination |
US8912078B1 (en) | 2014-04-16 | 2014-12-16 | Applied Materials, Inc. | Dicing wafers having solder bumps on wafer backside |
US8999816B1 (en) | 2014-04-18 | 2015-04-07 | Applied Materials, Inc. | Pre-patterned dry laminate mask for wafer dicing processes |
US9159621B1 (en) | 2014-04-29 | 2015-10-13 | Applied Materials, Inc. | Dicing tape protection for wafer dicing using laser scribe process |
US8912075B1 (en) | 2014-04-29 | 2014-12-16 | Applied Materials, Inc. | Wafer edge warp supression for thin wafer supported by tape frame |
US8980727B1 (en) | 2014-05-07 | 2015-03-17 | Applied Materials, Inc. | Substrate patterning using hybrid laser scribing and plasma etching processing schemes |
US9112050B1 (en) | 2014-05-13 | 2015-08-18 | Applied Materials, Inc. | Dicing tape thermal management by wafer frame support ring cooling during plasma dicing |
US9034771B1 (en) | 2014-05-23 | 2015-05-19 | Applied Materials, Inc. | Cooling pedestal for dicing tape thermal management during plasma dicing |
US9130057B1 (en) | 2014-06-30 | 2015-09-08 | Applied Materials, Inc. | Hybrid dicing process using a blade and laser |
US9142459B1 (en) | 2014-06-30 | 2015-09-22 | Applied Materials, Inc. | Wafer dicing using hybrid laser scribing and plasma etch approach with mask application by vacuum lamination |
US9165832B1 (en) | 2014-06-30 | 2015-10-20 | Applied Materials, Inc. | Method of die singulation using laser ablation and induction of internal defects with a laser |
US9093518B1 (en) | 2014-06-30 | 2015-07-28 | Applied Materials, Inc. | Singulation of wafers having wafer-level underfill |
US9349648B2 (en) | 2014-07-22 | 2016-05-24 | Applied Materials, Inc. | Hybrid wafer dicing approach using a rectangular shaped two-dimensional top hat laser beam profile or a linear shaped one-dimensional top hat laser beam profile laser scribing process and plasma etch process |
US9117868B1 (en) | 2014-08-12 | 2015-08-25 | Applied Materials, Inc. | Bipolar electrostatic chuck for dicing tape thermal management during plasma dicing |
US9196498B1 (en) | 2014-08-12 | 2015-11-24 | Applied Materials, Inc. | Stationary actively-cooled shadow ring for heat dissipation in plasma chamber |
US9281244B1 (en) | 2014-09-18 | 2016-03-08 | Applied Materials, Inc. | Hybrid wafer dicing approach using an adaptive optics-controlled laser scribing process and plasma etch process |
US11195756B2 (en) | 2014-09-19 | 2021-12-07 | Applied Materials, Inc. | Proximity contact cover ring for plasma dicing |
US9177861B1 (en) | 2014-09-19 | 2015-11-03 | Applied Materials, Inc. | Hybrid wafer dicing approach using laser scribing process based on an elliptical laser beam profile or a spatio-temporal controlled laser beam profile |
US9196536B1 (en) | 2014-09-25 | 2015-11-24 | Applied Materials, Inc. | Hybrid wafer dicing approach using a phase modulated laser beam profile laser scribing process and plasma etch process |
US9130056B1 (en) | 2014-10-03 | 2015-09-08 | Applied Materials, Inc. | Bi-layer wafer-level underfill mask for wafer dicing and approaches for performing wafer dicing |
US9245803B1 (en) | 2014-10-17 | 2016-01-26 | Applied Materials, Inc. | Hybrid wafer dicing approach using a bessel beam shaper laser scribing process and plasma etch process |
US10692765B2 (en) | 2014-11-07 | 2020-06-23 | Applied Materials, Inc. | Transfer arm for film frame substrate handling during plasma singulation of wafers |
US9355907B1 (en) | 2015-01-05 | 2016-05-31 | Applied Materials, Inc. | Hybrid wafer dicing approach using a line shaped laser beam profile laser scribing process and plasma etch process |
US9159624B1 (en) | 2015-01-05 | 2015-10-13 | Applied Materials, Inc. | Vacuum lamination of polymeric dry films for wafer dicing using hybrid laser scribing and plasma etch approach |
US9330977B1 (en) | 2015-01-05 | 2016-05-03 | Applied Materials, Inc. | Hybrid wafer dicing approach using a galvo scanner and linear stage hybrid motion laser scribing process and plasma etch process |
US9601375B2 (en) | 2015-04-27 | 2017-03-21 | Applied Materials, Inc. | UV-cure pre-treatment of carrier film for wafer dicing using hybrid laser scribing and plasma etch approach |
US9721839B2 (en) | 2015-06-12 | 2017-08-01 | Applied Materials, Inc. | Etch-resistant water soluble mask for hybrid wafer dicing using laser scribing and plasma etch |
US9478455B1 (en) | 2015-06-12 | 2016-10-25 | Applied Materials, Inc. | Thermal pyrolytic graphite shadow ring assembly for heat dissipation in plasma chamber |
EP3376526B1 (en) * | 2015-11-09 | 2022-06-22 | Furukawa Electric Co., Ltd. | Method for manufacturing semiconductor chip, and mask-integrated surface protection tape used therein |
US9972575B2 (en) | 2016-03-03 | 2018-05-15 | Applied Materials, Inc. | Hybrid wafer dicing approach using a split beam laser scribing process and plasma etch process |
US9852997B2 (en) | 2016-03-25 | 2017-12-26 | Applied Materials, Inc. | Hybrid wafer dicing approach using a rotating beam laser scribing process and plasma etch process |
US9793132B1 (en) | 2016-05-13 | 2017-10-17 | Applied Materials, Inc. | Etch mask for hybrid laser scribing and plasma etch wafer singulation process |
US11158540B2 (en) | 2017-05-26 | 2021-10-26 | Applied Materials, Inc. | Light-absorbing mask for hybrid laser scribing and plasma etch wafer singulation process |
US10363629B2 (en) | 2017-06-01 | 2019-07-30 | Applied Materials, Inc. | Mitigation of particle contamination for wafer dicing processes |
US10535561B2 (en) | 2018-03-12 | 2020-01-14 | Applied Materials, Inc. | Hybrid wafer dicing approach using a multiple pass laser scribing process and plasma etch process |
US11355394B2 (en) | 2018-09-13 | 2022-06-07 | Applied Materials, Inc. | Wafer dicing using hybrid laser scribing and plasma etch approach with intermediate breakthrough treatment |
US11011424B2 (en) | 2019-08-06 | 2021-05-18 | Applied Materials, Inc. | Hybrid wafer dicing approach using a spatially multi-focused laser beam laser scribing process and plasma etch process |
US11342226B2 (en) | 2019-08-13 | 2022-05-24 | Applied Materials, Inc. | Hybrid wafer dicing approach using an actively-focused laser beam laser scribing process and plasma etch process |
US10903121B1 (en) | 2019-08-14 | 2021-01-26 | Applied Materials, Inc. | Hybrid wafer dicing approach using a uniform rotating beam laser scribing process and plasma etch process |
US11600492B2 (en) | 2019-12-10 | 2023-03-07 | Applied Materials, Inc. | Electrostatic chuck with reduced current leakage for hybrid laser scribing and plasma etch wafer singulation process |
US11908784B2 (en) * | 2020-09-23 | 2024-02-20 | Nxp Usa, Inc. | Packaged semiconductor device assembly |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5117272A (en) * | 1989-04-19 | 1992-05-26 | Asahi Glass Company Ltd. | Having a protective film of a polymer having a fluorine-containing aliphatic cyclic structure |
US5661831A (en) * | 1994-12-22 | 1997-08-26 | Nec Corporation | Optical module having self-aligned optical element and optical wave-guide by means of bumps on rectangular pads and method of assembling thereof |
US6050832A (en) * | 1998-08-07 | 2000-04-18 | Fujitsu Limited | Chip and board stress relief interposer |
US6177729B1 (en) * | 1999-04-03 | 2001-01-23 | International Business Machines Corporation | Rolling ball connector |
US6583039B2 (en) * | 2001-10-15 | 2003-06-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a bump on a copper pad |
US6586322B1 (en) * | 2001-12-21 | 2003-07-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of making a bump on a substrate using multiple photoresist layers |
US6593220B1 (en) * | 2002-01-03 | 2003-07-15 | Taiwan Semiconductor Manufacturing Company | Elastomer plating mask sealed wafer level package method |
US6605524B1 (en) * | 2001-09-10 | 2003-08-12 | Taiwan Semiconductor Manufacturing Company | Bumping process to increase bump height and to create a more robust bump structure |
US6767411B2 (en) * | 2002-03-15 | 2004-07-27 | Delphi Technologies, Inc. | Lead-free solder alloy and solder reflow process |
US20060128135A1 (en) * | 2004-12-14 | 2006-06-15 | Taiwan Manufacturing Company, Ltd. | Solder bump composition for flip chip |
US20060131728A1 (en) * | 2004-12-16 | 2006-06-22 | Salmon Peter C | Repairable three-dimensional semiconductor subsystem |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6573610B1 (en) * | 2000-06-02 | 2003-06-03 | Siliconware Precision Industries Co., Ltd. | Substrate of semiconductor package for flip chip package |
US6599775B2 (en) * | 2001-05-18 | 2003-07-29 | Advanpack Solutions Pte Ltd | Method for forming a flip chip semiconductor package, a semiconductor package formed thereby, and a substrate therefor |
US7187476B2 (en) * | 2001-10-01 | 2007-03-06 | Canon Kabushiki Kaisha | Image processing apparatus and method, computer program, and recording medium |
JP2003303842A (en) * | 2002-04-12 | 2003-10-24 | Nec Electronics Corp | Semiconductor device and manufacturing method therefor |
-
2005
- 2005-03-17 US US11/082,298 patent/US7361990B2/en active Active
- 2005-11-04 TW TW094138745A patent/TWI267206B/en active
- 2005-12-02 CN CNB2005101277239A patent/CN100428459C/en active Active
-
2006
- 2006-01-23 JP JP2006013706A patent/JP2006261641A/en active Pending
-
2008
- 2008-02-25 US US12/036,928 patent/US20080142994A1/en not_active Abandoned
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5117272A (en) * | 1989-04-19 | 1992-05-26 | Asahi Glass Company Ltd. | Having a protective film of a polymer having a fluorine-containing aliphatic cyclic structure |
US5661831A (en) * | 1994-12-22 | 1997-08-26 | Nec Corporation | Optical module having self-aligned optical element and optical wave-guide by means of bumps on rectangular pads and method of assembling thereof |
US6050832A (en) * | 1998-08-07 | 2000-04-18 | Fujitsu Limited | Chip and board stress relief interposer |
US6177729B1 (en) * | 1999-04-03 | 2001-01-23 | International Business Machines Corporation | Rolling ball connector |
US6605524B1 (en) * | 2001-09-10 | 2003-08-12 | Taiwan Semiconductor Manufacturing Company | Bumping process to increase bump height and to create a more robust bump structure |
US6583039B2 (en) * | 2001-10-15 | 2003-06-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a bump on a copper pad |
US6586322B1 (en) * | 2001-12-21 | 2003-07-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of making a bump on a substrate using multiple photoresist layers |
US6593220B1 (en) * | 2002-01-03 | 2003-07-15 | Taiwan Semiconductor Manufacturing Company | Elastomer plating mask sealed wafer level package method |
US6767411B2 (en) * | 2002-03-15 | 2004-07-27 | Delphi Technologies, Inc. | Lead-free solder alloy and solder reflow process |
US20060128135A1 (en) * | 2004-12-14 | 2006-06-15 | Taiwan Manufacturing Company, Ltd. | Solder bump composition for flip chip |
US20060131728A1 (en) * | 2004-12-16 | 2006-06-22 | Salmon Peter C | Repairable three-dimensional semiconductor subsystem |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9607936B2 (en) | 2009-10-29 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper bump joint structures with improved crack resistance |
US20110101526A1 (en) * | 2009-10-29 | 2011-05-05 | Ching-Wen Hsiao | Copper Bump Joint Structures with Improved Crack Resistance |
US8847387B2 (en) * | 2009-10-29 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Robust joint structure for flip-chip bonding |
US20110101519A1 (en) * | 2009-10-29 | 2011-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Robust Joint Structure for Flip-Chip Bonding |
US9087882B2 (en) | 2011-06-03 | 2015-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical connection for chip scale packaging |
US9515038B2 (en) | 2011-06-03 | 2016-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical connection for chip scale packaging |
US20130087892A1 (en) * | 2011-10-07 | 2013-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd | Electrical Connection for Chip Scale Packaging |
US9548281B2 (en) * | 2011-10-07 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical connection for chip scale packaging |
US9997480B2 (en) | 2012-04-16 | 2018-06-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a semiconductor device including strain reduced structure |
US9806042B2 (en) | 2012-04-16 | 2017-10-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain reduced structure for IC packaging |
US10163839B2 (en) | 2012-07-31 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump on pad (BOP) bonding structure in semiconductor packaged device |
US9748188B2 (en) | 2012-07-31 | 2017-08-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a bump on pad (BOP) bonding structure in a semiconductor packaged device |
US9196573B2 (en) | 2012-07-31 | 2015-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump on pad (BOP) bonding structure |
US10515917B2 (en) | 2012-07-31 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump on pad (BOP) bonding structure in semiconductor packaged device |
US9673161B2 (en) | 2012-08-17 | 2017-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonded structures for package and substrate |
US9397059B2 (en) | 2012-08-17 | 2016-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonded structures for package and substrate |
US9123788B2 (en) | 2012-08-17 | 2015-09-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonded structures for package and substrate |
US10468366B2 (en) | 2012-08-17 | 2019-11-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonded structures for package and substrate |
US11088102B2 (en) | 2012-08-17 | 2021-08-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonded structures for package and substrate |
EP3940771A1 (en) * | 2020-07-15 | 2022-01-19 | Renesas Electronics Corporation | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US20060220244A1 (en) | 2006-10-05 |
US7361990B2 (en) | 2008-04-22 |
JP2006261641A (en) | 2006-09-28 |
TW200635056A (en) | 2006-10-01 |
CN1835218A (en) | 2006-09-20 |
CN100428459C (en) | 2008-10-22 |
TWI267206B (en) | 2006-11-21 |
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