US20080157350A1 - Package on package design to improve functionality and efficiency - Google Patents
Package on package design to improve functionality and efficiency Download PDFInfo
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- US20080157350A1 US20080157350A1 US11/648,143 US64814306A US2008157350A1 US 20080157350 A1 US20080157350 A1 US 20080157350A1 US 64814306 A US64814306 A US 64814306A US 2008157350 A1 US2008157350 A1 US 2008157350A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/20—Cooling means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Definitions
- the present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention generally relates to a package on package design.
- a computer system generally includes various components that may communicate with each other during operation of the computer system. Sometimes these components may be located on different dies. Hence, communication speed of these various dies may be paramount to the performance achieved by a computer system.
- dies may interlink via relatively long traces through a computer system motherboard and various substrate levels. Long vertical paths may minimize the extension of current motherboard system architecture, introduce signal propagation delay, and generation of additional heat.
- Some current computer systems aim to reduce the length of interlinks between various dies by stacked die technology and direct silicon via technology for direct die interlink. Utilization of direct silicon via technology for stacked dies may, however, require one die to carry the power source for another die. This approach creates thermal stress on the die that is responsible for carrying the power source.
- FIG. 1 illustrates a cross sectional view of a semiconductor device in accordance with an embodiment of the invention.
- FIG. 2 illustrates a top view of a semiconductor device according to an embodiment of the invention.
- FIG. 3 illustrates a block diagram of a method according to an embodiment.
- FIG. 4 illustrates a block diagram of a computing system, which may be utilized to implement various embodiments discussed herein.
- Coupled may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.
- Some of the embodiments discussed herein may utilize a package on package (PoP) design to provide efficient mechanisms for transferring data and/or power signals between a central processing unit (CPU) package and an embedded package (which may include a chipset, memory, etc.).
- PoP package on package
- a relatively shorter CPU linkage with chipset(s) and/or memory is provided to improve functionality and/or efficiency, e.g. by increasing communication speed between various packages.
- Some of the embodiments discussed herein may be provided in devices or computing systems that include multiple dies, such as those discussed with reference to FIGS. 1-4 .
- FIG. 1 illustrates a cross sectional view of a semiconductor device 100 in accordance with an embodiment of the invention.
- the device 100 may include a CPU package 102 and an embedded package 104 .
- the CPU package 102 may include one or more processor dies 106 .
- an integrated heat spreader (IHS) 110 may be provided to enhance dissipation of heat generated by the processor dies 106 and/or other components of the device 100 .
- the IHS 110 may be exposed to a fan (not shown) to extract heat away from components of the device 100 .
- One or more capacitors 111 may be provided on the CPU package substrate 108 .
- the embedded package 104 and all or a portion of the CPU package 102 may be mechanically coupled through a mold 112 .
- the embedded package 104 may include a flipped package 114 (which may include one or more chipset dies 116 mounted on a substrate 117 ), a bottom package 118 (which may include one or more memory dies 120 mounted on a substrate 121 ).
- the embedded package 104 may be coupled to a package substrate 122 .
- a mold 124 may be provided to mechanically couple the flipped package 114 and the bottom package 118 .
- at least some of the dies shown in FIG. 1 (such as dies 116 and/or 120 ) may include silicon vias 126 .
- one or more wire bonds 128 may electrically couple one or more pads 130 of the package substrate 122 to corresponding pads 132 of the flipped package 114 .
- the pads 132 on the flipped package 114 may be staggered, e.g., to provide a better fit, increase wire bond density, etc.
- the mold 124 may include one or more heat removal channels 134 to enhance heat removal from components of the device 100 such as components of the embedded package 104 , as will be further discussed herein, e.g., with reference to FIGS. 2-3 .
- various dies such as dies 106 , 116 , and/or 120
- under-fill may be provided along solder ball joints (such as shown in FIG. 1 ) to increase mechanical stability of the joints.
- one or more of the dies discussed herein may undergo wafer thinning process prior to assembly.
- the molds 112 and/or 124 may be constructed with material such as epoxy, epoxy with particles (such as silica particles), organic cylinders, plastic mold, plastic mold with particles/fiber, etc.
- vias 126 may be constructed with material such as aluminum, copper, silver, gold, combinations thereof, or other electrically conductive material.
- each of the dies 106 , 116 , and/or 120 may include circuitry corresponding to various components of a computing system, such as the components discussed with reference to FIG. 4 .
- FIG. 2 illustrates a top view of a semiconductor device 200 in accordance with an embodiment of the invention.
- the device 200 may include one or more dies 204 - 00 through 204 -NM (collectively referred to herein as “dies 204 ”).
- dies 204 may be the same or similar to the dies 106 , 116 , and/or 120 discussed with reference to FIG. 1 .
- the device 200 may include one or more heat removal channels 134 that may be interposed between one or more of the dies 204 , e.g., to enhance heat removal from components of the device 200 such as dies 204 .
- each of the dies 204 may include circuitry corresponding to various components of a computing system, such as the components discussed with reference to FIG. 4 .
- FIG. 3 illustrates a block diagram of an embodiment of a method 300 to provide a semiconductor device with a PoP design.
- various components discussed with reference to FIGS. 1-2 and 4 may be utilized to perform one or more of the operations discussed with reference to FIG. 3 .
- the method 300 may be used to provide the devices 100 and/or 200 , or one or more components of the system 400 of FIG. 4 .
- a first package (e.g., package 114 ) may be flipped.
- the interconnections of the first package and a second package e.g., package 118
- an embedded package e.g., package 104
- heat removal channel material such as one or more meshes of fiber (e.g., carbon fiber, organic cylinder, ceramic cylinder, metal cylinder, etc.) that surround one or more dies to dissipate heat generated by the dies
- the embedded package may be molded.
- the excessive/extended heat removal channel material of operation 306 may be removed, e.g., to create the heat removal channels 134 discussed with reference to FIGS. 1-2 .
- the channels 134 may carry liquid, liquid composite (such as liquid with particles/fiber) or gaseous media to enhance heat removal from components of the devices 100 and/or 200 .
- the molded embedded package (e.g., package 104 ) may be mounted to a package substrate (e.g., substrate 122 ).
- a CPU package (e.g., package 102 ) may be mounted to the embedded package (e.g., package 104 which may be molded at operation 308 and mounted on the package substrate 122 at operation 312 ).
- one or more wire bonds (e.g., wire bonds 128 ) may be added. In various operations, the order of operations 304 - 316 may be interchangeable.
- one or more portions of the CPU package such as its substrate (e.g., package substrate 108 ) may be molded to the embedded package (e.g., through the mold 112 ).
- the minimized vertical path in package and/or socket provided through the techniques discussed with reference to FIGS. 1-3 may allow for the extension of motherboard system architecture. Also, some of the embodiments may result in the floor space on the motherboard being optimized and/or improvement to I/ 0 density through silicon via, wire bonding, and/or controlled collapse chip connection (C 4 ) interconnections. Also, wire bond and C 4 interconnects may enable additional electrical connections to supply different voltage level for CPUs, Netcom processors (such as processors that process data communicated over a network such as the network 403 of FIG. 4 ), chipset(s), and/or memory. Further, additional interconnections may be provided between CPUs and external Netcom processors through wire bonds 128 .
- Embedded package 104 may provide direct communication between chipsets (e.g., dies 116 ) and memory (e.g., dies 120 ) or external board processors through silicon vias.
- chipsets e.g., dies 116
- memory e.g., dies 120
- CPUs, Netcom processors, chipsets, and/or memory may be integrated into a single package such as device 100 of FIG. 1 or device 200 of FIG. 2 .
- FIG. 4 illustrates a block diagram of a computing system 400 in accordance with an embodiment of the invention.
- the computing system 400 may include one or more central processing unit(s) (CPUs) 402 or processors that communicate via an interconnection network (or bus) 404 .
- the processors 402 may include a general purpose processor, a network processor (that processes data communicated over a computer network 403 ), or other types of a processor (including a reduced instruction set computer (RISC) processor or a complex instruction set computer (CISC)).
- RISC reduced instruction set computer
- CISC complex instruction set computer
- the processors 402 may have a single or multiple core design.
- the processors 402 with a multiple core design may integrate different types of processor cores on the same integrated circuit (IC) die.
- the processors 402 with a multiple core design may be implemented as symmetrical or asymmetrical multiprocessors.
- the operations discussed with reference to FIGS. 1-3 may be performed by one or more components of the system 400
- a chipset 406 may also communicate with the interconnection network 404 .
- the chipset 406 may include a memory control hub (MCH) 408 .
- the MCH 408 may include a memory controller 410 that communicates with a memory 412 .
- the memory 412 may store data, including sequences of instructions that are executed by the CPU 402 , or any other device included in the computing system 400 .
- the memory 412 may include one or more volatile storage (or memory) devices such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or other types of storage devices.
- RAM random access memory
- DRAM dynamic RAM
- SDRAM synchronous DRAM
- SRAM static RAM
- Nonvolatile memory may also be utilized such as a hard disk. Additional devices may communicate via the interconnection network 404 , such as multiple CPUs and/or multiple system memories.
- the MCH 408 may also include a graphics interface 414 that communicates with a display 416 .
- the graphics interface 414 may communicate with the display 416 via an accelerated graphics port (AGP).
- AGP accelerated graphics port
- the display 416 may be a flat panel display that communicates with the graphics interface 414 through, for example, a signal converter that translates a digital representation of an image stored in a storage device such as video memory or system memory into display signals that are interpreted and displayed by the display 416 .
- the display signals produced by the interface 414 may pass through various control devices before being interpreted by and subsequently displayed on the display 416 .
- a hub interface 418 may allow the MCH 408 and an input/output control hub (ICH) 420 to communicate.
- the ICH 420 may provide an interface to I/O devices that communicate with the computing system 400 .
- the ICH 420 may communicate with a bus 422 through a peripheral bridge (or controller) 424 , such as a peripheral component interconnect (PCI) bridge, a universal serial bus (USB) controller, or other types of peripheral bridges or controllers.
- the bridge 424 may provide a data path between the CPU 402 and peripheral devices. Other types of topologies may be utilized.
- multiple buses may communicate with the ICH 420 , e.g., through multiple bridges or controllers.
- peripherals in communication with the ICH 420 may include, in various embodiments of the invention, integrated drive electronics (IDE) or small computer system interface (SCSI) hard drive(s), USB port(s), a keyboard, a mouse, parallel port(s), serial port(s), floppy disk drive(s), digital output support (e.g., digital video interface (DVI)), or other devices.
- IDE integrated drive electronics
- SCSI small computer system interface
- the bus 422 may communicate with an audio device 426 , one or more disk drive(s) 428 , and a network interface device 430 (which is in communication with the computer network 403 ). Other devices may communicate via the bus 422 . Also, various components (such as the network interface device 430 ) may communicate with the MCH 408 in some embodiments of the invention. In addition, the processor 402 and the MCH 408 may be combined to form a single chip. Furthermore, the graphics accelerator 416 may be included within the MCH 408 in other embodiments of the invention.
- nonvolatile memory may include one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), a disk drive (e.g., 428 ), a floppy disk, a compact disk ROM (CD-ROM), a digital versatile disk (DVD), flash memory, a magneto-optical disk, or other types of nonvolatile machine-readable media that are capable of storing electronic data (e.g., including instructions).
- components of the system 400 may be arranged in a point-to-point (PtP) configuration.
- processors, memory, and/or input/output devices may be interconnected by a number of point-to-point interfaces.
- the operations discussed herein may be implemented as hardware (e.g., logic circuitry), software, firmware, or combinations thereof, which may be provided as a computer program product, e.g., including a machine-readable or computer-readable medium having stored thereon instructions (or software procedures) used to program a computer to perform a process discussed herein.
- the machine-readable medium may include a storage device such as those discussed with respect to FIGS. 1-4 .
- Such computer-readable media may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a bus, a modem, or a network connection).
- a remote computer e.g., a server
- a requesting computer e.g., a client
- a communication link e.g., a bus, a modem, or a network connection
Abstract
Description
- The present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention generally relates to a package on package design.
- A computer system generally includes various components that may communicate with each other during operation of the computer system. Sometimes these components may be located on different dies. Hence, communication speed of these various dies may be paramount to the performance achieved by a computer system.
- In some current computer systems, dies may interlink via relatively long traces through a computer system motherboard and various substrate levels. Long vertical paths may minimize the extension of current motherboard system architecture, introduce signal propagation delay, and generation of additional heat. Some current computer systems aim to reduce the length of interlinks between various dies by stacked die technology and direct silicon via technology for direct die interlink. Utilization of direct silicon via technology for stacked dies may, however, require one die to carry the power source for another die. This approach creates thermal stress on the die that is responsible for carrying the power source.
- The detailed description is provided with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items.
-
FIG. 1 illustrates a cross sectional view of a semiconductor device in accordance with an embodiment of the invention. -
FIG. 2 illustrates a top view of a semiconductor device according to an embodiment of the invention. -
FIG. 3 illustrates a block diagram of a method according to an embodiment. -
FIG. 4 illustrates a block diagram of a computing system, which may be utilized to implement various embodiments discussed herein. - In the following description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, various embodiments of the invention may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the particular embodiments of the invention. Further, various aspects of embodiments of the invention may be performed using various means, such as integrated semiconductor circuits (“hardware”), computer-readable instructions organized into one or more programs (“software”), or some combination of hardware and software. For the purposes of this disclosure reference to “logic” shall mean either hardware, software, or some combination thereof.
- Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment.
- Also, in the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. In some embodiments of the invention, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.
- Some of the embodiments discussed herein (such as the embodiments discussed with reference to
FIGS. 1-4 ) may utilize a package on package (PoP) design to provide efficient mechanisms for transferring data and/or power signals between a central processing unit (CPU) package and an embedded package (which may include a chipset, memory, etc.). In an embodiment, a relatively shorter CPU linkage with chipset(s) and/or memory (such as flash memory) is provided to improve functionality and/or efficiency, e.g. by increasing communication speed between various packages. Some of the embodiments discussed herein may be provided in devices or computing systems that include multiple dies, such as those discussed with reference toFIGS. 1-4 . - More particularly,
FIG. 1 illustrates a cross sectional view of asemiconductor device 100 in accordance with an embodiment of the invention. Thedevice 100 may include aCPU package 102 and an embeddedpackage 104. TheCPU package 102 may include one or more processor dies 106. In an embodiment, an integrated heat spreader (IHS) 110 may be provided to enhance dissipation of heat generated by the processor dies 106 and/or other components of thedevice 100. For example, the IHS 110 may be exposed to a fan (not shown) to extract heat away from components of thedevice 100. One ormore capacitors 111 may be provided on theCPU package substrate 108. - The embedded
package 104 and all or a portion of the CPU package 102 (such as the CPU package substrate 108) may be mechanically coupled through amold 112. The embeddedpackage 104 may include a flipped package 114 (which may include one or more chipset dies 116 mounted on a substrate 117), a bottom package 118 (which may include one or more memory dies 120 mounted on a substrate 121). As shown, the embeddedpackage 104 may be coupled to apackage substrate 122. In an embodiment, amold 124 may be provided to mechanically couple the flippedpackage 114 and thebottom package 118. Moreover, at least some of the dies shown inFIG. 1 (such as dies 116 and/or 120) may includesilicon vias 126. Also, one ormore wire bonds 128 may electrically couple one ormore pads 130 of thepackage substrate 122 tocorresponding pads 132 of the flippedpackage 114. As shown inFIG. 1 , in accordance with an embodiment, thepads 132 on the flippedpackage 114 may be staggered, e.g., to provide a better fit, increase wire bond density, etc. - In an embodiment, the
mold 124 may include one or moreheat removal channels 134 to enhance heat removal from components of thedevice 100 such as components of the embeddedpackage 104, as will be further discussed herein, e.g., with reference toFIGS. 2-3 . Furthermore, various dies (such as dies 106, 116, and/or 120) may be coupled through one or more solder balls or combination of pins and sockets. In some embodiments, under-fill may be provided along solder ball joints (such as shown inFIG. 1 ) to increase mechanical stability of the joints. In an embodiment, one or more of the dies discussed herein may undergo wafer thinning process prior to assembly. In some embodiments, themolds 112 and/or 124 may be constructed with material such as epoxy, epoxy with particles (such as silica particles), organic cylinders, plastic mold, plastic mold with particles/fiber, etc. - In an embodiment,
vias 126 may be constructed with material such as aluminum, copper, silver, gold, combinations thereof, or other electrically conductive material. Moreover, each of thedies FIG. 4 . -
FIG. 2 illustrates a top view of asemiconductor device 200 in accordance with an embodiment of the invention. As shown inFIG. 2 , thedevice 200 may include one or more dies 204-00 through 204-NM (collectively referred to herein as “dies 204”). In an embodiment, dies 204 may be the same or similar to thedies FIG. 1 . Thedevice 200 may include one or moreheat removal channels 134 that may be interposed between one or more of thedies 204, e.g., to enhance heat removal from components of thedevice 200 such as dies 204. Moreover, each of thedies 204 may include circuitry corresponding to various components of a computing system, such as the components discussed with reference toFIG. 4 . -
FIG. 3 illustrates a block diagram of an embodiment of amethod 300 to provide a semiconductor device with a PoP design. In an embodiment, various components discussed with reference toFIGS. 1-2 and 4 may be utilized to perform one or more of the operations discussed with reference toFIG. 3 . For example, themethod 300 may be used to provide thedevices 100 and/or 200, or one or more components of thesystem 400 ofFIG. 4 . - Referring to
FIGS. 1-3 , at anoperation 302, a first package (e.g., package 114) may be flipped. At anoperation 304, the interconnections of the first package and a second package (e.g., package 118) may be coupled to form an embedded package (e.g., package 104). At anoperation 306, heat removal channel material (such as one or more meshes of fiber (e.g., carbon fiber, organic cylinder, ceramic cylinder, metal cylinder, etc.) that surround one or more dies to dissipate heat generated by the dies) may be provided in the embedded package. At anoperation 308, the embedded package may be molded. At an operation 310, the excessive/extended heat removal channel material ofoperation 306 may be removed, e.g., to create theheat removal channels 134 discussed with reference toFIGS. 1-2 . In an embodiment, thechannels 134 may carry liquid, liquid composite (such as liquid with particles/fiber) or gaseous media to enhance heat removal from components of thedevices 100 and/or 200. - At an
operation 312, the molded embedded package (e.g., package 104) may be mounted to a package substrate (e.g., substrate 122). At anoperation 314, a CPU package (e.g., package 102) may be mounted to the embedded package (e.g.,package 104 which may be molded atoperation 308 and mounted on thepackage substrate 122 at operation 312). At anoperation 316, one or more wire bonds (e.g., wire bonds 128) may be added. In various operations, the order of operations 304-316 may be interchangeable. At anoperation 318, one or more portions of the CPU package such as its substrate (e.g., package substrate 108) may be molded to the embedded package (e.g., through the mold 112). - In some embodiments, the minimized vertical path in package and/or socket provided through the techniques discussed with reference to
FIGS. 1-3 may allow for the extension of motherboard system architecture. Also, some of the embodiments may result in the floor space on the motherboard being optimized and/or improvement to I/0 density through silicon via, wire bonding, and/or controlled collapse chip connection (C4) interconnections. Also, wire bond and C4 interconnects may enable additional electrical connections to supply different voltage level for CPUs, Netcom processors (such as processors that process data communicated over a network such as thenetwork 403 ofFIG. 4 ), chipset(s), and/or memory. Further, additional interconnections may be provided between CPUs and external Netcom processors throughwire bonds 128. Embeddedpackage 104 may provide direct communication between chipsets (e.g., dies 116) and memory (e.g., dies 120) or external board processors through silicon vias. Hence, in an embodiment, CPUs, Netcom processors, chipsets, and/or memory may be integrated into a single package such asdevice 100 ofFIG. 1 ordevice 200 ofFIG. 2 . -
FIG. 4 illustrates a block diagram of acomputing system 400 in accordance with an embodiment of the invention. Thecomputing system 400 may include one or more central processing unit(s) (CPUs) 402 or processors that communicate via an interconnection network (or bus) 404. Theprocessors 402 may include a general purpose processor, a network processor (that processes data communicated over a computer network 403), or other types of a processor (including a reduced instruction set computer (RISC) processor or a complex instruction set computer (CISC)). Moreover, theprocessors 402 may have a single or multiple core design. Theprocessors 402 with a multiple core design may integrate different types of processor cores on the same integrated circuit (IC) die. Also, theprocessors 402 with a multiple core design may be implemented as symmetrical or asymmetrical multiprocessors. Moreover, the operations discussed with reference toFIGS. 1-3 may be performed by one or more components of thesystem 400. - A
chipset 406 may also communicate with theinterconnection network 404. Thechipset 406 may include a memory control hub (MCH) 408. TheMCH 408 may include amemory controller 410 that communicates with amemory 412. Thememory 412 may store data, including sequences of instructions that are executed by theCPU 402, or any other device included in thecomputing system 400. In one embodiment of the invention, thememory 412 may include one or more volatile storage (or memory) devices such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or other types of storage devices. Nonvolatile memory may also be utilized such as a hard disk. Additional devices may communicate via theinterconnection network 404, such as multiple CPUs and/or multiple system memories. - The
MCH 408 may also include agraphics interface 414 that communicates with adisplay 416. In one embodiment of the invention, thegraphics interface 414 may communicate with thedisplay 416 via an accelerated graphics port (AGP). In an embodiment of the invention, thedisplay 416 may be a flat panel display that communicates with the graphics interface 414 through, for example, a signal converter that translates a digital representation of an image stored in a storage device such as video memory or system memory into display signals that are interpreted and displayed by thedisplay 416. The display signals produced by theinterface 414 may pass through various control devices before being interpreted by and subsequently displayed on thedisplay 416. - A
hub interface 418 may allow theMCH 408 and an input/output control hub (ICH) 420 to communicate. TheICH 420 may provide an interface to I/O devices that communicate with thecomputing system 400. TheICH 420 may communicate with abus 422 through a peripheral bridge (or controller) 424, such as a peripheral component interconnect (PCI) bridge, a universal serial bus (USB) controller, or other types of peripheral bridges or controllers. Thebridge 424 may provide a data path between theCPU 402 and peripheral devices. Other types of topologies may be utilized. Also, multiple buses may communicate with theICH 420, e.g., through multiple bridges or controllers. Moreover, other peripherals in communication with theICH 420 may include, in various embodiments of the invention, integrated drive electronics (IDE) or small computer system interface (SCSI) hard drive(s), USB port(s), a keyboard, a mouse, parallel port(s), serial port(s), floppy disk drive(s), digital output support (e.g., digital video interface (DVI)), or other devices. - The
bus 422 may communicate with anaudio device 426, one or more disk drive(s) 428, and a network interface device 430 (which is in communication with the computer network 403). Other devices may communicate via thebus 422. Also, various components (such as the network interface device 430) may communicate with theMCH 408 in some embodiments of the invention. In addition, theprocessor 402 and theMCH 408 may be combined to form a single chip. Furthermore, thegraphics accelerator 416 may be included within theMCH 408 in other embodiments of the invention. - Furthermore, the
computing system 400 may include volatile and/or nonvolatile memory (or storage). For example, nonvolatile memory may include one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), a disk drive (e.g., 428), a floppy disk, a compact disk ROM (CD-ROM), a digital versatile disk (DVD), flash memory, a magneto-optical disk, or other types of nonvolatile machine-readable media that are capable of storing electronic data (e.g., including instructions). In an embodiment, components of thesystem 400 may be arranged in a point-to-point (PtP) configuration. For example, processors, memory, and/or input/output devices may be interconnected by a number of point-to-point interfaces. - In various embodiments of the invention, the operations discussed herein, e.g., with reference to
FIGS. 1-4 , may be implemented as hardware (e.g., logic circuitry), software, firmware, or combinations thereof, which may be provided as a computer program product, e.g., including a machine-readable or computer-readable medium having stored thereon instructions (or software procedures) used to program a computer to perform a process discussed herein. The machine-readable medium may include a storage device such as those discussed with respect toFIGS. 1-4 . - Additionally, such computer-readable media may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a bus, a modem, or a network connection). Accordingly, herein, a carrier wave shall be regarded as comprising a machine-readable medium.
- Thus, although embodiments of the invention have been described in language specific to structural features and/or methodological acts, it is to be understood that claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.
Claims (15)
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