US20080173957A1 - Method of forming a semiconductor device having a symmetric dielectric regions and structure thereof - Google Patents
Method of forming a semiconductor device having a symmetric dielectric regions and structure thereof Download PDFInfo
- Publication number
- US20080173957A1 US20080173957A1 US11/848,612 US84861207A US2008173957A1 US 20080173957 A1 US20080173957 A1 US 20080173957A1 US 84861207 A US84861207 A US 84861207A US 2008173957 A1 US2008173957 A1 US 2008173957A1
- Authority
- US
- United States
- Prior art keywords
- gate electrode
- dielectric
- area
- oxidation
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 230000003647 oxidation Effects 0.000 claims description 77
- 238000007254 oxidation reaction Methods 0.000 claims description 77
- 230000002708 enhancing effect Effects 0.000 claims description 31
- 230000033116 oxidation-reduction process Effects 0.000 claims description 20
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 241000894007 species Species 0.000 description 55
- 239000000463 material Substances 0.000 description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000002513 implantation Methods 0.000 description 8
- 230000008901 benefit Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 239000007943 implant Substances 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 241000293849 Cordylanthus Species 0.000 description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 210000003323 beak Anatomy 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/981—Utilizing varying dielectric thickness
Abstract
Description
- This invention relates generally to semiconductor devices, and more specifically, to semiconductor devices having asymmetric dielectric regions.
- Semiconductor devices, such as MOSFETs (metal oxide semiconductor field effect transistors), may have asymmetrically doped source and drain regions to increase drive currents and reduce parities. In the prior art, the asymmetrical source and drain doped regions may have different dopants or different numbers of implanted regions. In addition, to form the different dopant regions, spacers on either side of a gate electrode may be different shapes or sizes. While these prior art techniques allow for increased drive current, to form these asymmetrically doped semiconductor devices additional process steps are used that undesirably increase cycle time. Therefore, a need exists for obtaining the advantages of asymmetrically doped source and drain regions without dramatically increasing cycle time.
- The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements.
-
FIGS. 1 illustrates a cross-sectional view of a portion of a workpiece while implanting an oxidation enhancing species in accordance with an embodiment of the present invention; -
FIG. 2 illustrates the workpiece ofFIG. 1 after implanting the oxidation enhancing species in accordance with an embodiment of the present invention; -
FIG. 3 illustrates the workpiece ofFIG. 2 after forming a dielectric layer in accordance with an embodiment of the present invention; -
FIG. 4 illustrates the workpiece ofFIG. 3 after additional processing to form a semiconductor device in accordance with an embodiment of the present invention; -
FIG. 5 illustrates the workpiece ofFIG. 2 while implanting an oxidation reduction species in accordance with an embodiment of the present invention; and -
FIG. 6 . illustrates the workpiece ofFIG. 5 after implanting the oxidation reduction species in accordance with an embodiment of the present invention. - Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
-
FIG. 1 illustrates a cross-sectional view of a portion of aworkpiece 10 having asemiconductor substrate 12, a firstdielectric layer 14, agate electrode 16, asource region 18, and adrain region 20, while an implantation is being performed. Theworkpiece 10 is a portion of a semiconductor wafer and will undergo various processing to form a semiconductor device. Thesemiconductor substrate 12 can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI) (e.g., fully depleted SOI (FDSOI)), silicon, monocrystalline silicon, the like, and combinations of the above. The firstdielectric layer 14 may be silicon dioxide, a high dielectric constant (hi-k) dielectric (such as hafnium oxide or zirconium oxide), the like, or a combination the above. In one embodiment, the firstdielectric layer 14 is hafnium oxide with an underlying layer of silicon dioxide, which may be a native silicon dioxide. Although as shown inFIG. 1 the firstdielectric layer 14 is not patterned, it may be patterned. For example, portions of the firstdielectric layer 14 that are not under thegate electrode 16 may be removed while patterning a gate electrode layer to form thegate electrode 16. Thegate electrode 16 may be any suitable material, such as polysilicon (which subsequently may be doped), a metal gate, the like, or combinations of the above. The firstdielectric layer 14 and thegate electrode 16 are formed by any suitable processes such as thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), the like, and combinations of the above. A skilled artisan should recognize that thesource region 18 and thedrain region 20 may be switched so that thesource region 18 is to the right of thegate electrode 16 and thedrain region 20 is to the left of thegate electrode 16. In one embodiment, at this point in the processing there has been no doping to form source and drain regions in thesource region 18 or thedrain region 20. In other words, no extensions or halo implants have occurred. - The
workpiece 10 inFIG. 1 is being implanted with anoxidation enhancing species 22. As will be better understood after further explanation, theoxidation enhancing species 22 is being implanted into portions of thesemiconductor substrate 12 and thegate electrode 16 so that oxidation growth will be increased in these regions. Although not shown, a mask, such as a photoresist, may be formed over the workpiece 10 (and over the semiconductor substrate 12) and be patterned to expose the areas where theoxidation enhancing species 22 are to be located within theworkpiece 10. If a mask is used, the implantation may occur perpendicular to theworkpiece 10 or at a tilt so that the angle between thesemiconductor substrate 12 and the implantation is less than ninety degrees. If a mask is not used or if the mask is patterned to expose both thesource region 18 and thedrain region 20, a tilt is preferred so that ashadow region 24 can be formed in one of the regions, which in a preferred embodiment is thesource region 18. Theshadow region 24 is a region where none of theoxidation enhancing species 22 will travel so that areas around theshadow region 24 will not be implanted with theoxidation enhancing species 22. In the embodiment illustrated inFIG. 1 , theshadow region 24 preventsoxidation enhancing species 22 from being implanted into portions of the firstdielectric layer 14, thegate electrode 16, and thesemiconductor substrate 12, as will be better understood after discussingFIG. 2 . In one embodiment, the tilt is approximately 5 to 30 degrees. However, the most desirable tilt will depend on the height and density of thegate electrode 16. The taller and more dense thegate electrode 16, it is desirable to use a lower tilt angle. - The
oxidation enhancing species 22 may be oxygen, germanium, fluorine, chlorine, the like or combinations of the above. The energy used is desirably low enough so that theoxidation enhancing species 22 reaches the desired depth in thesemiconductor substrate 12 and thegate electrode 16. In one embodiment, the desired depth is approximately 5 to 10 nm. In one embodiment, the energy is between approximately 2 and 8 keV. The actual energy chosen depends on the desired depth, which can vary based on the dimensions of the features, other processing that may occur, and the species used. Furthermore, any dose can be used. In one embodiment, a dose of 1e15/cm2 is used. In a preferred embodiment, germanium is used as theoxidation enhancing species 22 at a 5 keV and a dosage of 1E15/cm2. In one embodiment, it is desirable to use fluorine for an N-type semiconductor device and germanium for a P-type semiconductor device. -
FIG. 2 shows the resulting implanted oxidation enhancedregions 26 after performing an implantation of anoxidation enhancing species 22 at a tilt, in accordance with the embodiment illustrated inFIG. 1 . The oxidation enhancedregions 26 are present in thedrain region 20, the top surface of thegate electrode 16, and a first side of thegate electrode 16. The oxidation enhancedregions 26 are also present in a first portion of thesource region 18 and a first portion of a second side of thegate electrode 16. The absence of the oxidation enhancedregion 26 in a second portion of thesource region 18 and a second portion of the second side of thegate electrode 16 is due to the shadow region. Thus, the area that is under and adjacent the second side of the gate electrode and a portion of the area of the gate electrode that is adjacent the second side of the gate electrode do not include the oxidation enhancedregion 26. In contrast, the portion of the area under and adjacent the first side of the gate electrode and a portion of the area of the gate electrode that is adjacent the first side of the gate electrode does include the oxidation enhancedregion 26. - As shown in
FIG. 3 , After forming the oxidation enhancedregion 26, portions of thesemiconductor substrate 12, and optionally portions of thegate electrode 16, are converted to a seconddielectric layer 40. Portions of thegate electrode 16 may not be converted if the material chosen for thegate electrode 16 does not oxidize when exposed to the environment used to oxidize portions of thesemiconductor substrate 12. Hence, the resulting dielectric material depends on the material used for thegate electrode 16 and thesemiconductor substrate 12. In an embodiment, where thegate electrode 16 and thesemiconductor substrate 12 include silicon, the seconddielectric layer 40 is silicon dioxide. The seconddielectric layer 40 may or may not be the same material used for the firstdielectric layer 14. - In one embodiment, the conversion occurs by annealing the
workpiece 10. For example, the conversion can occur by thermal oxidation in a dry oxygen environment at a temperature between approximately 700 and 1,000 degrees Celsius. An ambient of nitrogen and possibly oxygen may be used. The time for the thermal oxidation will vary based on the temperature used. For example, the duration of the thermal oxidation may be between 10 minutes to 2 hours. However, if the temperature of the thermal oxidation is approximately 1,000 degrees Celsius the duration of the thermal oxidation can be short, such as 10 minutes. As the temperature decreases, the duration will increase. However, thesecond dielectric layer 40 can be formed by any suitable method, such as other oxidation processes besides thermal oxidation. - As illustrated in
FIG. 3 the portions of thesecond dielectric layer 40 that are formed in the oxidation enhancedregion 26 of thegate electrode 16 and thesemiconductor substrate 12 have a thickness greater than that of the rest of thesecond dielectric layer 40. If portions of thegate electrode 16 are converted to thesecond dielectric layer 40, the thickness of thesecond dielectric layer 40 on the second side of thegate electrode 16 is thinner than that of thesecond dielectric layer 40 on the first side of thegate electrode 16 due to the presence of theoxidation enhancement region 26 on the first side of thegate electrode 16 and the lack of theoxidation enhancement region 26 in areas adjacent the second side of thegate electrode 16. - Due to the oxidation enhanced
regions 26,region 46 in thesource region 18 is thicker thanregion 48 in thedrain region 20. At the intersection of thegate electrode 16, thefirst dielectric layer 14, and thesemiconductor substrate 12 that is adjacent the first side of thegate electrode 16 is afirst dielectric area 44. At the intersection of thegate electrode 16, thefirst dielectric layer 14, and thesemiconductor substrate 12 that is adjacent the second side of thegate electrode 16 is asecond dielectric area 42. Thefirst dielectric area 44 and thesecond dielectric area 42 both form bird's beaks, which is a name given to dielectric areas that have a bird beak shape, such as the bird's beaks that are created during LOCOS (local oxidation) processing to form isolation regions. Due to the absence of theoxidation enhancement region 26 in and near thesecond dielectric area 42, thesecond dielectric area 42 is smaller than thefirst dielectric area 44. In one embodiment, the thickness of thesecond dielectric area 42 is approximately ½ that of thefirst dielectric area 44. In one embodiment, the thickness of thesecond dielectric area 42 is approximately 2 nm and the thickness of thefirst dielectric area 44 is approximately 4 nm. As shown inFIG. 3 , a third dielectric area lies between thefirst dielectric area 44 and thesecond dielectric area 42. The third dielectric area is thinner than both thefirst dielectric area 44 and thesecond dielectric area 42 because it was not substantially oxidized during the conversion processing. The third dielectric area is a portion of thefirst dielectric layer 14. Thus, the gate dielectric, which is the dielectric under thegate electrode 16, includes thefirst dielectric area 44, thesecond dielectric area 42, and a portion of thefirst dielectric layer 14. Thus, the gate dielectric is a dielectric with asymmetric bird beak's or dielectric regions, where the dielectric region at one end is thicker than the dielectric region at the other end. Thefirst dielectric layer 14 may be the same material as thesecond dielectric layer 40. Alternatively, different materials may be used. In one embodiment, the gate dielectric is made of two dielectrics where the ends are the same material and the area between the ends is a different material; in addition, the ends are asymmetric dielectric regions, where the dielectric region at one end is thicker than the dielectric region at the other end. - The presence of the
first dielectric area 44 and thesecond dielectric area 42 as part of the gate dielectric reduces delay and reduced capacitance in the semiconductor device without degradation in current. As the width of thefirst dielectric area 44 and thesecond dielectric area 42 increase, the drive current degrades. Since the thickness of thefirst dielectric area 44 is greater than that of thefirst dielectric layer 14 that forms the gate dielectric, the inversion layer that is formed during the functioning of the semiconductor device is pinched-off near the drain the saturation region making the saturation drain current insensitive to gate-drain overlap. The gate-drain overlap capacitance improves when the thickness of thefirst dielectric area 44 increases. The maximum steep improvement that may be able to be obtained is approximately 3.4%. - The
first dielectric area 44 and thesecond dielectric area 42 may be entirely under the gate electrode or thegate electrode 16 and thesecond dielectric layer 40 surrounding thegate electrode 16, but some of these areas may extend outside the areas covered by thegate electrode 16 and thesecond dielectric layer 40. Regardless, at least part of thefirst dielectric area 44 and thesecond dielectric area 42 will be under thegate electrode 16. - After forming the
second dielectric layer 40, conventional processing is continued to form a semiconductor device, as shown inFIG. 4 . First, asource extension 50 and adrain extension 52 are formed in thesource region 18 and thedrain region 20, respectively. After forming thesource extension 50 and thedrain extension 52, a third dielectric layer, such as silicon nitride, is formed, for example by CVD, and patterned to formspacers 54. Next, adeep source region 56 is formed in thesource region 18 and adeep drain region 58 is formed in thedrain region 20. Portions of thesecond dielectric layer 40 may be removed to form thefourth dielectric 49 and thefifth dielectric 43 either when thespacers 54 are formed or after forming thedeep source region 56 and thedeep drain region 58. Thefourth dielectric 49 is thinner than thefifth dielectric 43 because more oxidation enhancing species was present in the area that was converted into thefifth dielectric 43 than in the area that was converted into thefourth dielectric 49. - Next,
silicide 60 is formed over thedeep source region 56 and thedeep drain region 58. In addition, if thegate electrode 16 includes silicon, silicide may be formed over thegate electrode 16. Next, an interleveldielectric layer 64 is formed over theworkpiece 10 and patterned to form openings, which are later filled with conductive material(s) to formcontacts 62. In the cross-section shown inFIG. 4 , thecontacts 62 are formed in thesource region 18 and thedrain region 20. In addition, a contact (not shown) is formed and coupled to thegate electrode 16. - In the embodiment illustrated in
FIGS. 1-4 , an oxidation enhancing species was implanted. Alternatively, an oxidation reduction species is implanted. In another embodiment, the oxidation reduction species may be implanted in addition to the oxidation enhancing species, as illustrated inFIGS. 5 and 6 . In other words, co-implantation of an oxidation enhancing species and an oxidation reduction species is performed in one embodiment. - As shown in
FIG. 5 anoxidation reduction species 28, such as nitrogen, is implanted into theworkpiece 10 after formingoxidation enhancement region 26. Theoxidation reduction species 28 is implanted into portions of thesemiconductor substrate 12 and thegate electrode 16 so that oxidation growth will be inhibited in these regions. Although not shown, a mask, such as photoresist, may be formed over the workpiece 10 (and over the semiconductor substrate 12) and be patterned to expose the areas where theoxidation reduction species 28 are to be implanted. If a mask is used, the implantation may occur perpendicular to theworkpiece 10 or at a tilt so that the angle between thesemiconductor substrate 12 and the implantation is less than ninety degrees. If a mask is not used or if the mask is patterned to expose both thesource region 18 and thedrain region 20, a tilt is preferred so that ashadow region 30 can be formed in one of the regions, which in a preferred embodiment is thedrain region 20. Theshadow region 30 is similar to theshadow region 24 ofFIG. 1 , because it is a region where none of theoxidation reduction species 28 will travel so that areas around theshadow region 30 will not be implanted with theoxidation reduction species 28. In the embodiment illustrated inFIG. 5 theshadow region 30 preventsoxidation reduction species 28 from being implanted into portions of thefirst dielectric layer 14, thegate electrode 16, and thesemiconductor substrate 12, as will be better understood after discussingFIG. 6 . In one embodiment, the tilt is approximately 5 to 30 degrees. However, the most desirable tilt will depend on the height and density of thegate electrode 16. The taller and more dense thegate electrode 16, it is desirable to use a lower tilt angle. - In one embodiment, the
oxidation reduction species 28 is nitrogen. The energy used is desirably low enough so that theoxidation reduction species 28 reaches the desired depth in thesemiconductor substrate 12 and thegate electrode 16. In one embodiment, the desired depth is between approximately 5 and 10 nm. In one embodiment, the energy is between approximately 1 and 3 keV. The energy chosen depends on the desired thickness, which can vary based on the dimensions of the features, other processing that may occur, and the species used. Furthermore, any dose can be used. In one embodiment, a dose of 1E15/cm2 is used. -
FIG. 6 shows the resulting implantedoxidation enhancement regions 26,oxidation reducing regions 32, and the combinedregions 34 that include both the oxidation reducing and enhancing species after performing an implantation of anoxidation reduction species 28 and theoxidation enhancing species 22 at a tilt. The oxidation enhancedregions 26 are present in the areas that were exposed to the oxidation enhancing species and were near theshadow region 30. The oxidation enhancedregions 26 are near the first side of thegate electrode 16. Theoxidation reducing regions 32 are area that were exposed to the oxidation reducing species and were near theshadow region 24. The oxidation reducing regions are near the first side of thegate electrode 16. The combinedregions 34 are in thedrain region 20 at a distance separated from the are underlying thegate electrode 16, in thesource region 18 at a distance separated from the are underlying thegate electrode 16, and in the top most area of thegate electrode 16. - After forming the
oxidation reducing regions 32, portions of thesemiconductor substrate 12, and optionally portions of thegate electrode 16, are converted to dielectric layer, using any process discussed in regards withFIG. 3 . Theoxidation reducing regions 32 will inhibit the growth of a dielectric and the oxidation enhancedregion 26 will increase dielectric growth. The effect of the combinedregions 34 on oxide growth will depend on the relative amounts of the oxidation reducing species and the oxidation enhancing species. The combinedregions 34 may inhibit or increase dielectric growth. Instead, the effect of the oxidation reducing species and the oxidation enhancing species may cancel each other and therefore, the combinedregions 34 will behave the same as the material would without any of oxidation reducing species and the oxidation enhancing species. Hence, the presence of the combinedregions 34 may not affect the dielectric growth. After forming the dielectric layer, additional processing discussed with respect toFIG. 4 is performed. - In one embodiment, method for forming a semiconductor device includes forming a semiconductor substrate, forming a gate electrode over the semiconductor substrate having a first side and a second side, forming a gate dielectric under the gate electrode, wherein the gate dielectric has a first area under the gate electrode and adjacent the first side of the gate electrode, a second area under the gate electrode and adjacent the second side of the gate electrode, and a third area under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area. In one embodiment, forming the gate dielectric under the gate electrode further includes forming a first dielectric layer, implanting an oxidation enhancing species into the semiconductor substrate to form oxidation enhancement regions, and oxidizing the oxidation enhancement regions; in one embodiment, implanting the oxidation enhancing species further includes implanting the oxidation enhancing species into the gate electrode to form oxidation enhancement regions; and in one embodiment, the implanting is performed at a tilt. In one embodiment, forming the gate dielectric under the gate electrode further includes forming a first dielectric layer, implanting an oxidation reduction species into the semiconductor substrate to form oxidation reducing regions, and oxidizing the semiconductor substrate. In one embodiment, implanting the oxidation enhancing species further includes implanting the oxidation reduction species into the gate electrode to form oxidation reducing regions, and in one embodiment, implanting is performed at a tilt. In one embodiment, forming the gate dielectric under the gate electrode further includes forming a first dielectric layer, implanting an oxidation enhancing species into the semiconductor substrate to form oxidation enhancement regions, implanting an oxidation reduction species into the semiconductor substrate to form oxidation reducing regions, and oxidizing the semiconductor substrate, wherein oxidizing includes forming a dielectric in the oxidation enhancement regions. In one embodiment, the method also includes forming a source extension region and a drain extension region after the forming the gate dielectric, wherein the source extension region is deeper than the drain extension region. In one embodiment, the method also includes forming a first spacer adjacent the first side of the gate electrode and a second spacer adjacent the second side of the gate electrode after the forming the gate dielectric
- In one embodiment, a method for forming a semiconductor device includes providing semiconductor substrate, forming a dielectric layer over the semiconductor substrate, forming a gate electrode over the dielectric layer, wherein the gate electrode has a first side and a second side opposite the first side, implanting an oxidation enhancing species into the first side of the gate electrode and a first area of the semiconductor substrate, wherein the first area is under the gate electrode and adjacent the first side of the gate electrode, converting the first area to a first dielectric and a second area of the semiconductor substrate, wherein the second area is under the gate electrode and adjacent the second side of the gate electrode, to a second dielectric, wherein the thickness of the first dielectric is greater than the thickness of the second dielectric. In one embodiment, converting includes annealing the semiconductor substrate. In one embodiment, implanting includes implanting at least a species selected from the group consisting of germanium, oxygen, fluorine, and chlorine. In one embodiment, the method also includes implanting an oxidation reduction species into the second area. In one embodiment, the implanting the oxidation reduction species includes implanting nitrogen. In one embodiment, the method also includes forming a source extension region and a drain extension region after the converting, the first area and the second area, wherein the source extension region is deeper than the drain extension region. In one embodiment, the method also includes forming a first spacer adjacent the first side of the gate electrode and a second spacer adjacent the second side of the gate electrode after the converting. In one embodiment, implanting is performed at a tilt.
- In one embodiment, semiconductor device includes a semiconductor substrate, a gate electrode over the semiconductor substrate having a first side and a second side, and a gate dielectric under the gate electrode, wherein the gate dielectric has a first area under the gate electrode and adjacent the first side of the gate electrode, a second area under the gate electrode and adjacent the second side of the gate electrode, and a third area under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third are is thinner than the first area and is thinner than the second area. In one embodiment, the first side of the gate electrode includes a first dielectric and second side includes a second dielectric, wherein the second dielectric is thicker than the first dielectric. In one embodiment, the first area is at least approximately 2 times the thickness of the second area. In one embodiment, the semiconductor device also includes extension regions wherein region under first area is deeper than region under the second area. In one embodiment, the first area is the source region and the second area is the drain region. In one embodiment, the first area is the drain region and the second area is the source region.
- By now it should be appreciated that there has been provided a structure in which a bird's beak dielectric is formed thicker on one side of a gate dielectric, such as the drain side of a semiconductor device. Alternatively, the thicker dielectric can be on the source side. In addition, a method to make such as structure is taught by performing an oxidation enhancing implant, an oxidation reducing implant, or both. In one embodiment, angled implants that allow shadow on one side and oxidation enhancing or reducing species on the other are used. This method is cost effective to implement since a maskless implant procedure or a process using only one additional mask is used. The resulting structure offers enhanced performance, such as reduced delay and reduced capacitance (both Cgd and Miller capacitance) without degradation in current. In addition, having a thick oxide at the point of the highest field (e.g., the drain region next to the gate electrode) will reduce leakage and improve reliability.
- In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, a different semiconductor device than that shown in the figures may be used. For example, the semiconductor device can be a FinFET or a nonvolatile memory (NVM) device.
- Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention.
- Moreover, the terms “front”, “back”, “top”, “bottom”, “over”, “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
- Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms “a” or “an”, as used herein, are defined as one or more than one.
Claims (11)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/848,612 US20080173957A1 (en) | 2005-03-29 | 2007-08-31 | Method of forming a semiconductor device having a symmetric dielectric regions and structure thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/092,289 US7282426B2 (en) | 2005-03-29 | 2005-03-29 | Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof |
US11/848,612 US20080173957A1 (en) | 2005-03-29 | 2007-08-31 | Method of forming a semiconductor device having a symmetric dielectric regions and structure thereof |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/092,289 Division US7282426B2 (en) | 2005-03-29 | 2005-03-29 | Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080173957A1 true US20080173957A1 (en) | 2008-07-24 |
Family
ID=37053834
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/092,289 Active 2026-01-21 US7282426B2 (en) | 2005-03-29 | 2005-03-29 | Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof |
US11/848,612 Abandoned US20080173957A1 (en) | 2005-03-29 | 2007-08-31 | Method of forming a semiconductor device having a symmetric dielectric regions and structure thereof |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/092,289 Active 2026-01-21 US7282426B2 (en) | 2005-03-29 | 2005-03-29 | Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof |
Country Status (5)
Country | Link |
---|---|
US (2) | US7282426B2 (en) |
JP (1) | JP5049955B2 (en) |
CN (1) | CN101385133B (en) |
TW (1) | TWI425576B (en) |
WO (1) | WO2006104562A2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8999786B1 (en) * | 2007-03-20 | 2015-04-07 | Marvell International Ltd. | Reducing source contact to gate spacing to decrease transistor pitch |
WO2018182627A1 (en) * | 2017-03-30 | 2018-10-04 | Intel Corporation | Transistors including asymmetric gate spacers |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6921691B1 (en) * | 2004-03-18 | 2005-07-26 | Infineon Technologies Ag | Transistor with dopant-bearing metal in source and drain |
US8399934B2 (en) * | 2004-12-20 | 2013-03-19 | Infineon Technologies Ag | Transistor device |
US8178902B2 (en) * | 2004-06-17 | 2012-05-15 | Infineon Technologies Ag | CMOS transistor with dual high-k gate dielectric and method of manufacture thereof |
US7344934B2 (en) | 2004-12-06 | 2008-03-18 | Infineon Technologies Ag | CMOS transistor and method of manufacture thereof |
US7160781B2 (en) * | 2005-03-21 | 2007-01-09 | Infineon Technologies Ag | Transistor device and methods of manufacture thereof |
US7361538B2 (en) * | 2005-04-14 | 2008-04-22 | Infineon Technologies Ag | Transistors and methods of manufacture thereof |
US20070052037A1 (en) * | 2005-09-02 | 2007-03-08 | Hongfa Luan | Semiconductor devices and methods of manufacture thereof |
US8188551B2 (en) | 2005-09-30 | 2012-05-29 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US20070052036A1 (en) * | 2005-09-02 | 2007-03-08 | Hongfa Luan | Transistors and methods of manufacture thereof |
US7462538B2 (en) * | 2005-11-15 | 2008-12-09 | Infineon Technologies Ag | Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials |
US7510943B2 (en) * | 2005-12-16 | 2009-03-31 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US20080050898A1 (en) * | 2006-08-23 | 2008-02-28 | Hongfa Luan | Semiconductor devices and methods of manufacture thereof |
KR100950473B1 (en) * | 2007-12-28 | 2010-03-31 | 주식회사 하이닉스반도체 | Method of fabricating the semiconductor device having gate spacer layer with uniform thickness |
KR100997290B1 (en) * | 2008-07-25 | 2010-11-29 | 주식회사 동부하이텍 | Semiconductor device and manufacturing method of semiconductor device |
WO2011112574A1 (en) * | 2010-03-08 | 2011-09-15 | Mears Technologies, Inc | Semiconductor device including a superlattice and dopant diffusion retarding implants and related methods |
US9397217B2 (en) * | 2012-12-28 | 2016-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of non-planar semiconductor device |
CN107039522B (en) * | 2016-02-04 | 2019-12-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6127248A (en) * | 1998-02-27 | 2000-10-03 | Hyundai Electronics Industries Co., Ltd. | Fabrication method for semiconductor device |
US6352885B1 (en) * | 2000-05-25 | 2002-03-05 | Advanced Micro Devices, Inc. | Transistor having a peripherally increased gate insulation thickness and a method of fabricating the same |
US6713333B2 (en) * | 2001-10-29 | 2004-03-30 | Nec Electronics Corporation | Method for fabricating a MOSFET |
US6746924B1 (en) * | 2003-02-27 | 2004-06-08 | International Business Machines Corporation | Method of forming asymmetric extension mosfet using a drain side spacer |
US6806584B2 (en) * | 2002-10-21 | 2004-10-19 | International Business Machines Corporation | Semiconductor device structure including multiple fets having different spacer widths |
US20060022264A1 (en) * | 2004-07-30 | 2006-02-02 | Leo Mathew | Method of making a double gate semiconductor device with self-aligned gates and structure thereof |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04246862A (en) * | 1991-02-01 | 1992-09-02 | Mitsubishi Electric Corp | Semiconductor integrated circuit and manufacture thereof |
JPH06151451A (en) * | 1992-11-09 | 1994-05-31 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
KR0136932B1 (en) * | 1994-07-30 | 1998-04-24 | 문정환 | Semiconductor device and manufacture method therefor |
US6518106B2 (en) * | 2001-05-26 | 2003-02-11 | Motorola, Inc. | Semiconductor device and a method therefor |
US6544848B1 (en) * | 2002-08-20 | 2003-04-08 | Chartered Semiconductor Manufacturing Ltd. | Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers |
-
2005
- 2005-03-29 US US11/092,289 patent/US7282426B2/en active Active
-
2006
- 2006-02-01 CN CN2006800033691A patent/CN101385133B/en active Active
- 2006-02-01 WO PCT/US2006/003528 patent/WO2006104562A2/en active Application Filing
- 2006-02-01 JP JP2008504031A patent/JP5049955B2/en active Active
- 2006-02-24 TW TW095106398A patent/TWI425576B/en active
-
2007
- 2007-08-31 US US11/848,612 patent/US20080173957A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6127248A (en) * | 1998-02-27 | 2000-10-03 | Hyundai Electronics Industries Co., Ltd. | Fabrication method for semiconductor device |
US6352885B1 (en) * | 2000-05-25 | 2002-03-05 | Advanced Micro Devices, Inc. | Transistor having a peripherally increased gate insulation thickness and a method of fabricating the same |
US6713333B2 (en) * | 2001-10-29 | 2004-03-30 | Nec Electronics Corporation | Method for fabricating a MOSFET |
US6806584B2 (en) * | 2002-10-21 | 2004-10-19 | International Business Machines Corporation | Semiconductor device structure including multiple fets having different spacer widths |
US6746924B1 (en) * | 2003-02-27 | 2004-06-08 | International Business Machines Corporation | Method of forming asymmetric extension mosfet using a drain side spacer |
US20060022264A1 (en) * | 2004-07-30 | 2006-02-02 | Leo Mathew | Method of making a double gate semiconductor device with self-aligned gates and structure thereof |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8999786B1 (en) * | 2007-03-20 | 2015-04-07 | Marvell International Ltd. | Reducing source contact to gate spacing to decrease transistor pitch |
US9245961B1 (en) | 2007-03-20 | 2016-01-26 | Marvell International Ltd. | Reducing source contact to gate spacing to decrease transistor pitch |
WO2018182627A1 (en) * | 2017-03-30 | 2018-10-04 | Intel Corporation | Transistors including asymmetric gate spacers |
Also Published As
Publication number | Publication date |
---|---|
CN101385133B (en) | 2010-12-08 |
WO2006104562A3 (en) | 2008-01-10 |
CN101385133A (en) | 2009-03-11 |
TWI425576B (en) | 2014-02-01 |
TW200711005A (en) | 2007-03-16 |
JP2009501432A (en) | 2009-01-15 |
US20060223335A1 (en) | 2006-10-05 |
US7282426B2 (en) | 2007-10-16 |
JP5049955B2 (en) | 2012-10-17 |
WO2006104562A2 (en) | 2006-10-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7282426B2 (en) | Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof | |
US6153455A (en) | Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer | |
US8476127B2 (en) | Integrated lateral high voltage MOSFET | |
US20080160706A1 (en) | Method for fabricating semiconductor device | |
US7582934B2 (en) | Isolation spacer for thin SOI devices | |
KR20030095402A (en) | Soi device with reduced junction capacitance | |
US20060131648A1 (en) | Ultra thin film SOI MOSFET having recessed source/drain structure and method of fabricating the same | |
JP2932434B2 (en) | Semiconductor device structure and method of manufacturing the same | |
JP2008527755A (en) | Structure and method for optimizing strain in a CMOSFET | |
JP2004079810A (en) | Semiconductor device and its fabricating method, cmos integrated circuit device | |
US6509613B1 (en) | Self-aligned floating body control for SOI device through leakage enhanced buried oxide | |
US11081357B2 (en) | Semiconductor device and method for fabricating the same including re-growth process to form non-uniform gate dielectric layer | |
US7098099B1 (en) | Semiconductor device having optimized shallow junction geometries and method for fabrication thereof | |
JP4134720B2 (en) | Manufacturing method of semiconductor device | |
KR100468785B1 (en) | Method of fabricating MOS Field Effect Transistor with pocket region | |
US20020173128A1 (en) | Gate-controlled, graded-extension device for deep sub-micron ultra-high-performance devices | |
KR20080020401A (en) | A semiconductor for a dual gate cmos and method for fabricating the same | |
JP3744694B2 (en) | Semiconductor device manufacturing method for improving transistor characteristics | |
JP2006210699A (en) | Semiconductor device | |
US20080023761A1 (en) | Semiconductor devices and methods of fabricating the same | |
US10418461B2 (en) | Semiconductor structure with barrier layers | |
US20040203210A1 (en) | Method of fabricating a semiconductor device having a shallow source/drain region | |
US7453121B2 (en) | Body contact formation in partially depleted silicon on insulator device | |
US6949471B2 (en) | Method for fabricating poly patterns | |
JP2004200595A (en) | Mis transistor and manufacturing method therefor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: CITIBANK, N.A., NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:020518/0215 Effective date: 20071025 Owner name: CITIBANK, N.A.,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:020518/0215 Effective date: 20071025 |
|
AS | Assignment |
Owner name: CITIBANK, N.A.,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024085/0001 Effective date: 20100219 Owner name: CITIBANK, N.A., NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024085/0001 Effective date: 20100219 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS COLLATERAL AGENT,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001 Effective date: 20100413 Owner name: CITIBANK, N.A., AS COLLATERAL AGENT, NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001 Effective date: 20100413 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0143 Effective date: 20151207 Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0553 Effective date: 20151207 Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037354/0704 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:038017/0058 Effective date: 20160218 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:039361/0212 Effective date: 20160218 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:042762/0145 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:042985/0001 Effective date: 20160218 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050745/0001 Effective date: 20190903 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051145/0184 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0387 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0387 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051030/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051145/0184 Effective date: 20160218 |