US20080186395A1 - Photo diode fuse-id for cmos imagers - Google Patents
Photo diode fuse-id for cmos imagers Download PDFInfo
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- US20080186395A1 US20080186395A1 US12/098,699 US9869908A US2008186395A1 US 20080186395 A1 US20080186395 A1 US 20080186395A1 US 9869908 A US9869908 A US 9869908A US 2008186395 A1 US2008186395 A1 US 2008186395A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/68—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to defects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/702—SSIS architectures characterised by non-identical, non-equidistant or non-planar pixel layout
Definitions
- the invention relates generally to semiconductor imaging devices, and more particularly to a CMOS pixel sensor imager having an array of pixel cells, in which a portion of the pixel array is programmed to store data.
- CMOS active pixel imagers There is a current interest in CMOS active pixel imagers for use as low cost imaging devices.
- An exemplary pixel circuit of a CMOS active pixel sensor (APS) is described below with reference to FIG. 1 , where the circuit is identified generally by reference number 100 .
- Active pixel sensors can have one or more active transistors within the pixel unit cell, can be made compatible with CMOS technologies, and promise higher readout rates compared to passive pixel sensors.
- the pixel cell shown in FIG. 1 is a 3T APS pixel cell, identified by reference number 150 , where the 3T is commonly used in the art to designate the use of three transistors to operate the pixel.
- a 3T APS includes has a photodiode 162 , a reset transistor 184 , a source follower transistor 186 , and a row select transistor 188 . It should be understood that while FIG. 1 shows the circuitry for operation of a single pixel, in practice the imager will be formed of an M times N array of identical pixels arranged in rows and columns, with the pixels of the array accessed using row and column select circuitry, as described in more detail below.
- the photodiode 162 converts incident photons to electrons which collect at node A.
- a source follower transistor 186 has its gate connected to node A and thus amplifies the signal appearing at Node A.
- the signal amplified by transistor 186 is passed on a column line 170 to the readout circuitry.
- the photodiode 162 accumulates a photo-generated charge in a doped region of the substrate.
- the CMOS imager might include a photogate or other photo conversion device, in lieu of a photodiode, for producing photo-generated charge.
- a reset voltage source Vrst is selectively coupled through reset transistor 184 to node A.
- the gate of reset transistor 184 is coupled to a reset control line 191 which serves to control the reset operation, i.e., the connection of Vrst to node A. Vrst may be equal to Vdd.
- the row select control line 160 is coupled to all of the pixels of the same row of the array.
- Voltage source Vdd is coupled to a source following transistor 186 and its output is selectively coupled to a column line 170 through row select transistor 188 .
- column line 170 is coupled to all of the pixels of the same column of the array and typically has a current sink at its lower end.
- the gate of row select transistor 188 is coupled to row select control line 160 .
- a value is read from pixel 150 in a two step process.
- the photodiode 162 converts photons to electrons which collect at the node A.
- the charge at node A is amplified by source follower transistor 186 and selectively passed to column line 170 by row access transistor 188 .
- node A is reset by turning on reset transistor 184 to apply the reset voltage Vrst to node A, and this voltage is then read out to column line 170 by the source follower transistor 186 through the activated row select transistor 188 .
- the two different values —the reset voltage Vrst and the image signal voltage Vsig—are readout from the pixel and sent by the column line 170 to the readout circuitry where each is sampled and held for further processing as known in the art.
- All pixels in a row are read out simultaneously onto respective column lines 170 and the column lines are activated in sequence for reset and signal voltage read out.
- the rows of pixels are also read out in sequence onto the respective column lines.
- FIG. 2 shows a CMOS active pixel sensor integrated circuit chip that includes an array of pixels 230 and a controller 232 which provides timing and control signals to control reading out of signals stored in the pixels in a manner commonly known to those skilled in the art.
- Exemplary arrays have dimensions of M times N pixels, with the size of the array 230 depending on a particular application.
- the imager is readout a row at a time using a column parallel readout architecture.
- the controller 232 selects a particular row of pixels in the array 230 by controlling the operation of row addressing circuit 234 and row drivers 240 . Charge signals stored in the selected row of pixels are provided on the column lines 170 ( FIG. 1 ) to a readout circuit 242 in the manner described above.
- the pixel signal read from each of the columns then can be read out sequentially using a column addressing circuit 244 .
- Differential pixel signals (Vrst, Vsig) corresponding to the read out reset signal and integrated charge signal are provided as respective outputs Vout 1 , Vout 2 of the readout circuit 242 .
- FIG. 3 more dearly shows the rows and columns 349 of pixels 350 .
- Each column includes multiple rows of pixels 350 .
- Signals from the pixels 350 in a particular column can be read out to a readout circuit 351 associated with that column.
- the read out circuit 351 includes sample and hold circuitry for storing the pixel reset (Vrst) and integrated charge signals (Vsig). Signals stored in the readout circuits 351 then can be read sequentially column-by-column to an output stage 354 which is common to the entire array of pixels 330 .
- the analog output signals can then be sent, for example, to a differential analog circuit and which subtracts the reset and integrated charge signals and sends them to an analog-to-digital converter (ADC), or the reset and integrated charge signals can be supplied directly to the analog-to-digital converter.
- ADC analog-to-digital converter
- FIG. 4 more clearly shows the column readout circuit 351 that includes a sample and hold read out circuit 401 and an amplifier 434 .
- the FIG. 4 circuit is capable of sampling and holding and then amplifying the Vsig and Vrst values for subsequent use by an output stage 354 ( FIG. 3 ).
- each imaging pixel array is usually tested individually. Tests detect defective pixel circuits, pixel signal level, and other array attributes, and the information is stored based on lot and individual device identification numbers. The information developed during testing can be utilized to enhance the operation of the device by, for example, compensating for defective pixels, differing pixel signal levels, and other tested pixel attributes.
- imaging sensors are not identifiable when they are being manufactured.
- the security/identification values are assigned after the complete system is manufactured, resulting in an additional step in manufacturing that also adds to the cost of manufacture.
- a certain number of defective pixels per sensor is tolerated so that a given amount of sensors are deemed usable and manufacturing costs are recovered.
- pixels that are found to be defective do not exceed a predetermined number for the entire sensor nor do they exceed a predetermined number within a predetermined area.
- the locations of these pixels are discovered during testing, it is an administrative burden, as described above, to keep track of this information during manufacture. More importantly, ensuring that information about defective pixels arc supplied with each sensor after manufacture adds to the cost of sensor production. For example, the company that manufactures the sensor must provide the company that manufactures the camera with defective pixel information.
- the defective pixel information is provided a separate media (e.g., a floppy disc, a computer-readable tape, or other computer-readable storage media), which adds to costs. And again, problems arise with matching each sensor with its defective pixel information.
- a separate media e.g., a floppy disc, a computer-readable tape, or other computer-readable storage media
- CMOS imagers with on-chip programmable memory for storing pixel and identification information for a CMOS sensor array are known.
- U.S. Pat. No. 6,396,539 discloses an on-chip programmable flash memory, which is complex and bulky.
- Using a programmable memory requires additional storage circuitry (i.e., the memory) and associated circuitry to read, write, and decipher the information in the memory. It would be desirable to provide an image sensor having on-chip storage system that muses the amount of additional circuitry needed to implement the memory. Additionally, it would be desirable to have an on chip storage system that does not require additional circuitry to access and interpret the stored information. A simple and easy way to store pixel array information on-chip for later use would also be desirable.
- the present invention provides a CMOS image censor array incorporating information storage system as pan of the sensor array.
- Pixel information such as identification numbers, pixel defect locations and fuse ID information, is stored within the image array.
- photodiodes as laser fuses, a row or rows of a pixel array can be programmed to store various information. No additional circuitry is required because system uses existing structures to decode the information.
- FIG. 1 is a prior art active pixel
- PIG. 2 is a block diagram of a prior art CMOS active sensor chip
- FIG. 3 is a block diagram of a prior art array of active pixels and an associated readout circuit
- FIG. 4 is a prior art column readout circuit
- FIG. 5 is a an exemplary embodiment of the CMOS array having programmed pixels
- FIG. 6 is a block diagram representation of a processor-based system incorporating a CMOS imaging device in accordance with an exemplary embodiment of the invention.
- CMOS pixel array a portion of the CMOS pixel array is programmed to store information. More specifically, photodiodes are used as fuse circuits to store information.
- the redundant rows and/or columns are used for the storage of additional pixel array information.
- Information is programmed into the array in a binary format; each pixel is programmed to represent either a “1” or a “0”. Consequently, a series of pixels (in a row) are used to represent a series of binary bits of information.
- a typical row in a pixel array may have 380 to 1024 photodiodes connected to it, a great deal of information can be stored. For example, the coded information may identify defective cell locations or manufacturing lot information.
- FIG. 5 shows an exemplary embodiment of the present invention.
- a portion of row 521 of CMOS pixel array 510 is shown having several representative pixels 552 a, b, c, y, and z which are modified.
- Pixels 552 b , 552 c , and 552 y are shown “altered”, i.e., intentionally physically modified.
- a pixel is programmed by determining what logic state is required in the bit to represent data. Depending on the desired logic state of the pixel, the pixel may be modified, where a modified pixel represents a first logic state and an unmodified pixel represents a second logic state.
- a pixel is modified by applying a laser to a photodiode during manufacturing, in a similar maser as when applying a laser, or a sufficient voltage, to a fuse during manufacturing, which causes the photodiode to be defective.
- Pixels 552 b , 552 c , and 552 y shown with their respective photodiodes marked with an “X” signifies that pixels 552 b , 552 c , and 552 y have intentionally manufactured defective photodiodes.
- individual pixels 552 are selected for writing by using the existing row and column switching transistors.
- a laser is applied with sufficient voltage to make the selected photodiode 562 defective. Programming continues in this manner until all of the data is stored appropriately as pixels 552 which are either programmed defective or not defective according to the data information pattern.
- Programmed data stored in pixel array 510 is accessed and read out using the existing circuitry structures. Access to the programmed data in the pixel array 510 is the same as is known in the art to read pixels 552 , or more specifically, rows of pixels 521 , where the data is accessed by the row and column decoders 234 , 244 ( FIG. 2 ) and the selected fuse and/or fuses are read to determine the stored data.
- An intentionally modified photodiode 562 will appear as a defective or incorrect photo diode voltage and is read as one logic state, e.g., “0”, while a non-defective photodiode 562 is read as another logic state, e.g., “1.”
- the existing circuit converts the read voltage from an analog data form, e.g., the voltage level read form the pixel 552 , to a digital data form, e.g. “0” or “1.”
- a metal fuse is used within a pixel in the place of a photosensitive region or photo diode. Programming of the metal fuse and the readout of signals from the pixel is analogous to the method described.
- the top row of an imager array is reserved for programming and therefore the pixel cells in the top row comprise metal fuses in place of photosensitive regions.
- the pixels are reprogrammable. For example, a pixel is programmed to indicated one logic state and can be subsequently reprogrammed to indicate another logic state.
- a processor based system such as a computer system, for example, generally comprises a central processing unit (CPU) 1110 , for example, a microprocessor, that communicates with one or more input/output (I/O) devices 1150 over one or more buses 1170 .
- the CPU 1110 also exchanges data with random access memory (RAM) 1160 over the one or more buses 1170 , typically through a memory controller.
- the processor system may also include peripheral devices such as a floppy disk drive 1120 and a compact disk (CD) ROM drive 1130 which also communicate with CPU 1110 over one or more buses 1170 .
Abstract
A CMOS image pixel array formed on a chip is used for storing programmed information within the pixel array. Manufacturing lot and other data is written to the array during manufacturing and testing by applying a laser to pixels to render the photodiode defective. The programmed data is read from the pixel array using existing circuitry.
Description
- The invention relates generally to semiconductor imaging devices, and more particularly to a CMOS pixel sensor imager having an array of pixel cells, in which a portion of the pixel array is programmed to store data.
- There is a current interest in CMOS active pixel imagers for use as low cost imaging devices. An exemplary pixel circuit of a CMOS active pixel sensor (APS) is described below with reference to
FIG. 1 , where the circuit is identified generally byreference number 100. Active pixel sensors can have one or more active transistors within the pixel unit cell, can be made compatible with CMOS technologies, and promise higher readout rates compared to passive pixel sensors. The pixel cell shown inFIG. 1 is a 3T APS pixel cell, identified byreference number 150, where the 3T is commonly used in the art to designate the use of three transistors to operate the pixel. A 3T APS includes has aphotodiode 162, areset transistor 184, a source follower transistor 186, and a rowselect transistor 188. It should be understood that whileFIG. 1 shows the circuitry for operation of a single pixel, in practice the imager will be formed of an M times N array of identical pixels arranged in rows and columns, with the pixels of the array accessed using row and column select circuitry, as described in more detail below. - The
photodiode 162 converts incident photons to electrons which collect at node A. A source follower transistor 186 has its gate connected to node A and thus amplifies the signal appearing at Node A. When a particularrow containing cell 150 is selected by arow selection transistor 188, the signal amplified by transistor 186 is passed on acolumn line 170 to the readout circuitry. Thephotodiode 162 accumulates a photo-generated charge in a doped region of the substrate. It should be understood that the CMOS imager might include a photogate or other photo conversion device, in lieu of a photodiode, for producing photo-generated charge. - A reset voltage source Vrst is selectively coupled through
reset transistor 184 to node A. The gate ofreset transistor 184 is coupled to areset control line 191 which serves to control the reset operation, i.e., the connection of Vrst to node A. Vrst may be equal to Vdd. The rowselect control line 160 is coupled to all of the pixels of the same row of the array. Voltage source Vdd is coupled to a source following transistor 186 and its output is selectively coupled to acolumn line 170 through rowselect transistor 188. Although not shown inFIG. 1 ,column line 170 is coupled to all of the pixels of the same column of the array and typically has a current sink at its lower end. The gate ofrow select transistor 188 is coupled to rowselect control line 160. - As known in the art, a value is read from
pixel 150 in a two step process. During a charge integration period, thephotodiode 162 converts photons to electrons which collect at the node A. The charge at node A is amplified by source follower transistor 186 and selectively passed tocolumn line 170 byrow access transistor 188. During a reset period, node A is reset by turning onreset transistor 184 to apply the reset voltage Vrst to node A, and this voltage is then read out tocolumn line 170 by the source follower transistor 186 through the activatedrow select transistor 188. As a result, the two different values—the reset voltage Vrst and the image signal voltage Vsig—are readout from the pixel and sent by thecolumn line 170 to the readout circuitry where each is sampled and held for further processing as known in the art. - All pixels in a row are read out simultaneously onto
respective column lines 170 and the column lines are activated in sequence for reset and signal voltage read out. The rows of pixels are also read out in sequence onto the respective column lines. -
FIG. 2 shows a CMOS active pixel sensor integrated circuit chip that includes an array ofpixels 230 and acontroller 232 which provides timing and control signals to control reading out of signals stored in the pixels in a manner commonly known to those skilled in the art. Exemplary arrays have dimensions of M times N pixels, with the size of thearray 230 depending on a particular application. The imager is readout a row at a time using a column parallel readout architecture. Thecontroller 232 selects a particular row of pixels in thearray 230 by controlling the operation ofrow addressing circuit 234 androw drivers 240. Charge signals stored in the selected row of pixels are provided on the column lines 170 (FIG. 1 ) to areadout circuit 242 in the manner described above. The pixel signal read from each of the columns then can be read out sequentially using acolumn addressing circuit 244. Differential pixel signals (Vrst, Vsig) corresponding to the read out reset signal and integrated charge signal are provided as respective outputs Vout1, Vout2 of thereadout circuit 242. -
FIG. 3 more dearly shows the rows andcolumns 349 ofpixels 350. Each column includes multiple rows ofpixels 350. Signals from thepixels 350 in a particular column can be read out to areadout circuit 351 associated with that column. The read outcircuit 351 includes sample and hold circuitry for storing the pixel reset (Vrst) and integrated charge signals (Vsig). Signals stored in thereadout circuits 351 then can be read sequentially column-by-column to anoutput stage 354 which is common to the entire array ofpixels 330. The analog output signals can then be sent, for example, to a differential analog circuit and which subtracts the reset and integrated charge signals and sends them to an analog-to-digital converter (ADC), or the reset and integrated charge signals can be supplied directly to the analog-to-digital converter. -
FIG. 4 more clearly shows thecolumn readout circuit 351 that includes a sample and hold read outcircuit 401 and anamplifier 434. TheFIG. 4 circuit is capable of sampling and holding and then amplifying the Vsig and Vrst values for subsequent use by an output stage 354 (FIG. 3 ). - During manufacture, each imaging pixel array is usually tested individually. Tests detect defective pixel circuits, pixel signal level, and other array attributes, and the information is stored based on lot and individual device identification numbers. The information developed during testing can be utilized to enhance the operation of the device by, for example, compensating for defective pixels, differing pixel signal levels, and other tested pixel attributes.
- Additionally, imaging sensors are not identifiable when they are being manufactured. The security/identification values are assigned after the complete system is manufactured, resulting in an additional step in manufacturing that also adds to the cost of manufacture. There is also an administrative burden with regard to keeping track of defective pixel information before an identification number is assigned, as the sensor and the defective pixel information related to the pixel must be physically tracked throughout the manufacturing process. If a sensor is misplaced in the manufacturing sequence, then the integrated circuit imaging array, and all the other integrated circuit imaging array that are mis-sequenced, must be re-tested.
- A certain number of defective pixels per sensor is tolerated so that a given amount of sensors are deemed usable and manufacturing costs are recovered. In these sensors, pixels that are found to be defective do not exceed a predetermined number for the entire sensor nor do they exceed a predetermined number within a predetermined area. Although the locations of these pixels are discovered during testing, it is an administrative burden, as described above, to keep track of this information during manufacture. More importantly, ensuring that information about defective pixels arc supplied with each sensor after manufacture adds to the cost of sensor production. For example, the company that manufactures the sensor must provide the company that manufactures the camera with defective pixel information. Most often, the defective pixel information is provided a separate media (e.g., a floppy disc, a computer-readable tape, or other computer-readable storage media), which adds to costs. And again, problems arise with matching each sensor with its defective pixel information.
- CMOS imagers with on-chip programmable memory for storing pixel and identification information for a CMOS sensor array are known. For example, U.S. Pat. No. 6,396,539 (Heller et al ) discloses an on-chip programmable flash memory, which is complex and bulky. Using a programmable memory requires additional storage circuitry (i.e., the memory) and associated circuitry to read, write, and decipher the information in the memory. It would be desirable to provide an image sensor having on-chip storage system that muses the amount of additional circuitry needed to implement the memory. Additionally, it would be desirable to have an on chip storage system that does not require additional circuitry to access and interpret the stored information. A simple and easy way to store pixel array information on-chip for later use would also be desirable.
- The present invention provides a CMOS image censor array incorporating information storage system as pan of the sensor array. Pixel information, such as identification numbers, pixel defect locations and fuse ID information, is stored within the image array. By using photodiodes as laser fuses, a row or rows of a pixel array can be programmed to store various information. No additional circuitry is required because system uses existing structures to decode the information.
- These and other features and advantages of the invention will be more readily understood from the following detailed description of the invention which is provided in connection with the accompanying drawings.
-
FIG. 1 is a prior art active pixel; - PIG. 2 is a block diagram of a prior art CMOS active sensor chip;
-
FIG. 3 is a block diagram of a prior art array of active pixels and an associated readout circuit; -
FIG. 4 is a prior art column readout circuit; -
FIG. 5 is a an exemplary embodiment of the CMOS array having programmed pixels; and -
FIG. 6 is a block diagram representation of a processor-based system incorporating a CMOS imaging device in accordance with an exemplary embodiment of the invention. - In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to make and use the invention, and it is to be understood that structural, logical or other changes may be made to the specific embodiments disclosed without departing from the spirit and scope of the present invention.
- In the present invention, a portion of the CMOS pixel array is programmed to store information. More specifically, photodiodes are used as fuse circuits to store information.
- In an M times N CMOS pixel array, it is common to incorporated the design of the array additional rows and/or columns of pixel to allow for redundancy when defective rows and columns are discovered during testing of the array. In accordance with the present invention, the redundant rows and/or columns are used for the storage of additional pixel array information. Information is programmed into the array in a binary format; each pixel is programmed to represent either a “1” or a “0”. Consequently, a series of pixels (in a row) are used to represent a series of binary bits of information. Where a typical row in a pixel array may have 380 to 1024 photodiodes connected to it, a great deal of information can be stored. For example, the coded information may identify defective cell locations or manufacturing lot information.
-
FIG. 5 shows an exemplary embodiment of the present invention. InFIG. 5 , a portion ofrow 521 ofCMOS pixel array 510 is shown having severalrepresentative pixels 552 a, b, c, y, and z which are modified. Although only five pixels 552 are shown inrow 521, the present invention is not so limited.Pixels Pixels pixels - During manufacturing, testing, and data storage operations of the
pixel array 510, individual pixels 552 are selected for writing by using the existing row and column switching transistors. When a pixel 552 is selected, a laser is applied with sufficient voltage to make the selectedphotodiode 562 defective. Programming continues in this manner until all of the data is stored appropriately as pixels 552 which are either programmed defective or not defective according to the data information pattern. - Programmed data stored in
pixel array 510 is accessed and read out using the existing circuitry structures. Access to the programmed data in thepixel array 510 is the same as is known in the art to read pixels 552, or more specifically, rows ofpixels 521, where the data is accessed by the row andcolumn decoders 234, 244 (FIG. 2 ) and the selected fuse and/or fuses are read to determine the stored data. An intentionally modifiedphotodiode 562 will appear as a defective or incorrect photo diode voltage and is read as one logic state, e.g., “0”, while anon-defective photodiode 562 is read as another logic state, e.g., “1.” The existing circuit converts the read voltage from an analog data form, e.g., the voltage level read form the pixel 552, to a digital data form, e.g. “0” or “1.” - In another aspect of the exemplary embodiment, a metal fuse is used within a pixel in the place of a photosensitive region or photo diode. Programming of the metal fuse and the readout of signals from the pixel is analogous to the method described. In a preferred embodiment, the top row of an imager array is reserved for programming and therefore the pixel cells in the top row comprise metal fuses in place of photosensitive regions. In yet another aspect of the invention, the pixels are reprogrammable. For example, a pixel is programmed to indicated one logic state and can be subsequently reprogrammed to indicate another logic state.
- The method and apparatus aspects of the invention are embodied in an image device 1140 shown in
FIG. 6 which provides an image output signal. The image output signal can also be used in a processor system 1100, also illustrated inFIG. 6 . A processor based system, such as a computer system, for example, generally comprises a central processing unit (CPU) 1110, for example, a microprocessor, that communicates with one or more input/output (I/O)devices 1150 over one ormore buses 1170. TheCPU 1110 also exchanges data with random access memory (RAM) 1160 over the one ormore buses 1170, typically through a memory controller. The processor system may also include peripheral devices such as afloppy disk drive 1120 and a compact disk (CD)ROM drive 1130 which also communicate withCPU 1110 over one ormore buses 1170. - While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Additions, deletions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention. For example, while die pixels containing a photo diode are disclosed, other types of pixels may be used. Other types of photo collectors can also be used, e.g., photo gates. The embodiments discussed above describe specific numbers of transistors, photodiodes, conductive lines, or pixel type (e.g., 3T, 4T), etc. the present invention is not so limited. Although the preferred embodiment discloses the use of active pixels, passive pixels and dummy pixels may also be used. Further, pixels selected for programming are not limited to being disposed in the redundant columns and rows of image array. Accordingly, the invention is not to be considered as limited by the foregoing description but is only limited by the scope of the claims.
Claims (17)
1-36. (canceled)
37. An imaging system with data storage, comprising:
a chip having a sensor array, said sensor array comprising a plurality of pixels, wherein a first portion of said pixels are used for providing a signal representative of light incident to said sensor array, wherein a second portion of said pixels are used for providing programmed data storage, said second portion of said pixels comprising pixels representing data of one of a first and second logic state.
38. The imaging system of claim 37 , wherein said pixels representing data of a first logic state include photodiodes that are programmed to be defective.
39. The imaging system of claim 38 , wherein said pixels representing data of a first logic state include defective photodiodes in which said programmed defect is reversible.
40. The imaging system of claim 38 , wherein said photodiode of each of said pixels representing data of a first logic state is capable of being made defective by a laser.
41. A method of operating an image sensor, comprising:
storing data in a pixel array of said image sensor by programming selected pixels of said pixel array, wherein said programming further comprises:
disabling at least one of said selected: pixels to store data representing a first logic state; and
not disabling at least one of said selected pixels to store data representing a second logic state,
wherein the disabling of a selected pixel comprises making a photosensor of said disabled selected pixel defective.
42. The method of claim 41 , further comprising the step of reading said stored data in said pixel array.
43. The method of claim 42 , further comprising the steps of:
interpreting said stored data in said pixel array; and
interpreting comprises converting said stored data to a logic state.
44. A method as in claim 41 , wherein said data comprises manufacturing information.
45. A method as in claim 41 , wherein said data comprises pixel identification information.
46. A method as in claim 41 , wherein said data comprises testing information.
47. A method as in claim 41 , wherein said data comprises defective pixel information.
48. A method as in claim 41 , wherein said step of storing the data comprises determining one or more locations within said pixel array at which data is stored.
49. A method as in claim 41 , wherein said disabled photosensor is made disabled by a laser.
50. A semiconductor chip, comprising:
a sensor array, comprising:
a plurality of pixels, wherein a first portion of said pixels are used for providing a signal representative of light incident to said sensor array, wherein a second portion of said pixels are used for providing data as different signal states, wherein said second portion of said pixels comprises pixels with intentionally defective photodiodes to represent data of a first logic state.
51. The semiconductor chip of claim 50 , wherein said second portion of said pixels used to provide said data further comprises:
pixels without defective photodiodes to represent data of a second logic state.
52. The semiconductor chip of claim 51 , wherein said defective photodiodes are laser modified photodiode.
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US12/098,699 US20080186395A1 (en) | 2003-06-02 | 2008-04-07 | Photo diode fuse-id for cmos imagers |
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US10/449,031 US7369167B2 (en) | 2003-06-02 | 2003-06-02 | Photo diode ID for CMOS imagers |
US12/098,699 US20080186395A1 (en) | 2003-06-02 | 2008-04-07 | Photo diode fuse-id for cmos imagers |
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US10/449,031 Expired - Fee Related US7369167B2 (en) | 2003-06-02 | 2003-06-02 | Photo diode ID for CMOS imagers |
US12/098,699 Abandoned US20080186395A1 (en) | 2003-06-02 | 2008-04-07 | Photo diode fuse-id for cmos imagers |
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KR101942337B1 (en) * | 2011-05-12 | 2019-01-25 | 디퍼이 신테스 프로덕츠, 인코포레이티드 | Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects |
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US11184564B2 (en) * | 2017-04-28 | 2021-11-23 | The Governing Council Of The University Of Toronto | Method and system for pixel-wise imaging |
JP2022537117A (en) | 2019-06-21 | 2022-08-24 | ザ ガバニング カウンシル オブ ザ ユニバーシティ オブ トロント | Method and system for extending image dynamic range using pixel-by-pixel encoding of pixel parameters |
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Also Published As
Publication number | Publication date |
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JP2006526959A (en) | 2006-11-24 |
US7369167B2 (en) | 2008-05-06 |
CN1833434A (en) | 2006-09-13 |
WO2004110059A1 (en) | 2004-12-16 |
JP4429311B2 (en) | 2010-03-10 |
KR20060005420A (en) | 2006-01-17 |
TW200511845A (en) | 2005-03-16 |
EP1629668A1 (en) | 2006-03-01 |
US20040239789A1 (en) | 2004-12-02 |
KR100718556B1 (en) | 2007-05-15 |
TWI303941B (en) | 2008-12-01 |
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