US20080186752A1 - Memory cell with independent-gate controlled access devices and memory using the cell - Google Patents
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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Abstract
Description
- This invention was made with Government support under contract number NBCH 3039004 awarded by the Defense Advanced Research Projects Agency (DARPA). The government has certain rights in this invention.
- The present invention generally relates to electronic circuitry and, more particularly, to electronic memory circuits.
- Static random access memories (SRAMs) are important components in microprocessor chips and applications, and the portion of SRAM allays in the total chip area has continued to increase. As devices are scaled down, process variations, including device random fluctuations, are key factors in SRAM design. Furthermore, devices in SRAM cells ate being aggressively scaled in terms of device width (or other characteristic dimension) to reduce the area. The smaller cell area aggravates random statistical fluctuations, and hence stable SRAM design is more challenging and complex as silicon technology is advanced.
- SRAM cells can be quite unstable in READ operations, since the data in the storage node is disturbed by the READ current, which can flip the logic values in the storage nodes VL, VR
FIG. 1 shows a READ operation in a prior-art SRAM cell 100. The voltage on node VR rises above zero to a voltage determined by the resistive voltage divider for theaccess devices 102, 104 (AL and AR) and pull-downdevices devices 106, 108 (NL and NR) relative toaccess devices 102, 104 (AL and AR) must be used to improve the READ margin (or to achieve a successful and reliable READ operation). The construction and operation ofconventional cell 100, including true andcomplementary bit lines word line 114, andtransistors 116, 118 (PL and PR) is well-known to the skilled artisan - The WRITE operation is also very unstable in prior-art cells due to increased process variations.
FIG. 2 shows a WRITE operation in the prior-art SRAM cell 100 (elements inFIG. 2 similar to those inFIG. 1 are designated by the same reference characters). In the WRITE operation,devices 102, 116 (AL and PL) (ordevices 104, 118 (AR and PR)) form a resistive voltage divider for the lower-voltage bit line 110 (BL) and the node (VL) having a logical “one” stored therein. In this case, device 102 (AL) (or device 104 (AR)) must be stronger than device 116 (PL) (or device 118 (PR)) to improve the WRITE margin (that is, to enable a quick exchange of the state of the stored data between the two cell nodes, VL and VR). - Double-gate (DC) complementary metal oxide semiconductor (CMOS) devices offer distinct advantages for scaling, due to much reduced short-channel effects, and DC CMOS also offers the opportunity to proceed beyond the performance of single-gate (SC) devices such as bulk silicon or silicon-on-insulator (SOI). A variety of DG device structures including FinFET, TriGate, and gate-all-around field effect transistors (FETs) awe proposed. Among these, the FinFET is quite promising due to its easy fabrication and process flow, and its superior performance
FIG. 3 shows a FinFET device structure andFIG. 4 shows a cross-sectional view, as known from E. J. Nowak, et al., “A Functional FinFET-DGCMOS SRAM Cell,” IEDM. Tech. Dig, pp. 411-414, December 2002. AFinFET device 300 can include multiplefins forming sources 302 anddrains 304 with acentral gate structure 306; as best seen in the insets inFIG. 3 , first and second (or front and back)gates FIG. 4 , device parameters include the oxide thickness for the front and back gates, toxf and toxb, and the dimension between the gates tSi. Each gate controls a separate channel - Interestingly, DG FinFET devices can be employed either with two gates tied, as shown in
FIG. 5 , or independently-biased, as shown inFIG. 6 , and as known from Y. Liu, et al., “A High Threshold Voltage-Controllable 4T FinFET with an 8.5-nm-Thick Si-Fin Channel, IEEE Elec. Dev. Lett., Vol. 25, No. 7, pp. 510-512, July 2004, and Chiang, et al., “Novel High-Density Low-Power High-Performance Double-Gate Logic techniques,” Proc. IEEE Internat. SOI Conf., Charleston, S.C., October 2004. Similar elements inFIGS. 3 through 6 have received the same reference characters - One way to improve SRAM READ/WRITE margins is to use the just-mentioned independently-controlled gates Reference should now be had to
FIGS. 7 and 8 , wherein elements similar toFIGS. 1 and 2 have received the same reference character incremented by six hundred (FIG. 7 ) and seven hundred (FIG. 8 ); note that double-gate FETs are depicted inFIGS. 7 and 8 . Yamaoka developed a “Yin-Yang” feedback technique for SRAM cells to improve the READ stability, as shown inFIG. 7 and as known from M. Yamaoka, et al., “Low-Power SEAM Menu for SOC Application Using Yin-Yang-Feedback Memory Cell,” Symp. VLSI Circuits Dig, pp. 288-291, June 2004 The main drawback of the device ofFIG. 7 is that the WRITE margin cannot be improved due to the reduction of the strength for theaccess devices FIG. 8 and as known from Z. Guo, “FinFET-Based SRAM Design,” Proc. Internat Symp. Lower Power Elec. Des, pp. 2-7, August 2005. The back gate ofdevice 802 is connected to left-hand node 890 and that ofdevice 804 is connected to right-hand node 892. However, the scheme ofFIG. 8 exhibits several drawbacks. First, the WRITE margin is not improved because bothaccess devices devices FIG. 7 Second, in a half selected WRITE mode, the scheme ofFIG. 8 has a serious problem due to the unwanted large leakage current flow from the storage node (storing a logical “one”) to the bit line (at ground voltage) because the back gates are biased to VDD. Under conditions of increased threshold voltage (Vt) variation, WRITE operations will be unstable for this scheme. - In summary, for prior art cells, the conventional scaled 6T cell of
FIGS. 1 and 2 is not stable; in the schemes ofFIGS. 7 and 8 , the WRITE margin is not improved; and writing is unstable in the half selected case for the scheme ofFIG. 8 . It would be desirable to overcome one or mole of the limitations in previous approaches - Principles of the present invention provide techniques for memory cells with independent-gate controlled access devices, and memories using the cells. One or mole embodiments of cells according to the present invention can obtain improved READ and/or WRITE margins.
- In an exemplary embodiment, according to one aspect of the invention, a memory cell for interconnection with true and complementary bit lines and READ and WRITE word lines includes a first inverter having a first inverter double-gate pull-down device, and a second inverter having a second inverter double-gate pull-down device. The second inverter is cross-coupled to the first inverter to form a storage flip-flop. The cell further includes first and second access devices configured to selectively interconnect the cross-coupled inverters with the true and complementary bit lines. The first and second access devices are double-gate devices, each having a first gate connected to the READ word line and a second gate connected to the WRITE word line. During a READ operation, the first and second access devices are configured to operate in a single-gate mode with the READ word line “ON” and the WRITE word line “OfF” while the double-gate pull-down devices are configured to operate in a double gate mode. During a WRITE operation, the first and second access devices ate configured to operate in a double-gate mode with the READ word line “ON” and the WRITE word line also “ON”. Optionally, the cell includes first and second inverter double-gate pull-up devices configured to operate in a double-gate mode during both the READ and WRITE operations.
- In another aspect, an exemplary embodiment of a memory circuit includes a plurality of bit line structures, the bit line structures in turn comprising true and complementary bit lines, a plurality of word lines structures, the word line structures in turn comprising READ and WRITE word lines and intersecting the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells, of the kind described, located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. The circuit further includes control circuitry connected to the bit line structures and the word line structures and configured to activate the READ word line but not the WRITE word line during a READ operation, so that the first and second access devices operate in a single-gate mode while the double-gate pull-down devices operate in a double gate mode, and further configured to activate both the READ word line and the WRITE word line during a WRITE operation, so that the first and second access devices operate in a double-gate mode.
- In yet another aspect, an exemplary method of operating a memory circuit of the kind described includes the steps of activating the READ word line but not the WRITE word line during a READ operation fox a given one of the cells, so that the first and second access devices of the given one of the cells operate in a single-gate mode while the double-gate pull-down devices of the given one of the cells operate in a double gate mode, and activating both the READ word line and the WRITE word line during a WRITE operation for the given one of the cells, so that the first and second access devices of the given one of the cells operate in a double-gate mode.
- One or more embodiments of the present invention may be realized in the form of an integrated circuit.
- These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be READ in connection with the accompanying drawings.
-
FIG. 1 shows a prior art cell during a REA-D operation; -
FIG. 2 shows a prior art cell during a WRITE operation; -
FIG. 3 shows a prior art FinFET device; -
FIG. 4 shows a cross-sectional view of a prior art FinFET device; -
FIGS. 5 and 6 show tied gates and independent gates, respectively, for prior art double-gate FETs; -
FIG. 7 shows a prior art “Yin-Yang” SRAM cell; -
FIG. 8 shows another prior art SRAM cell, employing a back-gated design; -
FIG. 9 shows an exemplary embodiment of a memory circuit using a first exemplary embodiment of a memory cell in accordance with an aspect of the invention; -
FIG. 10 shows an exemplary embodiment of a memory circuit using a second exemplary embodiment of a memory cell in accordance with an aspect of the invention; -
FIG. 11 shows predicted READ Static Noise Margins for conventional and proposed schemes; and -
FIG. 12 shows predicted WRITE Margins for conventional and proposed schemes. -
FIG. 1 depicts a memory, such as an SRAM, employing cells in accordance with an exemplary embodiment of the invention. It will be appreciated thatcells 900 ate part of the larger memory circuit having a plurality of bit line structures, such as those formed by true andcomplementary bit lines single cell 900 is depicted in detailFIG. 1 , the other cells being shown in block form. The skilled artisan will appreciate that a memory circuit can be provided, for example, in the form of an integrated circuit, having many such cells, as illustrated by the ellipses.Circuit 900 could, if desired, include some cells of the type shown in detail and some cells of a different type, either conventional or according to other embodiments of the present invention. Of course, all the cells could be identical. - A plurality of
cells 900 can be located at the plurality of cell locations Each of thecells 900 can be selectively coupled to a corresponding one of the bit line structures formed by true andcomplementary bit lines device 910 and a second inverter having a second inverter double-gate pull-downdevice 912. The second inverter is cross-coupled to the first inverter to form a storage flip-flop.Cell 900 further includes first andsecond access devices complementary bit lines second access devices READ word line 906 and a second gate connected to theWRITE word line 908. - The circuit further includes
control circuitry 918 connected to the bit line structures and the word line structures and configured to activate theREAD word line 906 but not theWRITE word line 908 during a READ operation, so that the first andsecond access devices devices Circuitry 918 is further configured to activate both theREAD word line 906 and theWRITE word line 908 during a WRITE operation, so that the first andsecond access devices Circuitry 918 is shown in block form. It will be appreciated that the skilled artisan, given the teachings herein, will be able to construct appropriate control circuitry to carry out the indicated operations. - The first inverter can be formed, for example, from
device 910 coupled to a first inverter pull-updevice 920, and the second inverter can be formed, for example, fromdevice 912 coupled to a second inverter pull-updevice 922. In the exemplary embodiment depicted, the first inverter double-gate pull-downdevice 910 is an n-type field effect transistor (NFET) having electrically interconnected first and second gates, the first inverter pull-updevice 920 is a p-type field effect transistor (PFET), the second inverter double-gate pull-downdevice 912 is an NFET having electrically interconnected first and second gates, and the second inverter pull-updevice 922 is a PFET. Further, the first andsecond access devices devices second access devices - The circuit can also include a
supply voltage terminal 924 for a supply voltage VDD and aground terminal 926, it being understood that terminal 926 need not necessarily be maintained at a potential of zero, and that theterminals cells 900 as may be required. Thefirst access device 914 has a first drain-source terminal connected to thetrue bit line 902, and a second drain-source terminal. The first inverter pull-updevice 920 has a first drain-source terminal coupled to thesupply voltage terminal 924, a second drain-source terminal coupled to the second drain-source terminal of thefirst access device 914, and at least one gate coupled to the first and second gates of the first inverter double-gate pull-downdevice 910. Further, the first inverter double-gate pull-downdevice 910 has a first drain-source terminal connected to the second drain-source terminal of the first inverter pull-updevice 920 and a second drain-source terminal coupled to theground terminal 926. Thesecond access device 916 has a first drain-source terminal connected to thecomplementary bit line 904, and a second drain-source terminal. The second inverter pull-updevice 922 has a first drain-source terminal coupled to thesupply voltage terminal 924, a second drain-source terminal coupled to the second drain-source terminal of thesecond access device 916 and the at least one gate of the first inverter pull-updevice 920, and at least one gate coupled to the first and second gates of the second inverter double-gate pull-downdevice 912 and the second drain-source terminal of the first inverter pull-updevice 920. - The second inverter double-gate pull-down
device 912 has a first drain-source terminal connected to the second drain-source terminal of the second inverter pull-updevice 922 and a second drain-source terminal coupled to theground terminal 926, and the first and second inverter pull-down and pull-updevices second access devices - It will be appreciated that the embodiment of
FIG. 9 employs twoseparate word lines access device WRITE word line 908 One gate of the access devices is connected to the READ word line 906 (RWL) and the other is connected to the WRITE word line 908 (WWL). In a READ operation, only RWL is “ON” (biased to VDD on RWL) and WWL is “OFF” (biased to 0 on WWL), thus weakening the strength ofaccess devices 914, 916 (AR and AL) relative to pull-downdevices 910, 912 (NL and NR) because AR and AL are operating in SG mode and NL and NR are operating in DG mode. In a WRITE operation, both RWL and WWL are “ON,” thus strengtheningdevices 916, 918 (AL and AR) relative to pull-updevices 920, 922 (PL and PR). - Attention should now be directed to
FIG. 10 . Elements similar to those inFIG. 9 have received the same reference character incremented by one hundred, and will not be described again except to the extent they differ materially from those inFIG. 9 . In the embodiment depicted, the first and second inverter pull-updevices device 1020 can be a double-gate p-type field effect transistor (PFET) having electrically interconnected first and second gates, and the second inverter pull-updevice 1022 can be a double-gate PFET having electrically interconnected first and second gates. The first inverter double-gate pull-updevice 1020 has a first drain-source terminal coupled to thesupply voltage terminal 1024, and a second drain-source terminal coupled to the second drain-source terminal of thefirst access device 1014. The first and second gates of the first inverter pull-updevice 1020 are coupled to the first and second gates of the first inverter double-gate pull-down device 1010. The second inverter double-gate pull-updevice 1022 has a first drain-source terminal coupled to thesupply voltage terminal 1024, and a second drain-source terminal coupled to the second drain-source terminal of thesecond access device 1016 and the gates of the first inverter pull-updevice 1020. The first and second gates of the second inverter double-gate pull-updevice 1022 are coupled to the first and second gates of the second inverter double-gate pull-down device 1012 and the second drain-source terminal of the first inverter pull-updevice 1020. - It will be appreciated that the READ stability is increased in the example of
FIG. 10 , compared withFIG. 9 . The pull-downdevices 1020, 1022 (PL and PR) can be strengthened by connecting two gates for each device. In this case, PL and PR are operating in DG mode. Although a READ operation is most stable in the example ofFIG. 10 , the WRITE margin of the embodiment ofFIG. 10 is lower than that ofFIG. 9 and it would be the same as with a conventional scheme. - It should be emphasized that the embodiments of
FIGS. 9 and 10 are exemplary in nature, and inventive cells and circuits can be implemented in many fashions; for example, with complementary polarities and device types. - Given the foregoing discussion, it will be apparent that a method of operating a memory circuit of the kind described can include the step of activating the
READ word line WRITE word line cells second access devices devices READ word line WRITE word line cells second access devices cells READ word line WRITE word line access devices devices READ word line WRITE word line access devices devices - For circuits such as that of
FIG. 10 , an additional step can include operating the first and second inverter double-gate pull-updevices FIG. 10 , the gates are permanently connected sodevices -
FIG. 11 compares READ margins for particular instances of conventional 6T cells and the exemplary embodiments of FIGS 9 and 10. MEDICI: 2-D Device Simulation, a mix-mode device/circuit simulator available from Synopsys Inc, Mountain View, Calif. (http://www.synopsyscorn/products/mixedsignal/taurus/device_sim_ds.html) was used, and FinFET devices were simulated, having a gate length of 25 nm, front-gate and back-gate thicknesses of 1 nm, and an undoped film thickness of 7 nm (parameters are depicted inFIG. 4 ). Note that all three schemes use a single fin-based FinFET device having Fin Height=50 nm; the actual device width is 0.1 μm in DG mode (which is the minimum device width in state-of-art CMOS technology). As shown inFIG. 11 , the conventional 6T cell (curve 1102) shows a very low READ margin of 100 mV in a single Fin-based design. In order to improve the READ margin, additional Fins would have to be used for pull-down devices, which significantly increases cell area. The inventive embodiments offer a more than twice higher READ SNM than the conventional scheme without increasing cell area. The Predicted READ SNM is 210 mV for the embodiment ofFIG. 9 (curve 1104) and 260 mV for the embodiment ofFIG. 11 (curve 1106). -
FIG. 12 shows MEDICI-predicted results of WRITE. Margin wave forms for the exemplary embodiments, compared with a conventional scheme. The WRITE margin is defined as the maximum bit line (BL) voltage that can flip the cell state. It is observed that the same WRITE margin is predicted for the conventional and the embodiment ofFIG. 10 (curve 1202), but the embodiment ofFIG. 9 (curve 1204) offers a 26% higher WRITE margin. - It is to be emphasized that the dimensions set forth in the examples of
FIGS. 11 and 12 are exemplary and not limiting, and different dimensions can be used with the embodiments ofFIGS. 9 and 10 , or other embodiments; further, the indicated performance improvements are for the specific cases discussed and are not intended to limit the scope of the invention. - It will be appreciated that one or more inventive embodiments enable improved READ and/or WRITE margins by using two separate READ and WRITE word lines in a single FinFET access device. One of more of the following advantages may be achieved by one or more inventive embodiments:
- (1) Improvements of READ and/or WRITE margins;
(2) Single Fin-based FinFET SRAM design with improved SRAM density;
(3) Applicable to many independent-gate controlled double-gate technologies including symmetrical and asymmetrical gates. - One or mote inventive embodiments can be used in future FinFET technology where the READ/WRITE margins may be hard to manage due to process variations, and where high-density cells (or a single Fin for each device) are required.
- Memory cells according to one more aspects of the invention may be formed into memory circuits, which may be realized as integrated circuits; thus, at least a portion of the techniques of one or more aspects or embodiments of the present invention described herein may be implemented in an integrated circuit. In forming integrated circuits, a plurality of identical die are typically fabricated in a repeated pattern on a surface of a semiconductor wafer. Each die can include one or more of the cells described herein, and may include other structures or circuits, or other types of cells. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. A person of skill in the art will know how to dice wafers and package die to produce integrated circuits. Integrated circuits so manufactured are considered part of the present invention.
- Circuits including cells as described above can be part of the design for an integrated circuit chip. The chip design can be created, for example, in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly ox indirectly. The stored design can then be converted into an appropriate format such as, for example, Graphic Design System II (GDSII), for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks can be utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
- Resulting integrated circuit chips can be distributed by the fabricator in law wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die or in a packaged form. In the latter case, the chip can be mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a mother board or other higher level carrier) or in a multi-chip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may then be integrated with other chips, discrete circuit elements and/or other signal processing devices as part of either (a) an intermediate product, such as a mother board, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor
- It will be appreciated and should be understood that the exemplary embodiments of the invention described above can be implemented in a number of different fashions. Given the teachings of the invention provided herein, one of ordinary skill in the related art will be able to contemplate other implementations of the invention
- Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope of spirit of the invention
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US12/757,648 US7990757B2 (en) | 2007-01-11 | 2010-04-09 | Method of operating a memory circuit using memory cells with independent-gate controlled access devices |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US20080019194A1 (en) * | 2006-07-19 | 2008-01-24 | Akira Katayama | Semiconductor memory device |
US20080237710A1 (en) * | 2007-03-28 | 2008-10-02 | Ibrahim Ban | Localized spacer for a multi-gate transistor |
US20100110774A1 (en) * | 2007-03-20 | 2010-05-06 | Shinichi Ouchi | Sram device |
US20100328990A1 (en) * | 2006-12-07 | 2010-12-30 | Nat.Inst. Of Adv Industrial Science And Technology | Sram device |
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US20080225574A1 (en) | 2008-09-18 |
US7400525B1 (en) | 2008-07-15 |
US7738284B2 (en) | 2010-06-15 |
US7990757B2 (en) | 2011-08-02 |
US20100195373A1 (en) | 2010-08-05 |
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