US20080237855A1 - Ball grid array package and its substrate - Google Patents
Ball grid array package and its substrate Download PDFInfo
- Publication number
- US20080237855A1 US20080237855A1 US11/727,902 US72790207A US2008237855A1 US 20080237855 A1 US20080237855 A1 US 20080237855A1 US 72790207 A US72790207 A US 72790207A US 2008237855 A1 US2008237855 A1 US 2008237855A1
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- substrate
- top surface
- chip
- bga package
- ball pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Definitions
- the present invention relates to an IC package, and more particularly to a Ball Grid Array (BGA) package and its substrate.
- BGA Ball Grid Array
- Ball Grid Array packages have become popular IC packages using a plurality of solder balls to solder onto an external Printed Circuit Board, PCB.
- PCB Printed Circuit Board
- a thermal cycle test is performed for reliability test. Thermal stresses would concentrate on some specific solder balls, especially at the corners of the substrate and under the corners of an encapsulated chip, causing breaking at the solder joints due to the differences of Coefficient of Thermal Expansion, CTE, between BGA and PCB. The similar result is observed during a drop test.
- a conventional BGA package 100 primarily comprises a substrate 110 , a chip 120 , a plurality of solder balls 130 and an encapsulant 150 .
- the substrate 110 has a top surface 111 , a bottom surface 112 and a plurality of ball pads 113 , where the ball pads 113 are formed on the bottom surface 112 .
- a die-attaching area 114 is defined on the top surface 111 of the substrate 110 where the active surface of the chip 120 is attached to the die-attaching area 114 of the top surface 111 of the substrate 110 by a die-attaching layer 160 .
- the chip 120 is electrically connected to the substrate 110 by a plurality of bonding wires 140 where the substrate 110 has a wire-bonding slot 115 for passing through the bonding wires 140 .
- the solder balls 130 are disposed on the ball pads 113 for electrical connection to an external PCB 10 .
- the chip 120 and the bonding wires 140 are encapsulated by the encapsulant 150 .
- thermal stresses will concentrate at several of the solder balls 130 disposed adjacent to some ball pads 113 A at the corners of the substrate 110 or under the corners of the chip 120 causing breaks 116 at the solder balls 130 and leading to electrical open.
- the main purpose of the present invention is to provide a BGA package and its substrate by creating corner cavities filled with low-modulus materials at the corners of the substrate to be stress buffers which can adsorb thermal stresses and avoid cracks in the solder balls at the corners of the substrate.
- the second purpose of the present invention is to provide a BGA package and its substrate to avoid the stresses from the corners of the chip directly transferring to the corresponding solder balls and ball pads under the corners of the chip.
- a BGA package mainly comprises a substrate, a chip, and a plurality of solder balls.
- the substrate has a top surface and a bottom surface where a plurality of ball pads are formed on the bottom surface.
- the chip is attached to the top surface of the substrate and is electrically connected to the substrate.
- the solder balls are disposed on the ball pads.
- the substrate includes at least a core layer between the top surface and the bottom surface, where the core layer has a plurality of corner cavities filled with low-modulus materials, moreover, some of the ball pads at the corners of the substrate are disposed under the corner cavities.
- the corner cavities filled with low-modulus materials at the corners of the substrate can be replaced by a plurality of stress buffering components.
- FIG. 1 shows a cross-sectional view of a conventional BGA package.
- FIG. 2 shows a bottom view of the conventional BGA package.
- FIG. 3 shows a cross-sectional view of a BGA package according to the first embodiment of the present invention.
- FIG. 4 shows a bottom view of the BGA package according to the first embodiment of the present invention.
- FIG. 5 shows a top view of the substrate of the BGA package according to the first embodiment of the present invention.
- FIG. 6A to 6E show cross-sectional views of the substrate during manufacturing processes according to the first embodiment of the present invention.
- FIG. 7 shows a cross-sectional view of a BGA package according to the second embodiment of the present invention.
- FIG. 8 shows a top view of the substrate of the BGA package according to the second embodiment of the present invention.
- FIG. 9A to 9D show cross-sectional views of the substrate during manufacturing processes according to the second embodiment of the present invention.
- a BGA package 200 mainly comprises a substrate 210 , a chip 220 , and a plurality of solder balls 230 .
- the substrate 210 has a top surface 211 and a bottom surface 212 where a plurality of ball pads 213 are formed on the bottom surface 212 , a die-attaching area 216 is defined on the top surface 211 for attaching the chip 220 .
- some of the ball pads 213 at the corners of the substrate 210 or/and at the corners of the die-attaching area 216 are defined as ball pads 213 A bearing the most intense thermal stresses.
- the chip 220 is disposed on the top surface 211 of the substrate 210 and is electrically connected to the substrate 210 .
- the active surface 221 of the chip 220 is attached to the top surface 211 of the substrate 210 by a die-attaching layer 270 aligned with the die-attaching area 216 .
- the substrate may have a wire-bonding slot 217 crossing the die-attaching area 216 , moreover, the BGA package 200 further has a plurality of bonding wires 250 passing through the wire-bonding slot 217 to electrically connect the bonding pads 222 of the chip 220 to the substrate 210 .
- the solder balls 230 are disposed on the ball pads 213 for surface mounting the BGA package 200 to an external PCB 20 , as shown in FIG. 3 .
- the substrate 210 includes at least a core layer 214 where the core layer 214 has a plurality of corner cavities 215 filled with low-modulus materials 240 such as rubber, silicone gel, or resin to be embedded stress buffers. Furthermore, the ball pads 213 A at the corners of the substrate 210 are disposed under the corner cavities 215 .
- the corner cavities 215 are rectangular and are not extended to the edges of the substrate 210 to avoid the low-modulus materials 240 exposed from the edges of the BGA package 200 and to have a better moisture resistance.
- FIG. 1 Preferably, as shown in FIG.
- the four corners of the die-attaching area 216 defined on the top surface 211 of the substrate 210 are overlapped on the corner cavities 215 so that the stresses induced by the corners of the chip 220 on the substrate 210 can be dispersed and absorbed by the low-modulus materials 240 without transferring the stresses to the solder balls 230 and the corresponding ball pads 213 A under the corners of the chip 220 .
- the BGA package 200 further has an encapsulant 260 formed on the top surface 211 of the substrate 210 to encapsulate at least a portion of the chip 220 , such as only the sidewalls of the chip 220 or the entire chip 220 .
- the encapsulant 260 is also formed inside the wire-bonding slot 217 to encapsulate the bonding wires 250 .
- the Young's modulus of the encapsulant 260 is higher than the one of the low-modulus materials 240 .
- FIG. 6A a core layer 218 is provided for the substrate 210 .
- FIG. 6B another core layer 214 is laminated on the core layer 218 and a plurality of corner cavities 215 are created from the core layer 214 .
- FIG. 6C low-modulus materials 240 are filled in the corner cavities 215 .
- FIG. 6A a core layer 218 is provided for the substrate 210 .
- FIG. 6B another core layer 214 is laminated on the core layer 218 and a plurality of corner cavities 215 are created from the core layer 214 .
- FIG. 6C low-modulus materials 240 are filled in the corner cavities 215 .
- FIG. 6C low-modulus materials 240 are filled in the corner cavities 215 .
- another core layer 219 is laminated on the patterned core layer 214 to embed and to completely encapsulate the low-modulus materials 240 among the core layer 214 , 218 , and 219 , i.e., the low-modulus materials 240 are embedded between the top surface 211 and the bottom surface 212 of the substrate 210 as shown in FIG. 6E .
- the ball pads 213 including the ball pads 213 A with the corresponding traces are created on the core layer 218 .
- a die-attaching layer 270 can be pre-disposed on the core layer 219 for attaching the chip 220 , as shown in FIG. 3 .
- the BGA package 300 primarily comprises a substrate 310 , a chip 320 , and a plurality of solder balls 330 .
- the substrate 310 has a top surface 311 and a bottom surface 212 where a plurality of ball pads 313 are formed on the bottom surface 312 .
- a die-attaching area 316 is defined on the top surface 311 .
- a chip 320 is attached to the die-attaching area 316 on the top surface 311 of the substrate 310 and is electrically connected to the substrate 310 .
- the active surface 321 of the chip 320 is attached to the top surface 311 of the substrate 310 .
- the solder balls 330 are disposed on the ball pads 313 to electrically connect the BGA package 330 to an external PCB 30 (as shown in FIG. 7 ) where the PCB 30 can be mother boards for electronic products or cellular phones or modular boards for memory devices.
- the BGA package 300 further includes a plurality of bonding wires 350 to electrically connect the bonding pads 322 of the chip 320 to the substrate 310 where the substrate 310 has a wire-bonding slot 317 for passing through the bonding wires 350 .
- the BGA package 300 further has an encapsulant 360 to encapsulate the chip 320 .
- the encapsulant 360 can be formed inside the wire-bonding slot 317 to encapsulate the bonding wires 350 .
- the substrate 310 includes at least a core layer 314 embedded with a plurality of low-modulus materials 340 as embedded stress buffers so that some of the ball pads 313 , especially the ball pads 313 A located at the corners of the substrate 310 where stresses are most concentrated, can be disposed under the low-modulus materials 340 .
- the low-modulus materials 340 can be formed in sections on the substrate 310 by printing.
- the low-modulus materials 340 can also be individually preformed as stress buffers such as elastic elements and be disposed in the corner cavities 315 of the core layer 314 .
- the thicknesses of the low-modulus materials 314 or the elastic elements are thicker than the core layer 314 such that the low-modulus materials 314 are exposed from the top surface 311 .
- the corners of the die-attaching area 316 of the substrate 310 are overlapped on the low-modulus materials 340 . Accordingly, the corners of the chip 320 contact the low-modulus materials 314 for stress dispersion in the substrate 310 .
- the low-modulus materials 314 are adhesive so that the contact with the chip 320 is direct.
- FIG. 9A a core layer 318 or a copper foil is provided for the substrate 310 .
- FIG. 9B another core layer 314 is laminated on the core layer 318 and a plurality of corner cavities 315 are created from the core layer 318 .
- FIG. 9C low-modulus materials 340 are filled in the corner cavities 315 by plug-in, dispensing or printing, where the thickness of the low-modulus materials 340 is thicker than the one of the core layer 314 .
- FIG. 9C low-modulus materials 340 are filled in the corner cavities 315 by plug-in, dispensing or printing, where the thickness of the low-modulus materials 340 is thicker than the one of the core layer 314 .
- the ball pads 313 including the ball pads 313 A located at the corners of the substrate 310 and the corresponding traces are disposed at the bottom surface of the core layer 318 or etching the copper foil to form the ball pads 313 .
- the low-modulus materials 340 can be used as a die-attaching material to attach the chip 320 .
Abstract
A BGA package and a substrate for the package are disclosed. A chip is disposed on a top surface of the substrate. A plurality of solder balls are disposed on a plurality of ball pads formed on a bottom surface of the substrate. The substrate has at least a core layer with a plurality of corner cavities filled with low-modulus materials as stress buffer. Additionally, some of the ball pads at the corners of the substrate are disposed under the corner cavities.
Description
- The present invention relates to an IC package, and more particularly to a Ball Grid Array (BGA) package and its substrate.
- Ball Grid Array packages, BGA, have become popular IC packages using a plurality of solder balls to solder onto an external Printed Circuit Board, PCB. When a BGA package is surface-mounted on a PCB, a thermal cycle test is performed for reliability test. Thermal stresses would concentrate on some specific solder balls, especially at the corners of the substrate and under the corners of an encapsulated chip, causing breaking at the solder joints due to the differences of Coefficient of Thermal Expansion, CTE, between BGA and PCB. The similar result is observed during a drop test.
- As shown in
FIG. 1 andFIG. 2 , aconventional BGA package 100 primarily comprises asubstrate 110, achip 120, a plurality ofsolder balls 130 and anencapsulant 150. Thesubstrate 110 has atop surface 111, abottom surface 112 and a plurality ofball pads 113, where theball pads 113 are formed on thebottom surface 112. A die-attachingarea 114 is defined on thetop surface 111 of thesubstrate 110 where the active surface of thechip 120 is attached to the die-attachingarea 114 of thetop surface 111 of thesubstrate 110 by a die-attachinglayer 160. Thechip 120 is electrically connected to thesubstrate 110 by a plurality ofbonding wires 140 where thesubstrate 110 has a wire-bonding slot 115 for passing through thebonding wires 140. Thesolder balls 130 are disposed on theball pads 113 for electrical connection to anexternal PCB 10. Thechip 120 and thebonding wires 140 are encapsulated by theencapsulant 150. As specifically shown inFIG. 1 , when theBGA package 100 is surface-mounted on thePCB 10, thermal stresses will concentrate at several of thesolder balls 130 disposed adjacent to someball pads 113A at the corners of thesubstrate 110 or under the corners of thechip 120 causingbreaks 116 at thesolder balls 130 and leading to electrical open. - The main purpose of the present invention is to provide a BGA package and its substrate by creating corner cavities filled with low-modulus materials at the corners of the substrate to be stress buffers which can adsorb thermal stresses and avoid cracks in the solder balls at the corners of the substrate.
- The second purpose of the present invention is to provide a BGA package and its substrate to avoid the stresses from the corners of the chip directly transferring to the corresponding solder balls and ball pads under the corners of the chip.
- According to the present invention, a BGA package mainly comprises a substrate, a chip, and a plurality of solder balls. The substrate has a top surface and a bottom surface where a plurality of ball pads are formed on the bottom surface. The chip is attached to the top surface of the substrate and is electrically connected to the substrate. The solder balls are disposed on the ball pads. The substrate includes at least a core layer between the top surface and the bottom surface, where the core layer has a plurality of corner cavities filled with low-modulus materials, moreover, some of the ball pads at the corners of the substrate are disposed under the corner cavities. In different embodiments, the corner cavities filled with low-modulus materials at the corners of the substrate can be replaced by a plurality of stress buffering components.
-
FIG. 1 shows a cross-sectional view of a conventional BGA package. -
FIG. 2 shows a bottom view of the conventional BGA package. -
FIG. 3 shows a cross-sectional view of a BGA package according to the first embodiment of the present invention. -
FIG. 4 shows a bottom view of the BGA package according to the first embodiment of the present invention. -
FIG. 5 shows a top view of the substrate of the BGA package according to the first embodiment of the present invention. -
FIG. 6A to 6E show cross-sectional views of the substrate during manufacturing processes according to the first embodiment of the present invention. -
FIG. 7 shows a cross-sectional view of a BGA package according to the second embodiment of the present invention. -
FIG. 8 shows a top view of the substrate of the BGA package according to the second embodiment of the present invention. -
FIG. 9A to 9D show cross-sectional views of the substrate during manufacturing processes according to the second embodiment of the present invention. - Please refer to the attached drawings, the present invention will be described by means of embodiment(s) below.
- According to the first embodiment of the present invention, as shown in
FIG. 3 andFIG. 4 , aBGA package 200 mainly comprises asubstrate 210, achip 220, and a plurality ofsolder balls 230. Thesubstrate 210 has atop surface 211 and abottom surface 212 where a plurality ofball pads 213 are formed on thebottom surface 212, a die-attachingarea 216 is defined on thetop surface 211 for attaching thechip 220. Moreover, as shown inFIG. 5 , some of theball pads 213 at the corners of thesubstrate 210 or/and at the corners of the die-attachingarea 216 are defined asball pads 213A bearing the most intense thermal stresses. - The
chip 220 is disposed on thetop surface 211 of thesubstrate 210 and is electrically connected to thesubstrate 210. In the present embodiment, theactive surface 221 of thechip 220 is attached to thetop surface 211 of thesubstrate 210 by a die-attachinglayer 270 aligned with the die-attachingarea 216. As shown inFIG. 3 , the substrate may have a wire-bonding slot 217 crossing the die-attachingarea 216, moreover, theBGA package 200 further has a plurality ofbonding wires 250 passing through the wire-bonding slot 217 to electrically connect thebonding pads 222 of thechip 220 to thesubstrate 210. - The
solder balls 230 are disposed on theball pads 213 for surface mounting theBGA package 200 to anexternal PCB 20, as shown inFIG. 3 . - As shown in
FIG. 3 ,FIG. 4 , andFIG. 5 again, thesubstrate 210 includes at least acore layer 214 where thecore layer 214 has a plurality ofcorner cavities 215 filled with low-modulus materials 240 such as rubber, silicone gel, or resin to be embedded stress buffers. Furthermore, theball pads 213A at the corners of thesubstrate 210 are disposed under thecorner cavities 215. Thecorner cavities 215 are rectangular and are not extended to the edges of thesubstrate 210 to avoid the low-modulus materials 240 exposed from the edges of theBGA package 200 and to have a better moisture resistance. Preferably, as shown inFIG. 5 , the four corners of the die-attachingarea 216 defined on thetop surface 211 of thesubstrate 210 are overlapped on thecorner cavities 215 so that the stresses induced by the corners of thechip 220 on thesubstrate 210 can be dispersed and absorbed by the low-modulus materials 240 without transferring the stresses to thesolder balls 230 and thecorresponding ball pads 213A under the corners of thechip 220. - Furthermore, the BGA
package 200 further has an encapsulant 260 formed on thetop surface 211 of thesubstrate 210 to encapsulate at least a portion of thechip 220, such as only the sidewalls of thechip 220 or theentire chip 220. In the present embodiment, the encapsulant 260 is also formed inside the wire-bonding slot 217 to encapsulate thebonding wires 250. Normally, the Young's modulus of theencapsulant 260 is higher than the one of the low-modulus materials 240. - The manufacturing processes of the
substrate 210 are described in detail fromFIG. 6A toFIG. 6E . Firstly, as shown inFIG. 6A , acore layer 218 is provided for thesubstrate 210. Then, as shown inFIG. 6B , anothercore layer 214 is laminated on thecore layer 218 and a plurality ofcorner cavities 215 are created from thecore layer 214. Then, as shown inFIG. 6C , low-modulus materials 240 are filled in thecorner cavities 215. Then, as shown inFIG. 6D , anothercore layer 219 is laminated on the patternedcore layer 214 to embed and to completely encapsulate the low-modulus materials 240 among thecore layer modulus materials 240 are embedded between thetop surface 211 and thebottom surface 212 of thesubstrate 210 as shown inFIG. 6E . Finally, as shown inFIG. 6E , theball pads 213 including theball pads 213A with the corresponding traces are created on thecore layer 218. A die-attachinglayer 270 can be pre-disposed on thecore layer 219 for attaching thechip 220, as shown inFIG. 3 . - In the second embodiment, another BGA package is revealed in
FIG. 7 andFIG. 8 . TheBGA package 300 primarily comprises asubstrate 310, achip 320, and a plurality ofsolder balls 330. Thesubstrate 310 has atop surface 311 and abottom surface 212 where a plurality ofball pads 313 are formed on thebottom surface 312. A die-attachingarea 316 is defined on thetop surface 311. - A
chip 320 is attached to the die-attachingarea 316 on thetop surface 311 of thesubstrate 310 and is electrically connected to thesubstrate 310. In the present embodiment, theactive surface 321 of thechip 320 is attached to thetop surface 311 of thesubstrate 310. Thesolder balls 330 are disposed on theball pads 313 to electrically connect theBGA package 330 to an external PCB 30 (as shown inFIG. 7 ) where thePCB 30 can be mother boards for electronic products or cellular phones or modular boards for memory devices. - The
BGA package 300 further includes a plurality ofbonding wires 350 to electrically connect thebonding pads 322 of thechip 320 to thesubstrate 310 where thesubstrate 310 has a wire-bonding slot 317 for passing through thebonding wires 350. In the present embodiment, theBGA package 300 further has anencapsulant 360 to encapsulate thechip 320. Moreover, theencapsulant 360 can be formed inside the wire-bonding slot 317 to encapsulate thebonding wires 350. - The
substrate 310 includes at least acore layer 314 embedded with a plurality of low-modulus materials 340 as embedded stress buffers so that some of theball pads 313, especially theball pads 313A located at the corners of thesubstrate 310 where stresses are most concentrated, can be disposed under the low-modulus materials 340. The low-modulus materials 340 can be formed in sections on thesubstrate 310 by printing. The low-modulus materials 340 can also be individually preformed as stress buffers such as elastic elements and be disposed in thecorner cavities 315 of thecore layer 314. In the present embodiment, the thicknesses of the low-modulus materials 314 or the elastic elements are thicker than thecore layer 314 such that the low-modulus materials 314 are exposed from thetop surface 311. Preferably, the corners of the die-attachingarea 316 of thesubstrate 310 are overlapped on the low-modulus materials 340. Accordingly, the corners of thechip 320 contact the low-modulus materials 314 for stress dispersion in thesubstrate 310. Preferably, the low-modulus materials 314 are adhesive so that the contact with thechip 320 is direct. - The manufacturing processes of the
substrate 310 are described in detail fromFIG. 9A to 9D . Firstly, as shown inFIG. 9A , acore layer 318 or a copper foil is provided for thesubstrate 310. Then, as shown inFIG. 9B , anothercore layer 314 is laminated on thecore layer 318 and a plurality ofcorner cavities 315 are created from thecore layer 318. Then, as shown inFIG. 9C , low-modulus materials 340 are filled in thecorner cavities 315 by plug-in, dispensing or printing, where the thickness of the low-modulus materials 340 is thicker than the one of thecore layer 314. Finally, as shown inFIG. 9D , theball pads 313 including theball pads 313A located at the corners of thesubstrate 310 and the corresponding traces are disposed at the bottom surface of thecore layer 318 or etching the copper foil to form theball pads 313. In the present embodiment, the low-modulus materials 340 can be used as a die-attaching material to attach thechip 320. - The above description of embodiments of this invention is intended to be illustrative and not limiting. Other embodiments of this invention will be obvious to those skilled in the art in view of the above disclosure.
Claims (20)
1. A BGA package comprising:
a substrate having a top surface, a bottom surface, a plurality of ball pads formed on the bottom surface and at least a core layer between the top surface and the bottom surface;
a chip disposed on the top surface of the substrate and electrically connected to the substrate; and
a plurality of solder balls disposed on the ball pads;
wherein the core layer has a plurality of corner cavities filled with low-modulus materials, and some of the ball pads at the corners of the substrate are disposed under the corner cavities.
2. The BGA package of claim 1 , wherein the corner cavities are rectangular.
3. The BGA package of claim 1 , wherein the chip is attached to a die-attaching area on the top surface of the substrate, the die-attaching area having a plurality of corners overlapped on the corner cavities.
4. The BGA package of claim 1 , wherein the low-modulus materials are embedded between the top surface and the bottom surface of the substrate.
5. The BGA package of claim 3 , wherein the low-modulus materials are exposed on the top surface and contacted the corners of the chip.
6. The BGA package of claim 1 , further comprising a plurality of bonding wires electrically connecting the chip to the substrate.
7. The BGA package of claim 6 , further comprising an encapsulant encapsulating at least a portion of the chip and the bonding wires.
8. A substrate for BGA packages, having a top surface and a bottom surface and comprising:
at least a core layer between the top surface and the bottom surface; and
a plurality of ball pads formed on the bottom surface;
wherein the core layer has a plurality of corner cavities filled with low-modulus materials, and some of the ball pads at the corners of the substrate are disposed under the corner cavities.
9. The substrate of claim 8 , wherein the corner cavities are rectangular.
10. The substrate of claim 8 , wherein the top surface of the substrate includes a die-attaching area having a plurality of corners overlapped on the corner cavities.
11. The substrate of claim 8 , wherein the low-modulus materials are embedded between the top surface and the bottom surface of the substrate.
12. The substrate of claim 8 , wherein the low-modulus materials are exposed on the top surface for contacting a plurality of corners of a chip.
13. A BGA package comprising:
a substrate having a top surface, a bottom surface, a plurality of ball pads formed on the bottom surface, and at least a core layer between the top surface and the bottom surface;
a chip disposed on the top surface of the substrate and electrically connected to the substrate;
a plurality of solder balls disposed on the ball pads; and
a stress buffer patterned and embedded in the core layer;
wherein at least one of the ball pads bearing the most concentrated stress is disposed under the stress buffer.
14. The BGA package of claim 13 , wherein the stress buffer is an elastic rectangular block.
15. The BGA package of claim 13 , wherein the chip is attached to a die-attaching area on the top surface of the substrate, the die-attaching area having a plurality of corners overlapped on the stress buffer.
16. The BGA package of claim 13 , further comprising a plurality of bonding wires electrically connecting the chip to the substrate.
17. The BGA package of claim 16 , further comprising an encapsulant encapsulating at least a portion of the chip and the bonding wires.
18. A substrate for BGA packages, having a top surface and a bottom surface and comprising:
at least a core layer between the top surface and the bottom surface; and
a plurality of ball pads formed on the bottom surface; and
a stress buffer patterned and embedded in the core layer;
wherein at least one of the ball pads bearing the most concentrated stress is disposed under the stress buffer.
19. The substrate of claim 18 , wherein the stress buffer is an elastic rectangular block.
20. The substrate of claim 18 , wherein the top surface of the substrate includes a die-attaching area having a plurality of corners overlapped on the stress buffer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US11/727,902 US20080237855A1 (en) | 2007-03-28 | 2007-03-28 | Ball grid array package and its substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US11/727,902 US20080237855A1 (en) | 2007-03-28 | 2007-03-28 | Ball grid array package and its substrate |
Publications (1)
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US20080237855A1 true US20080237855A1 (en) | 2008-10-02 |
Family
ID=39792833
Family Applications (1)
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US11/727,902 Abandoned US20080237855A1 (en) | 2007-03-28 | 2007-03-28 | Ball grid array package and its substrate |
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